target-arm: A64: Implement WFI
Implement the WFI instruction for A64; this just involves wiringup the instruction, and adding a gen_a64_set_pc_im() which wasaccidentally omitted from the A64 decoder top loop.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
target-arm: Store AIF bits in env->pstate for AArch32
To avoid complication in code that otherwise would not need tocare about whether EL1 is AArch32 or AArch64, we should storethe interrupt mask bits (CPSR.AIF in AArch32 and PSTATE.DAIFin AArch64) in one place consistently regardless of EL1's mode....
target-arm: Implement AArch64 generic timers
Implement the AArch64 view of the generic timer system registers.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Implement AArch64 ID and feature registers
Implement the AArch64-specific ID and feature registers. Althoughmany of these are currently not used by the architecture (and soalways zero for all implementations), we define the full set offields in the ARMCPU struct for symmetry....
target-arm: Implement AArch64 dummy breakpoint and watchpoint registers
In AArch64 the breakpoint and watchpoint registers are mandatory, so thekernel always accesses them on bootup. Implement dummy versions, whichread as written but have no actual effect....
target-arm: Implement AArch64 OSLAR_EL1 sysreg as WI
Define a dummy version of the AArch64 OSLAR_EL1 system registerwhich just ignores writes. Linux will always write to this (itis the OS lock used for debugging), but we don't support debug.
target-arm: Get MMU index information correct for A64 code
Emit the correct MMU index information for loads and stores fromA64 code, rather than hardwiring it to "always kernel mode",by storing the exception level in the TB flags, and makecpu_mmu_index() return the right answer when the CPU is in...
target-arm: Implement AArch64 VBAR_EL1
Implement the A64 view of the VBAR system register.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
target-arm: Implement AArch64 TTBR*
Implement the AArch64 TTBR* registers. For v7 these were already 64 bitsto handle LPAE, but implemented as two separate uint32_t fields.Combine them into a single uint64_t which can be used for all purposes.Since this requires touching every use, take the opportunity to rename...
target-arm: Implement AArch64 MPIDR
Implement the AArch64 MPIDR system register.
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