root / hw / mc146818rtc.c @ 4e17eae9
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1 | 80cabfad | bellard | /*
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2 | 80cabfad | bellard | * QEMU MC146818 RTC emulation
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3 | 5fafdf24 | ths | *
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4 | 80cabfad | bellard | * Copyright (c) 2003-2004 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 80cabfad | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 80cabfad | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 80cabfad | bellard | * in the Software without restriction, including without limitation the rights
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9 | 80cabfad | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 80cabfad | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 80cabfad | bellard | * furnished to do so, subject to the following conditions:
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12 | 80cabfad | bellard | *
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13 | 80cabfad | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 80cabfad | bellard | * all copies or substantial portions of the Software.
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15 | 80cabfad | bellard | *
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16 | 80cabfad | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 80cabfad | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 80cabfad | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 80cabfad | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 80cabfad | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 80cabfad | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 80cabfad | bellard | * THE SOFTWARE.
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23 | 80cabfad | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "qemu-timer.h" |
26 | 87ecb68b | pbrook | #include "sysemu.h" |
27 | 87ecb68b | pbrook | #include "pc.h" |
28 | 87ecb68b | pbrook | #include "isa.h" |
29 | 16b29ae1 | aliguori | #include "hpet_emul.h" |
30 | 80cabfad | bellard | |
31 | 80cabfad | bellard | //#define DEBUG_CMOS
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32 | 80cabfad | bellard | |
33 | dd17765b | Gleb Natapov | #define RTC_REINJECT_ON_ACK_COUNT 20 |
34 | ba32edab | Gleb Natapov | |
35 | 80cabfad | bellard | #define RTC_SECONDS 0 |
36 | 80cabfad | bellard | #define RTC_SECONDS_ALARM 1 |
37 | 80cabfad | bellard | #define RTC_MINUTES 2 |
38 | 80cabfad | bellard | #define RTC_MINUTES_ALARM 3 |
39 | 80cabfad | bellard | #define RTC_HOURS 4 |
40 | 80cabfad | bellard | #define RTC_HOURS_ALARM 5 |
41 | 80cabfad | bellard | #define RTC_ALARM_DONT_CARE 0xC0 |
42 | 80cabfad | bellard | |
43 | 80cabfad | bellard | #define RTC_DAY_OF_WEEK 6 |
44 | 80cabfad | bellard | #define RTC_DAY_OF_MONTH 7 |
45 | 80cabfad | bellard | #define RTC_MONTH 8 |
46 | 80cabfad | bellard | #define RTC_YEAR 9 |
47 | 80cabfad | bellard | |
48 | 80cabfad | bellard | #define RTC_REG_A 10 |
49 | 80cabfad | bellard | #define RTC_REG_B 11 |
50 | 80cabfad | bellard | #define RTC_REG_C 12 |
51 | 80cabfad | bellard | #define RTC_REG_D 13 |
52 | 80cabfad | bellard | |
53 | dff38e7b | bellard | #define REG_A_UIP 0x80 |
54 | 80cabfad | bellard | |
55 | 100d9891 | aurel32 | #define REG_B_SET 0x80 |
56 | 100d9891 | aurel32 | #define REG_B_PIE 0x40 |
57 | 100d9891 | aurel32 | #define REG_B_AIE 0x20 |
58 | 100d9891 | aurel32 | #define REG_B_UIE 0x10 |
59 | 100d9891 | aurel32 | #define REG_B_SQWE 0x08 |
60 | 100d9891 | aurel32 | #define REG_B_DM 0x04 |
61 | dff38e7b | bellard | |
62 | 72716184 | Anthony Liguori | #define REG_C_UF 0x10 |
63 | 72716184 | Anthony Liguori | #define REG_C_IRQF 0x80 |
64 | 72716184 | Anthony Liguori | #define REG_C_PF 0x40 |
65 | 72716184 | Anthony Liguori | #define REG_C_AF 0x20 |
66 | 72716184 | Anthony Liguori | |
67 | dff38e7b | bellard | struct RTCState {
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68 | 32e0c826 | Gerd Hoffmann | ISADevice dev; |
69 | dff38e7b | bellard | uint8_t cmos_data[128];
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70 | dff38e7b | bellard | uint8_t cmos_index; |
71 | 43f493af | bellard | struct tm current_tm;
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72 | 32e0c826 | Gerd Hoffmann | int32_t base_year; |
73 | d537cf6c | pbrook | qemu_irq irq; |
74 | 100d9891 | aurel32 | qemu_irq sqw_irq; |
75 | 18c6e2ff | ths | int it_shift;
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76 | dff38e7b | bellard | /* periodic timer */
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77 | dff38e7b | bellard | QEMUTimer *periodic_timer; |
78 | dff38e7b | bellard | int64_t next_periodic_time; |
79 | dff38e7b | bellard | /* second update */
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80 | dff38e7b | bellard | int64_t next_second_time; |
81 | ba32edab | Gleb Natapov | uint16_t irq_reinject_on_ack_count; |
82 | 73822ec8 | aliguori | uint32_t irq_coalesced; |
83 | 73822ec8 | aliguori | uint32_t period; |
84 | 93b66569 | aliguori | QEMUTimer *coalesced_timer; |
85 | dff38e7b | bellard | QEMUTimer *second_timer; |
86 | dff38e7b | bellard | QEMUTimer *second_timer2; |
87 | dff38e7b | bellard | }; |
88 | dff38e7b | bellard | |
89 | e0ca7b94 | Juan Quintela | static void rtc_irq_raise(qemu_irq irq) |
90 | e0ca7b94 | Juan Quintela | { |
91 | c50c2d68 | aurel32 | /* When HPET is operating in legacy mode, RTC interrupts are disabled
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92 | 16b29ae1 | aliguori | * We block qemu_irq_raise, but not qemu_irq_lower, in case legacy
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93 | c50c2d68 | aurel32 | * mode is established while interrupt is raised. We want it to
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94 | 16b29ae1 | aliguori | * be lowered in any case
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95 | c50c2d68 | aurel32 | */
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96 | ce88f890 | Juan Quintela | #if defined TARGET_I386
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97 | c50c2d68 | aurel32 | if (!hpet_in_legacy_mode())
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98 | 16b29ae1 | aliguori | #endif
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99 | 16b29ae1 | aliguori | qemu_irq_raise(irq); |
100 | 16b29ae1 | aliguori | } |
101 | 16b29ae1 | aliguori | |
102 | dff38e7b | bellard | static void rtc_set_time(RTCState *s); |
103 | dff38e7b | bellard | static void rtc_copy_date(RTCState *s); |
104 | dff38e7b | bellard | |
105 | 93b66569 | aliguori | #ifdef TARGET_I386
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106 | 93b66569 | aliguori | static void rtc_coalesced_timer_update(RTCState *s) |
107 | 93b66569 | aliguori | { |
108 | 93b66569 | aliguori | if (s->irq_coalesced == 0) { |
109 | 93b66569 | aliguori | qemu_del_timer(s->coalesced_timer); |
110 | 93b66569 | aliguori | } else {
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111 | 93b66569 | aliguori | /* divide each RTC interval to 2 - 8 smaller intervals */
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112 | 93b66569 | aliguori | int c = MIN(s->irq_coalesced, 7) + 1; |
113 | 6875204c | Jan Kiszka | int64_t next_clock = qemu_get_clock(rtc_clock) + |
114 | 6875204c | Jan Kiszka | muldiv64(s->period / c, get_ticks_per_sec(), 32768);
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115 | 93b66569 | aliguori | qemu_mod_timer(s->coalesced_timer, next_clock); |
116 | 93b66569 | aliguori | } |
117 | 93b66569 | aliguori | } |
118 | 93b66569 | aliguori | |
119 | 93b66569 | aliguori | static void rtc_coalesced_timer(void *opaque) |
120 | 93b66569 | aliguori | { |
121 | 93b66569 | aliguori | RTCState *s = opaque; |
122 | 93b66569 | aliguori | |
123 | 93b66569 | aliguori | if (s->irq_coalesced != 0) { |
124 | 93b66569 | aliguori | apic_reset_irq_delivered(); |
125 | 93b66569 | aliguori | s->cmos_data[RTC_REG_C] |= 0xc0;
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126 | 93b66569 | aliguori | rtc_irq_raise(s->irq); |
127 | 93b66569 | aliguori | if (apic_get_irq_delivered()) {
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128 | 93b66569 | aliguori | s->irq_coalesced--; |
129 | 93b66569 | aliguori | } |
130 | 93b66569 | aliguori | } |
131 | 93b66569 | aliguori | |
132 | 93b66569 | aliguori | rtc_coalesced_timer_update(s); |
133 | 93b66569 | aliguori | } |
134 | 93b66569 | aliguori | #endif
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135 | 93b66569 | aliguori | |
136 | dff38e7b | bellard | static void rtc_timer_update(RTCState *s, int64_t current_time) |
137 | dff38e7b | bellard | { |
138 | dff38e7b | bellard | int period_code, period;
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139 | dff38e7b | bellard | int64_t cur_clock, next_irq_clock; |
140 | 100d9891 | aurel32 | int enable_pie;
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141 | dff38e7b | bellard | |
142 | dff38e7b | bellard | period_code = s->cmos_data[RTC_REG_A] & 0x0f;
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143 | ce88f890 | Juan Quintela | #if defined TARGET_I386
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144 | c50c2d68 | aurel32 | /* disable periodic timer if hpet is in legacy mode, since interrupts are
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145 | 16b29ae1 | aliguori | * disabled anyway.
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146 | 16b29ae1 | aliguori | */
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147 | a8b01dd8 | pbrook | enable_pie = !hpet_in_legacy_mode(); |
148 | 16b29ae1 | aliguori | #else
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149 | 100d9891 | aurel32 | enable_pie = 1;
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150 | 16b29ae1 | aliguori | #endif
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151 | 100d9891 | aurel32 | if (period_code != 0 |
152 | 100d9891 | aurel32 | && (((s->cmos_data[RTC_REG_B] & REG_B_PIE) && enable_pie) |
153 | 100d9891 | aurel32 | || ((s->cmos_data[RTC_REG_B] & REG_B_SQWE) && s->sqw_irq))) { |
154 | dff38e7b | bellard | if (period_code <= 2) |
155 | dff38e7b | bellard | period_code += 7;
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156 | dff38e7b | bellard | /* period in 32 Khz cycles */
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157 | dff38e7b | bellard | period = 1 << (period_code - 1); |
158 | 73822ec8 | aliguori | #ifdef TARGET_I386
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159 | 73822ec8 | aliguori | if(period != s->period)
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160 | 73822ec8 | aliguori | s->irq_coalesced = (s->irq_coalesced * s->period) / period; |
161 | 73822ec8 | aliguori | s->period = period; |
162 | 73822ec8 | aliguori | #endif
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163 | dff38e7b | bellard | /* compute 32 khz clock */
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164 | 6ee093c9 | Juan Quintela | cur_clock = muldiv64(current_time, 32768, get_ticks_per_sec());
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165 | dff38e7b | bellard | next_irq_clock = (cur_clock & ~(period - 1)) + period;
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166 | 6875204c | Jan Kiszka | s->next_periodic_time = |
167 | 6875204c | Jan Kiszka | muldiv64(next_irq_clock, get_ticks_per_sec(), 32768) + 1; |
168 | dff38e7b | bellard | qemu_mod_timer(s->periodic_timer, s->next_periodic_time); |
169 | dff38e7b | bellard | } else {
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170 | 73822ec8 | aliguori | #ifdef TARGET_I386
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171 | 73822ec8 | aliguori | s->irq_coalesced = 0;
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172 | 73822ec8 | aliguori | #endif
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173 | dff38e7b | bellard | qemu_del_timer(s->periodic_timer); |
174 | dff38e7b | bellard | } |
175 | dff38e7b | bellard | } |
176 | dff38e7b | bellard | |
177 | dff38e7b | bellard | static void rtc_periodic_timer(void *opaque) |
178 | dff38e7b | bellard | { |
179 | dff38e7b | bellard | RTCState *s = opaque; |
180 | dff38e7b | bellard | |
181 | dff38e7b | bellard | rtc_timer_update(s, s->next_periodic_time); |
182 | 100d9891 | aurel32 | if (s->cmos_data[RTC_REG_B] & REG_B_PIE) {
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183 | 100d9891 | aurel32 | s->cmos_data[RTC_REG_C] |= 0xc0;
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184 | 93b66569 | aliguori | #ifdef TARGET_I386
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185 | 93b66569 | aliguori | if(rtc_td_hack) {
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186 | ba32edab | Gleb Natapov | if (s->irq_reinject_on_ack_count >= RTC_REINJECT_ON_ACK_COUNT)
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187 | ba32edab | Gleb Natapov | s->irq_reinject_on_ack_count = 0;
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188 | 93b66569 | aliguori | apic_reset_irq_delivered(); |
189 | 93b66569 | aliguori | rtc_irq_raise(s->irq); |
190 | 93b66569 | aliguori | if (!apic_get_irq_delivered()) {
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191 | 93b66569 | aliguori | s->irq_coalesced++; |
192 | 93b66569 | aliguori | rtc_coalesced_timer_update(s); |
193 | 93b66569 | aliguori | } |
194 | 93b66569 | aliguori | } else
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195 | 93b66569 | aliguori | #endif
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196 | 100d9891 | aurel32 | rtc_irq_raise(s->irq); |
197 | 100d9891 | aurel32 | } |
198 | 100d9891 | aurel32 | if (s->cmos_data[RTC_REG_B] & REG_B_SQWE) {
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199 | 100d9891 | aurel32 | /* Not square wave at all but we don't want 2048Hz interrupts!
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200 | 100d9891 | aurel32 | Must be seen as a pulse. */
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201 | 100d9891 | aurel32 | qemu_irq_raise(s->sqw_irq); |
202 | 100d9891 | aurel32 | } |
203 | dff38e7b | bellard | } |
204 | 80cabfad | bellard | |
205 | b41a2cd1 | bellard | static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data) |
206 | 80cabfad | bellard | { |
207 | b41a2cd1 | bellard | RTCState *s = opaque; |
208 | 80cabfad | bellard | |
209 | 80cabfad | bellard | if ((addr & 1) == 0) { |
210 | 80cabfad | bellard | s->cmos_index = data & 0x7f;
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211 | 80cabfad | bellard | } else {
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212 | 80cabfad | bellard | #ifdef DEBUG_CMOS
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213 | 80cabfad | bellard | printf("cmos: write index=0x%02x val=0x%02x\n",
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214 | 80cabfad | bellard | s->cmos_index, data); |
215 | 3b46e624 | ths | #endif
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216 | dff38e7b | bellard | switch(s->cmos_index) {
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217 | 80cabfad | bellard | case RTC_SECONDS_ALARM:
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218 | 80cabfad | bellard | case RTC_MINUTES_ALARM:
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219 | 80cabfad | bellard | case RTC_HOURS_ALARM:
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220 | 80cabfad | bellard | /* XXX: not supported */
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221 | 80cabfad | bellard | s->cmos_data[s->cmos_index] = data; |
222 | 80cabfad | bellard | break;
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223 | 80cabfad | bellard | case RTC_SECONDS:
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224 | 80cabfad | bellard | case RTC_MINUTES:
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225 | 80cabfad | bellard | case RTC_HOURS:
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226 | 80cabfad | bellard | case RTC_DAY_OF_WEEK:
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227 | 80cabfad | bellard | case RTC_DAY_OF_MONTH:
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228 | 80cabfad | bellard | case RTC_MONTH:
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229 | 80cabfad | bellard | case RTC_YEAR:
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230 | 80cabfad | bellard | s->cmos_data[s->cmos_index] = data; |
231 | dff38e7b | bellard | /* if in set mode, do not update the time */
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232 | dff38e7b | bellard | if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
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233 | dff38e7b | bellard | rtc_set_time(s); |
234 | dff38e7b | bellard | } |
235 | 80cabfad | bellard | break;
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236 | 80cabfad | bellard | case RTC_REG_A:
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237 | dff38e7b | bellard | /* UIP bit is read only */
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238 | dff38e7b | bellard | s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) | |
239 | dff38e7b | bellard | (s->cmos_data[RTC_REG_A] & REG_A_UIP); |
240 | 6875204c | Jan Kiszka | rtc_timer_update(s, qemu_get_clock(rtc_clock)); |
241 | dff38e7b | bellard | break;
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242 | 80cabfad | bellard | case RTC_REG_B:
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243 | dff38e7b | bellard | if (data & REG_B_SET) {
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244 | dff38e7b | bellard | /* set mode: reset UIP mode */
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245 | dff38e7b | bellard | s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; |
246 | dff38e7b | bellard | data &= ~REG_B_UIE; |
247 | dff38e7b | bellard | } else {
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248 | dff38e7b | bellard | /* if disabling set mode, update the time */
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249 | dff38e7b | bellard | if (s->cmos_data[RTC_REG_B] & REG_B_SET) {
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250 | dff38e7b | bellard | rtc_set_time(s); |
251 | dff38e7b | bellard | } |
252 | dff38e7b | bellard | } |
253 | dff38e7b | bellard | s->cmos_data[RTC_REG_B] = data; |
254 | 6875204c | Jan Kiszka | rtc_timer_update(s, qemu_get_clock(rtc_clock)); |
255 | 80cabfad | bellard | break;
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256 | 80cabfad | bellard | case RTC_REG_C:
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257 | 80cabfad | bellard | case RTC_REG_D:
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258 | 80cabfad | bellard | /* cannot write to them */
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259 | 80cabfad | bellard | break;
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260 | 80cabfad | bellard | default:
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261 | 80cabfad | bellard | s->cmos_data[s->cmos_index] = data; |
262 | 80cabfad | bellard | break;
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263 | 80cabfad | bellard | } |
264 | 80cabfad | bellard | } |
265 | 80cabfad | bellard | } |
266 | 80cabfad | bellard | |
267 | abd0c6bd | Paul Brook | static inline int rtc_to_bcd(RTCState *s, int a) |
268 | 80cabfad | bellard | { |
269 | 6f1bf24d | aurel32 | if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
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270 | dff38e7b | bellard | return a;
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271 | dff38e7b | bellard | } else {
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272 | dff38e7b | bellard | return ((a / 10) << 4) | (a % 10); |
273 | dff38e7b | bellard | } |
274 | 80cabfad | bellard | } |
275 | 80cabfad | bellard | |
276 | abd0c6bd | Paul Brook | static inline int rtc_from_bcd(RTCState *s, int a) |
277 | 80cabfad | bellard | { |
278 | 6f1bf24d | aurel32 | if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
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279 | dff38e7b | bellard | return a;
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280 | dff38e7b | bellard | } else {
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281 | dff38e7b | bellard | return ((a >> 4) * 10) + (a & 0x0f); |
282 | dff38e7b | bellard | } |
283 | dff38e7b | bellard | } |
284 | dff38e7b | bellard | |
285 | dff38e7b | bellard | static void rtc_set_time(RTCState *s) |
286 | dff38e7b | bellard | { |
287 | 43f493af | bellard | struct tm *tm = &s->current_tm;
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288 | dff38e7b | bellard | |
289 | abd0c6bd | Paul Brook | tm->tm_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS]); |
290 | abd0c6bd | Paul Brook | tm->tm_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES]); |
291 | abd0c6bd | Paul Brook | tm->tm_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f);
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292 | 43f493af | bellard | if (!(s->cmos_data[RTC_REG_B] & 0x02) && |
293 | 43f493af | bellard | (s->cmos_data[RTC_HOURS] & 0x80)) {
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294 | 43f493af | bellard | tm->tm_hour += 12;
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295 | 43f493af | bellard | } |
296 | abd0c6bd | Paul Brook | tm->tm_wday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]) - 1;
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297 | abd0c6bd | Paul Brook | tm->tm_mday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]); |
298 | abd0c6bd | Paul Brook | tm->tm_mon = rtc_from_bcd(s, s->cmos_data[RTC_MONTH]) - 1;
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299 | abd0c6bd | Paul Brook | tm->tm_year = rtc_from_bcd(s, s->cmos_data[RTC_YEAR]) + s->base_year - 1900;
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300 | 80cd3478 | Luiz Capitulino | |
301 | 80cd3478 | Luiz Capitulino | rtc_change_mon_event(tm); |
302 | 43f493af | bellard | } |
303 | 43f493af | bellard | |
304 | 43f493af | bellard | static void rtc_copy_date(RTCState *s) |
305 | 43f493af | bellard | { |
306 | 43f493af | bellard | const struct tm *tm = &s->current_tm; |
307 | 42fc73a1 | aurel32 | int year;
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308 | dff38e7b | bellard | |
309 | abd0c6bd | Paul Brook | s->cmos_data[RTC_SECONDS] = rtc_to_bcd(s, tm->tm_sec); |
310 | abd0c6bd | Paul Brook | s->cmos_data[RTC_MINUTES] = rtc_to_bcd(s, tm->tm_min); |
311 | 43f493af | bellard | if (s->cmos_data[RTC_REG_B] & 0x02) { |
312 | 43f493af | bellard | /* 24 hour format */
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313 | abd0c6bd | Paul Brook | s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, tm->tm_hour); |
314 | 43f493af | bellard | } else {
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315 | 43f493af | bellard | /* 12 hour format */
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316 | abd0c6bd | Paul Brook | s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, tm->tm_hour % 12);
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317 | 43f493af | bellard | if (tm->tm_hour >= 12) |
318 | 43f493af | bellard | s->cmos_data[RTC_HOURS] |= 0x80;
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319 | 43f493af | bellard | } |
320 | abd0c6bd | Paul Brook | s->cmos_data[RTC_DAY_OF_WEEK] = rtc_to_bcd(s, tm->tm_wday + 1);
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321 | abd0c6bd | Paul Brook | s->cmos_data[RTC_DAY_OF_MONTH] = rtc_to_bcd(s, tm->tm_mday); |
322 | abd0c6bd | Paul Brook | s->cmos_data[RTC_MONTH] = rtc_to_bcd(s, tm->tm_mon + 1);
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323 | 42fc73a1 | aurel32 | year = (tm->tm_year - s->base_year) % 100;
|
324 | 42fc73a1 | aurel32 | if (year < 0) |
325 | 42fc73a1 | aurel32 | year += 100;
|
326 | abd0c6bd | Paul Brook | s->cmos_data[RTC_YEAR] = rtc_to_bcd(s, year); |
327 | 43f493af | bellard | } |
328 | 43f493af | bellard | |
329 | 43f493af | bellard | /* month is between 0 and 11. */
|
330 | 43f493af | bellard | static int get_days_in_month(int month, int year) |
331 | 43f493af | bellard | { |
332 | 5fafdf24 | ths | static const int days_tab[12] = { |
333 | 5fafdf24 | ths | 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 |
334 | 43f493af | bellard | }; |
335 | 43f493af | bellard | int d;
|
336 | 43f493af | bellard | if ((unsigned )month >= 12) |
337 | 43f493af | bellard | return 31; |
338 | 43f493af | bellard | d = days_tab[month]; |
339 | 43f493af | bellard | if (month == 1) { |
340 | 43f493af | bellard | if ((year % 4) == 0 && ((year % 100) != 0 || (year % 400) == 0)) |
341 | 43f493af | bellard | d++; |
342 | 43f493af | bellard | } |
343 | 43f493af | bellard | return d;
|
344 | 43f493af | bellard | } |
345 | 43f493af | bellard | |
346 | 43f493af | bellard | /* update 'tm' to the next second */
|
347 | 43f493af | bellard | static void rtc_next_second(struct tm *tm) |
348 | 43f493af | bellard | { |
349 | 43f493af | bellard | int days_in_month;
|
350 | 43f493af | bellard | |
351 | 43f493af | bellard | tm->tm_sec++; |
352 | 43f493af | bellard | if ((unsigned)tm->tm_sec >= 60) { |
353 | 43f493af | bellard | tm->tm_sec = 0;
|
354 | 43f493af | bellard | tm->tm_min++; |
355 | 43f493af | bellard | if ((unsigned)tm->tm_min >= 60) { |
356 | 43f493af | bellard | tm->tm_min = 0;
|
357 | 43f493af | bellard | tm->tm_hour++; |
358 | 43f493af | bellard | if ((unsigned)tm->tm_hour >= 24) { |
359 | 43f493af | bellard | tm->tm_hour = 0;
|
360 | 43f493af | bellard | /* next day */
|
361 | 43f493af | bellard | tm->tm_wday++; |
362 | 43f493af | bellard | if ((unsigned)tm->tm_wday >= 7) |
363 | 43f493af | bellard | tm->tm_wday = 0;
|
364 | 5fafdf24 | ths | days_in_month = get_days_in_month(tm->tm_mon, |
365 | 43f493af | bellard | tm->tm_year + 1900);
|
366 | 43f493af | bellard | tm->tm_mday++; |
367 | 43f493af | bellard | if (tm->tm_mday < 1) { |
368 | 43f493af | bellard | tm->tm_mday = 1;
|
369 | 43f493af | bellard | } else if (tm->tm_mday > days_in_month) { |
370 | 43f493af | bellard | tm->tm_mday = 1;
|
371 | 43f493af | bellard | tm->tm_mon++; |
372 | 43f493af | bellard | if (tm->tm_mon >= 12) { |
373 | 43f493af | bellard | tm->tm_mon = 0;
|
374 | 43f493af | bellard | tm->tm_year++; |
375 | 43f493af | bellard | } |
376 | 43f493af | bellard | } |
377 | 43f493af | bellard | } |
378 | 43f493af | bellard | } |
379 | 43f493af | bellard | } |
380 | dff38e7b | bellard | } |
381 | dff38e7b | bellard | |
382 | 43f493af | bellard | |
383 | dff38e7b | bellard | static void rtc_update_second(void *opaque) |
384 | dff38e7b | bellard | { |
385 | dff38e7b | bellard | RTCState *s = opaque; |
386 | 4721c457 | bellard | int64_t delay; |
387 | dff38e7b | bellard | |
388 | dff38e7b | bellard | /* if the oscillator is not in normal operation, we do not update */
|
389 | dff38e7b | bellard | if ((s->cmos_data[RTC_REG_A] & 0x70) != 0x20) { |
390 | 6ee093c9 | Juan Quintela | s->next_second_time += get_ticks_per_sec(); |
391 | dff38e7b | bellard | qemu_mod_timer(s->second_timer, s->next_second_time); |
392 | dff38e7b | bellard | } else {
|
393 | 43f493af | bellard | rtc_next_second(&s->current_tm); |
394 | 3b46e624 | ths | |
395 | dff38e7b | bellard | if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
|
396 | dff38e7b | bellard | /* update in progress bit */
|
397 | dff38e7b | bellard | s->cmos_data[RTC_REG_A] |= REG_A_UIP; |
398 | dff38e7b | bellard | } |
399 | 4721c457 | bellard | /* should be 244 us = 8 / 32768 seconds, but currently the
|
400 | 4721c457 | bellard | timers do not have the necessary resolution. */
|
401 | 6ee093c9 | Juan Quintela | delay = (get_ticks_per_sec() * 1) / 100; |
402 | 4721c457 | bellard | if (delay < 1) |
403 | 4721c457 | bellard | delay = 1;
|
404 | 5fafdf24 | ths | qemu_mod_timer(s->second_timer2, |
405 | 4721c457 | bellard | s->next_second_time + delay); |
406 | dff38e7b | bellard | } |
407 | dff38e7b | bellard | } |
408 | dff38e7b | bellard | |
409 | dff38e7b | bellard | static void rtc_update_second2(void *opaque) |
410 | dff38e7b | bellard | { |
411 | dff38e7b | bellard | RTCState *s = opaque; |
412 | dff38e7b | bellard | |
413 | dff38e7b | bellard | if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
|
414 | dff38e7b | bellard | rtc_copy_date(s); |
415 | dff38e7b | bellard | } |
416 | dff38e7b | bellard | |
417 | dff38e7b | bellard | /* check alarm */
|
418 | dff38e7b | bellard | if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
|
419 | dff38e7b | bellard | if (((s->cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0 || |
420 | 43f493af | bellard | s->cmos_data[RTC_SECONDS_ALARM] == s->current_tm.tm_sec) && |
421 | dff38e7b | bellard | ((s->cmos_data[RTC_MINUTES_ALARM] & 0xc0) == 0xc0 || |
422 | 43f493af | bellard | s->cmos_data[RTC_MINUTES_ALARM] == s->current_tm.tm_mon) && |
423 | dff38e7b | bellard | ((s->cmos_data[RTC_HOURS_ALARM] & 0xc0) == 0xc0 || |
424 | 43f493af | bellard | s->cmos_data[RTC_HOURS_ALARM] == s->current_tm.tm_hour)) { |
425 | dff38e7b | bellard | |
426 | 5fafdf24 | ths | s->cmos_data[RTC_REG_C] |= 0xa0;
|
427 | 16b29ae1 | aliguori | rtc_irq_raise(s->irq); |
428 | dff38e7b | bellard | } |
429 | dff38e7b | bellard | } |
430 | dff38e7b | bellard | |
431 | dff38e7b | bellard | /* update ended interrupt */
|
432 | 98815437 | Bernhard Kauer | s->cmos_data[RTC_REG_C] |= REG_C_UF; |
433 | dff38e7b | bellard | if (s->cmos_data[RTC_REG_B] & REG_B_UIE) {
|
434 | 98815437 | Bernhard Kauer | s->cmos_data[RTC_REG_C] |= REG_C_IRQF; |
435 | 98815437 | Bernhard Kauer | rtc_irq_raise(s->irq); |
436 | dff38e7b | bellard | } |
437 | dff38e7b | bellard | |
438 | dff38e7b | bellard | /* clear update in progress bit */
|
439 | dff38e7b | bellard | s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; |
440 | dff38e7b | bellard | |
441 | 6ee093c9 | Juan Quintela | s->next_second_time += get_ticks_per_sec(); |
442 | dff38e7b | bellard | qemu_mod_timer(s->second_timer, s->next_second_time); |
443 | 80cabfad | bellard | } |
444 | 80cabfad | bellard | |
445 | b41a2cd1 | bellard | static uint32_t cmos_ioport_read(void *opaque, uint32_t addr) |
446 | 80cabfad | bellard | { |
447 | b41a2cd1 | bellard | RTCState *s = opaque; |
448 | 80cabfad | bellard | int ret;
|
449 | 80cabfad | bellard | if ((addr & 1) == 0) { |
450 | 80cabfad | bellard | return 0xff; |
451 | 80cabfad | bellard | } else {
|
452 | 80cabfad | bellard | switch(s->cmos_index) {
|
453 | 80cabfad | bellard | case RTC_SECONDS:
|
454 | 80cabfad | bellard | case RTC_MINUTES:
|
455 | 80cabfad | bellard | case RTC_HOURS:
|
456 | 80cabfad | bellard | case RTC_DAY_OF_WEEK:
|
457 | 80cabfad | bellard | case RTC_DAY_OF_MONTH:
|
458 | 80cabfad | bellard | case RTC_MONTH:
|
459 | 80cabfad | bellard | case RTC_YEAR:
|
460 | 80cabfad | bellard | ret = s->cmos_data[s->cmos_index]; |
461 | 80cabfad | bellard | break;
|
462 | 80cabfad | bellard | case RTC_REG_A:
|
463 | 80cabfad | bellard | ret = s->cmos_data[s->cmos_index]; |
464 | 80cabfad | bellard | break;
|
465 | 80cabfad | bellard | case RTC_REG_C:
|
466 | 80cabfad | bellard | ret = s->cmos_data[s->cmos_index]; |
467 | d537cf6c | pbrook | qemu_irq_lower(s->irq); |
468 | ba32edab | Gleb Natapov | #ifdef TARGET_I386
|
469 | ba32edab | Gleb Natapov | if(s->irq_coalesced &&
|
470 | ba32edab | Gleb Natapov | s->irq_reinject_on_ack_count < RTC_REINJECT_ON_ACK_COUNT) { |
471 | ba32edab | Gleb Natapov | s->irq_reinject_on_ack_count++; |
472 | ba32edab | Gleb Natapov | apic_reset_irq_delivered(); |
473 | ba32edab | Gleb Natapov | qemu_irq_raise(s->irq); |
474 | ba32edab | Gleb Natapov | if (apic_get_irq_delivered())
|
475 | ba32edab | Gleb Natapov | s->irq_coalesced--; |
476 | ba32edab | Gleb Natapov | break;
|
477 | ba32edab | Gleb Natapov | } |
478 | ba32edab | Gleb Natapov | #endif
|
479 | ba32edab | Gleb Natapov | |
480 | 5fafdf24 | ths | s->cmos_data[RTC_REG_C] = 0x00;
|
481 | 80cabfad | bellard | break;
|
482 | 80cabfad | bellard | default:
|
483 | 80cabfad | bellard | ret = s->cmos_data[s->cmos_index]; |
484 | 80cabfad | bellard | break;
|
485 | 80cabfad | bellard | } |
486 | 80cabfad | bellard | #ifdef DEBUG_CMOS
|
487 | 80cabfad | bellard | printf("cmos: read index=0x%02x val=0x%02x\n",
|
488 | 80cabfad | bellard | s->cmos_index, ret); |
489 | 80cabfad | bellard | #endif
|
490 | 80cabfad | bellard | return ret;
|
491 | 80cabfad | bellard | } |
492 | 80cabfad | bellard | } |
493 | 80cabfad | bellard | |
494 | dff38e7b | bellard | void rtc_set_memory(RTCState *s, int addr, int val) |
495 | dff38e7b | bellard | { |
496 | dff38e7b | bellard | if (addr >= 0 && addr <= 127) |
497 | dff38e7b | bellard | s->cmos_data[addr] = val; |
498 | dff38e7b | bellard | } |
499 | dff38e7b | bellard | |
500 | dff38e7b | bellard | void rtc_set_date(RTCState *s, const struct tm *tm) |
501 | dff38e7b | bellard | { |
502 | 43f493af | bellard | s->current_tm = *tm; |
503 | dff38e7b | bellard | rtc_copy_date(s); |
504 | dff38e7b | bellard | } |
505 | dff38e7b | bellard | |
506 | ea55ffb3 | ths | /* PC cmos mappings */
|
507 | ea55ffb3 | ths | #define REG_IBM_CENTURY_BYTE 0x32 |
508 | ea55ffb3 | ths | #define REG_IBM_PS2_CENTURY_BYTE 0x37 |
509 | ea55ffb3 | ths | |
510 | 9596ebb7 | pbrook | static void rtc_set_date_from_host(RTCState *s) |
511 | ea55ffb3 | ths | { |
512 | f6503059 | balrog | struct tm tm;
|
513 | ea55ffb3 | ths | int val;
|
514 | ea55ffb3 | ths | |
515 | ea55ffb3 | ths | /* set the CMOS date */
|
516 | f6503059 | balrog | qemu_get_timedate(&tm, 0);
|
517 | f6503059 | balrog | rtc_set_date(s, &tm); |
518 | ea55ffb3 | ths | |
519 | abd0c6bd | Paul Brook | val = rtc_to_bcd(s, (tm.tm_year / 100) + 19); |
520 | ea55ffb3 | ths | rtc_set_memory(s, REG_IBM_CENTURY_BYTE, val); |
521 | ea55ffb3 | ths | rtc_set_memory(s, REG_IBM_PS2_CENTURY_BYTE, val); |
522 | ea55ffb3 | ths | } |
523 | ea55ffb3 | ths | |
524 | 6b075b8a | Juan Quintela | static int rtc_post_load(void *opaque, int version_id) |
525 | 80cabfad | bellard | { |
526 | 6b075b8a | Juan Quintela | #ifdef TARGET_I386
|
527 | dff38e7b | bellard | RTCState *s = opaque; |
528 | dff38e7b | bellard | |
529 | 048c74c4 | Juan Quintela | if (version_id >= 2) { |
530 | 048c74c4 | Juan Quintela | if (rtc_td_hack) {
|
531 | 048c74c4 | Juan Quintela | rtc_coalesced_timer_update(s); |
532 | 048c74c4 | Juan Quintela | } |
533 | 048c74c4 | Juan Quintela | } |
534 | 6b075b8a | Juan Quintela | #endif
|
535 | 73822ec8 | aliguori | return 0; |
536 | 73822ec8 | aliguori | } |
537 | 73822ec8 | aliguori | |
538 | 6b075b8a | Juan Quintela | static const VMStateDescription vmstate_rtc = { |
539 | 6b075b8a | Juan Quintela | .name = "mc146818rtc",
|
540 | 6b075b8a | Juan Quintela | .version_id = 2,
|
541 | 6b075b8a | Juan Quintela | .minimum_version_id = 1,
|
542 | 6b075b8a | Juan Quintela | .minimum_version_id_old = 1,
|
543 | 6b075b8a | Juan Quintela | .post_load = rtc_post_load, |
544 | 6b075b8a | Juan Quintela | .fields = (VMStateField []) { |
545 | 6b075b8a | Juan Quintela | VMSTATE_BUFFER(cmos_data, RTCState), |
546 | 6b075b8a | Juan Quintela | VMSTATE_UINT8(cmos_index, RTCState), |
547 | 6b075b8a | Juan Quintela | VMSTATE_INT32(current_tm.tm_sec, RTCState), |
548 | 6b075b8a | Juan Quintela | VMSTATE_INT32(current_tm.tm_min, RTCState), |
549 | 6b075b8a | Juan Quintela | VMSTATE_INT32(current_tm.tm_hour, RTCState), |
550 | 6b075b8a | Juan Quintela | VMSTATE_INT32(current_tm.tm_wday, RTCState), |
551 | 6b075b8a | Juan Quintela | VMSTATE_INT32(current_tm.tm_mday, RTCState), |
552 | 6b075b8a | Juan Quintela | VMSTATE_INT32(current_tm.tm_mon, RTCState), |
553 | 6b075b8a | Juan Quintela | VMSTATE_INT32(current_tm.tm_year, RTCState), |
554 | 6b075b8a | Juan Quintela | VMSTATE_TIMER(periodic_timer, RTCState), |
555 | 6b075b8a | Juan Quintela | VMSTATE_INT64(next_periodic_time, RTCState), |
556 | 6b075b8a | Juan Quintela | VMSTATE_INT64(next_second_time, RTCState), |
557 | 6b075b8a | Juan Quintela | VMSTATE_TIMER(second_timer, RTCState), |
558 | 6b075b8a | Juan Quintela | VMSTATE_TIMER(second_timer2, RTCState), |
559 | 6b075b8a | Juan Quintela | VMSTATE_UINT32_V(irq_coalesced, RTCState, 2),
|
560 | 6b075b8a | Juan Quintela | VMSTATE_UINT32_V(period, RTCState, 2),
|
561 | 6b075b8a | Juan Quintela | VMSTATE_END_OF_LIST() |
562 | 6b075b8a | Juan Quintela | } |
563 | 6b075b8a | Juan Quintela | }; |
564 | 6b075b8a | Juan Quintela | |
565 | eeb7c03c | Gleb Natapov | static void rtc_reset(void *opaque) |
566 | eeb7c03c | Gleb Natapov | { |
567 | eeb7c03c | Gleb Natapov | RTCState *s = opaque; |
568 | eeb7c03c | Gleb Natapov | |
569 | 72716184 | Anthony Liguori | s->cmos_data[RTC_REG_B] &= ~(REG_B_PIE | REG_B_AIE | REG_B_SQWE); |
570 | 72716184 | Anthony Liguori | s->cmos_data[RTC_REG_C] &= ~(REG_C_UF | REG_C_IRQF | REG_C_PF | REG_C_AF); |
571 | eeb7c03c | Gleb Natapov | |
572 | 72716184 | Anthony Liguori | qemu_irq_lower(s->irq); |
573 | eeb7c03c | Gleb Natapov | |
574 | eeb7c03c | Gleb Natapov | #ifdef TARGET_I386
|
575 | eeb7c03c | Gleb Natapov | if (rtc_td_hack)
|
576 | eeb7c03c | Gleb Natapov | s->irq_coalesced = 0;
|
577 | eeb7c03c | Gleb Natapov | #endif
|
578 | eeb7c03c | Gleb Natapov | } |
579 | eeb7c03c | Gleb Natapov | |
580 | 32e0c826 | Gerd Hoffmann | static int rtc_initfn(ISADevice *dev) |
581 | dff38e7b | bellard | { |
582 | 32e0c826 | Gerd Hoffmann | RTCState *s = DO_UPCAST(RTCState, dev, dev); |
583 | 32e0c826 | Gerd Hoffmann | int base = 0x70; |
584 | 32e0c826 | Gerd Hoffmann | int isairq = 8; |
585 | dff38e7b | bellard | |
586 | 32e0c826 | Gerd Hoffmann | isa_init_irq(dev, &s->irq, isairq); |
587 | 80cabfad | bellard | |
588 | 80cabfad | bellard | s->cmos_data[RTC_REG_A] = 0x26;
|
589 | 80cabfad | bellard | s->cmos_data[RTC_REG_B] = 0x02;
|
590 | 80cabfad | bellard | s->cmos_data[RTC_REG_C] = 0x00;
|
591 | 80cabfad | bellard | s->cmos_data[RTC_REG_D] = 0x80;
|
592 | 80cabfad | bellard | |
593 | ea55ffb3 | ths | rtc_set_date_from_host(s); |
594 | ea55ffb3 | ths | |
595 | 6875204c | Jan Kiszka | s->periodic_timer = qemu_new_timer(rtc_clock, rtc_periodic_timer, s); |
596 | 93b66569 | aliguori | #ifdef TARGET_I386
|
597 | 93b66569 | aliguori | if (rtc_td_hack)
|
598 | 6875204c | Jan Kiszka | s->coalesced_timer = |
599 | 6875204c | Jan Kiszka | qemu_new_timer(rtc_clock, rtc_coalesced_timer, s); |
600 | 93b66569 | aliguori | #endif
|
601 | 6875204c | Jan Kiszka | s->second_timer = qemu_new_timer(rtc_clock, rtc_update_second, s); |
602 | 6875204c | Jan Kiszka | s->second_timer2 = qemu_new_timer(rtc_clock, rtc_update_second2, s); |
603 | dff38e7b | bellard | |
604 | 6875204c | Jan Kiszka | s->next_second_time = |
605 | 6875204c | Jan Kiszka | qemu_get_clock(rtc_clock) + (get_ticks_per_sec() * 99) / 100; |
606 | dff38e7b | bellard | qemu_mod_timer(s->second_timer2, s->next_second_time); |
607 | dff38e7b | bellard | |
608 | b41a2cd1 | bellard | register_ioport_write(base, 2, 1, cmos_ioport_write, s); |
609 | b41a2cd1 | bellard | register_ioport_read(base, 2, 1, cmos_ioport_read, s); |
610 | dff38e7b | bellard | |
611 | 6b075b8a | Juan Quintela | vmstate_register(base, &vmstate_rtc, s); |
612 | a08d4367 | Jan Kiszka | qemu_register_reset(rtc_reset, s); |
613 | 32e0c826 | Gerd Hoffmann | return 0; |
614 | 32e0c826 | Gerd Hoffmann | } |
615 | 32e0c826 | Gerd Hoffmann | |
616 | 32e0c826 | Gerd Hoffmann | RTCState *rtc_init(int base_year)
|
617 | 32e0c826 | Gerd Hoffmann | { |
618 | 32e0c826 | Gerd Hoffmann | ISADevice *dev; |
619 | eeb7c03c | Gleb Natapov | |
620 | 32e0c826 | Gerd Hoffmann | dev = isa_create("mc146818rtc");
|
621 | 32e0c826 | Gerd Hoffmann | qdev_prop_set_int32(&dev->qdev, "base_year", base_year);
|
622 | e23a1b33 | Markus Armbruster | qdev_init_nofail(&dev->qdev); |
623 | 32e0c826 | Gerd Hoffmann | return DO_UPCAST(RTCState, dev, dev);
|
624 | 80cabfad | bellard | } |
625 | 80cabfad | bellard | |
626 | 32e0c826 | Gerd Hoffmann | static ISADeviceInfo mc146818rtc_info = {
|
627 | 32e0c826 | Gerd Hoffmann | .qdev.name = "mc146818rtc",
|
628 | 32e0c826 | Gerd Hoffmann | .qdev.size = sizeof(RTCState),
|
629 | 32e0c826 | Gerd Hoffmann | .qdev.no_user = 1,
|
630 | 32e0c826 | Gerd Hoffmann | .init = rtc_initfn, |
631 | 32e0c826 | Gerd Hoffmann | .qdev.props = (Property[]) { |
632 | 32e0c826 | Gerd Hoffmann | DEFINE_PROP_INT32("base_year", RTCState, base_year, 1980), |
633 | 32e0c826 | Gerd Hoffmann | DEFINE_PROP_END_OF_LIST(), |
634 | 32e0c826 | Gerd Hoffmann | } |
635 | 32e0c826 | Gerd Hoffmann | }; |
636 | 32e0c826 | Gerd Hoffmann | |
637 | 32e0c826 | Gerd Hoffmann | static void mc146818rtc_register(void) |
638 | 100d9891 | aurel32 | { |
639 | 32e0c826 | Gerd Hoffmann | isa_qdev_register(&mc146818rtc_info); |
640 | 100d9891 | aurel32 | } |
641 | 32e0c826 | Gerd Hoffmann | device_init(mc146818rtc_register) |