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1 | a541f297 | bellard | /*
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2 | 819385c5 | bellard | * QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms
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3 | 5fafdf24 | ths | *
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4 | 3ccacc4a | blueswir1 | * Copyright (c) 2003-2005, 2007 Jocelyn Mayer
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5 | 5fafdf24 | ths | *
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6 | a541f297 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | a541f297 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | a541f297 | bellard | * in the Software without restriction, including without limitation the rights
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9 | a541f297 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | a541f297 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | a541f297 | bellard | * furnished to do so, subject to the following conditions:
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12 | a541f297 | bellard | *
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13 | a541f297 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | a541f297 | bellard | * all copies or substantial portions of the Software.
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15 | a541f297 | bellard | *
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16 | a541f297 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | a541f297 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | a541f297 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | a541f297 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | a541f297 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | a541f297 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | a541f297 | bellard | * THE SOFTWARE.
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23 | a541f297 | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "nvram.h" |
26 | 87ecb68b | pbrook | #include "isa.h" |
27 | 87ecb68b | pbrook | #include "qemu-timer.h" |
28 | 87ecb68b | pbrook | #include "sysemu.h" |
29 | a541f297 | bellard | |
30 | 13ab5daa | bellard | //#define DEBUG_NVRAM
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31 | a541f297 | bellard | |
32 | 13ab5daa | bellard | #if defined(DEBUG_NVRAM)
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33 | a541f297 | bellard | #define NVRAM_PRINTF(fmt, args...) do { printf(fmt , ##args); } while (0) |
34 | a541f297 | bellard | #else
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35 | a541f297 | bellard | #define NVRAM_PRINTF(fmt, args...) do { } while (0) |
36 | a541f297 | bellard | #endif
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37 | a541f297 | bellard | |
38 | 819385c5 | bellard | /*
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39 | 4aed2c33 | blueswir1 | * The M48T02, M48T08 and M48T59 chips are very similar. The newer '59 has
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40 | 819385c5 | bellard | * alarm and a watchdog timer and related control registers. In the
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41 | 819385c5 | bellard | * PPC platform there is also a nvram lock function.
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42 | 819385c5 | bellard | */
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43 | c5df018e | bellard | struct m48t59_t {
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44 | 819385c5 | bellard | /* Model parameters */
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45 | 4aed2c33 | blueswir1 | int type; // 2 = m48t02, 8 = m48t08, 59 = m48t59 |
46 | a541f297 | bellard | /* Hardware parameters */
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47 | d537cf6c | pbrook | qemu_irq IRQ; |
48 | e1bb04f7 | bellard | int mem_index;
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49 | 5dcb6b91 | blueswir1 | target_phys_addr_t mem_base; |
50 | a541f297 | bellard | uint32_t io_base; |
51 | a541f297 | bellard | uint16_t size; |
52 | a541f297 | bellard | /* RTC management */
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53 | a541f297 | bellard | time_t time_offset; |
54 | a541f297 | bellard | time_t stop_time; |
55 | a541f297 | bellard | /* Alarm & watchdog */
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56 | a541f297 | bellard | time_t alarm; |
57 | a541f297 | bellard | struct QEMUTimer *alrm_timer;
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58 | a541f297 | bellard | struct QEMUTimer *wd_timer;
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59 | a541f297 | bellard | /* NVRAM storage */
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60 | 13ab5daa | bellard | uint8_t lock; |
61 | a541f297 | bellard | uint16_t addr; |
62 | a541f297 | bellard | uint8_t *buffer; |
63 | c5df018e | bellard | }; |
64 | a541f297 | bellard | |
65 | a541f297 | bellard | /* Fake timer functions */
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66 | a541f297 | bellard | /* Generic helpers for BCD */
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67 | a541f297 | bellard | static inline uint8_t toBCD (uint8_t value) |
68 | a541f297 | bellard | { |
69 | a541f297 | bellard | return (((value / 10) % 10) << 4) | (value % 10); |
70 | a541f297 | bellard | } |
71 | a541f297 | bellard | |
72 | a541f297 | bellard | static inline uint8_t fromBCD (uint8_t BCD) |
73 | a541f297 | bellard | { |
74 | a541f297 | bellard | return ((BCD >> 4) * 10) + (BCD & 0x0F); |
75 | a541f297 | bellard | } |
76 | a541f297 | bellard | |
77 | a541f297 | bellard | /* RTC management helpers */
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78 | a541f297 | bellard | static void get_time (m48t59_t *NVRAM, struct tm *tm) |
79 | a541f297 | bellard | { |
80 | a541f297 | bellard | time_t t; |
81 | a541f297 | bellard | |
82 | a541f297 | bellard | t = time(NULL) + NVRAM->time_offset;
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83 | d157e205 | bellard | #ifdef _WIN32
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84 | d157e205 | bellard | memcpy(tm,localtime(&t),sizeof(*tm));
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85 | d157e205 | bellard | #else
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86 | 36cbaae5 | blueswir1 | if (rtc_utc)
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87 | 36cbaae5 | blueswir1 | gmtime_r (&t, tm); |
88 | 36cbaae5 | blueswir1 | else
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89 | 36cbaae5 | blueswir1 | localtime_r (&t, tm) ; |
90 | d157e205 | bellard | #endif
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91 | a541f297 | bellard | } |
92 | a541f297 | bellard | |
93 | a541f297 | bellard | static void set_time (m48t59_t *NVRAM, struct tm *tm) |
94 | a541f297 | bellard | { |
95 | a541f297 | bellard | time_t now, new_time; |
96 | 3b46e624 | ths | |
97 | a541f297 | bellard | new_time = mktime(tm); |
98 | a541f297 | bellard | now = time(NULL);
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99 | a541f297 | bellard | NVRAM->time_offset = new_time - now; |
100 | a541f297 | bellard | } |
101 | a541f297 | bellard | |
102 | a541f297 | bellard | /* Alarm management */
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103 | a541f297 | bellard | static void alarm_cb (void *opaque) |
104 | a541f297 | bellard | { |
105 | a541f297 | bellard | struct tm tm, tm_now;
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106 | a541f297 | bellard | uint64_t next_time; |
107 | a541f297 | bellard | m48t59_t *NVRAM = opaque; |
108 | a541f297 | bellard | |
109 | d537cf6c | pbrook | qemu_set_irq(NVRAM->IRQ, 1);
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110 | 5fafdf24 | ths | if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 && |
111 | a541f297 | bellard | (NVRAM->buffer[0x1FF4] & 0x80) == 0 && |
112 | a541f297 | bellard | (NVRAM->buffer[0x1FF3] & 0x80) == 0 && |
113 | a541f297 | bellard | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
114 | a541f297 | bellard | /* Repeat once a month */
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115 | a541f297 | bellard | get_time(NVRAM, &tm_now); |
116 | a541f297 | bellard | memcpy(&tm, &tm_now, sizeof(struct tm)); |
117 | a541f297 | bellard | tm.tm_mon++; |
118 | a541f297 | bellard | if (tm.tm_mon == 13) { |
119 | a541f297 | bellard | tm.tm_mon = 1;
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120 | a541f297 | bellard | tm.tm_year++; |
121 | a541f297 | bellard | } |
122 | a541f297 | bellard | next_time = mktime(&tm); |
123 | a541f297 | bellard | } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
124 | a541f297 | bellard | (NVRAM->buffer[0x1FF4] & 0x80) == 0 && |
125 | a541f297 | bellard | (NVRAM->buffer[0x1FF3] & 0x80) == 0 && |
126 | a541f297 | bellard | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
127 | a541f297 | bellard | /* Repeat once a day */
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128 | a541f297 | bellard | next_time = 24 * 60 * 60 + mktime(&tm_now); |
129 | a541f297 | bellard | } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
130 | a541f297 | bellard | (NVRAM->buffer[0x1FF4] & 0x80) != 0 && |
131 | a541f297 | bellard | (NVRAM->buffer[0x1FF3] & 0x80) == 0 && |
132 | a541f297 | bellard | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
133 | a541f297 | bellard | /* Repeat once an hour */
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134 | a541f297 | bellard | next_time = 60 * 60 + mktime(&tm_now); |
135 | a541f297 | bellard | } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
136 | a541f297 | bellard | (NVRAM->buffer[0x1FF4] & 0x80) != 0 && |
137 | a541f297 | bellard | (NVRAM->buffer[0x1FF3] & 0x80) != 0 && |
138 | a541f297 | bellard | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
139 | a541f297 | bellard | /* Repeat once a minute */
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140 | a541f297 | bellard | next_time = 60 + mktime(&tm_now);
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141 | a541f297 | bellard | } else {
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142 | a541f297 | bellard | /* Repeat once a second */
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143 | a541f297 | bellard | next_time = 1 + mktime(&tm_now);
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144 | a541f297 | bellard | } |
145 | a541f297 | bellard | qemu_mod_timer(NVRAM->alrm_timer, next_time * 1000);
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146 | d537cf6c | pbrook | qemu_set_irq(NVRAM->IRQ, 0);
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147 | a541f297 | bellard | } |
148 | a541f297 | bellard | |
149 | a541f297 | bellard | |
150 | a541f297 | bellard | static void get_alarm (m48t59_t *NVRAM, struct tm *tm) |
151 | a541f297 | bellard | { |
152 | d157e205 | bellard | #ifdef _WIN32
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153 | d157e205 | bellard | memcpy(tm,localtime(&NVRAM->alarm),sizeof(*tm));
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154 | d157e205 | bellard | #else
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155 | 36cbaae5 | blueswir1 | if (rtc_utc)
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156 | 36cbaae5 | blueswir1 | gmtime_r (&NVRAM->alarm, tm); |
157 | 36cbaae5 | blueswir1 | else
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158 | 36cbaae5 | blueswir1 | localtime_r (&NVRAM->alarm, tm); |
159 | d157e205 | bellard | #endif
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160 | a541f297 | bellard | } |
161 | a541f297 | bellard | |
162 | a541f297 | bellard | static void set_alarm (m48t59_t *NVRAM, struct tm *tm) |
163 | a541f297 | bellard | { |
164 | a541f297 | bellard | NVRAM->alarm = mktime(tm); |
165 | a541f297 | bellard | if (NVRAM->alrm_timer != NULL) { |
166 | a541f297 | bellard | qemu_del_timer(NVRAM->alrm_timer); |
167 | 868d585a | j_mayer | if (NVRAM->alarm - time(NULL) > 0) |
168 | 868d585a | j_mayer | qemu_mod_timer(NVRAM->alrm_timer, NVRAM->alarm * 1000);
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169 | a541f297 | bellard | } |
170 | a541f297 | bellard | } |
171 | a541f297 | bellard | |
172 | a541f297 | bellard | /* Watchdog management */
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173 | a541f297 | bellard | static void watchdog_cb (void *opaque) |
174 | a541f297 | bellard | { |
175 | a541f297 | bellard | m48t59_t *NVRAM = opaque; |
176 | a541f297 | bellard | |
177 | a541f297 | bellard | NVRAM->buffer[0x1FF0] |= 0x80; |
178 | a541f297 | bellard | if (NVRAM->buffer[0x1FF7] & 0x80) { |
179 | a541f297 | bellard | NVRAM->buffer[0x1FF7] = 0x00; |
180 | a541f297 | bellard | NVRAM->buffer[0x1FFC] &= ~0x40; |
181 | 13ab5daa | bellard | /* May it be a hw CPU Reset instead ? */
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182 | d7d02e3c | bellard | qemu_system_reset_request(); |
183 | a541f297 | bellard | } else {
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184 | d537cf6c | pbrook | qemu_set_irq(NVRAM->IRQ, 1);
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185 | d537cf6c | pbrook | qemu_set_irq(NVRAM->IRQ, 0);
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186 | a541f297 | bellard | } |
187 | a541f297 | bellard | } |
188 | a541f297 | bellard | |
189 | a541f297 | bellard | static void set_up_watchdog (m48t59_t *NVRAM, uint8_t value) |
190 | a541f297 | bellard | { |
191 | a541f297 | bellard | uint64_t interval; /* in 1/16 seconds */
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192 | a541f297 | bellard | |
193 | 868d585a | j_mayer | NVRAM->buffer[0x1FF0] &= ~0x80; |
194 | a541f297 | bellard | if (NVRAM->wd_timer != NULL) { |
195 | a541f297 | bellard | qemu_del_timer(NVRAM->wd_timer); |
196 | 868d585a | j_mayer | if (value != 0) { |
197 | 868d585a | j_mayer | interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F); |
198 | 868d585a | j_mayer | qemu_mod_timer(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) + |
199 | 868d585a | j_mayer | ((interval * 1000) >> 4)); |
200 | 868d585a | j_mayer | } |
201 | a541f297 | bellard | } |
202 | a541f297 | bellard | } |
203 | a541f297 | bellard | |
204 | a541f297 | bellard | /* Direct access to NVRAM */
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205 | 897b4c6c | j_mayer | void m48t59_write (void *opaque, uint32_t addr, uint32_t val) |
206 | a541f297 | bellard | { |
207 | 897b4c6c | j_mayer | m48t59_t *NVRAM = opaque; |
208 | a541f297 | bellard | struct tm tm;
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209 | a541f297 | bellard | int tmp;
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210 | a541f297 | bellard | |
211 | 819385c5 | bellard | if (addr > 0x1FF8 && addr < 0x2000) |
212 | 819385c5 | bellard | NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
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213 | 4aed2c33 | blueswir1 | |
214 | 4aed2c33 | blueswir1 | /* check for NVRAM access */
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215 | 4aed2c33 | blueswir1 | if ((NVRAM->type == 2 && addr < 0x7f8) || |
216 | 4aed2c33 | blueswir1 | (NVRAM->type == 8 && addr < 0x1ff8) || |
217 | 4aed2c33 | blueswir1 | (NVRAM->type == 59 && addr < 0x1ff0)) |
218 | 819385c5 | bellard | goto do_write;
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219 | 4aed2c33 | blueswir1 | |
220 | 4aed2c33 | blueswir1 | /* TOD access */
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221 | 819385c5 | bellard | switch (addr) {
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222 | a541f297 | bellard | case 0x1FF0: |
223 | a541f297 | bellard | /* flags register : read-only */
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224 | a541f297 | bellard | break;
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225 | a541f297 | bellard | case 0x1FF1: |
226 | a541f297 | bellard | /* unused */
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227 | a541f297 | bellard | break;
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228 | a541f297 | bellard | case 0x1FF2: |
229 | a541f297 | bellard | /* alarm seconds */
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230 | 819385c5 | bellard | tmp = fromBCD(val & 0x7F);
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231 | 819385c5 | bellard | if (tmp >= 0 && tmp <= 59) { |
232 | 819385c5 | bellard | get_alarm(NVRAM, &tm); |
233 | 819385c5 | bellard | tm.tm_sec = tmp; |
234 | 819385c5 | bellard | NVRAM->buffer[0x1FF2] = val;
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235 | 819385c5 | bellard | set_alarm(NVRAM, &tm); |
236 | 819385c5 | bellard | } |
237 | a541f297 | bellard | break;
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238 | a541f297 | bellard | case 0x1FF3: |
239 | a541f297 | bellard | /* alarm minutes */
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240 | 819385c5 | bellard | tmp = fromBCD(val & 0x7F);
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241 | 819385c5 | bellard | if (tmp >= 0 && tmp <= 59) { |
242 | 819385c5 | bellard | get_alarm(NVRAM, &tm); |
243 | 819385c5 | bellard | tm.tm_min = tmp; |
244 | 819385c5 | bellard | NVRAM->buffer[0x1FF3] = val;
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245 | 819385c5 | bellard | set_alarm(NVRAM, &tm); |
246 | 819385c5 | bellard | } |
247 | a541f297 | bellard | break;
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248 | a541f297 | bellard | case 0x1FF4: |
249 | a541f297 | bellard | /* alarm hours */
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250 | 819385c5 | bellard | tmp = fromBCD(val & 0x3F);
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251 | 819385c5 | bellard | if (tmp >= 0 && tmp <= 23) { |
252 | 819385c5 | bellard | get_alarm(NVRAM, &tm); |
253 | 819385c5 | bellard | tm.tm_hour = tmp; |
254 | 819385c5 | bellard | NVRAM->buffer[0x1FF4] = val;
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255 | 819385c5 | bellard | set_alarm(NVRAM, &tm); |
256 | 819385c5 | bellard | } |
257 | a541f297 | bellard | break;
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258 | a541f297 | bellard | case 0x1FF5: |
259 | a541f297 | bellard | /* alarm date */
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260 | 819385c5 | bellard | tmp = fromBCD(val & 0x1F);
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261 | 819385c5 | bellard | if (tmp != 0) { |
262 | 819385c5 | bellard | get_alarm(NVRAM, &tm); |
263 | 819385c5 | bellard | tm.tm_mday = tmp; |
264 | 819385c5 | bellard | NVRAM->buffer[0x1FF5] = val;
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265 | 819385c5 | bellard | set_alarm(NVRAM, &tm); |
266 | 819385c5 | bellard | } |
267 | a541f297 | bellard | break;
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268 | a541f297 | bellard | case 0x1FF6: |
269 | a541f297 | bellard | /* interrupts */
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270 | 819385c5 | bellard | NVRAM->buffer[0x1FF6] = val;
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271 | a541f297 | bellard | break;
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272 | a541f297 | bellard | case 0x1FF7: |
273 | a541f297 | bellard | /* watchdog */
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274 | 819385c5 | bellard | NVRAM->buffer[0x1FF7] = val;
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275 | 819385c5 | bellard | set_up_watchdog(NVRAM, val); |
276 | a541f297 | bellard | break;
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277 | a541f297 | bellard | case 0x1FF8: |
278 | 4aed2c33 | blueswir1 | case 0x07F8: |
279 | a541f297 | bellard | /* control */
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280 | 4aed2c33 | blueswir1 | NVRAM->buffer[addr] = (val & ~0xA0) | 0x90; |
281 | a541f297 | bellard | break;
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282 | a541f297 | bellard | case 0x1FF9: |
283 | 4aed2c33 | blueswir1 | case 0x07F9: |
284 | a541f297 | bellard | /* seconds (BCD) */
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285 | a541f297 | bellard | tmp = fromBCD(val & 0x7F);
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286 | a541f297 | bellard | if (tmp >= 0 && tmp <= 59) { |
287 | a541f297 | bellard | get_time(NVRAM, &tm); |
288 | a541f297 | bellard | tm.tm_sec = tmp; |
289 | a541f297 | bellard | set_time(NVRAM, &tm); |
290 | a541f297 | bellard | } |
291 | 4aed2c33 | blueswir1 | if ((val & 0x80) ^ (NVRAM->buffer[addr] & 0x80)) { |
292 | a541f297 | bellard | if (val & 0x80) { |
293 | a541f297 | bellard | NVRAM->stop_time = time(NULL);
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294 | a541f297 | bellard | } else {
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295 | a541f297 | bellard | NVRAM->time_offset += NVRAM->stop_time - time(NULL);
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296 | a541f297 | bellard | NVRAM->stop_time = 0;
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297 | a541f297 | bellard | } |
298 | a541f297 | bellard | } |
299 | 4aed2c33 | blueswir1 | NVRAM->buffer[addr] = val & 0x80;
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300 | a541f297 | bellard | break;
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301 | a541f297 | bellard | case 0x1FFA: |
302 | 4aed2c33 | blueswir1 | case 0x07FA: |
303 | a541f297 | bellard | /* minutes (BCD) */
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304 | a541f297 | bellard | tmp = fromBCD(val & 0x7F);
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305 | a541f297 | bellard | if (tmp >= 0 && tmp <= 59) { |
306 | a541f297 | bellard | get_time(NVRAM, &tm); |
307 | a541f297 | bellard | tm.tm_min = tmp; |
308 | a541f297 | bellard | set_time(NVRAM, &tm); |
309 | a541f297 | bellard | } |
310 | a541f297 | bellard | break;
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311 | a541f297 | bellard | case 0x1FFB: |
312 | 4aed2c33 | blueswir1 | case 0x07FB: |
313 | a541f297 | bellard | /* hours (BCD) */
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314 | a541f297 | bellard | tmp = fromBCD(val & 0x3F);
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315 | a541f297 | bellard | if (tmp >= 0 && tmp <= 23) { |
316 | a541f297 | bellard | get_time(NVRAM, &tm); |
317 | a541f297 | bellard | tm.tm_hour = tmp; |
318 | a541f297 | bellard | set_time(NVRAM, &tm); |
319 | a541f297 | bellard | } |
320 | a541f297 | bellard | break;
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321 | a541f297 | bellard | case 0x1FFC: |
322 | 4aed2c33 | blueswir1 | case 0x07FC: |
323 | a541f297 | bellard | /* day of the week / century */
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324 | a541f297 | bellard | tmp = fromBCD(val & 0x07);
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325 | a541f297 | bellard | get_time(NVRAM, &tm); |
326 | a541f297 | bellard | tm.tm_wday = tmp; |
327 | a541f297 | bellard | set_time(NVRAM, &tm); |
328 | 4aed2c33 | blueswir1 | NVRAM->buffer[addr] = val & 0x40;
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329 | a541f297 | bellard | break;
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330 | a541f297 | bellard | case 0x1FFD: |
331 | 4aed2c33 | blueswir1 | case 0x07FD: |
332 | a541f297 | bellard | /* date */
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333 | a541f297 | bellard | tmp = fromBCD(val & 0x1F);
|
334 | a541f297 | bellard | if (tmp != 0) { |
335 | a541f297 | bellard | get_time(NVRAM, &tm); |
336 | a541f297 | bellard | tm.tm_mday = tmp; |
337 | a541f297 | bellard | set_time(NVRAM, &tm); |
338 | a541f297 | bellard | } |
339 | a541f297 | bellard | break;
|
340 | a541f297 | bellard | case 0x1FFE: |
341 | 4aed2c33 | blueswir1 | case 0x07FE: |
342 | a541f297 | bellard | /* month */
|
343 | a541f297 | bellard | tmp = fromBCD(val & 0x1F);
|
344 | a541f297 | bellard | if (tmp >= 1 && tmp <= 12) { |
345 | a541f297 | bellard | get_time(NVRAM, &tm); |
346 | a541f297 | bellard | tm.tm_mon = tmp - 1;
|
347 | a541f297 | bellard | set_time(NVRAM, &tm); |
348 | a541f297 | bellard | } |
349 | a541f297 | bellard | break;
|
350 | a541f297 | bellard | case 0x1FFF: |
351 | 4aed2c33 | blueswir1 | case 0x07FF: |
352 | a541f297 | bellard | /* year */
|
353 | a541f297 | bellard | tmp = fromBCD(val); |
354 | a541f297 | bellard | if (tmp >= 0 && tmp <= 99) { |
355 | a541f297 | bellard | get_time(NVRAM, &tm); |
356 | 180b700d | bellard | if (NVRAM->type == 8) |
357 | 180b700d | bellard | tm.tm_year = fromBCD(val) + 68; // Base year is 1968 |
358 | 180b700d | bellard | else
|
359 | 180b700d | bellard | tm.tm_year = fromBCD(val); |
360 | a541f297 | bellard | set_time(NVRAM, &tm); |
361 | a541f297 | bellard | } |
362 | a541f297 | bellard | break;
|
363 | a541f297 | bellard | default:
|
364 | 13ab5daa | bellard | /* Check lock registers state */
|
365 | 819385c5 | bellard | if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1)) |
366 | 13ab5daa | bellard | break;
|
367 | 819385c5 | bellard | if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2)) |
368 | 13ab5daa | bellard | break;
|
369 | 819385c5 | bellard | do_write:
|
370 | 819385c5 | bellard | if (addr < NVRAM->size) {
|
371 | 819385c5 | bellard | NVRAM->buffer[addr] = val & 0xFF;
|
372 | a541f297 | bellard | } |
373 | a541f297 | bellard | break;
|
374 | a541f297 | bellard | } |
375 | a541f297 | bellard | } |
376 | a541f297 | bellard | |
377 | 897b4c6c | j_mayer | uint32_t m48t59_read (void *opaque, uint32_t addr)
|
378 | a541f297 | bellard | { |
379 | 897b4c6c | j_mayer | m48t59_t *NVRAM = opaque; |
380 | a541f297 | bellard | struct tm tm;
|
381 | a541f297 | bellard | uint32_t retval = 0xFF;
|
382 | a541f297 | bellard | |
383 | 4aed2c33 | blueswir1 | /* check for NVRAM access */
|
384 | 4aed2c33 | blueswir1 | if ((NVRAM->type == 2 && addr < 0x078f) || |
385 | 4aed2c33 | blueswir1 | (NVRAM->type == 8 && addr < 0x1ff8) || |
386 | 4aed2c33 | blueswir1 | (NVRAM->type == 59 && addr < 0x1ff0)) |
387 | 819385c5 | bellard | goto do_read;
|
388 | 4aed2c33 | blueswir1 | |
389 | 4aed2c33 | blueswir1 | /* TOD access */
|
390 | 819385c5 | bellard | switch (addr) {
|
391 | a541f297 | bellard | case 0x1FF0: |
392 | a541f297 | bellard | /* flags register */
|
393 | a541f297 | bellard | goto do_read;
|
394 | a541f297 | bellard | case 0x1FF1: |
395 | a541f297 | bellard | /* unused */
|
396 | a541f297 | bellard | retval = 0;
|
397 | a541f297 | bellard | break;
|
398 | a541f297 | bellard | case 0x1FF2: |
399 | a541f297 | bellard | /* alarm seconds */
|
400 | a541f297 | bellard | goto do_read;
|
401 | a541f297 | bellard | case 0x1FF3: |
402 | a541f297 | bellard | /* alarm minutes */
|
403 | a541f297 | bellard | goto do_read;
|
404 | a541f297 | bellard | case 0x1FF4: |
405 | a541f297 | bellard | /* alarm hours */
|
406 | a541f297 | bellard | goto do_read;
|
407 | a541f297 | bellard | case 0x1FF5: |
408 | a541f297 | bellard | /* alarm date */
|
409 | a541f297 | bellard | goto do_read;
|
410 | a541f297 | bellard | case 0x1FF6: |
411 | a541f297 | bellard | /* interrupts */
|
412 | a541f297 | bellard | goto do_read;
|
413 | a541f297 | bellard | case 0x1FF7: |
414 | a541f297 | bellard | /* A read resets the watchdog */
|
415 | a541f297 | bellard | set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]);
|
416 | a541f297 | bellard | goto do_read;
|
417 | a541f297 | bellard | case 0x1FF8: |
418 | 4aed2c33 | blueswir1 | case 0x07F8: |
419 | a541f297 | bellard | /* control */
|
420 | a541f297 | bellard | goto do_read;
|
421 | a541f297 | bellard | case 0x1FF9: |
422 | 4aed2c33 | blueswir1 | case 0x07F9: |
423 | a541f297 | bellard | /* seconds (BCD) */
|
424 | a541f297 | bellard | get_time(NVRAM, &tm); |
425 | 4aed2c33 | blueswir1 | retval = (NVRAM->buffer[addr] & 0x80) | toBCD(tm.tm_sec);
|
426 | a541f297 | bellard | break;
|
427 | a541f297 | bellard | case 0x1FFA: |
428 | 4aed2c33 | blueswir1 | case 0x07FA: |
429 | a541f297 | bellard | /* minutes (BCD) */
|
430 | a541f297 | bellard | get_time(NVRAM, &tm); |
431 | a541f297 | bellard | retval = toBCD(tm.tm_min); |
432 | a541f297 | bellard | break;
|
433 | a541f297 | bellard | case 0x1FFB: |
434 | 4aed2c33 | blueswir1 | case 0x07FB: |
435 | a541f297 | bellard | /* hours (BCD) */
|
436 | a541f297 | bellard | get_time(NVRAM, &tm); |
437 | a541f297 | bellard | retval = toBCD(tm.tm_hour); |
438 | a541f297 | bellard | break;
|
439 | a541f297 | bellard | case 0x1FFC: |
440 | 4aed2c33 | blueswir1 | case 0x07FC: |
441 | a541f297 | bellard | /* day of the week / century */
|
442 | a541f297 | bellard | get_time(NVRAM, &tm); |
443 | 4aed2c33 | blueswir1 | retval = NVRAM->buffer[addr] | tm.tm_wday; |
444 | a541f297 | bellard | break;
|
445 | a541f297 | bellard | case 0x1FFD: |
446 | 4aed2c33 | blueswir1 | case 0x07FD: |
447 | a541f297 | bellard | /* date */
|
448 | a541f297 | bellard | get_time(NVRAM, &tm); |
449 | a541f297 | bellard | retval = toBCD(tm.tm_mday); |
450 | a541f297 | bellard | break;
|
451 | a541f297 | bellard | case 0x1FFE: |
452 | 4aed2c33 | blueswir1 | case 0x07FE: |
453 | a541f297 | bellard | /* month */
|
454 | a541f297 | bellard | get_time(NVRAM, &tm); |
455 | a541f297 | bellard | retval = toBCD(tm.tm_mon + 1);
|
456 | a541f297 | bellard | break;
|
457 | a541f297 | bellard | case 0x1FFF: |
458 | 4aed2c33 | blueswir1 | case 0x07FF: |
459 | a541f297 | bellard | /* year */
|
460 | a541f297 | bellard | get_time(NVRAM, &tm); |
461 | 5fafdf24 | ths | if (NVRAM->type == 8) |
462 | 180b700d | bellard | retval = toBCD(tm.tm_year - 68); // Base year is 1968 |
463 | 180b700d | bellard | else
|
464 | 180b700d | bellard | retval = toBCD(tm.tm_year); |
465 | a541f297 | bellard | break;
|
466 | a541f297 | bellard | default:
|
467 | 13ab5daa | bellard | /* Check lock registers state */
|
468 | 819385c5 | bellard | if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1)) |
469 | 13ab5daa | bellard | break;
|
470 | 819385c5 | bellard | if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2)) |
471 | 13ab5daa | bellard | break;
|
472 | 819385c5 | bellard | do_read:
|
473 | 819385c5 | bellard | if (addr < NVRAM->size) {
|
474 | 819385c5 | bellard | retval = NVRAM->buffer[addr]; |
475 | a541f297 | bellard | } |
476 | a541f297 | bellard | break;
|
477 | a541f297 | bellard | } |
478 | 819385c5 | bellard | if (addr > 0x1FF9 && addr < 0x2000) |
479 | 9ed1e667 | blueswir1 | NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
|
480 | a541f297 | bellard | |
481 | a541f297 | bellard | return retval;
|
482 | a541f297 | bellard | } |
483 | a541f297 | bellard | |
484 | 897b4c6c | j_mayer | void m48t59_set_addr (void *opaque, uint32_t addr) |
485 | a541f297 | bellard | { |
486 | 897b4c6c | j_mayer | m48t59_t *NVRAM = opaque; |
487 | 897b4c6c | j_mayer | |
488 | a541f297 | bellard | NVRAM->addr = addr; |
489 | a541f297 | bellard | } |
490 | a541f297 | bellard | |
491 | 897b4c6c | j_mayer | void m48t59_toggle_lock (void *opaque, int lock) |
492 | 13ab5daa | bellard | { |
493 | 897b4c6c | j_mayer | m48t59_t *NVRAM = opaque; |
494 | 897b4c6c | j_mayer | |
495 | 13ab5daa | bellard | NVRAM->lock ^= 1 << lock;
|
496 | 13ab5daa | bellard | } |
497 | 13ab5daa | bellard | |
498 | a541f297 | bellard | /* IO access to NVRAM */
|
499 | a541f297 | bellard | static void NVRAM_writeb (void *opaque, uint32_t addr, uint32_t val) |
500 | a541f297 | bellard | { |
501 | a541f297 | bellard | m48t59_t *NVRAM = opaque; |
502 | a541f297 | bellard | |
503 | a541f297 | bellard | addr -= NVRAM->io_base; |
504 | 9ed1e667 | blueswir1 | NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
|
505 | a541f297 | bellard | switch (addr) {
|
506 | a541f297 | bellard | case 0: |
507 | a541f297 | bellard | NVRAM->addr &= ~0x00FF;
|
508 | a541f297 | bellard | NVRAM->addr |= val; |
509 | a541f297 | bellard | break;
|
510 | a541f297 | bellard | case 1: |
511 | a541f297 | bellard | NVRAM->addr &= ~0xFF00;
|
512 | a541f297 | bellard | NVRAM->addr |= val << 8;
|
513 | a541f297 | bellard | break;
|
514 | a541f297 | bellard | case 3: |
515 | 819385c5 | bellard | m48t59_write(NVRAM, val, NVRAM->addr); |
516 | a541f297 | bellard | NVRAM->addr = 0x0000;
|
517 | a541f297 | bellard | break;
|
518 | a541f297 | bellard | default:
|
519 | a541f297 | bellard | break;
|
520 | a541f297 | bellard | } |
521 | a541f297 | bellard | } |
522 | a541f297 | bellard | |
523 | a541f297 | bellard | static uint32_t NVRAM_readb (void *opaque, uint32_t addr) |
524 | a541f297 | bellard | { |
525 | a541f297 | bellard | m48t59_t *NVRAM = opaque; |
526 | 13ab5daa | bellard | uint32_t retval; |
527 | a541f297 | bellard | |
528 | 13ab5daa | bellard | addr -= NVRAM->io_base; |
529 | 13ab5daa | bellard | switch (addr) {
|
530 | 13ab5daa | bellard | case 3: |
531 | 819385c5 | bellard | retval = m48t59_read(NVRAM, NVRAM->addr); |
532 | 13ab5daa | bellard | break;
|
533 | 13ab5daa | bellard | default:
|
534 | 13ab5daa | bellard | retval = -1;
|
535 | 13ab5daa | bellard | break;
|
536 | 13ab5daa | bellard | } |
537 | 9ed1e667 | blueswir1 | NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
|
538 | a541f297 | bellard | |
539 | 13ab5daa | bellard | return retval;
|
540 | a541f297 | bellard | } |
541 | a541f297 | bellard | |
542 | e1bb04f7 | bellard | static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value) |
543 | e1bb04f7 | bellard | { |
544 | e1bb04f7 | bellard | m48t59_t *NVRAM = opaque; |
545 | 3b46e624 | ths | |
546 | e1bb04f7 | bellard | addr -= NVRAM->mem_base; |
547 | 819385c5 | bellard | m48t59_write(NVRAM, addr, value & 0xff);
|
548 | e1bb04f7 | bellard | } |
549 | e1bb04f7 | bellard | |
550 | e1bb04f7 | bellard | static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value) |
551 | e1bb04f7 | bellard | { |
552 | e1bb04f7 | bellard | m48t59_t *NVRAM = opaque; |
553 | 3b46e624 | ths | |
554 | e1bb04f7 | bellard | addr -= NVRAM->mem_base; |
555 | 819385c5 | bellard | m48t59_write(NVRAM, addr, (value >> 8) & 0xff); |
556 | 819385c5 | bellard | m48t59_write(NVRAM, addr + 1, value & 0xff); |
557 | e1bb04f7 | bellard | } |
558 | e1bb04f7 | bellard | |
559 | e1bb04f7 | bellard | static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
560 | e1bb04f7 | bellard | { |
561 | e1bb04f7 | bellard | m48t59_t *NVRAM = opaque; |
562 | 3b46e624 | ths | |
563 | e1bb04f7 | bellard | addr -= NVRAM->mem_base; |
564 | 819385c5 | bellard | m48t59_write(NVRAM, addr, (value >> 24) & 0xff); |
565 | 819385c5 | bellard | m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff); |
566 | 819385c5 | bellard | m48t59_write(NVRAM, addr + 2, (value >> 8) & 0xff); |
567 | 819385c5 | bellard | m48t59_write(NVRAM, addr + 3, value & 0xff); |
568 | e1bb04f7 | bellard | } |
569 | e1bb04f7 | bellard | |
570 | e1bb04f7 | bellard | static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr) |
571 | e1bb04f7 | bellard | { |
572 | e1bb04f7 | bellard | m48t59_t *NVRAM = opaque; |
573 | 819385c5 | bellard | uint32_t retval; |
574 | 3b46e624 | ths | |
575 | e1bb04f7 | bellard | addr -= NVRAM->mem_base; |
576 | 819385c5 | bellard | retval = m48t59_read(NVRAM, addr); |
577 | e1bb04f7 | bellard | return retval;
|
578 | e1bb04f7 | bellard | } |
579 | e1bb04f7 | bellard | |
580 | e1bb04f7 | bellard | static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr) |
581 | e1bb04f7 | bellard | { |
582 | e1bb04f7 | bellard | m48t59_t *NVRAM = opaque; |
583 | 819385c5 | bellard | uint32_t retval; |
584 | 3b46e624 | ths | |
585 | e1bb04f7 | bellard | addr -= NVRAM->mem_base; |
586 | 819385c5 | bellard | retval = m48t59_read(NVRAM, addr) << 8;
|
587 | 819385c5 | bellard | retval |= m48t59_read(NVRAM, addr + 1);
|
588 | e1bb04f7 | bellard | return retval;
|
589 | e1bb04f7 | bellard | } |
590 | e1bb04f7 | bellard | |
591 | e1bb04f7 | bellard | static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr) |
592 | e1bb04f7 | bellard | { |
593 | e1bb04f7 | bellard | m48t59_t *NVRAM = opaque; |
594 | 819385c5 | bellard | uint32_t retval; |
595 | e1bb04f7 | bellard | |
596 | 819385c5 | bellard | addr -= NVRAM->mem_base; |
597 | 819385c5 | bellard | retval = m48t59_read(NVRAM, addr) << 24;
|
598 | 819385c5 | bellard | retval |= m48t59_read(NVRAM, addr + 1) << 16; |
599 | 819385c5 | bellard | retval |= m48t59_read(NVRAM, addr + 2) << 8; |
600 | 819385c5 | bellard | retval |= m48t59_read(NVRAM, addr + 3);
|
601 | e1bb04f7 | bellard | return retval;
|
602 | e1bb04f7 | bellard | } |
603 | e1bb04f7 | bellard | |
604 | e1bb04f7 | bellard | static CPUWriteMemoryFunc *nvram_write[] = {
|
605 | e1bb04f7 | bellard | &nvram_writeb, |
606 | e1bb04f7 | bellard | &nvram_writew, |
607 | e1bb04f7 | bellard | &nvram_writel, |
608 | e1bb04f7 | bellard | }; |
609 | e1bb04f7 | bellard | |
610 | e1bb04f7 | bellard | static CPUReadMemoryFunc *nvram_read[] = {
|
611 | e1bb04f7 | bellard | &nvram_readb, |
612 | e1bb04f7 | bellard | &nvram_readw, |
613 | e1bb04f7 | bellard | &nvram_readl, |
614 | e1bb04f7 | bellard | }; |
615 | 819385c5 | bellard | |
616 | 3ccacc4a | blueswir1 | static void m48t59_save(QEMUFile *f, void *opaque) |
617 | 3ccacc4a | blueswir1 | { |
618 | 3ccacc4a | blueswir1 | m48t59_t *s = opaque; |
619 | 3ccacc4a | blueswir1 | |
620 | 3ccacc4a | blueswir1 | qemu_put_8s(f, &s->lock); |
621 | 3ccacc4a | blueswir1 | qemu_put_be16s(f, &s->addr); |
622 | 3ccacc4a | blueswir1 | qemu_put_buffer(f, s->buffer, s->size); |
623 | 3ccacc4a | blueswir1 | } |
624 | 3ccacc4a | blueswir1 | |
625 | 3ccacc4a | blueswir1 | static int m48t59_load(QEMUFile *f, void *opaque, int version_id) |
626 | 3ccacc4a | blueswir1 | { |
627 | 3ccacc4a | blueswir1 | m48t59_t *s = opaque; |
628 | 3ccacc4a | blueswir1 | |
629 | 3ccacc4a | blueswir1 | if (version_id != 1) |
630 | 3ccacc4a | blueswir1 | return -EINVAL;
|
631 | 3ccacc4a | blueswir1 | |
632 | 3ccacc4a | blueswir1 | qemu_get_8s(f, &s->lock); |
633 | 3ccacc4a | blueswir1 | qemu_get_be16s(f, &s->addr); |
634 | 3ccacc4a | blueswir1 | qemu_get_buffer(f, s->buffer, s->size); |
635 | 3ccacc4a | blueswir1 | |
636 | 3ccacc4a | blueswir1 | return 0; |
637 | 3ccacc4a | blueswir1 | } |
638 | 3ccacc4a | blueswir1 | |
639 | 3ccacc4a | blueswir1 | static void m48t59_reset(void *opaque) |
640 | 3ccacc4a | blueswir1 | { |
641 | 3ccacc4a | blueswir1 | m48t59_t *NVRAM = opaque; |
642 | 3ccacc4a | blueswir1 | |
643 | 3ccacc4a | blueswir1 | if (NVRAM->alrm_timer != NULL) |
644 | 3ccacc4a | blueswir1 | qemu_del_timer(NVRAM->alrm_timer); |
645 | 3ccacc4a | blueswir1 | |
646 | 3ccacc4a | blueswir1 | if (NVRAM->wd_timer != NULL) |
647 | 3ccacc4a | blueswir1 | qemu_del_timer(NVRAM->wd_timer); |
648 | 3ccacc4a | blueswir1 | } |
649 | 3ccacc4a | blueswir1 | |
650 | a541f297 | bellard | /* Initialisation routine */
|
651 | 5dcb6b91 | blueswir1 | m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base, |
652 | 819385c5 | bellard | uint32_t io_base, uint16_t size, |
653 | 819385c5 | bellard | int type)
|
654 | a541f297 | bellard | { |
655 | c5df018e | bellard | m48t59_t *s; |
656 | 5dcb6b91 | blueswir1 | target_phys_addr_t save_base; |
657 | a541f297 | bellard | |
658 | c5df018e | bellard | s = qemu_mallocz(sizeof(m48t59_t));
|
659 | c5df018e | bellard | if (!s)
|
660 | a541f297 | bellard | return NULL; |
661 | c5df018e | bellard | s->buffer = qemu_mallocz(size); |
662 | c5df018e | bellard | if (!s->buffer) {
|
663 | c5df018e | bellard | qemu_free(s); |
664 | c5df018e | bellard | return NULL; |
665 | c5df018e | bellard | } |
666 | c5df018e | bellard | s->IRQ = IRQ; |
667 | c5df018e | bellard | s->size = size; |
668 | e1bb04f7 | bellard | s->mem_base = mem_base; |
669 | c5df018e | bellard | s->io_base = io_base; |
670 | c5df018e | bellard | s->addr = 0;
|
671 | 819385c5 | bellard | s->type = type; |
672 | 819385c5 | bellard | if (io_base != 0) { |
673 | 819385c5 | bellard | register_ioport_read(io_base, 0x04, 1, NVRAM_readb, s); |
674 | 819385c5 | bellard | register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, s); |
675 | 819385c5 | bellard | } |
676 | e1bb04f7 | bellard | if (mem_base != 0) { |
677 | e1bb04f7 | bellard | s->mem_index = cpu_register_io_memory(0, nvram_read, nvram_write, s);
|
678 | 4aed2c33 | blueswir1 | cpu_register_physical_memory(mem_base, size, s->mem_index); |
679 | e1bb04f7 | bellard | } |
680 | 819385c5 | bellard | if (type == 59) { |
681 | 819385c5 | bellard | s->alrm_timer = qemu_new_timer(vm_clock, &alarm_cb, s); |
682 | 819385c5 | bellard | s->wd_timer = qemu_new_timer(vm_clock, &watchdog_cb, s); |
683 | 819385c5 | bellard | } |
684 | 13ab5daa | bellard | s->lock = 0;
|
685 | 13ab5daa | bellard | |
686 | 3ccacc4a | blueswir1 | qemu_register_reset(m48t59_reset, s); |
687 | 3ccacc4a | blueswir1 | save_base = mem_base ? mem_base : io_base; |
688 | 3ccacc4a | blueswir1 | register_savevm("m48t59", save_base, 1, m48t59_save, m48t59_load, s); |
689 | 3ccacc4a | blueswir1 | |
690 | c5df018e | bellard | return s;
|
691 | a541f297 | bellard | } |