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Name Size
Makefile.objs 169 Bytes
arm-semi.c 17.1 kB
cpu-qom.h 3.1 kB
cpu.c 26.6 kB
cpu.h 26.5 kB
helper.c 111.6 kB
helper.h 17 kB
iwmmxt_helper.c 24.8 kB
kvm.c 14.2 kB
kvm_arm.h 907 Bytes
machine.c 7.8 kB
neon_helper.c 52.8 kB
op_addsub.h 1.8 kB
op_helper.c 8.9 kB
translate.c 346.4 kB

Latest revisions

# Date Author Comment
eb035b48 03/05/2013 02:45 am Peter Maydell

target-arm: Use MemoryListener to identify GIC base address for KVM

When using an in-kernel GIC with KVM, we need to tell the kernel where
the GIC's memory mapped registers live. Do this by registering a
MemoryListener which tracks where the board model maps the A15's...
81635574 03/05/2013 02:45 am Peter Maydell

ARM KVM: save and load VFP registers from kernel

Add support for saving and restoring VFP register state from the
kernel. This includes a check that the KVM-created CPU has full
VFP support (as the TCG Cortex-A15 model always does), since for
the moment ARM QEMU doesn't have any way to tweak optional features...
494b00c7 03/05/2013 02:45 am Christoffer Dall

ARM: KVM: Add support for KVM on ARM architecture

Add basic support for KVM on ARM architecture.

Signed-off-by: Christoffer Dall <>
[PMM: Minor tweaks and code cleanup, switch to ONE_REG]
Signed-off-by: Peter Maydell <>...
f5206413 03/05/2013 02:34 am Peter Maydell

target-arm: Drop CPUARMState* argument from bank_number()

Drop the CPUARMState* argument from bank_number(), since we only
use it for passing to cpu_abort(). Use hw_error() instead.
This avoids propagating further interfaces using env pointers.

In the long term this function's callers need auditing to fix...
81465888 03/05/2013 02:31 am Peter Maydell

target-arm: Factor out handling of SRS instruction

Factor out the handling of the SRS instruction rather than
duplicating it between the Thumb and ARM decoders. This in
passing fixes two bugs in the Thumb decoder's SRS handling
which didn't exist in the ARM decoder:...
00115976 03/05/2013 02:31 am Peter Maydell

target-arm: Don't decode RFE or SRS on M profile cores

M profile cores do not have the RFE or SRS instructions, so
correctly UNDEF these insn patterns on those cores.

Signed-off-by: Peter Maydell <>
806f352d 03/03/2013 04:29 pm Peter Maydell

gen-icount.h: Rename gen_icount_start/end to gen_tb_start/end

The gen_icount_start/end functions are now somewhat misnamed since they
are useful for generic "start/end of TB" code, used for more than just
icount. Rename them to gen_tb_start/end.

Signed-off-by: Peter Maydell <>...
fadf9825 03/03/2013 04:28 pm Andreas Färber

cpu: Introduce ENV_OFFSET macros

Introduce ENV_OFFSET macros which can be used in non-target-specific
code that needs to generate TCG instructions which reference CPUState
fields given the cpu_env register that TCG targets set up with a
pointer to the CPUArchState struct....
8c3ac601 02/25/2013 10:32 pm Peter Crosthwaite

arm/translate.c: Fix adc_CC/sbc_CC implementation

commits 49b4c31efcce45ab714f286f14fa5d5173f9069d and
2de68a4900ef6eb67380b0c128abfe1976bc66e8 reworked the implementation of adc_CC
and sub_CC. The new implementations (on the TCG_TARGET_HAS_add2_i32 code path)...
e77f0832 02/25/2013 10:32 pm Richard Henderson

target-arm: Fix sbc_CC carry

While T0+~T1+CF = T0-T1+CF-1 is true for the low 32-bits,
it does not produce the correct carry-out to bit 33. Do
exactly what the manual says.

Using the ~T1 makes the add and subtract code paths nearly
identical, so have sbc_CC use adc_CC....

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