Statistics
| Branch: | Revision:

root / target-arm @ 5433a0a8

Name Size
Makefile.objs 465 Bytes
arm-semi.c 17.2 kB
cpu-qom.h 5.9 kB
cpu.c 32.4 kB
cpu.h 35 kB
cpu64.c 3.5 kB
crypto_helper.c 13 kB
gdbstub.c 2.8 kB
gdbstub64.c 1.9 kB
helper-a64.c 1.9 kB
helper-a64.h 1.1 kB
helper.c 133.3 kB
helper.h 17.4 kB
iwmmxt_helper.c 24.8 kB
kvm-consts.h 1.9 kB
kvm-stub.c 437 Bytes
kvm.c 9.4 kB
kvm32.c 15.7 kB
kvm64.c 5.2 kB
kvm_arm.h 3.8 kB
machine.c 7.9 kB
neon_helper.c 52.8 kB
op_addsub.h 1.8 kB
op_helper.c 8.9 kB
translate-a64.c 51.3 kB
translate.c 365.8 kB
translate.h 1.9 kB

Latest revisions

# Date Author Comment
5433a0a8 01/06/2014 10:02 pm Peter Crosthwaite

hw: Remove assert_no_error usages

Replace assert_no_error() usages with the error_abort system.
&error_abort is passed into API calls to signal to the Error sub-system
that any errors are fatal. Removes need for caller assertions.

Signed-off-by: Peter Crosthwaite <>...
e801de93 12/17/2013 10:12 pm Alexander Graf

target-arm: A64: add support for EXTR

This patch adds emulation support for the EXTR instruction.

Signed-off-by: Alexander Graf <>

[claudio: adapted for new decoder, removed a few temporaries,
fixed the 32bit bug, added checks for more...
8220e911 12/17/2013 10:12 pm Alexander Graf

target-arm: A64: add support for 2-src data processing and DIV

This patch adds support for decoding 2-src data processing insns,
and the first users, UDIV and SDIV.

Signed-off-by: Alexander Graf <>
[claudio: adapted to new decoder adding the 2-src decoding level,...
6c1adc91 12/17/2013 10:12 pm Alexander Graf

target-arm: A64: add support for 2-src shift reg insns

This adds 2-src variable shift register instructions:
C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV

Signed-off-by: Alexander Graf <>
[claudio: adapted to new decoder, use enums for shift types]...
680ead21 12/17/2013 10:12 pm Claudio Fontana

target-arm: A64: add support for 1-src data processing and CLZ

This patch adds support for decoding 1-src data processing insns,
and the first user, C5.6.40 CLZ (count leading zeroes).

Signed-off-by: Claudio Fontana <>
Signed-off-by: Peter Maydell <>...
82e14b02 12/17/2013 10:12 pm Alexander Graf

target-arm: A64: add support for 1-src RBIT insn

This adds support for the C5.6.147 RBIT instruction.

Signed-off-by: Alexander Graf <>
[claudio: adapted to new decoder, use bswap64,
make RBIT part standalone from the rest of the patch,...
45323209 12/17/2013 10:12 pm Claudio Fontana

target-arm: A64: add support for 1-src REV insns

This adds support for C5.6.149 REV, C5.6.151 REV32, C5.6.150 REV16.

Signed-off-by: Claudio Fontana <>
Signed-off-by: Peter Maydell <>
Reviewed-by: Richard Henderson <>
88077742 12/17/2013 10:12 pm Claudio Fontana

target-arm: A64: add support for bitfield insns

This patch implements the C3.4.2 Bitfield instructions:
SBFM, BFM, UBFM.

Signed-off-by: Claudio Fontana <>
Signed-off-by: Peter Maydell <>
Reviewed-by: Richard Henderson <>
e80c5020 12/17/2013 10:12 pm Claudio Fontana

target-arm: A64: add support for 1-src CLS insn

this patch adds support for the CLS instruction.

Signed-off-by: Claudio Fontana <>
Signed-off-by: Peter Maydell <>
Reviewed-by: Richard Henderson <>
71b46089 12/17/2013 10:12 pm Alexander Graf

target-arm: A64: add support for logical (immediate) insns

This patch adds support for C3.4.4 Logical (immediate),
which include AND, ANDS, ORR, EOR.

Signed-off-by: Alexander Graf <>
[claudio: adapted to new decoder, function renaming,
removed a TCG temp variable]...

View revisions

Also available in: Atom