root / target-arm / cpu.c @ 599d64f6
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/*
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* QEMU ARM CPU
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*
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* Copyright (c) 2012 SUSE LINUX Products GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see
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* <http://www.gnu.org/licenses/gpl-2.0.html>
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*/
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#include "cpu.h" |
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#include "qemu-common.h" |
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#if !defined(CONFIG_USER_ONLY)
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#include "hw/loader.h" |
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#endif
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#include "sysemu.h" |
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static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) |
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{
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/* Reset a single ARMCPRegInfo register */
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ARMCPRegInfo *ri = value; |
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ARMCPU *cpu = opaque; |
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if (ri->type & ARM_CP_SPECIAL) {
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return;
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} |
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|
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if (ri->resetfn) {
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ri->resetfn(&cpu->env, ri); |
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return;
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} |
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/* A zero offset is never possible as it would be regs[0]
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* so we use it to indicate that reset is being handled elsewhere.
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* This is basically only used for fields in non-core coprocessors
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* (like the pxa2xx ones).
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*/
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if (!ri->fieldoffset) {
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return;
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} |
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|
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if (ri->type & ARM_CP_64BIT) {
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CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; |
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} else {
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CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; |
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} |
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} |
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|
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/* CPUClass::reset() */
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static void arm_cpu_reset(CPUState *s) |
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{
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ARMCPU *cpu = ARM_CPU(s); |
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ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); |
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CPUARMState *env = &cpu->env; |
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|
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if (qemu_loglevel_mask(CPU_LOG_RESET)) {
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qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
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log_cpu_state(env, 0);
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} |
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acc->parent_reset(s); |
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memset(env, 0, offsetof(CPUARMState, breakpoints));
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g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); |
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env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; |
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env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0; |
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env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1; |
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if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
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env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; |
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} |
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#if defined(CONFIG_USER_ONLY)
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env->uncached_cpsr = ARM_CPU_MODE_USR; |
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/* For user mode we must enable access to coprocessors */
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env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; |
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if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
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env->cp15.c15_cpar = 3;
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} else if (arm_feature(env, ARM_FEATURE_XSCALE)) { |
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env->cp15.c15_cpar = 1;
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} |
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#else
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/* SVC mode with interrupts disabled. */
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env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I; |
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/* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
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clear at reset. Initial SP and PC are loaded from ROM. */
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if (IS_M(env)) {
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uint32_t pc; |
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uint8_t *rom; |
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env->uncached_cpsr &= ~CPSR_I; |
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rom = rom_ptr(0);
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if (rom) {
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/* We should really use ldl_phys here, in case the guest
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modified flash and reset itself. However images
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loaded via -kernel have not been copied yet, so load the
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values directly from there. */
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env->regs[13] = ldl_p(rom);
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pc = ldl_p(rom + 4);
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env->thumb = pc & 1;
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env->regs[15] = pc & ~1; |
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} |
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} |
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env->vfp.xregs[ARM_VFP_FPEXC] = 0;
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#endif
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set_flush_to_zero(1, &env->vfp.standard_fp_status);
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set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
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set_default_nan_mode(1, &env->vfp.standard_fp_status);
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set_float_detect_tininess(float_tininess_before_rounding, |
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&env->vfp.fp_status); |
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set_float_detect_tininess(float_tininess_before_rounding, |
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&env->vfp.standard_fp_status); |
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tlb_flush(env, 1);
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/* Reset is a state change for some CPUARMState fields which we
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* bake assumptions about into translated code, so we need to
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* tb_flush().
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*/
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tb_flush(env); |
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} |
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static inline void set_feature(CPUARMState *env, int feature) |
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{
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env->features |= 1ULL << feature;
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} |
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static void arm_cpu_initfn(Object *obj) |
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{
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ARMCPU *cpu = ARM_CPU(obj); |
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cpu_exec_init(&cpu->env); |
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cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, |
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g_free, g_free); |
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} |
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static void arm_cpu_finalizefn(Object *obj) |
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{
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ARMCPU *cpu = ARM_CPU(obj); |
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g_hash_table_destroy(cpu->cp_regs); |
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} |
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void arm_cpu_realize(ARMCPU *cpu)
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{
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/* This function is called by cpu_arm_init() because it
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* needs to do common actions based on feature bits, etc
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* that have been set by the subclass init functions.
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* When we have QOM realize support it should become
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* a true realize function instead.
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*/
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CPUARMState *env = &cpu->env; |
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/* Some features automatically imply others: */
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if (arm_feature(env, ARM_FEATURE_V7)) {
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set_feature(env, ARM_FEATURE_VAPA); |
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set_feature(env, ARM_FEATURE_THUMB2); |
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set_feature(env, ARM_FEATURE_MPIDR); |
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if (!arm_feature(env, ARM_FEATURE_M)) {
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set_feature(env, ARM_FEATURE_V6K); |
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} else {
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set_feature(env, ARM_FEATURE_V6); |
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} |
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} |
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if (arm_feature(env, ARM_FEATURE_V6K)) {
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set_feature(env, ARM_FEATURE_V6); |
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set_feature(env, ARM_FEATURE_MVFR); |
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} |
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if (arm_feature(env, ARM_FEATURE_V6)) {
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set_feature(env, ARM_FEATURE_V5); |
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if (!arm_feature(env, ARM_FEATURE_M)) {
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set_feature(env, ARM_FEATURE_AUXCR); |
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} |
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} |
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if (arm_feature(env, ARM_FEATURE_V5)) {
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set_feature(env, ARM_FEATURE_V4T); |
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} |
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if (arm_feature(env, ARM_FEATURE_M)) {
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set_feature(env, ARM_FEATURE_THUMB_DIV); |
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} |
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if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
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set_feature(env, ARM_FEATURE_THUMB_DIV); |
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} |
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if (arm_feature(env, ARM_FEATURE_VFP4)) {
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set_feature(env, ARM_FEATURE_VFP3); |
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} |
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if (arm_feature(env, ARM_FEATURE_VFP3)) {
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set_feature(env, ARM_FEATURE_VFP); |
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} |
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if (arm_feature(env, ARM_FEATURE_LPAE)) {
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set_feature(env, ARM_FEATURE_PXN); |
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} |
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register_cp_regs_for_features(cpu); |
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} |
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/* CPU models */
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static void arm926_initfn(Object *obj) |
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{
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ARMCPU *cpu = ARM_CPU(obj); |
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set_feature(&cpu->env, ARM_FEATURE_V5); |
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set_feature(&cpu->env, ARM_FEATURE_VFP); |
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set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
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set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); |
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cpu->midr = 0x41069265;
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cpu->reset_fpsid = 0x41011090;
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cpu->ctr = 0x1dd20d2;
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cpu->reset_sctlr = 0x00090078;
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} |
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static void arm946_initfn(Object *obj) |
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{
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ARMCPU *cpu = ARM_CPU(obj); |
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set_feature(&cpu->env, ARM_FEATURE_V5); |
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set_feature(&cpu->env, ARM_FEATURE_MPU); |
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set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
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cpu->midr = 0x41059461;
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cpu->ctr = 0x0f004006;
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cpu->reset_sctlr = 0x00000078;
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} |
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static void arm1026_initfn(Object *obj) |
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{
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ARMCPU *cpu = ARM_CPU(obj); |
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set_feature(&cpu->env, ARM_FEATURE_V5); |
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set_feature(&cpu->env, ARM_FEATURE_VFP); |
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set_feature(&cpu->env, ARM_FEATURE_AUXCR); |
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set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
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set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); |
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cpu->midr = 0x4106a262;
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cpu->reset_fpsid = 0x410110a0;
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cpu->ctr = 0x1dd20d2;
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cpu->reset_sctlr = 0x00090078;
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cpu->reset_auxcr = 1;
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{
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/* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
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ARMCPRegInfo ifar = {
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.name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, |
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.access = PL1_RW, |
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.fieldoffset = offsetof(CPUARMState, cp15.c6_insn), |
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.resetvalue = 0
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}; |
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define_one_arm_cp_reg(cpu, &ifar); |
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} |
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} |
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static void arm1136_r2_initfn(Object *obj) |
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{
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ARMCPU *cpu = ARM_CPU(obj); |
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/* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
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* older core than plain "arm1136". In particular this does not
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* have the v6K features.
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* These ID register values are correct for 1136 but may be wrong
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* for 1136_r2 (in particular r0p2 does not actually implement most
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* of the ID registers).
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*/
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set_feature(&cpu->env, ARM_FEATURE_V6); |
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set_feature(&cpu->env, ARM_FEATURE_VFP); |
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set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
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set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); |
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set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); |
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cpu->midr = 0x4107b362;
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cpu->reset_fpsid = 0x410120b4;
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cpu->mvfr0 = 0x11111111;
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cpu->mvfr1 = 0x00000000;
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cpu->ctr = 0x1dd20d2;
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cpu->reset_sctlr = 0x00050078;
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cpu->id_pfr0 = 0x111;
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cpu->id_pfr1 = 0x1;
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cpu->id_dfr0 = 0x2;
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cpu->id_afr0 = 0x3;
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cpu->id_mmfr0 = 0x01130003;
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cpu->id_mmfr1 = 0x10030302;
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cpu->id_mmfr2 = 0x01222110;
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cpu->id_isar0 = 0x00140011;
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cpu->id_isar1 = 0x12002111;
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cpu->id_isar2 = 0x11231111;
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cpu->id_isar3 = 0x01102131;
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cpu->id_isar4 = 0x141;
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cpu->reset_auxcr = 7;
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} |
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static void arm1136_initfn(Object *obj) |
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{
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ARMCPU *cpu = ARM_CPU(obj); |
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set_feature(&cpu->env, ARM_FEATURE_V6K); |
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set_feature(&cpu->env, ARM_FEATURE_V6); |
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set_feature(&cpu->env, ARM_FEATURE_VFP); |
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set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
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set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); |
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set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); |
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cpu->midr = 0x4117b363;
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cpu->reset_fpsid = 0x410120b4;
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cpu->mvfr0 = 0x11111111;
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cpu->mvfr1 = 0x00000000;
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cpu->ctr = 0x1dd20d2;
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cpu->reset_sctlr = 0x00050078;
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cpu->id_pfr0 = 0x111;
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cpu->id_pfr1 = 0x1;
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cpu->id_dfr0 = 0x2;
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cpu->id_afr0 = 0x3;
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cpu->id_mmfr0 = 0x01130003;
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cpu->id_mmfr1 = 0x10030302;
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cpu->id_mmfr2 = 0x01222110;
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cpu->id_isar0 = 0x00140011;
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cpu->id_isar1 = 0x12002111;
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cpu->id_isar2 = 0x11231111;
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cpu->id_isar3 = 0x01102131;
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cpu->id_isar4 = 0x141;
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cpu->reset_auxcr = 7;
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} |
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|
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static void arm1176_initfn(Object *obj) |
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{
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ARMCPU *cpu = ARM_CPU(obj); |
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set_feature(&cpu->env, ARM_FEATURE_V6K); |
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set_feature(&cpu->env, ARM_FEATURE_VFP); |
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set_feature(&cpu->env, ARM_FEATURE_VAPA); |
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set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
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set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); |
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set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); |
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cpu->midr = 0x410fb767;
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cpu->reset_fpsid = 0x410120b5;
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cpu->mvfr0 = 0x11111111;
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cpu->mvfr1 = 0x00000000;
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cpu->ctr = 0x1dd20d2;
|
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cpu->reset_sctlr = 0x00050078;
|
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cpu->id_pfr0 = 0x111;
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cpu->id_pfr1 = 0x11;
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cpu->id_dfr0 = 0x33;
|
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cpu->id_afr0 = 0;
|
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cpu->id_mmfr0 = 0x01130003;
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cpu->id_mmfr1 = 0x10030302;
|
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cpu->id_mmfr2 = 0x01222100;
|
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cpu->id_isar0 = 0x0140011;
|
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cpu->id_isar1 = 0x12002111;
|
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cpu->id_isar2 = 0x11231121;
|
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cpu->id_isar3 = 0x01102131;
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cpu->id_isar4 = 0x01141;
|
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cpu->reset_auxcr = 7;
|
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} |
| 348 |
|
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static void arm11mpcore_initfn(Object *obj) |
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{
|
| 351 |
ARMCPU *cpu = ARM_CPU(obj); |
| 352 |
set_feature(&cpu->env, ARM_FEATURE_V6K); |
| 353 |
set_feature(&cpu->env, ARM_FEATURE_VFP); |
| 354 |
set_feature(&cpu->env, ARM_FEATURE_VAPA); |
| 355 |
set_feature(&cpu->env, ARM_FEATURE_MPIDR); |
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set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
| 357 |
cpu->midr = 0x410fb022;
|
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cpu->reset_fpsid = 0x410120b4;
|
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cpu->mvfr0 = 0x11111111;
|
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cpu->mvfr1 = 0x00000000;
|
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cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ |
| 362 |
cpu->id_pfr0 = 0x111;
|
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cpu->id_pfr1 = 0x1;
|
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cpu->id_dfr0 = 0;
|
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cpu->id_afr0 = 0x2;
|
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cpu->id_mmfr0 = 0x01100103;
|
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cpu->id_mmfr1 = 0x10020302;
|
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cpu->id_mmfr2 = 0x01222000;
|
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cpu->id_isar0 = 0x00100011;
|
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cpu->id_isar1 = 0x12002111;
|
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cpu->id_isar2 = 0x11221011;
|
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cpu->id_isar3 = 0x01102131;
|
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cpu->id_isar4 = 0x141;
|
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cpu->reset_auxcr = 1;
|
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} |
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|
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static void cortex_m3_initfn(Object *obj) |
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{
|
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ARMCPU *cpu = ARM_CPU(obj); |
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set_feature(&cpu->env, ARM_FEATURE_V7); |
| 381 |
set_feature(&cpu->env, ARM_FEATURE_M); |
| 382 |
cpu->midr = 0x410fc231;
|
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} |
| 384 |
|
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static const ARMCPRegInfo cortexa8_cp_reginfo[] = { |
| 386 |
{ .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
|
| 387 |
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
|
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{ .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
|
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
|
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REGINFO_SENTINEL |
| 391 |
}; |
| 392 |
|
| 393 |
static void cortex_a8_initfn(Object *obj) |
| 394 |
{
|
| 395 |
ARMCPU *cpu = ARM_CPU(obj); |
| 396 |
set_feature(&cpu->env, ARM_FEATURE_V7); |
| 397 |
set_feature(&cpu->env, ARM_FEATURE_VFP3); |
| 398 |
set_feature(&cpu->env, ARM_FEATURE_NEON); |
| 399 |
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); |
| 400 |
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
| 401 |
cpu->midr = 0x410fc080;
|
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cpu->reset_fpsid = 0x410330c0;
|
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cpu->mvfr0 = 0x11110222;
|
| 404 |
cpu->mvfr1 = 0x00011100;
|
| 405 |
cpu->ctr = 0x82048004;
|
| 406 |
cpu->reset_sctlr = 0x00c50078;
|
| 407 |
cpu->id_pfr0 = 0x1031;
|
| 408 |
cpu->id_pfr1 = 0x11;
|
| 409 |
cpu->id_dfr0 = 0x400;
|
| 410 |
cpu->id_afr0 = 0;
|
| 411 |
cpu->id_mmfr0 = 0x31100003;
|
| 412 |
cpu->id_mmfr1 = 0x20000000;
|
| 413 |
cpu->id_mmfr2 = 0x01202000;
|
| 414 |
cpu->id_mmfr3 = 0x11;
|
| 415 |
cpu->id_isar0 = 0x00101111;
|
| 416 |
cpu->id_isar1 = 0x12112111;
|
| 417 |
cpu->id_isar2 = 0x21232031;
|
| 418 |
cpu->id_isar3 = 0x11112131;
|
| 419 |
cpu->id_isar4 = 0x00111142;
|
| 420 |
cpu->clidr = (1 << 27) | (2 << 24) | 3; |
| 421 |
cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ |
| 422 |
cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ |
| 423 |
cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ |
| 424 |
cpu->reset_auxcr = 2;
|
| 425 |
define_arm_cp_regs(cpu, cortexa8_cp_reginfo); |
| 426 |
} |
| 427 |
|
| 428 |
static const ARMCPRegInfo cortexa9_cp_reginfo[] = { |
| 429 |
/* power_control should be set to maximum latency. Again,
|
| 430 |
* default to 0 and set by private hook
|
| 431 |
*/
|
| 432 |
{ .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
|
| 433 |
.access = PL1_RW, .resetvalue = 0,
|
| 434 |
.fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, |
| 435 |
{ .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
|
| 436 |
.access = PL1_RW, .resetvalue = 0,
|
| 437 |
.fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, |
| 438 |
{ .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
|
| 439 |
.access = PL1_RW, .resetvalue = 0,
|
| 440 |
.fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, |
| 441 |
{ .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
|
| 442 |
.access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
|
| 443 |
/* TLB lockdown control */
|
| 444 |
{ .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
|
| 445 |
.access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
|
| 446 |
{ .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
|
| 447 |
.access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
|
| 448 |
{ .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
|
| 449 |
.access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
|
| 450 |
{ .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
|
| 451 |
.access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
|
| 452 |
{ .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
|
| 453 |
.access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
|
| 454 |
REGINFO_SENTINEL |
| 455 |
}; |
| 456 |
|
| 457 |
static void cortex_a9_initfn(Object *obj) |
| 458 |
{
|
| 459 |
ARMCPU *cpu = ARM_CPU(obj); |
| 460 |
set_feature(&cpu->env, ARM_FEATURE_V7); |
| 461 |
set_feature(&cpu->env, ARM_FEATURE_VFP3); |
| 462 |
set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); |
| 463 |
set_feature(&cpu->env, ARM_FEATURE_NEON); |
| 464 |
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); |
| 465 |
/* Note that A9 supports the MP extensions even for
|
| 466 |
* A9UP and single-core A9MP (which are both different
|
| 467 |
* and valid configurations; we don't model A9UP).
|
| 468 |
*/
|
| 469 |
set_feature(&cpu->env, ARM_FEATURE_V7MP); |
| 470 |
cpu->midr = 0x410fc090;
|
| 471 |
cpu->reset_fpsid = 0x41033090;
|
| 472 |
cpu->mvfr0 = 0x11110222;
|
| 473 |
cpu->mvfr1 = 0x01111111;
|
| 474 |
cpu->ctr = 0x80038003;
|
| 475 |
cpu->reset_sctlr = 0x00c50078;
|
| 476 |
cpu->id_pfr0 = 0x1031;
|
| 477 |
cpu->id_pfr1 = 0x11;
|
| 478 |
cpu->id_dfr0 = 0x000;
|
| 479 |
cpu->id_afr0 = 0;
|
| 480 |
cpu->id_mmfr0 = 0x00100103;
|
| 481 |
cpu->id_mmfr1 = 0x20000000;
|
| 482 |
cpu->id_mmfr2 = 0x01230000;
|
| 483 |
cpu->id_mmfr3 = 0x00002111;
|
| 484 |
cpu->id_isar0 = 0x00101111;
|
| 485 |
cpu->id_isar1 = 0x13112111;
|
| 486 |
cpu->id_isar2 = 0x21232041;
|
| 487 |
cpu->id_isar3 = 0x11112131;
|
| 488 |
cpu->id_isar4 = 0x00111142;
|
| 489 |
cpu->clidr = (1 << 27) | (1 << 24) | 3; |
| 490 |
cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */ |
| 491 |
cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */ |
| 492 |
{
|
| 493 |
ARMCPRegInfo cbar = {
|
| 494 |
.name = "CBAR", .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, |
| 495 |
.opc2 = 0, .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
|
| 496 |
.fieldoffset = offsetof(CPUARMState, cp15.c15_config_base_address) |
| 497 |
}; |
| 498 |
define_one_arm_cp_reg(cpu, &cbar); |
| 499 |
define_arm_cp_regs(cpu, cortexa9_cp_reginfo); |
| 500 |
} |
| 501 |
} |
| 502 |
|
| 503 |
#ifndef CONFIG_USER_ONLY
|
| 504 |
static int a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri, |
| 505 |
uint64_t *value) |
| 506 |
{
|
| 507 |
/* Linux wants the number of processors from here.
|
| 508 |
* Might as well set the interrupt-controller bit too.
|
| 509 |
*/
|
| 510 |
*value = ((smp_cpus - 1) << 24) | (1 << 23); |
| 511 |
return 0; |
| 512 |
} |
| 513 |
#endif
|
| 514 |
|
| 515 |
static const ARMCPRegInfo cortexa15_cp_reginfo[] = { |
| 516 |
#ifndef CONFIG_USER_ONLY
|
| 517 |
{ .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
|
| 518 |
.access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
|
| 519 |
.writefn = arm_cp_write_ignore, }, |
| 520 |
#endif
|
| 521 |
{ .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
|
| 522 |
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
|
| 523 |
REGINFO_SENTINEL |
| 524 |
}; |
| 525 |
|
| 526 |
static void cortex_a15_initfn(Object *obj) |
| 527 |
{
|
| 528 |
ARMCPU *cpu = ARM_CPU(obj); |
| 529 |
set_feature(&cpu->env, ARM_FEATURE_V7); |
| 530 |
set_feature(&cpu->env, ARM_FEATURE_VFP4); |
| 531 |
set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); |
| 532 |
set_feature(&cpu->env, ARM_FEATURE_NEON); |
| 533 |
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); |
| 534 |
set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); |
| 535 |
set_feature(&cpu->env, ARM_FEATURE_V7MP); |
| 536 |
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); |
| 537 |
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
| 538 |
set_feature(&cpu->env, ARM_FEATURE_LPAE); |
| 539 |
cpu->midr = 0x412fc0f1;
|
| 540 |
cpu->reset_fpsid = 0x410430f0;
|
| 541 |
cpu->mvfr0 = 0x10110222;
|
| 542 |
cpu->mvfr1 = 0x11111111;
|
| 543 |
cpu->ctr = 0x8444c004;
|
| 544 |
cpu->reset_sctlr = 0x00c50078;
|
| 545 |
cpu->id_pfr0 = 0x00001131;
|
| 546 |
cpu->id_pfr1 = 0x00011011;
|
| 547 |
cpu->id_dfr0 = 0x02010555;
|
| 548 |
cpu->id_afr0 = 0x00000000;
|
| 549 |
cpu->id_mmfr0 = 0x10201105;
|
| 550 |
cpu->id_mmfr1 = 0x20000000;
|
| 551 |
cpu->id_mmfr2 = 0x01240000;
|
| 552 |
cpu->id_mmfr3 = 0x02102211;
|
| 553 |
cpu->id_isar0 = 0x02101110;
|
| 554 |
cpu->id_isar1 = 0x13112111;
|
| 555 |
cpu->id_isar2 = 0x21232041;
|
| 556 |
cpu->id_isar3 = 0x11112131;
|
| 557 |
cpu->id_isar4 = 0x10011142;
|
| 558 |
cpu->clidr = 0x0a200023;
|
| 559 |
cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ |
| 560 |
cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ |
| 561 |
cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ |
| 562 |
define_arm_cp_regs(cpu, cortexa15_cp_reginfo); |
| 563 |
} |
| 564 |
|
| 565 |
static void ti925t_initfn(Object *obj) |
| 566 |
{
|
| 567 |
ARMCPU *cpu = ARM_CPU(obj); |
| 568 |
set_feature(&cpu->env, ARM_FEATURE_V4T); |
| 569 |
set_feature(&cpu->env, ARM_FEATURE_OMAPCP); |
| 570 |
cpu->midr = ARM_CPUID_TI925T; |
| 571 |
cpu->ctr = 0x5109149;
|
| 572 |
cpu->reset_sctlr = 0x00000070;
|
| 573 |
} |
| 574 |
|
| 575 |
static void sa1100_initfn(Object *obj) |
| 576 |
{
|
| 577 |
ARMCPU *cpu = ARM_CPU(obj); |
| 578 |
set_feature(&cpu->env, ARM_FEATURE_STRONGARM); |
| 579 |
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
| 580 |
cpu->midr = 0x4401A11B;
|
| 581 |
cpu->reset_sctlr = 0x00000070;
|
| 582 |
} |
| 583 |
|
| 584 |
static void sa1110_initfn(Object *obj) |
| 585 |
{
|
| 586 |
ARMCPU *cpu = ARM_CPU(obj); |
| 587 |
set_feature(&cpu->env, ARM_FEATURE_STRONGARM); |
| 588 |
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
| 589 |
cpu->midr = 0x6901B119;
|
| 590 |
cpu->reset_sctlr = 0x00000070;
|
| 591 |
} |
| 592 |
|
| 593 |
static void pxa250_initfn(Object *obj) |
| 594 |
{
|
| 595 |
ARMCPU *cpu = ARM_CPU(obj); |
| 596 |
set_feature(&cpu->env, ARM_FEATURE_V5); |
| 597 |
set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
| 598 |
cpu->midr = 0x69052100;
|
| 599 |
cpu->ctr = 0xd172172;
|
| 600 |
cpu->reset_sctlr = 0x00000078;
|
| 601 |
} |
| 602 |
|
| 603 |
static void pxa255_initfn(Object *obj) |
| 604 |
{
|
| 605 |
ARMCPU *cpu = ARM_CPU(obj); |
| 606 |
set_feature(&cpu->env, ARM_FEATURE_V5); |
| 607 |
set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
| 608 |
cpu->midr = 0x69052d00;
|
| 609 |
cpu->ctr = 0xd172172;
|
| 610 |
cpu->reset_sctlr = 0x00000078;
|
| 611 |
} |
| 612 |
|
| 613 |
static void pxa260_initfn(Object *obj) |
| 614 |
{
|
| 615 |
ARMCPU *cpu = ARM_CPU(obj); |
| 616 |
set_feature(&cpu->env, ARM_FEATURE_V5); |
| 617 |
set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
| 618 |
cpu->midr = 0x69052903;
|
| 619 |
cpu->ctr = 0xd172172;
|
| 620 |
cpu->reset_sctlr = 0x00000078;
|
| 621 |
} |
| 622 |
|
| 623 |
static void pxa261_initfn(Object *obj) |
| 624 |
{
|
| 625 |
ARMCPU *cpu = ARM_CPU(obj); |
| 626 |
set_feature(&cpu->env, ARM_FEATURE_V5); |
| 627 |
set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
| 628 |
cpu->midr = 0x69052d05;
|
| 629 |
cpu->ctr = 0xd172172;
|
| 630 |
cpu->reset_sctlr = 0x00000078;
|
| 631 |
} |
| 632 |
|
| 633 |
static void pxa262_initfn(Object *obj) |
| 634 |
{
|
| 635 |
ARMCPU *cpu = ARM_CPU(obj); |
| 636 |
set_feature(&cpu->env, ARM_FEATURE_V5); |
| 637 |
set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
| 638 |
cpu->midr = 0x69052d06;
|
| 639 |
cpu->ctr = 0xd172172;
|
| 640 |
cpu->reset_sctlr = 0x00000078;
|
| 641 |
} |
| 642 |
|
| 643 |
static void pxa270a0_initfn(Object *obj) |
| 644 |
{
|
| 645 |
ARMCPU *cpu = ARM_CPU(obj); |
| 646 |
set_feature(&cpu->env, ARM_FEATURE_V5); |
| 647 |
set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
| 648 |
set_feature(&cpu->env, ARM_FEATURE_IWMMXT); |
| 649 |
cpu->midr = 0x69054110;
|
| 650 |
cpu->ctr = 0xd172172;
|
| 651 |
cpu->reset_sctlr = 0x00000078;
|
| 652 |
} |
| 653 |
|
| 654 |
static void pxa270a1_initfn(Object *obj) |
| 655 |
{
|
| 656 |
ARMCPU *cpu = ARM_CPU(obj); |
| 657 |
set_feature(&cpu->env, ARM_FEATURE_V5); |
| 658 |
set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
| 659 |
set_feature(&cpu->env, ARM_FEATURE_IWMMXT); |
| 660 |
cpu->midr = 0x69054111;
|
| 661 |
cpu->ctr = 0xd172172;
|
| 662 |
cpu->reset_sctlr = 0x00000078;
|
| 663 |
} |
| 664 |
|
| 665 |
static void pxa270b0_initfn(Object *obj) |
| 666 |
{
|
| 667 |
ARMCPU *cpu = ARM_CPU(obj); |
| 668 |
set_feature(&cpu->env, ARM_FEATURE_V5); |
| 669 |
set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
| 670 |
set_feature(&cpu->env, ARM_FEATURE_IWMMXT); |
| 671 |
cpu->midr = 0x69054112;
|
| 672 |
cpu->ctr = 0xd172172;
|
| 673 |
cpu->reset_sctlr = 0x00000078;
|
| 674 |
} |
| 675 |
|
| 676 |
static void pxa270b1_initfn(Object *obj) |
| 677 |
{
|
| 678 |
ARMCPU *cpu = ARM_CPU(obj); |
| 679 |
set_feature(&cpu->env, ARM_FEATURE_V5); |
| 680 |
set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
| 681 |
set_feature(&cpu->env, ARM_FEATURE_IWMMXT); |
| 682 |
cpu->midr = 0x69054113;
|
| 683 |
cpu->ctr = 0xd172172;
|
| 684 |
cpu->reset_sctlr = 0x00000078;
|
| 685 |
} |
| 686 |
|
| 687 |
static void pxa270c0_initfn(Object *obj) |
| 688 |
{
|
| 689 |
ARMCPU *cpu = ARM_CPU(obj); |
| 690 |
set_feature(&cpu->env, ARM_FEATURE_V5); |
| 691 |
set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
| 692 |
set_feature(&cpu->env, ARM_FEATURE_IWMMXT); |
| 693 |
cpu->midr = 0x69054114;
|
| 694 |
cpu->ctr = 0xd172172;
|
| 695 |
cpu->reset_sctlr = 0x00000078;
|
| 696 |
} |
| 697 |
|
| 698 |
static void pxa270c5_initfn(Object *obj) |
| 699 |
{
|
| 700 |
ARMCPU *cpu = ARM_CPU(obj); |
| 701 |
set_feature(&cpu->env, ARM_FEATURE_V5); |
| 702 |
set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
| 703 |
set_feature(&cpu->env, ARM_FEATURE_IWMMXT); |
| 704 |
cpu->midr = 0x69054117;
|
| 705 |
cpu->ctr = 0xd172172;
|
| 706 |
cpu->reset_sctlr = 0x00000078;
|
| 707 |
} |
| 708 |
|
| 709 |
static void arm_any_initfn(Object *obj) |
| 710 |
{
|
| 711 |
ARMCPU *cpu = ARM_CPU(obj); |
| 712 |
set_feature(&cpu->env, ARM_FEATURE_V7); |
| 713 |
set_feature(&cpu->env, ARM_FEATURE_VFP4); |
| 714 |
set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); |
| 715 |
set_feature(&cpu->env, ARM_FEATURE_NEON); |
| 716 |
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); |
| 717 |
set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); |
| 718 |
set_feature(&cpu->env, ARM_FEATURE_V7MP); |
| 719 |
cpu->midr = 0xffffffff;
|
| 720 |
} |
| 721 |
|
| 722 |
typedef struct ARMCPUInfo { |
| 723 |
const char *name; |
| 724 |
void (*initfn)(Object *obj);
|
| 725 |
} ARMCPUInfo; |
| 726 |
|
| 727 |
static const ARMCPUInfo arm_cpus[] = { |
| 728 |
{ .name = "arm926", .initfn = arm926_initfn },
|
| 729 |
{ .name = "arm946", .initfn = arm946_initfn },
|
| 730 |
{ .name = "arm1026", .initfn = arm1026_initfn },
|
| 731 |
/* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
|
| 732 |
* older core than plain "arm1136". In particular this does not
|
| 733 |
* have the v6K features.
|
| 734 |
*/
|
| 735 |
{ .name = "arm1136-r2", .initfn = arm1136_r2_initfn },
|
| 736 |
{ .name = "arm1136", .initfn = arm1136_initfn },
|
| 737 |
{ .name = "arm1176", .initfn = arm1176_initfn },
|
| 738 |
{ .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
|
| 739 |
{ .name = "cortex-m3", .initfn = cortex_m3_initfn },
|
| 740 |
{ .name = "cortex-a8", .initfn = cortex_a8_initfn },
|
| 741 |
{ .name = "cortex-a9", .initfn = cortex_a9_initfn },
|
| 742 |
{ .name = "cortex-a15", .initfn = cortex_a15_initfn },
|
| 743 |
{ .name = "ti925t", .initfn = ti925t_initfn },
|
| 744 |
{ .name = "sa1100", .initfn = sa1100_initfn },
|
| 745 |
{ .name = "sa1110", .initfn = sa1110_initfn },
|
| 746 |
{ .name = "pxa250", .initfn = pxa250_initfn },
|
| 747 |
{ .name = "pxa255", .initfn = pxa255_initfn },
|
| 748 |
{ .name = "pxa260", .initfn = pxa260_initfn },
|
| 749 |
{ .name = "pxa261", .initfn = pxa261_initfn },
|
| 750 |
{ .name = "pxa262", .initfn = pxa262_initfn },
|
| 751 |
/* "pxa270" is an alias for "pxa270-a0" */
|
| 752 |
{ .name = "pxa270", .initfn = pxa270a0_initfn },
|
| 753 |
{ .name = "pxa270-a0", .initfn = pxa270a0_initfn },
|
| 754 |
{ .name = "pxa270-a1", .initfn = pxa270a1_initfn },
|
| 755 |
{ .name = "pxa270-b0", .initfn = pxa270b0_initfn },
|
| 756 |
{ .name = "pxa270-b1", .initfn = pxa270b1_initfn },
|
| 757 |
{ .name = "pxa270-c0", .initfn = pxa270c0_initfn },
|
| 758 |
{ .name = "pxa270-c5", .initfn = pxa270c5_initfn },
|
| 759 |
{ .name = "any", .initfn = arm_any_initfn },
|
| 760 |
}; |
| 761 |
|
| 762 |
static void arm_cpu_class_init(ObjectClass *oc, void *data) |
| 763 |
{
|
| 764 |
ARMCPUClass *acc = ARM_CPU_CLASS(oc); |
| 765 |
CPUClass *cc = CPU_CLASS(acc); |
| 766 |
|
| 767 |
acc->parent_reset = cc->reset; |
| 768 |
cc->reset = arm_cpu_reset; |
| 769 |
} |
| 770 |
|
| 771 |
static void cpu_register(const ARMCPUInfo *info) |
| 772 |
{
|
| 773 |
TypeInfo type_info = {
|
| 774 |
.name = info->name, |
| 775 |
.parent = TYPE_ARM_CPU, |
| 776 |
.instance_size = sizeof(ARMCPU),
|
| 777 |
.instance_init = info->initfn, |
| 778 |
.class_size = sizeof(ARMCPUClass),
|
| 779 |
}; |
| 780 |
|
| 781 |
type_register_static(&type_info); |
| 782 |
} |
| 783 |
|
| 784 |
static const TypeInfo arm_cpu_type_info = { |
| 785 |
.name = TYPE_ARM_CPU, |
| 786 |
.parent = TYPE_CPU, |
| 787 |
.instance_size = sizeof(ARMCPU),
|
| 788 |
.instance_init = arm_cpu_initfn, |
| 789 |
.instance_finalize = arm_cpu_finalizefn, |
| 790 |
.abstract = true,
|
| 791 |
.class_size = sizeof(ARMCPUClass),
|
| 792 |
.class_init = arm_cpu_class_init, |
| 793 |
}; |
| 794 |
|
| 795 |
static void arm_cpu_register_types(void) |
| 796 |
{
|
| 797 |
int i;
|
| 798 |
|
| 799 |
type_register_static(&arm_cpu_type_info); |
| 800 |
for (i = 0; i < ARRAY_SIZE(arm_cpus); i++) { |
| 801 |
cpu_register(&arm_cpus[i]); |
| 802 |
} |
| 803 |
} |
| 804 |
|
| 805 |
type_init(arm_cpu_register_types) |