Archipelago » qemu

target-arm: Implement privileged-execute-never (PXN)

Implement the privileged-execute-never (PXN) translation table bit.
It is implementation-defined whether this is implemented, so we give
it its own ARM_FEATURE_ flag. LPAE requires PXN, so add also an
LPAE feature flag and the implication logic, as a placeholder...

target-arm: Remove ARM_CPUID_* macros

All the uses of ARM_CPUID() to vary behaviour have now been
removed, so we can delete the ARM_CPUID_* macros now.
The one exception is the TI915T/925T, because of its odd behaviour
where the MIDR value can be changed at runtime....

target-arm: Convert MPIDR

Convert the MPIDR to the new cp15 register scheme.
This includes giving it its own feature bit rather
than doing a CPUID value check.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

target-arm: Convert cp15 crn=0 crm={1,2} feature registers

Convert the cp15 crn=0 crm={1,2} features registers to
the new cp reg framework.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

target-arm: Convert cp15 crn=9 registers

Convert cp15 crn=9 registers (mostly cache lockdown) to the new scheme.

Note that this change makes OMAPCP cores RAZ/WI the whole c9 space. This is
a change from previous behaviour, but a return to the behaviour of commit...

target-arm: convert cp15 crn=7 registers

Convert the cp15 crn=7 registers to the new scheme.
Note that to do this we have to distinguish some registers
used on the ARM9 and ARM10 from some which are ARM1176
only. This is because the old code returned a value of 0...

target-arm: Convert cp15 crn=2 registers

Convert the cp15 crn=2 registers (MMU page table control,
MPU cache control) to the new scheme.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

target-arm: Add register_cp_regs_for_features()

Add new function register_cp_regs_for_features() as a place to
register coprocessor registers dependent on feature flags.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

target-arm: Fix 11MPCore cache type register value

Make the 11MPCore report a valid value in its cache type register
(the previous value appears to have been incorrectly copied from
the 1136/1176). In particular, do not report that we have an
aliasing VIPT cache, because this causes Linux to attempt to use...

target-arm: Change cpu_arm_init() return type to ARMCPU

Make cpu_arm_init() return a QOM ARMCPU, so that we don't need to
obtain an ARMCPU through arm_env_get_cpu() in machine init code.
This requires to adjust the inclusion site of cpu-qom.h and in turn,...

target-arm: Move cache ID register setup to cpu specific init fns

Move cache ID register reset out of cpu_reset_model_id() by
creating a field for the reset value in ARMCPU and setting it
up in the cpu specific init functions.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...

target-arm: Move SCTLR reset value setup to per cpu init fns

Move the reset value of SCTLR to ARMCPU, initialised in
the per-cpu init functions. It can then be reset by a
simple copy, and we can drop the code from cpu_reset_model_id().

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...

target-arm: Move MVFR* setup to per cpu init fns

Move the MVFR* VFP feature register values to ARMCPU,
so they are set up by the implementation-specific instance
init functions rather than in cpu_reset_model_id().

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...

target-arm: Move feature bit settings to CPU init fns

Move the setting of the feature bits from cpu_reset_model_id()
to each CPU's instance init function. This requires us to move
the features field in CPUARMState so that it is not cleared
on reset.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...

target-arm: Minimalistic CPU QOM'ification

Introduce only one non-abstract type TYPE_ARM_CPU and do not touch
cp15 registers to not interfere with Peter's ongoing remodelling.
Embed CPUARMState as first (additional) field of ARMCPU.

Let CPUClass::reset() call cpu_state_reset() for now....