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root / tcg @ 5e0f40cf

# Date Author Comment
29b69198 09/25/2013 05:46 pm Richard Henderson

tcg-ppc64: More use of TAI and SAI helper macros

Finish conversion of all memory operations.

Signed-off-by: Richard Henderson <>
8327a470 09/25/2013 05:46 pm Richard Henderson

tcg-ppc64: Use TCG_REG_Rn constants

Instead of bare N, for clarity. The only (intentional) exception made
is for insns that encode R|0, i.e. when R0 encoded into the insn is
interpreted as zero not the contents of the register.

Signed-off-by: Richard Henderson <>
5e0f40cf 09/25/2013 05:46 pm Richard Henderson

tcg-ppc64: Use tcg_out64

Signed-off-by: Richard Henderson <>
4b2b114d 09/25/2013 05:46 pm Richard Henderson

tcg-ppc: Avoid code for nop move

While these are rare from code that's been through the optimizer,
it's not uncommon within the tcg backend.

Signed-off-by: Richard Henderson <>
1d10cf98 09/25/2013 05:46 pm Richard Henderson

tcg-ppc: Cleanup tcg_out_qemu_ld/st_slow_path

Coding style fixes. Use TCGReg enumeration values instead of raw
numbers. Don't needlessly pull the whole TCGLabelQemuLdst struct
into local variables. Less conditional compilation.

No functional changes....
5b1c985b 09/25/2013 05:46 pm Richard Henderson

tcg-ppc: Use conditional branch and link to slow path

Saves one insn per slow path. Note that we can no longer use
a tail call into the store helper.

Signed-off-by: Richard Henderson <>
8f50c841 09/25/2013 05:46 pm Richard Henderson

tcg-ppc: Fix and cleanup tcg_out_tlb_check

The fix is that sparc has so many mmu modes that the last one overflowed
the 16-bit signed offset we assumed would fit. Handle this, and check
the new assumption at compile time.

Load the tlb addend earlier for the fast path....
541dd4ce 09/25/2013 05:46 pm Richard Henderson

tcg-ppc64: Reformat tcg-target.c

Whitespace and brace changes only.

Signed-off-by: Richard Henderson <>
619f90ba 09/25/2013 05:45 pm Paolo Bonzini

tcg-ppc: use new return-argument ld/st helpers

These use a 32-bit load-of-immediate to save a mflr+addi+mtlr sequence.
Tested with a Windows 98 guest (pretty much the most recent thing I
could run on my PPC machine) and kvm-unit-tests's sieve.flat. The
speed up for sieve.flat is as high as 10% for qemu-system-i386, 25%...
6a115579 09/25/2013 05:45 pm Paolo Bonzini

tcg-ppc: fix qemu_ld/qemu_st for AIX ABI

For the AIX ABI, the function pointer and small area pointer need
to be loaded in the trampoline. The trampoline instead is called
with a normal BL instruction.

Signed-off-by: Paolo Bonzini <>...
387e4176 09/20/2013 07:09 pm Richard Henderson

tcg-sparc: Fix parenthesis warning

error: suggest parentheses around comparison in operand of ‘&’ [-Werror=parentheses]

Signed-off-by: Richard Henderson <>
Signed-off-by: Michael Tokarev <>
5a93d5c2 09/03/2013 08:31 pm Anthony Liguori

Merge remote-tracking branch 'mjt/trivial-patches' into staging

  1. By Stefan Weil (6) and others
  2. Via Michael Tokarev
    • mjt/trivial-patches:
      aio / timers: use g_usleep() not sleep()
      adlib: sort offsets in portio registration
      qmp: fix integer usage in examples...
545825d4 09/03/2013 02:35 am Aurelien Jarno

Merge branch 'tcg-next' of git://github.com/rth7680/qemu

  • 'tcg-next' of git://github.com/rth7680/qemu: (29 commits)
    tcg-i386: Make use of zero-extended memory helper routines
    tcg: Introduce zero and sign-extended versions of load helpers
    exec: Split softmmu_defs.h...
988902fc 09/03/2013 02:34 am Aurelien Jarno

tcg/mips: detect available host instructions at runtime

Now that TCG supports enabling and disabling ops at runtime, it's
possible to detect the available host instructions at runtime, and
enable the corresponding ops accordingly.

Unfortunately it's not easy to probe for available instructions on...
df81ff51 09/03/2013 02:34 am Aurelien Jarno

tcg/mips: inline bswap16/bswap32 ops

Use an inline version for the bswap16 and bswap32 ops to avoid
testing for MIPS32R2 instructions availability, as these ops are
only available in that case.

Reviewed-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>
3207bf25 09/03/2013 02:34 am Aurelien Jarno

tcg/mips: only enable ext8s/ext16s ops on MIPS32R2

On MIPS ext8s and ext16s ops are implemented with a dedicated
instruction only on MIPS32R2, otherwise the same kind of implementation
than at TCG level (shift left followed by shift right) is used.

Change that by only implementing the ext8s and ext16s ops on MIPS32R2 so...
c8f94df5 09/02/2013 07:08 pm Richard Henderson

tcg: Introduce zero and sign-extended versions of load helpers

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
6fb58745 09/02/2013 07:08 pm Richard Henderson

tcg-i386: Make use of zero-extended memory helper routines

For 8 and 16-bit unsigned loads, rely on the zero-extension
from the helper and use a smaller 32-bit move insn.

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
8cfd0495 09/02/2013 07:08 pm Richard Henderson

tcg: Change tcg_gen_exit_tb argument to uintptr_t

And update all users.

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
a05b5b9b 09/02/2013 07:08 pm Richard Henderson

tcg: Change tcg_out_ld/st offset to intptr_t

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
d3452f1f 09/02/2013 07:08 pm Richard Henderson

tcg: Use appropriate types in tcg_reg_alloc_call

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
edee2579 09/02/2013 07:08 pm Richard Henderson

tcg: Fix jit debug for x32

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
357e3d8a 09/02/2013 07:08 pm Richard Henderson

tcg-i386: Use intptr_t appropriately

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
d5dad3be 09/02/2013 07:08 pm Richard Henderson

tcg-i386: Adjust tcg_out_tlb_load for x32

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
5bcebc25 09/02/2013 07:08 pm Richard Henderson

tcg-i386: Don't perform GETPC adjustment in TCG code

Since we now perform it inside the helper, no need to do it here.
This also lets us perform a tail-call from the store slow path to
the helper.

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
e58eb534 09/02/2013 07:08 pm Richard Henderson

exec: Split softmmu_defs.h

The _cmmu helpers can be moved to exec-all.h. The helpers that are
used from TCG will shortly need access to tcg_target_long so move
their declarations into tcg.h.

This requires minor include adjustments to all TCG backends.
...
03271524 09/02/2013 07:08 pm Richard Henderson

tcg: Add muluh and mulsh opcodes

Use them in places where mulu2 and muls2 are used.
Optimize mulx2 with dead low part to mulxh.

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
3c9a8f17 09/02/2013 07:08 pm Richard Henderson

tcg-mips: Implement mulsh, muluh

With the optimization in tcg_liveness_analysis,
we can avoid the MFLO when it is unused.

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
32f5717f 09/02/2013 07:08 pm Richard Henderson

tcg-ppc64: Implement muluh, mulsh

Using these instead of mulu2 and muls2 lets us avoid having to argument
overlap analysis in the backend. Normal register allocation will DTRT.

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
01547f7f 09/02/2013 07:08 pm Richard Henderson

tcg: Constant fold div, rem

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
b93949ef 09/02/2013 07:08 pm Richard Henderson

tcg: Change flush_icache_range arguments to uintptr_t

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
04d5a1da 09/02/2013 07:08 pm Richard Henderson

tcg: Change tcg_qemu_tb_exec return to uintptr_t

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
78cd7b83 09/02/2013 07:08 pm Richard Henderson

tcg: Allow TCG_TARGET_REG_BITS to be specified independantly

There are several hosts for which it would be useful to use the
available 64-bit registers in a 32-bit pointer environment.

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
d289837e 09/02/2013 07:08 pm Richard Henderson

tcg: Define TCG_TYPE_PTR properly

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
8b73d49f 09/02/2013 07:08 pm Richard Henderson

tcg: Define TCG_ptr properly

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
e2c6d1b4 09/02/2013 07:08 pm Richard Henderson

tcg: Change frame pointer offsets to intptr_t

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
2f2f244d 09/02/2013 07:08 pm Richard Henderson

tcg: Change memory offsets to intptr_t

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
2ba7fae2 09/02/2013 07:08 pm Richard Henderson

tcg: Change relocation offsets to intptr_t

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
48bc6bab 09/02/2013 07:08 pm Richard Henderson

tcg: Use uintptr_t in TCGHelperInfo

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
a32b1274 09/01/2013 06:36 pm Stefan Weil

tci: Remove function tcg_out64 (fix broken build)

Commit ac26eb69a311396668809eadbf7ff4e623447d4c added tcg_out64 to tcg/tcg.c.
tcg/tci/tcg-target.c already had a nearly identical implementation which is
now removed to fix a compiler error.

Signed-off-by: Stefan Weil <>...
401c227b 08/26/2013 11:31 pm Richard Henderson

tcg-i386: Use new return-argument ld/st helpers

Discontinue the jump-around-jump-to-jump scheme, trading it for a single
immediate move instruction. The two extra jumps always consume 7 bytes,
whereas the immediate move is either 5 or 7 bytes depending on where the...
2bb8656d 08/26/2013 11:31 pm Richard Henderson

tcg: Tidy generated code for tcg_outN

Aliasing was forcing s->code_ptr to be re-read after the store.
Keep the pointer in a local variable to help the compiler.

Signed-off-by: Richard Henderson <>
ac26eb69 08/26/2013 11:31 pm Richard Henderson

tcg-i386: Add and use tcg_out64

No point in splitting the write into 32-bit pieces.

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
8023ccda 08/26/2013 11:31 pm Richard Henderson

tcg-i386: Try pc-relative lea for constant formation

Use a 7 byte lea before the ultimate 10 byte movq.

Signed-off-by: Richard Henderson <>
c6f29ff0 08/26/2013 11:31 pm Richard Henderson

tcg-i386: Tidy qemu_ld/st slow path

Use existing stack space for arguments; don't push/pop.
Use less ifdefs and more C ifs.

Signed-off-by: Richard Henderson <>
85711e6b 08/09/2013 12:06 am James Hogan

tcg/mips: fix invalid op definition errors

tcg/mips/tcg-target.h defines various operations conditionally depending
upon the isa revision, however these operations are included in
mips_op_defs[] unconditionally resulting in the following runtime errors
if CONFIG_DEBUG_TCG is defined:...
5fe0d351 07/31/2013 02:48 am Stefan Weil

tci: Fix broken build (compiler warning caused by redefined macro BIT)

The definition of macro BIT in tci/tcg-target.c now conflicts with the
definition of the same macro in includes qemu/bitops.h.

This conflict was triggered by a recent change in the include chain of...
f290e498 07/15/2013 11:21 pm Richard Henderson

Merge git://github.com/hw-claudio/qemu-aarch64-queue into tcg-next
c6d8ed24 07/15/2013 02:13 pm Jani Kokkonen

tcg/aarch64: Implement tlb lookup fast path

Supports CONFIG_QEMU_LDST_OPTIMIZATION

Signed-off-by: Jani Kokkonen <>
Reviewed-by: Richard Henderson <>
Reviewed-by: Claudio Fontana <>
b5cc476d 07/09/2013 05:15 pm Richard Henderson

tcg-i386: Use QEMU_BUILD_BUG_ON instead of assert for frame size

We can check the condition at compile time, rather than run time.

Reviewed-by: Andreas Färber <>
Signed-off-by: Richard Henderson <>
0caa91fe 07/09/2013 05:15 pm Richard Henderson

tcg-arm: Implement tcg_register_jit

Allows unwinding past the code_gen_buffer.

Reviewed-by: Peter Maydell <>
Signed-off-by: Richard Henderson <>
45aba097 07/09/2013 05:15 pm Richard Henderson

tcg: Fix high_pc fields in .debug_info

I don't think the debugger actually looks at this for anything,
using the correct .debug_frame contents, but might as well get
it all correct.

Reviewed-by: Peter Maydell <>
Signed-off-by: Richard Henderson <>
497a22eb 07/09/2013 05:15 pm Richard Henderson

tcg: Move the CIE and FDE header definitions to common code

These will necessarily be the same layout for all hosts. This limits
the amount of boilerplate required to implement jit debug for a host.

Reviewed-by: Peter Maydell <>...
1e709f38 07/09/2013 05:15 pm Richard Henderson

tcg-arm: Use AT_PLATFORM to detect the host ISA

With this we can generate armv7 insns even when the OS compiles for a
lower common denominator. The macros are arranged so that when we do
compile for a given ISA, all of the runtime checks for that ISA are...
cb91021a 07/09/2013 05:15 pm Richard Henderson

tcg-arm: Simplify logic in detecting the ARM ISA in use

GCC 4.8 defines a handy __ARM_ARCH symbol that we can use, which
will make us nicely forward compatible with ARMv8 AArch32.

Reviewed-by: Peter Maydell <>
Signed-off-by: Richard Henderson <>
fb822738 07/09/2013 05:14 pm Richard Henderson

tcg-arm: Rename use_armv5_instructions to use_armvt5_instructions

As it really controls the availability of a thumb interworking
instruction on armv5t.

Reviewed-by: Peter Maydell <>
Signed-off-by: Richard Henderson <>
4ef76952 07/09/2013 05:14 pm Richard Henderson

tcg: Allow non-constant control macros

This allows TCG_TARGET_HAS_* to be a variable rather than a constant,
which allows easier support for differing ISA levels for the host.

Reviewed-by: Peter Maydell <>
Signed-off-by: Richard Henderson <>
c1a61f6c 07/09/2013 05:14 pm Richard Henderson

tcg: Simplify logic using TCG_OPF_NOT_PRESENT

Expand the definition of "not present" to include "should not be present".
This means we can simplify the logic surrounding the generic tcg opcodes
for which the host backend ought not be providing definitions....
72e1ccfc 07/09/2013 05:14 pm Richard Henderson

tcg-arm: Make use of conditional availability of opcodes for divide

We can now detect and use divide instructions at runtime, rather than
having to restrict their availability to compile-time.

Reviewed-by: Peter Maydell <>
Signed-off-by: Richard Henderson <>
5e1108b3 07/09/2013 05:14 pm Richard Henderson

tcg-arm: Don't implement rem

Reviewed-by: Peter Maydell <>
Signed-off-by: Richard Henderson <>
865a4671 07/09/2013 05:14 pm Richard Henderson

tcg-ppc: Don't implement rem

Reviewed-by: Andreas Färber <>
Signed-off-by: Richard Henderson <>
5b9f72ab 07/09/2013 05:14 pm Richard Henderson

tcg-ppc64: Don't implement rem

Reviewed-by: Andreas Färber <>
Signed-off-by: Richard Henderson <>
ca675f46 07/09/2013 05:14 pm Richard Henderson

tcg: Split rem requirement from div requirement

There are several hosts with only a "div" insn. Remainder is computed
manually from the quotient and inputs. We can do this generically.

Reviewed-by: Peter Maydell <>
Signed-off-by: Richard Henderson <>
b1f6dc0d 07/03/2013 03:43 pm Claudio Fontana

tcg/aarch64: implement ldst 12bit scaled uimm offset

implement the 12bit scaled unsigned immediate offset
variant of LDR/STR. This improves code size by avoiding
the movi + ldst_r for naturally aligned offsets in range.

Signed-off-by: Claudio Fontana <>...
82e0f917 06/17/2013 08:42 pm Anton Blanchard

tcg-ppc64: bswap64 rotates output 32 bits

If our input and output is in the same register, bswap64 tries to
undo a rotate of the input. This just ends up rotating the output.

Cc:
Signed-off-by: Anton Blanchard <>
Signed-off-by: Richard Henderson <>
84247357 06/17/2013 08:42 pm Anton Blanchard

tcg-ppc64: Fix add2_i64

add2_i64 was adding the lower double word to the upper double word
of each input. Fix this so we add the lower double words, then the
upper double words with carry propagation.

Cc:
Signed-off-by: Anton Blanchard <>...
d1bdd3af 06/17/2013 08:42 pm Anton Blanchard

tcg-ppc64: rotr_i32 rotates wrong amount

rotr_i32 calculates the amount to left shift and puts it into a
temporary, but then doesn't use it when doing the shift.

Cc:
Signed-off-by: Anton Blanchard <>
Signed-off-by: Richard Henderson <>
8a94cfb0 06/17/2013 08:41 pm Anton Blanchard

tcg-ppc64: Fix RLDCL opcode

The rldcl instruction doesn't have an sh field, so the minor opcode
is shifted 1 bit. We were using the XO30 macro which shifted the
minor opcode 2 bits.

Remove XO30 and add MD30 and MDS30 macros which match the
Power ISA categories....
86a6a077 06/14/2013 03:51 pm Anthony Liguori

Merge remote-tracking branch 'pmaydell/tcg-aarch64.next' into staging

  1. By Claudio Fontana (9) and others
  2. Via Peter Maydell
    • pmaydell/tcg-aarch64.next:
      MAINTAINERS: add tcg/aarch64 maintainer
      configure: permit compilation on arm aarch64
      tcg/aarch64: implement user mode qemu ld/st...
9c4a059d 06/12/2013 06:20 pm Claudio Fontana

tcg/aarch64: implement byte swap operations

implement the optional byte swap operations with the dedicated
aarch64 instructions.

Signed-off-by: Claudio Fontana <>
Reviewed-by: Richard Henderson <>
Message-id: ...
31f1275b 06/12/2013 06:20 pm Claudio Fontana

tcg/aarch64: implement sign/zero extend operations

implement the optional sign/zero extend operations with the dedicated
aarch64 instructions.

Signed-off-by: Claudio Fontana <>
Reviewed-by: Richard Henderson <>
Message-id: ...
6a91c7c9 06/12/2013 06:20 pm Jani Kokkonen

tcg/aarch64: implement user mode qemu ld/st

also put aarch64 in the list of archs that do not need an ldscript.

Signed-off-by: Jani Kokkoken <>
Signed-off-by: Claudio Fontana <>
Reviewed-by: Richard Henderson <>...
4a136e0a 06/12/2013 06:20 pm Claudio Fontana

tcg/aarch64: implement new TCG target for aarch64

add preliminary support for TCG target aarch64.

Signed-off-by: Claudio Fontana <>
Reviewed-by: Richard Henderson <>
Reviewed-by: Peter Maydell <>...
36fac14a 06/12/2013 06:20 pm Claudio Fontana

tcg/aarch64: improve arith shifted regs operations

for arith operations, add SUBS, ANDS, ADDS and add a shift parameter
so that all arith instructions can make use of shifted registers.

Signed-off-by: Claudio Fontana <>
Reviewed-by: Richard Henderson <>...
7deea126 06/12/2013 06:20 pm Claudio Fontana

tcg/aarch64: implement AND/TEST immediate pattern

add functions to AND/TEST registers with immediate patterns.

Signed-off-by: Claudio Fontana <>
Reviewed-by: Richard Henderson <>
Message-id: ...
56bbc2f9 06/05/2013 03:54 pm Richard Henderson

tcg: Remove redundant tcg_target_init checks

We've got a compile-time check for the condition in exec/cpu-defs.h.

Reviewed-by: Andreas Färber <>
Reviewed-by: liguang <>
Signed-off-by: Richard Henderson <>
66e61b55 05/09/2013 05:14 pm Aurelien Jarno

tcg/optimize: fix setcond2 optimization

When setcond2 is rewritten into setcond, the state of the destination
temp should be reset, so that a copy of the previous value is not
used instead of the result.

Reported-by: Michael Tokarev <>
Reviewed-by: Richard Henderson <>...
c9e53a4c 05/03/2013 12:53 pm Richard Henderson

tcg-arm: Use movi32 in exit_tb

Avoid the mini constant pool for armv7, and avoid replicating
the test for pre-v7.

Signed-off-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>
8ddaeb1b 05/03/2013 12:53 pm Richard Henderson

tcg-arm: Fix 64-bit tlb load for pre-v6

Found by inspection, since the effect of the bug was simply to
send all memory ops through the slow path.

Signed-off-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>
cee87be8 04/27/2013 03:16 am Richard Henderson

tcg-arm: Split out tcg_out_tlb_read

Share code between qemu_ld and qemu_st to process the tlb.

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
702b33b1 04/27/2013 03:16 am Richard Henderson

tcg-arm: Improve scheduling of tcg_out_tlb_read

The schedule was fully serial, with no possibility for dual issue.
The old schedule had a minimal issue of 7 cycles; the new schedule
has a minimal issue of 5 cycles.

Signed-off-by: Richard Henderson <>
595b5397 04/27/2013 03:16 am Richard Henderson

tcg-arm: Delete the 'S' constraint

After the previous patch, 's' and 'S' are the same.

Signed-off-by: Richard Henderson <>
302fdde7 04/27/2013 03:16 am Richard Henderson

tcg-arm: Use movi32 + blx for calls on v7

Work better with branch predition when we have movw+movt,
as the size of the code is the same. Perhaps re-evaluate
when we have a proper constant pool.

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
df5e0ef7 04/27/2013 03:16 am Richard Henderson

tcg-arm: Convert to CONFIG_QEMU_LDST_OPTIMIZATION

Move the slow path out of line, as the TODO's mention.
This allows the fast path to be unconditional, which can
speed up the fast path as well, depending on the core.

Signed-off-by: Richard Henderson <>
96fbd7de 04/27/2013 03:16 am Richard Henderson

tcg-arm: Remove long jump from tcg_out_goto_label

Branches within a TB will always be within 16MB.

Signed-off-by: Richard Henderson <>
b6b24cb0 04/27/2013 03:16 am Richard Henderson

tcg-arm: Implement deposit for armv7

We have BFI and BFC available for implementing it.

Signed-off-by: Richard Henderson <>
0637c56c 04/27/2013 03:16 am Richard Henderson

tcg-arm: Implement division instructions

An armv7 extension implements division, present on Cortex A15.

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
4346457a 04/27/2013 03:16 am Richard Henderson

tcg-arm: Use TCG_REG_TMP name for the tcg temporary

Don't hard-code R8.

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
13dd6fb9 04/27/2013 03:16 am Richard Henderson

tcg-arm: Use R12 for the tcg temporary

R12 is call clobbered, while R8 is call saved. This change
gives tcg one more call saved register for real data.

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
34358a12 04/27/2013 03:16 am Richard Henderson

tcg-arm: Cleanup multiply subroutines

Make the code more readable by only having one copy of the magic
numbers, swapping registers as needed prior to that. Speed the
compiler by not applying the rd == rn avoidance for v6 or later.

Reviewed-by: Aurelien Jarno <>...
9feac1d7 04/27/2013 03:16 am Richard Henderson

tcg-arm: Cleanup most primitive load store subroutines

Use even more primitive helper functions to avoid lots of duplicated code.

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
a9a86ae9 04/27/2013 03:16 am Richard Henderson

tcg-arm: Handle negated constant arguments to and/sub

This greatly improves code generation for addition of small
negative constants.

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
d9fda575 04/27/2013 03:16 am Richard Henderson

tcg-arm: Allow constant first argument to sub

This allows the generation of RSB instructions.

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
5d53b4c9 04/27/2013 03:16 am Richard Henderson

tcg-arm: Use tcg_out_dat_rIN for compares

This allows us to emit CMN instructions.

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
2df3f1ee 04/27/2013 03:16 am Richard Henderson

tcg-arm: Handle constant arguments to add2/sub2

We get to re-use the _rIN and _rIK subroutines to handle the various
combinations of add vs sub. Fold the << 21 into the opcode enum values
so that we can explicitly add TO_CPSR as desired.

Reviewed-by: Aurelien Jarno <>...
e86e0f28 04/27/2013 03:16 am Richard Henderson

tcg-arm: Improve constant generation

Try fully rotated arguments to mov and mvn before trying movt
or full decomposition. Begin decomposition with mvn when it
looks like it'll help. Examples include

: mov r9, #0x00000fa0
: orr r9, r9, #0x000ee000...
19b62bf4 04/27/2013 03:16 am Richard Henderson

tcg-arm: Use bic to implement and with constant

This greatly improves the code we can produce for deposit
without armv7 support.

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
d6b64b2b 04/27/2013 03:15 am Richard Henderson

tcg: Log the contents of the prologue with -d out_asm

This makes it easier to verify changes to the code
generating the prologue.

[Aurelien: change the format from %i to %zu]

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
fc4d60ee 04/27/2013 02:19 am Richard Henderson

tcg-arm: Fix local stack frame

We were not allocating TCG_STATIC_CALL_ARGS_SIZE, so this meant that
any helper with more than 4 arguments would clobber the saved regs.
Realizing that we're supposed to have this memory pre-allocated means
we can clean up the tcg_out_arg functions, which were trying to do...
ed605126 04/27/2013 02:10 am Aurelien Jarno

tcg: fix deposit_i64 op on 32-bit targets

On 32-bit TCG targets, when emulating deposit_i64 with a mov_i32 +
deposit_i32, care should be taken to not overwrite the low part of
the second argument before the deposit when it is the same the
destination.

This fixes the shld instruction in qemu-system-x86_64, which in turns...