root / hw / slavio_intctl.c @ 5e22c276
History | View | Annotate | Download (13.8 kB)
1 | e80cfcfc | bellard | /*
|
---|---|---|---|
2 | e80cfcfc | bellard | * QEMU Sparc SLAVIO interrupt controller emulation
|
3 | 5fafdf24 | ths | *
|
4 | 66321a11 | bellard | * Copyright (c) 2003-2005 Fabrice Bellard
|
5 | 5fafdf24 | ths | *
|
6 | e80cfcfc | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
|
7 | e80cfcfc | bellard | * of this software and associated documentation files (the "Software"), to deal
|
8 | e80cfcfc | bellard | * in the Software without restriction, including without limitation the rights
|
9 | e80cfcfc | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
10 | e80cfcfc | bellard | * copies of the Software, and to permit persons to whom the Software is
|
11 | e80cfcfc | bellard | * furnished to do so, subject to the following conditions:
|
12 | e80cfcfc | bellard | *
|
13 | e80cfcfc | bellard | * The above copyright notice and this permission notice shall be included in
|
14 | e80cfcfc | bellard | * all copies or substantial portions of the Software.
|
15 | e80cfcfc | bellard | *
|
16 | e80cfcfc | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
17 | e80cfcfc | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
18 | e80cfcfc | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
19 | e80cfcfc | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
20 | e80cfcfc | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
21 | e80cfcfc | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
22 | e80cfcfc | bellard | * THE SOFTWARE.
|
23 | e80cfcfc | bellard | */
|
24 | a1961a4b | Blue Swirl | |
25 | 87ecb68b | pbrook | #include "sun4m.h" |
26 | 83c9089e | Paolo Bonzini | #include "monitor/monitor.h" |
27 | a1961a4b | Blue Swirl | #include "sysbus.h" |
28 | 97bf4851 | Blue Swirl | #include "trace.h" |
29 | 87ecb68b | pbrook | |
30 | e80cfcfc | bellard | //#define DEBUG_IRQ_COUNT
|
31 | e80cfcfc | bellard | |
32 | e80cfcfc | bellard | /*
|
33 | e80cfcfc | bellard | * Registers of interrupt controller in sun4m.
|
34 | e80cfcfc | bellard | *
|
35 | e80cfcfc | bellard | * This is the interrupt controller part of chip STP2001 (Slave I/O), also
|
36 | e80cfcfc | bellard | * produced as NCR89C105. See
|
37 | e80cfcfc | bellard | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
|
38 | e80cfcfc | bellard | *
|
39 | e80cfcfc | bellard | * There is a system master controller and one for each cpu.
|
40 | 5fafdf24 | ths | *
|
41 | e80cfcfc | bellard | */
|
42 | e80cfcfc | bellard | |
43 | e80cfcfc | bellard | #define MAX_CPUS 16 |
44 | b3a23197 | blueswir1 | #define MAX_PILS 16 |
45 | e80cfcfc | bellard | |
46 | a1961a4b | Blue Swirl | struct SLAVIO_INTCTLState;
|
47 | a1961a4b | Blue Swirl | |
48 | a1961a4b | Blue Swirl | typedef struct SLAVIO_CPUINTCTLState { |
49 | 8bb5ef33 | Benoît Canet | MemoryRegion iomem; |
50 | a1961a4b | Blue Swirl | struct SLAVIO_INTCTLState *master;
|
51 | 07dd0035 | Blue Swirl | uint32_t intreg_pending; |
52 | a1961a4b | Blue Swirl | uint32_t cpu; |
53 | 462eda24 | Blue Swirl | uint32_t irl_out; |
54 | a1961a4b | Blue Swirl | } SLAVIO_CPUINTCTLState; |
55 | a8f48dcc | blueswir1 | |
56 | e80cfcfc | bellard | typedef struct SLAVIO_INTCTLState { |
57 | a1961a4b | Blue Swirl | SysBusDevice busdev; |
58 | 13c89a11 | Benoît Canet | MemoryRegion iomem; |
59 | e80cfcfc | bellard | #ifdef DEBUG_IRQ_COUNT
|
60 | e80cfcfc | bellard | uint64_t irq_count[32];
|
61 | e80cfcfc | bellard | #endif
|
62 | a1961a4b | Blue Swirl | qemu_irq cpu_irqs[MAX_CPUS][MAX_PILS]; |
63 | a1961a4b | Blue Swirl | SLAVIO_CPUINTCTLState slaves[MAX_CPUS]; |
64 | 07dd0035 | Blue Swirl | uint32_t intregm_pending; |
65 | 07dd0035 | Blue Swirl | uint32_t intregm_disabled; |
66 | 07dd0035 | Blue Swirl | uint32_t target_cpu; |
67 | e80cfcfc | bellard | } SLAVIO_INTCTLState; |
68 | e80cfcfc | bellard | |
69 | e80cfcfc | bellard | #define INTCTL_MAXADDR 0xf |
70 | 5aca8c3b | blueswir1 | #define INTCTL_SIZE (INTCTL_MAXADDR + 1) |
71 | a8f48dcc | blueswir1 | #define INTCTLM_SIZE 0x14 |
72 | 80be36b8 | blueswir1 | #define MASTER_IRQ_MASK ~0x0fa2007f |
73 | 9a87ce9b | blueswir1 | #define MASTER_DISABLE 0x80000000 |
74 | 6341fdcb | blueswir1 | #define CPU_SOFTIRQ_MASK 0xfffe0000 |
75 | 462eda24 | Blue Swirl | #define CPU_IRQ_INT15_IN (1 << 15) |
76 | 462eda24 | Blue Swirl | #define CPU_IRQ_TIMER_IN (1 << 14) |
77 | 9a87ce9b | blueswir1 | |
78 | 0d0a7e69 | Blue Swirl | static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs); |
79 | e80cfcfc | bellard | |
80 | e80cfcfc | bellard | // per-cpu interrupt controller
|
81 | a8170e5e | Avi Kivity | static uint64_t slavio_intctl_mem_readl(void *opaque, hwaddr addr, |
82 | 8bb5ef33 | Benoît Canet | unsigned size)
|
83 | e80cfcfc | bellard | { |
84 | a8f48dcc | blueswir1 | SLAVIO_CPUINTCTLState *s = opaque; |
85 | dd4131b3 | blueswir1 | uint32_t saddr, ret; |
86 | e80cfcfc | bellard | |
87 | a8f48dcc | blueswir1 | saddr = addr >> 2;
|
88 | e80cfcfc | bellard | switch (saddr) {
|
89 | e80cfcfc | bellard | case 0: |
90 | a8f48dcc | blueswir1 | ret = s->intreg_pending; |
91 | dd4131b3 | blueswir1 | break;
|
92 | e80cfcfc | bellard | default:
|
93 | dd4131b3 | blueswir1 | ret = 0;
|
94 | dd4131b3 | blueswir1 | break;
|
95 | e80cfcfc | bellard | } |
96 | 97bf4851 | Blue Swirl | trace_slavio_intctl_mem_readl(s->cpu, addr, ret); |
97 | dd4131b3 | blueswir1 | |
98 | dd4131b3 | blueswir1 | return ret;
|
99 | e80cfcfc | bellard | } |
100 | e80cfcfc | bellard | |
101 | a8170e5e | Avi Kivity | static void slavio_intctl_mem_writel(void *opaque, hwaddr addr, |
102 | 8bb5ef33 | Benoît Canet | uint64_t val, unsigned size)
|
103 | e80cfcfc | bellard | { |
104 | a8f48dcc | blueswir1 | SLAVIO_CPUINTCTLState *s = opaque; |
105 | e80cfcfc | bellard | uint32_t saddr; |
106 | e80cfcfc | bellard | |
107 | a8f48dcc | blueswir1 | saddr = addr >> 2;
|
108 | 97bf4851 | Blue Swirl | trace_slavio_intctl_mem_writel(s->cpu, addr, val); |
109 | e80cfcfc | bellard | switch (saddr) {
|
110 | e80cfcfc | bellard | case 1: // clear pending softints |
111 | 462eda24 | Blue Swirl | val &= CPU_SOFTIRQ_MASK | CPU_IRQ_INT15_IN; |
112 | a8f48dcc | blueswir1 | s->intreg_pending &= ~val; |
113 | 0d0a7e69 | Blue Swirl | slavio_check_interrupts(s->master, 1);
|
114 | 97bf4851 | Blue Swirl | trace_slavio_intctl_mem_writel_clear(s->cpu, val, s->intreg_pending); |
115 | f930d07e | blueswir1 | break;
|
116 | e80cfcfc | bellard | case 2: // set softint |
117 | 6341fdcb | blueswir1 | val &= CPU_SOFTIRQ_MASK; |
118 | a8f48dcc | blueswir1 | s->intreg_pending |= val; |
119 | 0d0a7e69 | Blue Swirl | slavio_check_interrupts(s->master, 1);
|
120 | 97bf4851 | Blue Swirl | trace_slavio_intctl_mem_writel_set(s->cpu, val, s->intreg_pending); |
121 | f930d07e | blueswir1 | break;
|
122 | e80cfcfc | bellard | default:
|
123 | f930d07e | blueswir1 | break;
|
124 | e80cfcfc | bellard | } |
125 | e80cfcfc | bellard | } |
126 | e80cfcfc | bellard | |
127 | 8bb5ef33 | Benoît Canet | static const MemoryRegionOps slavio_intctl_mem_ops = { |
128 | 8bb5ef33 | Benoît Canet | .read = slavio_intctl_mem_readl, |
129 | 8bb5ef33 | Benoît Canet | .write = slavio_intctl_mem_writel, |
130 | 8bb5ef33 | Benoît Canet | .endianness = DEVICE_NATIVE_ENDIAN, |
131 | 8bb5ef33 | Benoît Canet | .valid = { |
132 | 8bb5ef33 | Benoît Canet | .min_access_size = 4,
|
133 | 8bb5ef33 | Benoît Canet | .max_access_size = 4,
|
134 | 8bb5ef33 | Benoît Canet | }, |
135 | e80cfcfc | bellard | }; |
136 | e80cfcfc | bellard | |
137 | e80cfcfc | bellard | // master system interrupt controller
|
138 | a8170e5e | Avi Kivity | static uint64_t slavio_intctlm_mem_readl(void *opaque, hwaddr addr, |
139 | 13c89a11 | Benoît Canet | unsigned size)
|
140 | e80cfcfc | bellard | { |
141 | e80cfcfc | bellard | SLAVIO_INTCTLState *s = opaque; |
142 | dd4131b3 | blueswir1 | uint32_t saddr, ret; |
143 | e80cfcfc | bellard | |
144 | a8f48dcc | blueswir1 | saddr = addr >> 2;
|
145 | e80cfcfc | bellard | switch (saddr) {
|
146 | e80cfcfc | bellard | case 0: |
147 | 9a87ce9b | blueswir1 | ret = s->intregm_pending & ~MASTER_DISABLE; |
148 | dd4131b3 | blueswir1 | break;
|
149 | e80cfcfc | bellard | case 1: |
150 | 80be36b8 | blueswir1 | ret = s->intregm_disabled & MASTER_IRQ_MASK; |
151 | dd4131b3 | blueswir1 | break;
|
152 | e80cfcfc | bellard | case 4: |
153 | dd4131b3 | blueswir1 | ret = s->target_cpu; |
154 | dd4131b3 | blueswir1 | break;
|
155 | e80cfcfc | bellard | default:
|
156 | dd4131b3 | blueswir1 | ret = 0;
|
157 | dd4131b3 | blueswir1 | break;
|
158 | e80cfcfc | bellard | } |
159 | 97bf4851 | Blue Swirl | trace_slavio_intctlm_mem_readl(addr, ret); |
160 | dd4131b3 | blueswir1 | |
161 | dd4131b3 | blueswir1 | return ret;
|
162 | e80cfcfc | bellard | } |
163 | e80cfcfc | bellard | |
164 | a8170e5e | Avi Kivity | static void slavio_intctlm_mem_writel(void *opaque, hwaddr addr, |
165 | 13c89a11 | Benoît Canet | uint64_t val, unsigned size)
|
166 | e80cfcfc | bellard | { |
167 | e80cfcfc | bellard | SLAVIO_INTCTLState *s = opaque; |
168 | e80cfcfc | bellard | uint32_t saddr; |
169 | e80cfcfc | bellard | |
170 | a8f48dcc | blueswir1 | saddr = addr >> 2;
|
171 | 97bf4851 | Blue Swirl | trace_slavio_intctlm_mem_writel(addr, val); |
172 | e80cfcfc | bellard | switch (saddr) {
|
173 | e80cfcfc | bellard | case 2: // clear (enable) |
174 | f930d07e | blueswir1 | // Force clear unused bits
|
175 | 9a87ce9b | blueswir1 | val &= MASTER_IRQ_MASK; |
176 | f930d07e | blueswir1 | s->intregm_disabled &= ~val; |
177 | 97bf4851 | Blue Swirl | trace_slavio_intctlm_mem_writel_enable(val, s->intregm_disabled); |
178 | 0d0a7e69 | Blue Swirl | slavio_check_interrupts(s, 1);
|
179 | f930d07e | blueswir1 | break;
|
180 | 10760f0f | Artyom Tarasenko | case 3: // set (disable; doesn't affect pending) |
181 | f930d07e | blueswir1 | // Force clear unused bits
|
182 | 9a87ce9b | blueswir1 | val &= MASTER_IRQ_MASK; |
183 | f930d07e | blueswir1 | s->intregm_disabled |= val; |
184 | 0d0a7e69 | Blue Swirl | slavio_check_interrupts(s, 1);
|
185 | 97bf4851 | Blue Swirl | trace_slavio_intctlm_mem_writel_disable(val, s->intregm_disabled); |
186 | f930d07e | blueswir1 | break;
|
187 | e80cfcfc | bellard | case 4: |
188 | f930d07e | blueswir1 | s->target_cpu = val & (MAX_CPUS - 1);
|
189 | 0d0a7e69 | Blue Swirl | slavio_check_interrupts(s, 1);
|
190 | 97bf4851 | Blue Swirl | trace_slavio_intctlm_mem_writel_target(s->target_cpu); |
191 | f930d07e | blueswir1 | break;
|
192 | e80cfcfc | bellard | default:
|
193 | f930d07e | blueswir1 | break;
|
194 | e80cfcfc | bellard | } |
195 | e80cfcfc | bellard | } |
196 | e80cfcfc | bellard | |
197 | 13c89a11 | Benoît Canet | static const MemoryRegionOps slavio_intctlm_mem_ops = { |
198 | 13c89a11 | Benoît Canet | .read = slavio_intctlm_mem_readl, |
199 | 13c89a11 | Benoît Canet | .write = slavio_intctlm_mem_writel, |
200 | 13c89a11 | Benoît Canet | .endianness = DEVICE_NATIVE_ENDIAN, |
201 | 13c89a11 | Benoît Canet | .valid = { |
202 | 13c89a11 | Benoît Canet | .min_access_size = 4,
|
203 | 13c89a11 | Benoît Canet | .max_access_size = 4,
|
204 | 13c89a11 | Benoît Canet | }, |
205 | e80cfcfc | bellard | }; |
206 | e80cfcfc | bellard | |
207 | d453c2c3 | Blue Swirl | void slavio_pic_info(Monitor *mon, DeviceState *dev)
|
208 | e80cfcfc | bellard | { |
209 | d453c2c3 | Blue Swirl | SysBusDevice *sd; |
210 | d453c2c3 | Blue Swirl | SLAVIO_INTCTLState *s; |
211 | e80cfcfc | bellard | int i;
|
212 | e80cfcfc | bellard | |
213 | d453c2c3 | Blue Swirl | sd = sysbus_from_qdev(dev); |
214 | d453c2c3 | Blue Swirl | s = FROM_SYSBUS(SLAVIO_INTCTLState, sd); |
215 | e80cfcfc | bellard | for (i = 0; i < MAX_CPUS; i++) { |
216 | 376253ec | aliguori | monitor_printf(mon, "per-cpu %d: pending 0x%08x\n", i,
|
217 | a1961a4b | Blue Swirl | s->slaves[i].intreg_pending); |
218 | e80cfcfc | bellard | } |
219 | 376253ec | aliguori | monitor_printf(mon, "master: pending 0x%08x, disabled 0x%08x\n",
|
220 | 376253ec | aliguori | s->intregm_pending, s->intregm_disabled); |
221 | e80cfcfc | bellard | } |
222 | e80cfcfc | bellard | |
223 | d453c2c3 | Blue Swirl | void slavio_irq_info(Monitor *mon, DeviceState *dev)
|
224 | e80cfcfc | bellard | { |
225 | e80cfcfc | bellard | #ifndef DEBUG_IRQ_COUNT
|
226 | 376253ec | aliguori | monitor_printf(mon, "irq statistic code not compiled.\n");
|
227 | e80cfcfc | bellard | #else
|
228 | d453c2c3 | Blue Swirl | SysBusDevice *sd; |
229 | d453c2c3 | Blue Swirl | SLAVIO_INTCTLState *s; |
230 | e80cfcfc | bellard | int i;
|
231 | e80cfcfc | bellard | int64_t count; |
232 | e80cfcfc | bellard | |
233 | d453c2c3 | Blue Swirl | sd = sysbus_from_qdev(dev); |
234 | d453c2c3 | Blue Swirl | s = FROM_SYSBUS(SLAVIO_INTCTLState, sd); |
235 | 376253ec | aliguori | monitor_printf(mon, "IRQ statistics:\n");
|
236 | e80cfcfc | bellard | for (i = 0; i < 32; i++) { |
237 | e80cfcfc | bellard | count = s->irq_count[i]; |
238 | e80cfcfc | bellard | if (count > 0) |
239 | 376253ec | aliguori | monitor_printf(mon, "%2d: %" PRId64 "\n", i, count); |
240 | e80cfcfc | bellard | } |
241 | e80cfcfc | bellard | #endif
|
242 | e80cfcfc | bellard | } |
243 | e80cfcfc | bellard | |
244 | 68556e2e | Blue Swirl | static const uint32_t intbit_to_level[] = { |
245 | 462eda24 | Blue Swirl | 2, 3, 5, 7, 9, 11, 13, 2, 3, 5, 7, 9, 11, 13, 12, 12, |
246 | 462eda24 | Blue Swirl | 6, 13, 4, 10, 8, 9, 11, 0, 0, 0, 0, 15, 15, 15, 15, 0, |
247 | 68556e2e | Blue Swirl | }; |
248 | 68556e2e | Blue Swirl | |
249 | 0d0a7e69 | Blue Swirl | static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs) |
250 | 66321a11 | bellard | { |
251 | 327ac2e7 | blueswir1 | uint32_t pending = s->intregm_pending, pil_pending; |
252 | 327ac2e7 | blueswir1 | unsigned int i, j; |
253 | 66321a11 | bellard | |
254 | 66321a11 | bellard | pending &= ~s->intregm_disabled; |
255 | 66321a11 | bellard | |
256 | 97bf4851 | Blue Swirl | trace_slavio_check_interrupts(pending, s->intregm_disabled); |
257 | ba3c64fb | bellard | for (i = 0; i < MAX_CPUS; i++) { |
258 | 327ac2e7 | blueswir1 | pil_pending = 0;
|
259 | 462eda24 | Blue Swirl | |
260 | 462eda24 | Blue Swirl | /* If we are the current interrupt target, get hard interrupts */
|
261 | 9a87ce9b | blueswir1 | if (pending && !(s->intregm_disabled & MASTER_DISABLE) &&
|
262 | b3a23197 | blueswir1 | (i == s->target_cpu)) { |
263 | b3a23197 | blueswir1 | for (j = 0; j < 32; j++) { |
264 | 462eda24 | Blue Swirl | if ((pending & (1 << j)) && intbit_to_level[j]) { |
265 | 68556e2e | Blue Swirl | pil_pending |= 1 << intbit_to_level[j];
|
266 | 462eda24 | Blue Swirl | } |
267 | 462eda24 | Blue Swirl | } |
268 | 462eda24 | Blue Swirl | } |
269 | 462eda24 | Blue Swirl | |
270 | 462eda24 | Blue Swirl | /* Calculate current pending hard interrupts for display */
|
271 | 462eda24 | Blue Swirl | s->slaves[i].intreg_pending &= CPU_SOFTIRQ_MASK | CPU_IRQ_INT15_IN | |
272 | 462eda24 | Blue Swirl | CPU_IRQ_TIMER_IN; |
273 | 462eda24 | Blue Swirl | if (i == s->target_cpu) {
|
274 | 462eda24 | Blue Swirl | for (j = 0; j < 32; j++) { |
275 | 462eda24 | Blue Swirl | if ((s->intregm_pending & (1 << j)) && intbit_to_level[j]) { |
276 | 462eda24 | Blue Swirl | s->slaves[i].intreg_pending |= 1 << intbit_to_level[j];
|
277 | 462eda24 | Blue Swirl | } |
278 | b3a23197 | blueswir1 | } |
279 | b3a23197 | blueswir1 | } |
280 | 462eda24 | Blue Swirl | |
281 | 94c5f455 | Artyom Tarasenko | /* Level 15 and CPU timer interrupts are only masked when
|
282 | 94c5f455 | Artyom Tarasenko | the MASTER_DISABLE bit is set */
|
283 | 94c5f455 | Artyom Tarasenko | if (!(s->intregm_disabled & MASTER_DISABLE)) {
|
284 | 94c5f455 | Artyom Tarasenko | pil_pending |= s->slaves[i].intreg_pending & |
285 | 94c5f455 | Artyom Tarasenko | (CPU_IRQ_INT15_IN | CPU_IRQ_TIMER_IN); |
286 | 94c5f455 | Artyom Tarasenko | } |
287 | 462eda24 | Blue Swirl | |
288 | 462eda24 | Blue Swirl | /* Add soft interrupts */
|
289 | a1961a4b | Blue Swirl | pil_pending |= (s->slaves[i].intreg_pending & CPU_SOFTIRQ_MASK) >> 16;
|
290 | 327ac2e7 | blueswir1 | |
291 | 0d0a7e69 | Blue Swirl | if (set_irqs) {
|
292 | c84a88d8 | Peter Maydell | /* Since there is not really an interrupt 0 (and pil_pending
|
293 | c84a88d8 | Peter Maydell | * and irl_out bit zero are thus always zero) there is no need
|
294 | c84a88d8 | Peter Maydell | * to do anything with cpu_irqs[i][0] and it is OK not to do
|
295 | c84a88d8 | Peter Maydell | * the j=0 iteration of this loop.
|
296 | c84a88d8 | Peter Maydell | */
|
297 | c84a88d8 | Peter Maydell | for (j = MAX_PILS-1; j > 0; j--) { |
298 | 0d0a7e69 | Blue Swirl | if (pil_pending & (1 << j)) { |
299 | 462eda24 | Blue Swirl | if (!(s->slaves[i].irl_out & (1 << j))) { |
300 | 0d0a7e69 | Blue Swirl | qemu_irq_raise(s->cpu_irqs[i][j]); |
301 | 0d0a7e69 | Blue Swirl | } |
302 | 0d0a7e69 | Blue Swirl | } else {
|
303 | 462eda24 | Blue Swirl | if (s->slaves[i].irl_out & (1 << j)) { |
304 | 0d0a7e69 | Blue Swirl | qemu_irq_lower(s->cpu_irqs[i][j]); |
305 | 0d0a7e69 | Blue Swirl | } |
306 | 0d0a7e69 | Blue Swirl | } |
307 | ba3c64fb | bellard | } |
308 | ba3c64fb | bellard | } |
309 | 462eda24 | Blue Swirl | s->slaves[i].irl_out = pil_pending; |
310 | ba3c64fb | bellard | } |
311 | 66321a11 | bellard | } |
312 | 66321a11 | bellard | |
313 | e80cfcfc | bellard | /*
|
314 | e80cfcfc | bellard | * "irq" here is the bit number in the system interrupt register to
|
315 | e80cfcfc | bellard | * separate serial and keyboard interrupts sharing a level.
|
316 | e80cfcfc | bellard | */
|
317 | d7edfd27 | blueswir1 | static void slavio_set_irq(void *opaque, int irq, int level) |
318 | e80cfcfc | bellard | { |
319 | e80cfcfc | bellard | SLAVIO_INTCTLState *s = opaque; |
320 | b3a23197 | blueswir1 | uint32_t mask = 1 << irq;
|
321 | 68556e2e | Blue Swirl | uint32_t pil = intbit_to_level[irq]; |
322 | 462eda24 | Blue Swirl | unsigned int i; |
323 | b3a23197 | blueswir1 | |
324 | 97bf4851 | Blue Swirl | trace_slavio_set_irq(s->target_cpu, irq, pil, level); |
325 | b3a23197 | blueswir1 | if (pil > 0) { |
326 | b3a23197 | blueswir1 | if (level) {
|
327 | 327ac2e7 | blueswir1 | #ifdef DEBUG_IRQ_COUNT
|
328 | 327ac2e7 | blueswir1 | s->irq_count[pil]++; |
329 | 327ac2e7 | blueswir1 | #endif
|
330 | b3a23197 | blueswir1 | s->intregm_pending |= mask; |
331 | 462eda24 | Blue Swirl | if (pil == 15) { |
332 | 462eda24 | Blue Swirl | for (i = 0; i < MAX_CPUS; i++) { |
333 | 462eda24 | Blue Swirl | s->slaves[i].intreg_pending |= 1 << pil;
|
334 | 462eda24 | Blue Swirl | } |
335 | 462eda24 | Blue Swirl | } |
336 | b3a23197 | blueswir1 | } else {
|
337 | b3a23197 | blueswir1 | s->intregm_pending &= ~mask; |
338 | 462eda24 | Blue Swirl | if (pil == 15) { |
339 | 462eda24 | Blue Swirl | for (i = 0; i < MAX_CPUS; i++) { |
340 | 462eda24 | Blue Swirl | s->slaves[i].intreg_pending &= ~(1 << pil);
|
341 | 462eda24 | Blue Swirl | } |
342 | 462eda24 | Blue Swirl | } |
343 | b3a23197 | blueswir1 | } |
344 | 0d0a7e69 | Blue Swirl | slavio_check_interrupts(s, 1);
|
345 | e80cfcfc | bellard | } |
346 | e80cfcfc | bellard | } |
347 | e80cfcfc | bellard | |
348 | d7edfd27 | blueswir1 | static void slavio_set_timer_irq_cpu(void *opaque, int cpu, int level) |
349 | ba3c64fb | bellard | { |
350 | ba3c64fb | bellard | SLAVIO_INTCTLState *s = opaque; |
351 | ba3c64fb | bellard | |
352 | 97bf4851 | Blue Swirl | trace_slavio_set_timer_irq_cpu(cpu, level); |
353 | d7edfd27 | blueswir1 | |
354 | e3a79bca | blueswir1 | if (level) {
|
355 | 462eda24 | Blue Swirl | s->slaves[cpu].intreg_pending |= CPU_IRQ_TIMER_IN; |
356 | e3a79bca | blueswir1 | } else {
|
357 | 462eda24 | Blue Swirl | s->slaves[cpu].intreg_pending &= ~CPU_IRQ_TIMER_IN; |
358 | e3a79bca | blueswir1 | } |
359 | d7edfd27 | blueswir1 | |
360 | 0d0a7e69 | Blue Swirl | slavio_check_interrupts(s, 1);
|
361 | ba3c64fb | bellard | } |
362 | ba3c64fb | bellard | |
363 | a1961a4b | Blue Swirl | static void slavio_set_irq_all(void *opaque, int irq, int level) |
364 | a1961a4b | Blue Swirl | { |
365 | a1961a4b | Blue Swirl | if (irq < 32) { |
366 | a1961a4b | Blue Swirl | slavio_set_irq(opaque, irq, level); |
367 | a1961a4b | Blue Swirl | } else {
|
368 | a1961a4b | Blue Swirl | slavio_set_timer_irq_cpu(opaque, irq - 32, level);
|
369 | a1961a4b | Blue Swirl | } |
370 | a1961a4b | Blue Swirl | } |
371 | a1961a4b | Blue Swirl | |
372 | e59fb374 | Juan Quintela | static int vmstate_intctl_post_load(void *opaque, int version_id) |
373 | e80cfcfc | bellard | { |
374 | e80cfcfc | bellard | SLAVIO_INTCTLState *s = opaque; |
375 | 3b46e624 | ths | |
376 | c9e95029 | Blue Swirl | slavio_check_interrupts(s, 0);
|
377 | c9e95029 | Blue Swirl | return 0; |
378 | e80cfcfc | bellard | } |
379 | e80cfcfc | bellard | |
380 | c9e95029 | Blue Swirl | static const VMStateDescription vmstate_intctl_cpu = { |
381 | c9e95029 | Blue Swirl | .name ="slavio_intctl_cpu",
|
382 | c9e95029 | Blue Swirl | .version_id = 1,
|
383 | c9e95029 | Blue Swirl | .minimum_version_id = 1,
|
384 | c9e95029 | Blue Swirl | .minimum_version_id_old = 1,
|
385 | c9e95029 | Blue Swirl | .fields = (VMStateField []) { |
386 | c9e95029 | Blue Swirl | VMSTATE_UINT32(intreg_pending, SLAVIO_CPUINTCTLState), |
387 | c9e95029 | Blue Swirl | VMSTATE_END_OF_LIST() |
388 | c9e95029 | Blue Swirl | } |
389 | c9e95029 | Blue Swirl | }; |
390 | e80cfcfc | bellard | |
391 | c9e95029 | Blue Swirl | static const VMStateDescription vmstate_intctl = { |
392 | c9e95029 | Blue Swirl | .name ="slavio_intctl",
|
393 | c9e95029 | Blue Swirl | .version_id = 1,
|
394 | c9e95029 | Blue Swirl | .minimum_version_id = 1,
|
395 | c9e95029 | Blue Swirl | .minimum_version_id_old = 1,
|
396 | 752ff2fa | Juan Quintela | .post_load = vmstate_intctl_post_load, |
397 | c9e95029 | Blue Swirl | .fields = (VMStateField []) { |
398 | c9e95029 | Blue Swirl | VMSTATE_STRUCT_ARRAY(slaves, SLAVIO_INTCTLState, MAX_CPUS, 1,
|
399 | c9e95029 | Blue Swirl | vmstate_intctl_cpu, SLAVIO_CPUINTCTLState), |
400 | c9e95029 | Blue Swirl | VMSTATE_UINT32(intregm_pending, SLAVIO_INTCTLState), |
401 | c9e95029 | Blue Swirl | VMSTATE_UINT32(intregm_disabled, SLAVIO_INTCTLState), |
402 | c9e95029 | Blue Swirl | VMSTATE_UINT32(target_cpu, SLAVIO_INTCTLState), |
403 | c9e95029 | Blue Swirl | VMSTATE_END_OF_LIST() |
404 | e80cfcfc | bellard | } |
405 | c9e95029 | Blue Swirl | }; |
406 | e80cfcfc | bellard | |
407 | 78971d57 | Blue Swirl | static void slavio_intctl_reset(DeviceState *d) |
408 | e80cfcfc | bellard | { |
409 | 78971d57 | Blue Swirl | SLAVIO_INTCTLState *s = container_of(d, SLAVIO_INTCTLState, busdev.qdev); |
410 | e80cfcfc | bellard | int i;
|
411 | e80cfcfc | bellard | |
412 | e80cfcfc | bellard | for (i = 0; i < MAX_CPUS; i++) { |
413 | a1961a4b | Blue Swirl | s->slaves[i].intreg_pending = 0;
|
414 | 462eda24 | Blue Swirl | s->slaves[i].irl_out = 0;
|
415 | e80cfcfc | bellard | } |
416 | 9a87ce9b | blueswir1 | s->intregm_disabled = ~MASTER_IRQ_MASK; |
417 | e80cfcfc | bellard | s->intregm_pending = 0;
|
418 | e80cfcfc | bellard | s->target_cpu = 0;
|
419 | 0d0a7e69 | Blue Swirl | slavio_check_interrupts(s, 0);
|
420 | e80cfcfc | bellard | } |
421 | e80cfcfc | bellard | |
422 | 81a322d4 | Gerd Hoffmann | static int slavio_intctl_init1(SysBusDevice *dev) |
423 | e80cfcfc | bellard | { |
424 | a1961a4b | Blue Swirl | SLAVIO_INTCTLState *s = FROM_SYSBUS(SLAVIO_INTCTLState, dev); |
425 | a1961a4b | Blue Swirl | unsigned int i, j; |
426 | 8bb5ef33 | Benoît Canet | char slave_name[45]; |
427 | e80cfcfc | bellard | |
428 | a1961a4b | Blue Swirl | qdev_init_gpio_in(&dev->qdev, slavio_set_irq_all, 32 + MAX_CPUS);
|
429 | 13c89a11 | Benoît Canet | memory_region_init_io(&s->iomem, &slavio_intctlm_mem_ops, s, |
430 | 13c89a11 | Benoît Canet | "master-interrupt-controller", INTCTLM_SIZE);
|
431 | 750ecd44 | Avi Kivity | sysbus_init_mmio(dev, &s->iomem); |
432 | e80cfcfc | bellard | |
433 | e80cfcfc | bellard | for (i = 0; i < MAX_CPUS; i++) { |
434 | 8bb5ef33 | Benoît Canet | snprintf(slave_name, sizeof(slave_name),
|
435 | 8bb5ef33 | Benoît Canet | "slave-interrupt-controller-%i", i);
|
436 | a1961a4b | Blue Swirl | for (j = 0; j < MAX_PILS; j++) { |
437 | a1961a4b | Blue Swirl | sysbus_init_irq(dev, &s->cpu_irqs[i][j]); |
438 | a1961a4b | Blue Swirl | } |
439 | 8bb5ef33 | Benoît Canet | memory_region_init_io(&s->slaves[i].iomem, &slavio_intctl_mem_ops, |
440 | 8bb5ef33 | Benoît Canet | &s->slaves[i], slave_name, INTCTL_SIZE); |
441 | 750ecd44 | Avi Kivity | sysbus_init_mmio(dev, &s->slaves[i].iomem); |
442 | a1961a4b | Blue Swirl | s->slaves[i].cpu = i; |
443 | a1961a4b | Blue Swirl | s->slaves[i].master = s; |
444 | a1961a4b | Blue Swirl | } |
445 | 78971d57 | Blue Swirl | |
446 | 81a322d4 | Gerd Hoffmann | return 0; |
447 | a1961a4b | Blue Swirl | } |
448 | a1961a4b | Blue Swirl | |
449 | 999e12bb | Anthony Liguori | static void slavio_intctl_class_init(ObjectClass *klass, void *data) |
450 | 999e12bb | Anthony Liguori | { |
451 | 39bffca2 | Anthony Liguori | DeviceClass *dc = DEVICE_CLASS(klass); |
452 | 999e12bb | Anthony Liguori | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
453 | 999e12bb | Anthony Liguori | |
454 | 999e12bb | Anthony Liguori | k->init = slavio_intctl_init1; |
455 | 39bffca2 | Anthony Liguori | dc->reset = slavio_intctl_reset; |
456 | 39bffca2 | Anthony Liguori | dc->vmsd = &vmstate_intctl; |
457 | 999e12bb | Anthony Liguori | } |
458 | 999e12bb | Anthony Liguori | |
459 | 39bffca2 | Anthony Liguori | static TypeInfo slavio_intctl_info = {
|
460 | 39bffca2 | Anthony Liguori | .name = "slavio_intctl",
|
461 | 39bffca2 | Anthony Liguori | .parent = TYPE_SYS_BUS_DEVICE, |
462 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(SLAVIO_INTCTLState),
|
463 | 39bffca2 | Anthony Liguori | .class_init = slavio_intctl_class_init, |
464 | a1961a4b | Blue Swirl | }; |
465 | d7edfd27 | blueswir1 | |
466 | 83f7d43a | Andreas Färber | static void slavio_intctl_register_types(void) |
467 | a1961a4b | Blue Swirl | { |
468 | 39bffca2 | Anthony Liguori | type_register_static(&slavio_intctl_info); |
469 | e80cfcfc | bellard | } |
470 | a1961a4b | Blue Swirl | |
471 | 83f7d43a | Andreas Färber | type_init(slavio_intctl_register_types) |