openpic: make register names correspond better with hw docs
The base openpic specification doesn't provide abbreviated registernames, so it's somewhat understandable that the QEMU code made upits own, except that most of the names that QEMU used didn't correspond...
openpic: rework critical interrupt support
Critical interrupts on FSL MPIC are not supposed to payattention to priority, IACK, EOI, etc. On the currently modeledversion it's not supposed to pay attention to the mask bit either.
Also reorganize to make it easier to implement newer FSL MPIC models,...
openpic: s/opp->nb_irqs 1/opp>nb_cpus - 1/
"opp->nb_irqs-1" would have been a minor coding style error,but putting in one space but not the other makes it lookconfusingly like a numeric literal "-1".
Signed-off-by: Scott Wood <scottwood@freescale.com>...
openpic: don't crash on a register access without a CPU context
If we access a register via the QEMU memory inspection commands (e.g."xp") rather than from guest code, we won't have a CPU context.Gracefully fail to access the register in that case, rather than...
openpic: fix coding style issues
This patch fixes the following coding style violations:
- structs have to be typedef and be CamelCase - if()s are always surrounded by curly braces
Signed-off-by: Alexander Graf <agraf@suse.de>
PPC: Reset qemu timers when guest reset
This patch install the timer reset handler. This will be called whenthe guest is reset.
Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com>[agraf: adjust for QOM'ification]Signed-off-by: Alexander Graf <agraf@suse.de>
openpic: fix debug prints
Fix various format errors when debug prints are enabled. Alsocause error checking to happen even when debug prints are notenabled, and consistently use 0x for hex output.
Signed-off-by: Scott Wood <scottwood@freescale.com>[agraf: adjust for more recent code base, prettify DPRINTF macro]...
openpic: lower interrupt when reading the MSI register
This will stop things from breaking once it's properly treated as alevel-triggered interrupt. Note that it's the MPIC's MSI cascadeinterrupts that are level-triggered; the individual MSIs areedge-triggered....
openpic: support large vectors on FSL mpic
Previously only the spurious vector was sized appropriatelyto the openpic model.
Also, instances of "IPVP_VECTOR(opp->spve)" were replace withjust "opp->spve", as opp->spve is already just a vector and notan IVPR....
openpic: BRR1 is not a CPU-specific register.
It's in the address range that normally contains a magic redirectionto the CPU-specific region of the curretn CPU, but it isn't actuallya per-CPU register. On real hardware BRR1 shows up only at 0x40000,not at 0x60000 or other non-magic per-CPU areas. Plus, this makes...
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