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target-ppc: Move TCG initialization to PowerPCCPU initfn
Ensures that a QOM-created PowerPCCPU is usable.
Signed-off-by: Andreas Färber <afaerber@suse.de>
target-ppc: Update PowerPCCPU to QOM realizefn
Adapt ppc_cpu_realize() signature, hook it up to DeviceClass and setrealized = true in cpu_ppc_init().
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>Signed-off-by: Andreas Färber <afaerber@suse.de>
error: Strip trailing '\n' from error string arguments (again)
Commit 6daf194d and be62a2eb got rid of a bunch, but they keep comingback. Tracked down with this Coccinelle semantic patch:
r expression err, eno, cls, fmt; position p; @@ (...
r
cpu: do not use object_delete
CPUs are never added to the composition tree, so delete is achievedsimply by removing the last references to them.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
PPC: Unify dcbzl code path
The bit that makes a dcbz instruction a dcbzl instruction was declared asreserved in ppc32 ISAs. However, hardware simply ignores the bit, makingcode valid if it simply invokes dcbzl instead of dcbz even on 750 and G4.
Thus, mark the bit as unreserved so that we properly emulate a simple dcbz...
cpu: Add model resolution support to CPUClass
Introduce CPUClass::class_by_name and add a default implementation.Hook up the alpha and ppc implementations.
Introduce a wrapper function cpu_class_by_name().
target-ppc: Give a meaningful error if too many threads are specified
Currently the target-ppc tcg code only supports a single thread. You canspecify more, but they're treated identically to multiple cores. On KVMwe obviously can't support more threads than the hardware; if more are...
PPC: Provide zero SVR for -cpu e500mc and e5500
Even though our -cpu types for e500mc and e5500 are no real CPUs thatactually have version registers, a guest might still want to accesssaid version register and that has to succeed for a guest to be happy....
cpu: Move cpu_index field to CPUState
Note that target-alpha accesses this field from TCG, now using anegative offset. Therefore the field is placed last in CPUState.
Pass PowerPCCPU to [kvm]ppc_fixup_cpu() to facilitate this change.
Move common parts of mips cpu_state_reset() to mips_cpu_reset()....
PPC: Bring EPR support closer to reality
We already used to support the external proxy facility of FSL MPICs,but only implemented it halfway correctly.
This patch adds support for
target-ppc: Slim conversion of model definitions to QOM subclasses
Since the model list is highly macrofied, keep ppc_def_t for now andsave a pointer to it in PowerPCCPUClass. This results in a flat list ofsubclasses including aliases, to be refined later....
softmmu: move include files to include/sysemu/
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
exec: move include files to include/exec/
build: kill libdis, move disassemblers to disas/
PPC: 440: Emulate DCBR0
The DCBR0 register on 440 is used to implement system reset. The sameregister is used on 405 as well, so just reuse the code.
Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Rework storage of VPA registration state
With PAPR guests, hypercalls allow registration of the Virtual ProcessorArea (VPA), SLB shadow and dispatch trace log (DTL), each of which allowfor certain communication between the guest and hypervisor. Currently, we...
ppc/pseries: Reset VPA registration on CPU reset
The ppc specific CPU state contains several variables which track theVPA, SLB shadow and dispatch trace log. These are structures sharedbetween OS and hypervisor that are used on the pseries machine to track...
win32: provide separate macros for weak decls and definitions
mingw32 seems to want the declaration to also carry the weak attribute.Strangely, gcc on Linux absolutely does not want the declaration to be markedas weak. This may not be the right fix, but it seems to do the trick....
target-ppc: add implementation of query-cpu-definitions (v2)
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>Signed-off-by: Luiz Capitulino <lcapitulino@redhat.com>
target-ppc: Fix 2nd parameter for tcg_gen_shri_tl
This fixes a compiler error when QEMU was configured with --enable-debug.
Signed-off-by: Stefan Weil <sw@weilnetz.de>Signed-off-by: Alexander Graf <agraf@suse.de>
PPC: BookE: Make ivpr selectable by CPU type
IVPR can either hold 32 or 64 bit addresses, depending on the CPU type. Letthe CPU initialization function pass in its mask itself, so we can easilyextend it.
PPC: Add e5500 CPU target
This patch adds e5500's CPU initialization to the TCG CPU initializationcode.
PPC: Extract SPR dump generation into its own function
This patch moves the debug #ifdef'ed SPR trace generation into itsown function, so we can call it from multiple places.
PPC: BookE: Support 32 and 64 bit wide MAS2
The MAS registers on BookE are all 32 bit wide, except for MAS2, whichcan hold up to 64 bit on 64 bit capable CPUs. Reflect this in the SPRsetting code, so that the guest can never write invalid values in them....
ppc64: Rudimentary Support for extra page sizes on server CPUs
More recent Power server chips (i.e. based on the 64 bit hash MMU)support more than just the traditional 4k and 16M page sizes. Thiscan get quite complicated, because which page sizes are supported,...
ppc: Avoid AREG0 for timebase helpers
Add an explicit CPUPPCState parameter instead of relying on AREG0.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>Signed-off-by: Alexander Graf <agraf@suse.de>Signed-off-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Alexander Graf <agraf@suse.de>
ppc: Avoid AREG0 for misc helpers
ppc: Avoid AREG0 for MMU etc. helpers
PPC: Fix up e500 cache size setting
When initializing the e500 code, we need to expose itscache line size for user and system mode, while the mmudetails are only interesting for system emulation.
Split the 2 switch statements apart, allowing us to #ifdef...
target-ppc: Init dcache and icache size for e500 user mode
commit f7aa558396dd0f6b7a2b22c05cb503c655854102 pulled the dcache and icacheline size initialization inside of a '#if !defined(CONFIG_USER_ONLY)' block.This is not correct because instructions like 'dcbz' need the dcache size...
target-ppc: Fix type casts for w64 (uintptr_t)
This changes nothing for other hosts.
Signed-off-by: Stefan Weil <sw@weilnetz.de>Signed-off-by: Andreas Färber <afaerber@suse.de>
target-ppc: QOM'ify CPU reset
Move code from cpu_state_reset() into ppc_cpu_reset().Reorder #include of helper_regs.h to use it in translate_init.c.
Adjust whitespace and add braces.
Signed-off-by: Andreas Färber <afaerber@suse.de>Acked-by: David Gibson <david@gibson.dropbear.id.au>
target-ppc: Start QOM'ifying CPU init
Move code not dependent on ppc_def_t from cpu_ppc_init() into an initfn.
target-ppc: QOM'ify CPU
Embed CPUPPCState as first member of PowerPCCPU.Distinguish between "powerpc-cpu", "powerpc64-cpu" and"embedded-powerpc-cpu".
Let CPUClass::reset() call cpu_state_reset() for now.
Signed-off-by: Andreas Färber <afaerber@suse.de>...
target-ppc: Add hooks for handling tcg and kvm limitations
On target-ppc, our table of CPU types and features encodes the features asfound on the hardware, regardless of whether these features are actuallyusable under TCG or KVM. We already have cases where the information from...
Replace Qemu by QEMU in comments
The official spelling is QEMU.
Signed-off-by: Stefan Weil <sw@weilnetz.de>Reviewed-by: Andreas Färber <afaerber@suse.de>[blauwirbel@gmail.com: fixed comment style in hw/sun4m.c]Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
ppc: Correctly define POWERPC_INSNS2_DEFAULT
'POWERPC_INSNS2_DEFAULT' was defined incorrectly which was causing theopcode table creation code to erroneously register 'eieio' and 'mbar'for the "default" processor:
PPC64: Add support for ldbrx and stdbrx instructions
These instructions for loading and storing byte-swapped 64-bit values havebeen introduced in PowerISA 2.06.
Signed-off-by: Thomas Huth <thuth@linux.vnet.ibm.com>Signed-off-by: David Gibson <david@gibson.dropbear.id.au>...
PPC: Add PIR register to POWER7 CPU
The POWER7 emulation is missing the Processor Identification Register,mandatory in recent POWER CPUs, that is required for SMP on at leastsome operating systems (e.g. FreeBSD) to function properly. This patchcopies the existing PIR code from the other CPUs that implement it....
target-ppc: Don't overuse CPUState
Scripted conversion: sed -i "s/CPUState/CPUPPCState/g" target-ppc/*.[hc] sed -i "s/#define CPUPPCState/#define CPUState/" target-ppc/cpu.h
Signed-off-by: Andreas Färber <afaerber@suse.de>Acked-by: Anthony Liguori <aliguori@us.ibm.com>
PPC: E500: Populate L1CFG0 SPR
When running Linux on e500 with powersave-nap enabled, Linux tries toread out the L1CFG0 register and calculates some things from it. Passing0 there ends up in a division by 0, resulting in -1, resulting in badness.
So let's populate the L1CFG0 register with reasonable defaults. That way...
PPC: e500mc: Enable processor control
The e500mc implements Embedded.Processor Control, so enable it andthus enable guests to IPI each other. This makes -smp work with -cpue500mc.
PPC: Add IVOR 38-42
Our code only knows IVORs up to 37. Add the new ones defined in ISA 2.06from 38 - 42.
Signed-off-by: Alexander Graf <agraf@suse.de>Reviewed-by: Andreas Färber <afaerber@suse.de>
PPC: e500mc: add missing IVORs to bitmap
E500mc supports IVORs 36-41. Add them to the support mask. Drop SPEsupport too.
PPC: e500: msync is 440 only, e500 has real sync
The e500 CPUs don't use 440's msync which falls on the same opcode IDs,but instead use the real powerpc sync instruction. This is important,since the invalid mask differs between the two.
PPC: Enable 440EP CPU target
Now that we have 440 TLB emulation, we can also support running the 440EPCPU target in system emulation mode.
PPC: Add description for the Freescale e500mc core.
This core is found on chips such as p4080, p3041, p2040, and p5020.
More needs to be done to make this viable for TCG (such as missing SPRsand instructions), but this suffices to get KVM running with appropriate...
ppc: Alter CPU state to mask out TCG unimplemented instructions as appropriate
The CPU state contains two bitmaps, initialized from the CPU specwhich describes which instructions are implemented on the CPU. Acouple of bits are defined which cover instructions (VSX and DFP)...
PPC: Disable non-440 CPUs for ppcemb target
The sole reason we have the ppcemb target is to support MMUs that haveless than the usual 4k possible page size. There are very few of thesechips and I don't want to add additional QA and testing burden to everyone...
pseries: Correct vmx/dfp handling in both KVM and TCG cases
Currently, when KVM is enabled, the pseries machine checks if the hostCPU supports VMX, VSX and/or DFP instructions and advertisesaccordingly in the guest device tree. It does this regardless of what...
ppc: Remove broken partial PVR matching
The ppc target contains a ppc_find_by_pvr() function, which looks up aCPU spec based on a PVR (that is, based on the value in the target cpu'sProcessor Version Register). PVR values contain information on both the...
ppc: First cut implementation of -cpu host
For convenience with kvm, x86 allows the user to specify -cpu host on theqemu command line, which means make the guest cpu the same as the hostcpu. This patch implements the same option for ppc targets.
For now, this just read the host PVR (Processor Version Register) and...
ppc: Add cpu defs for POWER7 revisions 2.1 and 2.3
This patch adds cpu specs to the table for POWER7 revisions 2.1 and 2.3.This allows -cpu host to be used on these host cpus.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>Signed-off-by: Alexander Graf <agraf@suse.de>
PPC: booke timers
While working on the emulation of the freescale p2010 (e500v2) I realized thatthere's no implementation of booke's timers features. Currently mpc8544 usesppc_emb (ppc_emb_timers_init) which is close but not exactly like booke (forexample booke uses different SPR)....
Gdbstub: handle read of fpscr
Signed-off-by: Fabien Chouteau <chouteau@adacore.com>Signed-off-by: Alexander Graf <agraf@suse.de>
Implement POWER7's CFAR in TCG
This patch implements support for the CFAR SPR on POWER7 (Come FromAddress Register), which snapshots the PC value at the time of a branch oran rfid. The latest powerpc-next kernel also catches it and can show it inxmon or in the signal frames....
Use glib memory allocation and free functions
qemu_malloc/qemu_free no longer exist after this commit.
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
PPC: move TLBs to their own arrays
Until now, we've created a union over multiple different TLB types andallocated that union. While it's a waste of memory (and cache) to allocateTLB information for a TLB type with much information when you only needlittle, it also inflicts another issue....
ppc: Fix compilation for ppc64-softmmu
When QEMU was configured with --enable-debug-tcg,compilation fails in spr_write_booke206_mmucsr0() and inspr_write_booke_pid(). Similar changes are also neededin conditional code which is normally unused.
Cc: Alexander Graf <agraf@suse.de>...
Merge branch 'ppc-next' of git://repo.or.cz/qemu/agraf
PPC: Add another 64 bits to instruction feature mask
To enable quick runtime detection of instruction groups to the currentlyselected CPU emulation, we have a feature mask of what exactly the respectiveinstruction supports.
This feature mask is 64 bits long and we just successfully exceeded those 64...
PPC: Implement e500 (FSL) MMU
Most of the code to support e500 style MMUs is already in place, butwe're missing on some of the special TLB0-TLB1 handling code and slightlydifferent TLB modification.
This patch adds support for the FSL style MMU.
Fix typos in comments (instanciation -> instantiation)
Signed-off-by: Stefan Weil <weil@mail.berlios.de>Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
Parse SDR1 on mtspr instead of at translate time
On ppc machines with hash table MMUs, the special purpose register SDR1contains both the base address of the encoded size (hashed) page tables.
At present, we interpret the SDR1 value within the address translation...
Add POWER7 support for ppc
This adds emulation support for the recent POWER7 cpu to qemu. It's farfrom perfect - it's missing a number of POWER7 features so far, includingany support for VSX or decimal floating point instructions. However, it'sclose enough to boot a kernel with the POWER7 PVR....
Implement missing parts of the logic for the POWER PURR
The PURR (Processor Utilization Resource Register) is a register foundon recent POWER CPUs. The guts of implementing it at least enough toget by are already present in qemu, however some of the helper...
Handle icount for powerpc tbl/tbu/decr load and store.
Handle option '-icount X' on powerpc targets.
Signed-off-by: Tristan Gingold <gingold@adacore.com>Signed-off-by: Edgar E. Iglesias <edgar.iglesias@petalogix.com>
target-xxx: Use fprintf_function (format checking)
fprintf_function uses format checking with GCC_FMT_ATTR.
Cc: Blue Swirl <blauwirbel@gmail.com>Signed-off-by: Stefan Weil <weil@mail.berlios.de>...
powerpc: Add a ppc-440x5 Xilinx model
Add a powerpc 440x5 with the model ID on the Xilinx virtex5.Connect the 440x5 to the 40x interrupt logic.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: fix power mode checking on 7400/7410
Only the PowerPC 7440/7450 family don't support DOZE mode. PowerPC7400 and 7410 support it.
target-ppc: generic PowerPC TBL
Time base SPRs TBL/TBU should be accessible in user/priv modes for readingas specified in POWER ISA documentation. Therefore SPRs permissions werechanged in gen_tbl function.
Signed-off-by: Dmitry Ilyevsky <ilyevsky@gmail.com>...
target-ppc: simpler definitions for microcontrollers based on e300
No need to alias e300 core for each CPU package.Differences between microcontrollers have to be implemented in a higher layerthan translate_init.c
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>...
target-ppc: add declarations of microcontrollers based on e300
Add CPU declarations of MPC8343, MPC8343E, MPC8347 and MPC8347E.
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-ppc: better support of e300 CPU core
Declare HID2 register.
Use high BATs for e300 (8 instead of 4).
Fix index of high BATs registers.Before the fix, IBAT4-7 were overwriting IBAT0-3.
Signed-off-by: François Armand <francois.armand@os4i.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Revert "Get rid of _t suffix"
In the very least, a change like this requires discussion on the list.
The naming convention is goofy and it causes a massive merge problem. Somethinglike this must be presented on the list first so people can provide input...
Get rid of _t suffix
Some not so obvious bits, slirp and Xen were left alone for the timebeing.
Signed-off-by: malc <av1474@comtv.ru>
Replace local ADDRX/PADDRX macros with TARGET_FMT_lx/plx
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
rename WORDS_BIGENDIAN to HOST_WORDS_BIGENDIAN
Signed-off-by: Juan Quintela <quintela@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Update to a hopefully more future proof FSF address
target-ppc: enable PPC_MFTB for 44x
According to PPC440 user manual, PPC 440 supports ``mftb'' even it's apreserved instruction:
PPC440_UM2013.pdf, p.445, table A-3
when I compile a kernel (2.6.30, bamboo_defconfig/440EP &canyonlands/460EX), I can see ``mftb'' by using ppc-xxx-objdump...
target-ppc: permit linux-user to read PVR
Access to the PVR SPR is normally forbidden from userspace apps. TheLinux kernel, however, fixes up reads in the appropriate trap handler.To permit applications that read PVR to run on QEMU, then, we need toimplement the same handling of PVR reads....
Replace ELF section hack with normal table
target-ppc: expose cpu capability flags
Do this so other pieces of code can make decisions based on thecapabilities of the CPU we're emulating.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>Signed-off-by: malc <av1474@comtv.ru>
Fix powerpc 604 reset vector
According to 604eUM_book (see 8.3.3 Reset inputs p8-54), the IP bit is setfor hreset and the vector is at offset 0x100 from the exception prefix.
No difference in this area between 604 and 604e.
Signed-off-by: Tristan Gingold <gingold@adacore.com>
Fix PPC reset
target-ppc: fix commit r6789
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6804 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: free a tcg temp variable
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6790 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: add support for reading/writing spefscr
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6789 c046a42c-6fe2-441c-8c8c-71466251a162
Fix off-by-one errors for Altivec and SPE registers
Altivec and SPE both have 34 registers in their register sets, not 35with a missing register 32.
GDB would ask for register 32 of the Altivec (resp. SPE) registers andthe code would claim it had zero width. The QEMU GDB stub code would...
Keep SLB in-CPU
Real 970 CPUs have the SLB not memory backed, but inside the CPU.This breaks bridge mode for 970 for now, but at least keeps us fromoverwriting physical addresses 0x0 - 0x300, rendering our interrupthandlers useless.
I put in a stub for bridge mode operation that could be enabled...
Nop some SPRs on 970fx
Linux tries to access some SPRs on PPC64 boot. Let's just ignore thosefor the 970fx for now to make it happy.
Signed-off-by: Alexander Graf <alex@csgraf.de>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6751 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: improve mfcr/mtcrf
- use ctz32 instead of ffs - 1- small optimisation of mtcrf- add the name of both opcodes
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6669 c046a42c-6fe2-441c-8c8c-71466251a162
kvm/powerpc: Add irq support for E500 core
Signed-off-by: Liu Yu <yu.liu@freescale.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6662 c046a42c-6fe2-441c-8c8c-71466251a162
Implement HIOR
A real 970 CPU starts up with HIOR=0xfff00000 and triggers a resetexception, basically ending up at IP 0xfff001000.
Later on this HIOR has to be set to 0 by the firmware in order toenable the OS to handle interrupts on its own.
This patch maps HIOR to exec_prefix, which does the same thing...
target-ppc: Model e500v{1,2} CPUs more accurately
The e500v1 chips only have single-precision floating point; don't say wesupport the double-precision floating-point instructions on such chips.Also add an e500v1 -cpu argument for a generic e500v1.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>...
target-ppc: Model SPE floating-point instructions more accurately
Single-precision and double-precision floating-point instructions shouldbe separated into their own categories, since some chips only supportsingle-precision instructions.
targets: remove error handling from qemu_malloc() callers (Avi Kivity)
Signed-off-by: Avi Kivity <avi@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6530 c046a42c-6fe2-441c-8c8c-71466251a162
Add calls to initialize VSCR on appropriate machines
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6507 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: Add SPE register read/write using XML
Don't read/write SPEFSCR until we figure out what to do about exceptions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6425 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: Add Altivec register read/write using XML
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6424 c046a42c-6fe2-441c-8c8c-71466251a162