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1 | d4e8164f | bellard | /*
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2 | d4e8164f | bellard | * internal execution defines for qemu
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3 | 5fafdf24 | ths | *
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4 | d4e8164f | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | d4e8164f | bellard | *
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6 | d4e8164f | bellard | * This library is free software; you can redistribute it and/or
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7 | d4e8164f | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | d4e8164f | bellard | * License as published by the Free Software Foundation; either
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9 | d4e8164f | bellard | * version 2 of the License, or (at your option) any later version.
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10 | d4e8164f | bellard | *
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11 | d4e8164f | bellard | * This library is distributed in the hope that it will be useful,
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12 | d4e8164f | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | d4e8164f | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | d4e8164f | bellard | * Lesser General Public License for more details.
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15 | d4e8164f | bellard | *
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16 | d4e8164f | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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18 | d4e8164f | bellard | */
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19 | d4e8164f | bellard | |
20 | 875cdcf6 | aliguori | #ifndef _EXEC_ALL_H_
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21 | 875cdcf6 | aliguori | #define _EXEC_ALL_H_
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22 | 7d99a001 | blueswir1 | |
23 | 7d99a001 | blueswir1 | #include "qemu-common.h" |
24 | 7d99a001 | blueswir1 | |
25 | b346ff46 | bellard | /* allow to see translation results - the slowdown should be negligible, so we leave it */
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26 | de9a95f0 | aurel32 | #define DEBUG_DISAS
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27 | b346ff46 | bellard | |
28 | 41c1b1c9 | Paul Brook | /* Page tracking code uses ram addresses in system mode, and virtual
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29 | 41c1b1c9 | Paul Brook | addresses in userspace mode. Define tb_page_addr_t to be an appropriate
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30 | 41c1b1c9 | Paul Brook | type. */
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31 | 41c1b1c9 | Paul Brook | #if defined(CONFIG_USER_ONLY)
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32 | b480d9b7 | Paul Brook | typedef abi_ulong tb_page_addr_t;
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33 | 41c1b1c9 | Paul Brook | #else
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34 | 41c1b1c9 | Paul Brook | typedef ram_addr_t tb_page_addr_t;
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35 | 41c1b1c9 | Paul Brook | #endif
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36 | 41c1b1c9 | Paul Brook | |
37 | b346ff46 | bellard | /* is_jmp field values */
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38 | b346ff46 | bellard | #define DISAS_NEXT 0 /* next instruction can be analyzed */ |
39 | b346ff46 | bellard | #define DISAS_JUMP 1 /* only pc was modified dynamically */ |
40 | b346ff46 | bellard | #define DISAS_UPDATE 2 /* cpu state was modified dynamically */ |
41 | b346ff46 | bellard | #define DISAS_TB_JUMP 3 /* only pc was modified statically */ |
42 | b346ff46 | bellard | |
43 | f081c76c | Blue Swirl | struct TranslationBlock;
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44 | 2e70f6ef | pbrook | typedef struct TranslationBlock TranslationBlock; |
45 | b346ff46 | bellard | |
46 | b346ff46 | bellard | /* XXX: make safe guess about sizes */
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47 | 5b620fb6 | Peter Maydell | #define MAX_OP_PER_INSTR 208 |
48 | 4d0e4ac7 | Stuart Brady | |
49 | 4d0e4ac7 | Stuart Brady | #if HOST_LONG_BITS == 32 |
50 | 4d0e4ac7 | Stuart Brady | #define MAX_OPC_PARAM_PER_ARG 2 |
51 | 4d0e4ac7 | Stuart Brady | #else
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52 | 4d0e4ac7 | Stuart Brady | #define MAX_OPC_PARAM_PER_ARG 1 |
53 | 4d0e4ac7 | Stuart Brady | #endif
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54 | 4d0e4ac7 | Stuart Brady | #define MAX_OPC_PARAM_IARGS 4 |
55 | 4d0e4ac7 | Stuart Brady | #define MAX_OPC_PARAM_OARGS 1 |
56 | 4d0e4ac7 | Stuart Brady | #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS)
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57 | 4d0e4ac7 | Stuart Brady | |
58 | 4d0e4ac7 | Stuart Brady | /* A Call op needs up to 4 + 2N parameters on 32-bit archs,
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59 | 4d0e4ac7 | Stuart Brady | * and up to 4 + N parameters on 64-bit archs
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60 | 4d0e4ac7 | Stuart Brady | * (N = number of input arguments + output arguments). */
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61 | 4d0e4ac7 | Stuart Brady | #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS)) |
62 | 6db73509 | Aurelien Jarno | #define OPC_BUF_SIZE 640 |
63 | b346ff46 | bellard | #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
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64 | b346ff46 | bellard | |
65 | a208e54a | pbrook | /* Maximum size a TCG op can expand to. This is complicated because a
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66 | 0cbfcd2b | Aurelien Jarno | single op may require several host instructions and register reloads.
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67 | 0cbfcd2b | Aurelien Jarno | For now take a wild guess at 192 bytes, which should allow at least
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68 | a208e54a | pbrook | a couple of fixup instructions per argument. */
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69 | 0cbfcd2b | Aurelien Jarno | #define TCG_MAX_OP_SIZE 192 |
70 | a208e54a | pbrook | |
71 | 0115be31 | pbrook | #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
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72 | b346ff46 | bellard | |
73 | c27004ec | bellard | extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
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74 | b346ff46 | bellard | extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
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75 | 2e70f6ef | pbrook | extern uint16_t gen_opc_icount[OPC_BUF_SIZE];
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76 | b346ff46 | bellard | |
77 | 79383c9c | blueswir1 | #include "qemu-log.h" |
78 | b346ff46 | bellard | |
79 | 2cfc5f17 | ths | void gen_intermediate_code(CPUState *env, struct TranslationBlock *tb); |
80 | 2cfc5f17 | ths | void gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb); |
81 | e87b7cb0 | Stefan Weil | void restore_state_to_opc(CPUState *env, struct TranslationBlock *tb, |
82 | e87b7cb0 | Stefan Weil | int pc_pos);
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83 | d2856f1a | aurel32 | |
84 | 57fec1fe | bellard | void cpu_gen_init(void); |
85 | 4c3a88a2 | bellard | int cpu_gen_code(CPUState *env, struct TranslationBlock *tb, |
86 | d07bde88 | blueswir1 | int *gen_code_size_ptr);
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87 | 5fafdf24 | ths | int cpu_restore_state(struct TranslationBlock *tb, |
88 | 618ba8e6 | Stefan Weil | CPUState *env, unsigned long searched_pc); |
89 | 2e12669a | bellard | void cpu_resume_from_signal(CPUState *env1, void *puc); |
90 | 2e70f6ef | pbrook | void cpu_io_recompile(CPUState *env, void *retaddr); |
91 | 2e70f6ef | pbrook | TranslationBlock *tb_gen_code(CPUState *env, |
92 | 2e70f6ef | pbrook | target_ulong pc, target_ulong cs_base, int flags,
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93 | 2e70f6ef | pbrook | int cflags);
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94 | 6a00d601 | bellard | void cpu_exec_init(CPUState *env);
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95 | 1162c041 | Blue Swirl | void QEMU_NORETURN cpu_loop_exit(CPUState *env1);
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96 | 53a5960a | pbrook | int page_unprotect(target_ulong address, unsigned long pc, void *puc); |
97 | 41c1b1c9 | Paul Brook | void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
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98 | 2e12669a | bellard | int is_cpu_write_access);
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99 | 2e12669a | bellard | void tlb_flush_page(CPUState *env, target_ulong addr);
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100 | ee8b7021 | bellard | void tlb_flush(CPUState *env, int flush_global); |
101 | c527ee8f | Paul Brook | #if !defined(CONFIG_USER_ONLY)
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102 | d4c430a8 | Paul Brook | void tlb_set_page(CPUState *env, target_ulong vaddr,
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103 | d4c430a8 | Paul Brook | target_phys_addr_t paddr, int prot,
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104 | d4c430a8 | Paul Brook | int mmu_idx, target_ulong size);
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105 | c527ee8f | Paul Brook | #endif
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106 | d4e8164f | bellard | |
107 | d4e8164f | bellard | #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ |
108 | d4e8164f | bellard | |
109 | 4390df51 | bellard | #define CODE_GEN_PHYS_HASH_BITS 15 |
110 | 4390df51 | bellard | #define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS) |
111 | 4390df51 | bellard | |
112 | 26a5f13b | bellard | #define MIN_CODE_GEN_BUFFER_SIZE (1024 * 1024) |
113 | d4e8164f | bellard | |
114 | 4390df51 | bellard | /* estimated block size for TB allocation */
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115 | 4390df51 | bellard | /* XXX: use a per code average code fragment size and modulate it
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116 | 4390df51 | bellard | according to the host CPU */
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117 | 4390df51 | bellard | #if defined(CONFIG_SOFTMMU)
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118 | 4390df51 | bellard | #define CODE_GEN_AVG_BLOCK_SIZE 128 |
119 | 4390df51 | bellard | #else
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120 | 4390df51 | bellard | #define CODE_GEN_AVG_BLOCK_SIZE 64 |
121 | 4390df51 | bellard | #endif
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122 | 4390df51 | bellard | |
123 | a8cd70fc | Filip Navara | #if defined(_ARCH_PPC) || defined(__x86_64__) || defined(__arm__) || defined(__i386__)
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124 | d4e8164f | bellard | #define USE_DIRECT_JUMP
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125 | 7316329a | Stefan Weil | #elif defined(CONFIG_TCG_INTERPRETER)
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126 | 7316329a | Stefan Weil | #define USE_DIRECT_JUMP
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127 | d4e8164f | bellard | #endif
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128 | d4e8164f | bellard | |
129 | 2e70f6ef | pbrook | struct TranslationBlock {
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130 | 2e12669a | bellard | target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
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131 | 2e12669a | bellard | target_ulong cs_base; /* CS base for this block */
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132 | c068688b | j_mayer | uint64_t flags; /* flags defining in which context the code was generated */
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133 | d4e8164f | bellard | uint16_t size; /* size of target code for this block (1 <=
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134 | d4e8164f | bellard | size <= TARGET_PAGE_SIZE) */
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135 | 58fe2f10 | bellard | uint16_t cflags; /* compile flags */
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136 | 2e70f6ef | pbrook | #define CF_COUNT_MASK 0x7fff |
137 | 2e70f6ef | pbrook | #define CF_LAST_IO 0x8000 /* Last insn may be an IO access. */ |
138 | 58fe2f10 | bellard | |
139 | d4e8164f | bellard | uint8_t *tc_ptr; /* pointer to the translated code */
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140 | 4390df51 | bellard | /* next matching tb for physical address. */
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141 | 5fafdf24 | ths | struct TranslationBlock *phys_hash_next;
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142 | 4390df51 | bellard | /* first and second physical page containing code. The lower bit
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143 | 4390df51 | bellard | of the pointer tells the index in page_next[] */
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144 | 5fafdf24 | ths | struct TranslationBlock *page_next[2]; |
145 | 41c1b1c9 | Paul Brook | tb_page_addr_t page_addr[2];
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146 | 4390df51 | bellard | |
147 | d4e8164f | bellard | /* the following data are used to directly call another TB from
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148 | d4e8164f | bellard | the code of this one. */
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149 | d4e8164f | bellard | uint16_t tb_next_offset[2]; /* offset of original jump target */ |
150 | d4e8164f | bellard | #ifdef USE_DIRECT_JUMP
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151 | efc0a514 | Filip Navara | uint16_t tb_jmp_offset[2]; /* offset of jump instruction */ |
152 | d4e8164f | bellard | #else
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153 | 57fec1fe | bellard | unsigned long tb_next[2]; /* address of jump generated code */ |
154 | d4e8164f | bellard | #endif
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155 | d4e8164f | bellard | /* list of TBs jumping to this one. This is a circular list using
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156 | d4e8164f | bellard | the two least significant bits of the pointers to tell what is
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157 | d4e8164f | bellard | the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
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158 | d4e8164f | bellard | jmp_first */
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159 | 5fafdf24 | ths | struct TranslationBlock *jmp_next[2]; |
160 | d4e8164f | bellard | struct TranslationBlock *jmp_first;
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161 | 2e70f6ef | pbrook | uint32_t icount; |
162 | 2e70f6ef | pbrook | }; |
163 | d4e8164f | bellard | |
164 | b362e5e0 | pbrook | static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc) |
165 | b362e5e0 | pbrook | { |
166 | b362e5e0 | pbrook | target_ulong tmp; |
167 | b362e5e0 | pbrook | tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)); |
168 | b5e19d4c | edgar_igl | return (tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK;
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169 | b362e5e0 | pbrook | } |
170 | b362e5e0 | pbrook | |
171 | 8a40a180 | bellard | static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc) |
172 | d4e8164f | bellard | { |
173 | b362e5e0 | pbrook | target_ulong tmp; |
174 | b362e5e0 | pbrook | tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)); |
175 | b5e19d4c | edgar_igl | return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK)
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176 | b5e19d4c | edgar_igl | | (tmp & TB_JMP_ADDR_MASK)); |
177 | d4e8164f | bellard | } |
178 | d4e8164f | bellard | |
179 | 41c1b1c9 | Paul Brook | static inline unsigned int tb_phys_hash_func(tb_page_addr_t pc) |
180 | 4390df51 | bellard | { |
181 | f96a3834 | Aurelien Jarno | return (pc >> 2) & (CODE_GEN_PHYS_HASH_SIZE - 1); |
182 | 4390df51 | bellard | } |
183 | 4390df51 | bellard | |
184 | 2e70f6ef | pbrook | void tb_free(TranslationBlock *tb);
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185 | 0124311e | bellard | void tb_flush(CPUState *env);
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186 | 41c1b1c9 | Paul Brook | void tb_link_page(TranslationBlock *tb,
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187 | 41c1b1c9 | Paul Brook | tb_page_addr_t phys_pc, tb_page_addr_t phys_page2); |
188 | 41c1b1c9 | Paul Brook | void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
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189 | d4e8164f | bellard | |
190 | 4390df51 | bellard | extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
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191 | d4e8164f | bellard | |
192 | 4390df51 | bellard | #if defined(USE_DIRECT_JUMP)
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193 | 4390df51 | bellard | |
194 | 7316329a | Stefan Weil | #if defined(CONFIG_TCG_INTERPRETER)
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195 | 7316329a | Stefan Weil | static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr) |
196 | 7316329a | Stefan Weil | { |
197 | 7316329a | Stefan Weil | /* patch the branch destination */
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198 | 7316329a | Stefan Weil | *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
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199 | 7316329a | Stefan Weil | /* no need to flush icache explicitly */
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200 | 7316329a | Stefan Weil | } |
201 | 7316329a | Stefan Weil | #elif defined(_ARCH_PPC)
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202 | 64b85a8f | Blue Swirl | void ppc_tb_set_jmp_target(unsigned long jmp_addr, unsigned long addr); |
203 | 810260a8 | malc | #define tb_set_jmp_target1 ppc_tb_set_jmp_target
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204 | 57fec1fe | bellard | #elif defined(__i386__) || defined(__x86_64__)
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205 | 4390df51 | bellard | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) |
206 | 4390df51 | bellard | { |
207 | 4390df51 | bellard | /* patch the branch destination */
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208 | 4390df51 | bellard | *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
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209 | 1235fc06 | ths | /* no need to flush icache explicitly */
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210 | 4390df51 | bellard | } |
211 | 811d4cf4 | balrog | #elif defined(__arm__)
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212 | 811d4cf4 | balrog | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) |
213 | 811d4cf4 | balrog | { |
214 | 4a1e19ae | Aurelien Jarno | #if !QEMU_GNUC_PREREQ(4, 1) |
215 | 811d4cf4 | balrog | register unsigned long _beg __asm ("a1"); |
216 | 811d4cf4 | balrog | register unsigned long _end __asm ("a2"); |
217 | 811d4cf4 | balrog | register unsigned long _flg __asm ("a3"); |
218 | 3233f0d4 | balrog | #endif
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219 | 811d4cf4 | balrog | |
220 | 811d4cf4 | balrog | /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */
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221 | 87b78ad1 | Laurent Desnogues | *(uint32_t *)jmp_addr = |
222 | 87b78ad1 | Laurent Desnogues | (*(uint32_t *)jmp_addr & ~0xffffff)
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223 | 87b78ad1 | Laurent Desnogues | | (((addr - (jmp_addr + 8)) >> 2) & 0xffffff); |
224 | 811d4cf4 | balrog | |
225 | 3233f0d4 | balrog | #if QEMU_GNUC_PREREQ(4, 1) |
226 | 4a1e19ae | Aurelien Jarno | __builtin___clear_cache((char *) jmp_addr, (char *) jmp_addr + 4); |
227 | 3233f0d4 | balrog | #else
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228 | 811d4cf4 | balrog | /* flush icache */
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229 | 811d4cf4 | balrog | _beg = jmp_addr; |
230 | 811d4cf4 | balrog | _end = jmp_addr + 4;
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231 | 811d4cf4 | balrog | _flg = 0;
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232 | 811d4cf4 | balrog | __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg)); |
233 | 3233f0d4 | balrog | #endif
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234 | 811d4cf4 | balrog | } |
235 | 7316329a | Stefan Weil | #else
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236 | 7316329a | Stefan Weil | #error tb_set_jmp_target1 is missing
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237 | 4390df51 | bellard | #endif
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238 | d4e8164f | bellard | |
239 | 5fafdf24 | ths | static inline void tb_set_jmp_target(TranslationBlock *tb, |
240 | 4cbb86e1 | bellard | int n, unsigned long addr) |
241 | 4cbb86e1 | bellard | { |
242 | 4cbb86e1 | bellard | unsigned long offset; |
243 | 4cbb86e1 | bellard | |
244 | 4cbb86e1 | bellard | offset = tb->tb_jmp_offset[n]; |
245 | 4cbb86e1 | bellard | tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr); |
246 | 4cbb86e1 | bellard | } |
247 | 4cbb86e1 | bellard | |
248 | d4e8164f | bellard | #else
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249 | d4e8164f | bellard | |
250 | d4e8164f | bellard | /* set the jump target */
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251 | 5fafdf24 | ths | static inline void tb_set_jmp_target(TranslationBlock *tb, |
252 | d4e8164f | bellard | int n, unsigned long addr) |
253 | d4e8164f | bellard | { |
254 | 95f7652d | bellard | tb->tb_next[n] = addr; |
255 | d4e8164f | bellard | } |
256 | d4e8164f | bellard | |
257 | d4e8164f | bellard | #endif
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258 | d4e8164f | bellard | |
259 | 5fafdf24 | ths | static inline void tb_add_jump(TranslationBlock *tb, int n, |
260 | d4e8164f | bellard | TranslationBlock *tb_next) |
261 | d4e8164f | bellard | { |
262 | cf25629d | bellard | /* NOTE: this test is only needed for thread safety */
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263 | cf25629d | bellard | if (!tb->jmp_next[n]) {
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264 | cf25629d | bellard | /* patch the native jump address */
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265 | cf25629d | bellard | tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr); |
266 | 3b46e624 | ths | |
267 | cf25629d | bellard | /* add in TB jmp circular list */
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268 | cf25629d | bellard | tb->jmp_next[n] = tb_next->jmp_first; |
269 | cf25629d | bellard | tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
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270 | cf25629d | bellard | } |
271 | d4e8164f | bellard | } |
272 | d4e8164f | bellard | |
273 | a513fe19 | bellard | TranslationBlock *tb_find_pc(unsigned long pc_ptr); |
274 | a513fe19 | bellard | |
275 | d5975363 | pbrook | #include "qemu-lock.h" |
276 | d4e8164f | bellard | |
277 | c227f099 | Anthony Liguori | extern spinlock_t tb_lock;
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278 | d4e8164f | bellard | |
279 | 36bdbe54 | bellard | extern int tb_invalidated_flag; |
280 | 6e59c1db | bellard | |
281 | 3917149d | Blue Swirl | /* The return address may point to the start of the next instruction.
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282 | 3917149d | Blue Swirl | Subtracting one gets us the call instruction itself. */
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283 | 7316329a | Stefan Weil | #if defined(CONFIG_TCG_INTERPRETER)
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284 | 7316329a | Stefan Weil | /* Alpha and SH4 user mode emulations and Softmmu call GETPC().
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285 | 7316329a | Stefan Weil | For all others, GETPC remains undefined (which makes TCI a little faster. */
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286 | 7316329a | Stefan Weil | # if defined(CONFIG_SOFTMMU) || defined(TARGET_ALPHA) || defined(TARGET_SH4)
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287 | 7316329a | Stefan Weil | extern void *tci_tb_ptr; |
288 | 7316329a | Stefan Weil | # define GETPC() tci_tb_ptr
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289 | 7316329a | Stefan Weil | # endif
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290 | 7316329a | Stefan Weil | #elif defined(__s390__) && !defined(__s390x__)
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291 | 3917149d | Blue Swirl | # define GETPC() ((void*)(((unsigned long)__builtin_return_address(0) & 0x7fffffffUL) - 1)) |
292 | 3917149d | Blue Swirl | #elif defined(__arm__)
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293 | 3917149d | Blue Swirl | /* Thumb return addresses have the low bit set, so we need to subtract two.
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294 | 3917149d | Blue Swirl | This is still safe in ARM mode because instructions are 4 bytes. */
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295 | 3917149d | Blue Swirl | # define GETPC() ((void *)((unsigned long)__builtin_return_address(0) - 2)) |
296 | 3917149d | Blue Swirl | #else
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297 | 3917149d | Blue Swirl | # define GETPC() ((void *)((unsigned long)__builtin_return_address(0) - 1)) |
298 | 3917149d | Blue Swirl | #endif
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299 | 3917149d | Blue Swirl | |
300 | e95c8d51 | bellard | #if !defined(CONFIG_USER_ONLY)
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301 | 6e59c1db | bellard | |
302 | 37ec01d4 | Avi Kivity | struct MemoryRegion *iotlb_to_region(target_phys_addr_t index);
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303 | 37ec01d4 | Avi Kivity | uint64_t io_mem_read(struct MemoryRegion *mr, target_phys_addr_t addr,
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304 | 37ec01d4 | Avi Kivity | unsigned size);
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305 | 37ec01d4 | Avi Kivity | void io_mem_write(struct MemoryRegion *mr, target_phys_addr_t addr, |
306 | 37ec01d4 | Avi Kivity | uint64_t value, unsigned size);
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307 | b3755a91 | Paul Brook | |
308 | bccd9ec5 | Blue Swirl | void tlb_fill(CPUState *env1, target_ulong addr, int is_write, int mmu_idx, |
309 | 6e59c1db | bellard | void *retaddr);
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310 | 6e59c1db | bellard | |
311 | 79383c9c | blueswir1 | #include "softmmu_defs.h" |
312 | 79383c9c | blueswir1 | |
313 | 6ebbf390 | j_mayer | #define ACCESS_TYPE (NB_MMU_MODES + 1) |
314 | 6e59c1db | bellard | #define MEMSUFFIX _code
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315 | 6e59c1db | bellard | #define env cpu_single_env
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316 | 6e59c1db | bellard | |
317 | 6e59c1db | bellard | #define DATA_SIZE 1 |
318 | 6e59c1db | bellard | #include "softmmu_header.h" |
319 | 6e59c1db | bellard | |
320 | 6e59c1db | bellard | #define DATA_SIZE 2 |
321 | 6e59c1db | bellard | #include "softmmu_header.h" |
322 | 6e59c1db | bellard | |
323 | 6e59c1db | bellard | #define DATA_SIZE 4 |
324 | 6e59c1db | bellard | #include "softmmu_header.h" |
325 | 6e59c1db | bellard | |
326 | c27004ec | bellard | #define DATA_SIZE 8 |
327 | c27004ec | bellard | #include "softmmu_header.h" |
328 | c27004ec | bellard | |
329 | 6e59c1db | bellard | #undef ACCESS_TYPE
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330 | 6e59c1db | bellard | #undef MEMSUFFIX
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331 | 6e59c1db | bellard | #undef env
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332 | 6e59c1db | bellard | |
333 | 6e59c1db | bellard | #endif
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334 | 4390df51 | bellard | |
335 | 4390df51 | bellard | #if defined(CONFIG_USER_ONLY)
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336 | 41c1b1c9 | Paul Brook | static inline tb_page_addr_t get_page_addr_code(CPUState *env1, target_ulong addr) |
337 | 4390df51 | bellard | { |
338 | 4390df51 | bellard | return addr;
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339 | 4390df51 | bellard | } |
340 | 4390df51 | bellard | #else
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341 | d39e8222 | Avi Kivity | tb_page_addr_t get_page_addr_code(CPUState *env1, target_ulong addr); |
342 | 4390df51 | bellard | #endif
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343 | 9df217a3 | bellard | |
344 | dde2367e | aliguori | typedef void (CPUDebugExcpHandler)(CPUState *env); |
345 | dde2367e | aliguori | |
346 | dde2367e | aliguori | CPUDebugExcpHandler *cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler); |
347 | 1b530a6d | aurel32 | |
348 | 1b530a6d | aurel32 | /* vl.c */
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349 | 1b530a6d | aurel32 | extern int singlestep; |
350 | 1b530a6d | aurel32 | |
351 | 1a28cac3 | Marcelo Tosatti | /* cpu-exec.c */
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352 | 1a28cac3 | Marcelo Tosatti | extern volatile sig_atomic_t exit_request; |
353 | 1a28cac3 | Marcelo Tosatti | |
354 | 946fb27c | Paolo Bonzini | /* Deterministic execution requires that IO only be performed on the last
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355 | 946fb27c | Paolo Bonzini | instruction of a TB so that interrupts take effect immediately. */
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356 | 946fb27c | Paolo Bonzini | static inline int can_do_io(CPUState *env) |
357 | 946fb27c | Paolo Bonzini | { |
358 | 946fb27c | Paolo Bonzini | if (!use_icount) {
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359 | 946fb27c | Paolo Bonzini | return 1; |
360 | 946fb27c | Paolo Bonzini | } |
361 | 946fb27c | Paolo Bonzini | /* If not executing code then assume we are ok. */
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362 | 946fb27c | Paolo Bonzini | if (!env->current_tb) {
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363 | 946fb27c | Paolo Bonzini | return 1; |
364 | 946fb27c | Paolo Bonzini | } |
365 | 946fb27c | Paolo Bonzini | return env->can_do_io != 0; |
366 | 946fb27c | Paolo Bonzini | } |
367 | 946fb27c | Paolo Bonzini | |
368 | 875cdcf6 | aliguori | #endif |