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1 | 79aceca5 | bellard | /*
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2 | 3fc6c082 | bellard | * PowerPC emulation for qemu: main translation routines.
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3 | 5fafdf24 | ths | *
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4 | 76a66253 | j_mayer | * Copyright (c) 2003-2007 Jocelyn Mayer
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5 | 79aceca5 | bellard | *
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6 | 79aceca5 | bellard | * This library is free software; you can redistribute it and/or
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7 | 79aceca5 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 79aceca5 | bellard | * License as published by the Free Software Foundation; either
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9 | 79aceca5 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 79aceca5 | bellard | *
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11 | 79aceca5 | bellard | * This library is distributed in the hope that it will be useful,
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12 | 79aceca5 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 79aceca5 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 79aceca5 | bellard | * Lesser General Public License for more details.
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15 | 79aceca5 | bellard | *
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16 | 79aceca5 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 79aceca5 | bellard | * License along with this library; if not, write to the Free Software
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18 | fad6cb1a | aurel32 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
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19 | 79aceca5 | bellard | */
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20 | c6a1c22b | bellard | #include <stdarg.h> |
21 | c6a1c22b | bellard | #include <stdlib.h> |
22 | c6a1c22b | bellard | #include <stdio.h> |
23 | c6a1c22b | bellard | #include <string.h> |
24 | c6a1c22b | bellard | #include <inttypes.h> |
25 | c6a1c22b | bellard | |
26 | 79aceca5 | bellard | #include "cpu.h" |
27 | c6a1c22b | bellard | #include "exec-all.h" |
28 | 79aceca5 | bellard | #include "disas.h" |
29 | 57fec1fe | bellard | #include "tcg-op.h" |
30 | ca10f867 | aurel32 | #include "qemu-common.h" |
31 | 0cfe11ea | aurel32 | #include "host-utils.h" |
32 | 79aceca5 | bellard | |
33 | a7812ae4 | pbrook | #include "helper.h" |
34 | a7812ae4 | pbrook | #define GEN_HELPER 1 |
35 | a7812ae4 | pbrook | #include "helper.h" |
36 | a7812ae4 | pbrook | |
37 | 8cbcb4fa | aurel32 | #define CPU_SINGLE_STEP 0x1 |
38 | 8cbcb4fa | aurel32 | #define CPU_BRANCH_STEP 0x2 |
39 | 8cbcb4fa | aurel32 | #define GDBSTUB_SINGLE_STEP 0x4 |
40 | 8cbcb4fa | aurel32 | |
41 | a750fc0b | j_mayer | /* Include definitions for instructions classes and implementations flags */
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42 | 9fddaa0c | bellard | //#define PPC_DEBUG_DISAS
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43 | 76a66253 | j_mayer | //#define DO_PPC_STATISTICS
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44 | 79aceca5 | bellard | |
45 | d12d51d5 | aliguori | #ifdef PPC_DEBUG_DISAS
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46 | 93fcfe39 | aliguori | # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) |
47 | d12d51d5 | aliguori | #else
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48 | d12d51d5 | aliguori | # define LOG_DISAS(...) do { } while (0) |
49 | d12d51d5 | aliguori | #endif
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50 | a750fc0b | j_mayer | /*****************************************************************************/
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51 | a750fc0b | j_mayer | /* Code translation helpers */
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52 | c53be334 | bellard | |
53 | f78fb44e | aurel32 | /* global register indexes */
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54 | a7812ae4 | pbrook | static TCGv_ptr cpu_env;
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55 | 1d542695 | aurel32 | static char cpu_reg_names[10*3 + 22*4 /* GPR */ |
56 | f78fb44e | aurel32 | #if !defined(TARGET_PPC64)
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57 | 1d542695 | aurel32 | + 10*4 + 22*5 /* SPE GPRh */ |
58 | f78fb44e | aurel32 | #endif
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59 | a5e26afa | aurel32 | + 10*4 + 22*5 /* FPR */ |
60 | 47e4661c | aurel32 | + 2*(10*6 + 22*7) /* AVRh, AVRl */ |
61 | 47e4661c | aurel32 | + 8*5 /* CRF */]; |
62 | f78fb44e | aurel32 | static TCGv cpu_gpr[32]; |
63 | f78fb44e | aurel32 | #if !defined(TARGET_PPC64)
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64 | f78fb44e | aurel32 | static TCGv cpu_gprh[32]; |
65 | f78fb44e | aurel32 | #endif
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66 | a7812ae4 | pbrook | static TCGv_i64 cpu_fpr[32]; |
67 | a7812ae4 | pbrook | static TCGv_i64 cpu_avrh[32], cpu_avrl[32]; |
68 | a7812ae4 | pbrook | static TCGv_i32 cpu_crf[8]; |
69 | bd568f18 | aurel32 | static TCGv cpu_nip;
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70 | 6527f6ea | aurel32 | static TCGv cpu_msr;
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71 | cfdcd37a | aurel32 | static TCGv cpu_ctr;
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72 | cfdcd37a | aurel32 | static TCGv cpu_lr;
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73 | 3d7b417e | aurel32 | static TCGv cpu_xer;
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74 | cf360a32 | aurel32 | static TCGv cpu_reserve;
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75 | a7812ae4 | pbrook | static TCGv_i32 cpu_fpscr;
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76 | a7859e89 | aurel32 | static TCGv_i32 cpu_access_type;
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77 | f78fb44e | aurel32 | |
78 | 2e70f6ef | pbrook | #include "gen-icount.h" |
79 | 2e70f6ef | pbrook | |
80 | 2e70f6ef | pbrook | void ppc_translate_init(void) |
81 | 2e70f6ef | pbrook | { |
82 | f78fb44e | aurel32 | int i;
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83 | f78fb44e | aurel32 | char* p;
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84 | 2dc766da | blueswir1 | size_t cpu_reg_names_size; |
85 | b2437bf2 | pbrook | static int done_init = 0; |
86 | f78fb44e | aurel32 | |
87 | 2e70f6ef | pbrook | if (done_init)
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88 | 2e70f6ef | pbrook | return;
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89 | f78fb44e | aurel32 | |
90 | a7812ae4 | pbrook | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
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91 | a7812ae4 | pbrook | |
92 | f78fb44e | aurel32 | p = cpu_reg_names; |
93 | 2dc766da | blueswir1 | cpu_reg_names_size = sizeof(cpu_reg_names);
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94 | 47e4661c | aurel32 | |
95 | 47e4661c | aurel32 | for (i = 0; i < 8; i++) { |
96 | 2dc766da | blueswir1 | snprintf(p, cpu_reg_names_size, "crf%d", i);
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97 | a7812ae4 | pbrook | cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0, |
98 | a7812ae4 | pbrook | offsetof(CPUState, crf[i]), p); |
99 | 47e4661c | aurel32 | p += 5;
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100 | 2dc766da | blueswir1 | cpu_reg_names_size -= 5;
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101 | 47e4661c | aurel32 | } |
102 | 47e4661c | aurel32 | |
103 | f78fb44e | aurel32 | for (i = 0; i < 32; i++) { |
104 | 2dc766da | blueswir1 | snprintf(p, cpu_reg_names_size, "r%d", i);
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105 | a7812ae4 | pbrook | cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0, |
106 | f78fb44e | aurel32 | offsetof(CPUState, gpr[i]), p); |
107 | f78fb44e | aurel32 | p += (i < 10) ? 3 : 4; |
108 | 2dc766da | blueswir1 | cpu_reg_names_size -= (i < 10) ? 3 : 4; |
109 | f78fb44e | aurel32 | #if !defined(TARGET_PPC64)
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110 | 2dc766da | blueswir1 | snprintf(p, cpu_reg_names_size, "r%dH", i);
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111 | a7812ae4 | pbrook | cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0, |
112 | a7812ae4 | pbrook | offsetof(CPUState, gprh[i]), p); |
113 | f78fb44e | aurel32 | p += (i < 10) ? 4 : 5; |
114 | 2dc766da | blueswir1 | cpu_reg_names_size -= (i < 10) ? 4 : 5; |
115 | f78fb44e | aurel32 | #endif
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116 | 1d542695 | aurel32 | |
117 | 2dc766da | blueswir1 | snprintf(p, cpu_reg_names_size, "fp%d", i);
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118 | a7812ae4 | pbrook | cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0, |
119 | a7812ae4 | pbrook | offsetof(CPUState, fpr[i]), p); |
120 | ec1ac72d | aurel32 | p += (i < 10) ? 4 : 5; |
121 | 2dc766da | blueswir1 | cpu_reg_names_size -= (i < 10) ? 4 : 5; |
122 | a5e26afa | aurel32 | |
123 | 2dc766da | blueswir1 | snprintf(p, cpu_reg_names_size, "avr%dH", i);
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124 | fe1e5c53 | aurel32 | #ifdef WORDS_BIGENDIAN
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125 | fe1e5c53 | aurel32 | cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0, |
126 | fe1e5c53 | aurel32 | offsetof(CPUState, avr[i].u64[0]), p);
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127 | fe1e5c53 | aurel32 | #else
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128 | a7812ae4 | pbrook | cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0, |
129 | fe1e5c53 | aurel32 | offsetof(CPUState, avr[i].u64[1]), p);
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130 | fe1e5c53 | aurel32 | #endif
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131 | 1d542695 | aurel32 | p += (i < 10) ? 6 : 7; |
132 | 2dc766da | blueswir1 | cpu_reg_names_size -= (i < 10) ? 6 : 7; |
133 | ec1ac72d | aurel32 | |
134 | 2dc766da | blueswir1 | snprintf(p, cpu_reg_names_size, "avr%dL", i);
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135 | fe1e5c53 | aurel32 | #ifdef WORDS_BIGENDIAN
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136 | fe1e5c53 | aurel32 | cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0, |
137 | fe1e5c53 | aurel32 | offsetof(CPUState, avr[i].u64[1]), p);
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138 | fe1e5c53 | aurel32 | #else
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139 | a7812ae4 | pbrook | cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0, |
140 | fe1e5c53 | aurel32 | offsetof(CPUState, avr[i].u64[0]), p);
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141 | fe1e5c53 | aurel32 | #endif
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142 | 1d542695 | aurel32 | p += (i < 10) ? 6 : 7; |
143 | 2dc766da | blueswir1 | cpu_reg_names_size -= (i < 10) ? 6 : 7; |
144 | f78fb44e | aurel32 | } |
145 | f10dc08e | aurel32 | |
146 | a7812ae4 | pbrook | cpu_nip = tcg_global_mem_new(TCG_AREG0, |
147 | bd568f18 | aurel32 | offsetof(CPUState, nip), "nip");
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148 | bd568f18 | aurel32 | |
149 | 6527f6ea | aurel32 | cpu_msr = tcg_global_mem_new(TCG_AREG0, |
150 | 6527f6ea | aurel32 | offsetof(CPUState, msr), "msr");
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151 | 6527f6ea | aurel32 | |
152 | a7812ae4 | pbrook | cpu_ctr = tcg_global_mem_new(TCG_AREG0, |
153 | cfdcd37a | aurel32 | offsetof(CPUState, ctr), "ctr");
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154 | cfdcd37a | aurel32 | |
155 | a7812ae4 | pbrook | cpu_lr = tcg_global_mem_new(TCG_AREG0, |
156 | cfdcd37a | aurel32 | offsetof(CPUState, lr), "lr");
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157 | cfdcd37a | aurel32 | |
158 | a7812ae4 | pbrook | cpu_xer = tcg_global_mem_new(TCG_AREG0, |
159 | 3d7b417e | aurel32 | offsetof(CPUState, xer), "xer");
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160 | 3d7b417e | aurel32 | |
161 | cf360a32 | aurel32 | cpu_reserve = tcg_global_mem_new(TCG_AREG0, |
162 | cf360a32 | aurel32 | offsetof(CPUState, reserve), "reserve");
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163 | cf360a32 | aurel32 | |
164 | a7812ae4 | pbrook | cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0, |
165 | a7812ae4 | pbrook | offsetof(CPUState, fpscr), "fpscr");
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166 | e1571908 | aurel32 | |
167 | a7859e89 | aurel32 | cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0, |
168 | a7859e89 | aurel32 | offsetof(CPUState, access_type), "access_type");
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169 | a7859e89 | aurel32 | |
170 | f10dc08e | aurel32 | /* register helpers */
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171 | a7812ae4 | pbrook | #define GEN_HELPER 2 |
172 | f10dc08e | aurel32 | #include "helper.h" |
173 | f10dc08e | aurel32 | |
174 | 2e70f6ef | pbrook | done_init = 1;
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175 | 2e70f6ef | pbrook | } |
176 | 2e70f6ef | pbrook | |
177 | 79aceca5 | bellard | /* internal defines */
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178 | 79aceca5 | bellard | typedef struct DisasContext { |
179 | 79aceca5 | bellard | struct TranslationBlock *tb;
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180 | 0fa85d43 | bellard | target_ulong nip; |
181 | 79aceca5 | bellard | uint32_t opcode; |
182 | 9a64fbe4 | bellard | uint32_t exception; |
183 | 3cc62370 | bellard | /* Routine used to access memory */
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184 | 3cc62370 | bellard | int mem_idx;
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185 | 76db3ba4 | aurel32 | int access_type;
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186 | 3cc62370 | bellard | /* Translation flags */
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187 | 76db3ba4 | aurel32 | int le_mode;
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188 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
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189 | d9bce9d9 | j_mayer | int sf_mode;
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190 | d9bce9d9 | j_mayer | #endif
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191 | 3cc62370 | bellard | int fpu_enabled;
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192 | a9d9eb8f | j_mayer | int altivec_enabled;
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193 | 0487d6a8 | j_mayer | int spe_enabled;
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194 | 3fc6c082 | bellard | ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
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195 | ea4e754f | bellard | int singlestep_enabled;
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196 | 79aceca5 | bellard | } DisasContext; |
197 | 79aceca5 | bellard | |
198 | 3fc6c082 | bellard | struct opc_handler_t {
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199 | 79aceca5 | bellard | /* invalid bits */
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200 | 79aceca5 | bellard | uint32_t inval; |
201 | 9a64fbe4 | bellard | /* instruction type */
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202 | 0487d6a8 | j_mayer | uint64_t type; |
203 | 79aceca5 | bellard | /* handler */
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204 | 79aceca5 | bellard | void (*handler)(DisasContext *ctx);
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205 | a750fc0b | j_mayer | #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
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206 | b55266b5 | blueswir1 | const char *oname; |
207 | a750fc0b | j_mayer | #endif
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208 | a750fc0b | j_mayer | #if defined(DO_PPC_STATISTICS)
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209 | 76a66253 | j_mayer | uint64_t count; |
210 | 76a66253 | j_mayer | #endif
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211 | 3fc6c082 | bellard | }; |
212 | 79aceca5 | bellard | |
213 | 7c58044c | j_mayer | static always_inline void gen_reset_fpstatus (void) |
214 | 7c58044c | j_mayer | { |
215 | 7c58044c | j_mayer | #ifdef CONFIG_SOFTFLOAT
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216 | a44d2ce1 | aurel32 | gen_helper_reset_fpstatus(); |
217 | 7c58044c | j_mayer | #endif
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218 | 7c58044c | j_mayer | } |
219 | 7c58044c | j_mayer | |
220 | 0f2f39c2 | aurel32 | static always_inline void gen_compute_fprf (TCGv_i64 arg, int set_fprf, int set_rc) |
221 | 7c58044c | j_mayer | { |
222 | 0f2f39c2 | aurel32 | TCGv_i32 t0 = tcg_temp_new_i32(); |
223 | af12906f | aurel32 | |
224 | 7c58044c | j_mayer | if (set_fprf != 0) { |
225 | 7c58044c | j_mayer | /* This case might be optimized later */
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226 | 0f2f39c2 | aurel32 | tcg_gen_movi_i32(t0, 1);
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227 | af12906f | aurel32 | gen_helper_compute_fprf(t0, arg, t0); |
228 | a7812ae4 | pbrook | if (unlikely(set_rc)) {
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229 | 0f2f39c2 | aurel32 | tcg_gen_mov_i32(cpu_crf[1], t0);
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230 | a7812ae4 | pbrook | } |
231 | af12906f | aurel32 | gen_helper_float_check_status(); |
232 | 7c58044c | j_mayer | } else if (unlikely(set_rc)) { |
233 | 7c58044c | j_mayer | /* We always need to compute fpcc */
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234 | 0f2f39c2 | aurel32 | tcg_gen_movi_i32(t0, 0);
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235 | af12906f | aurel32 | gen_helper_compute_fprf(t0, arg, t0); |
236 | 0f2f39c2 | aurel32 | tcg_gen_mov_i32(cpu_crf[1], t0);
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237 | 7c58044c | j_mayer | } |
238 | af12906f | aurel32 | |
239 | 0f2f39c2 | aurel32 | tcg_temp_free_i32(t0); |
240 | 7c58044c | j_mayer | } |
241 | 7c58044c | j_mayer | |
242 | 76db3ba4 | aurel32 | static always_inline void gen_set_access_type (DisasContext *ctx, int access_type) |
243 | a7859e89 | aurel32 | { |
244 | 76db3ba4 | aurel32 | if (ctx->access_type != access_type) {
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245 | 76db3ba4 | aurel32 | tcg_gen_movi_i32(cpu_access_type, access_type); |
246 | 76db3ba4 | aurel32 | ctx->access_type = access_type; |
247 | 76db3ba4 | aurel32 | } |
248 | a7859e89 | aurel32 | } |
249 | a7859e89 | aurel32 | |
250 | b068d6a7 | j_mayer | static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip) |
251 | d9bce9d9 | j_mayer | { |
252 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
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253 | d9bce9d9 | j_mayer | if (ctx->sf_mode)
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254 | bd568f18 | aurel32 | tcg_gen_movi_tl(cpu_nip, nip); |
255 | d9bce9d9 | j_mayer | else
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256 | d9bce9d9 | j_mayer | #endif
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257 | bd568f18 | aurel32 | tcg_gen_movi_tl(cpu_nip, (uint32_t)nip); |
258 | d9bce9d9 | j_mayer | } |
259 | d9bce9d9 | j_mayer | |
260 | e06fcd75 | aurel32 | static always_inline void gen_exception_err (DisasContext *ctx, uint32_t excp, uint32_t error) |
261 | e06fcd75 | aurel32 | { |
262 | e06fcd75 | aurel32 | TCGv_i32 t0, t1; |
263 | e06fcd75 | aurel32 | if (ctx->exception == POWERPC_EXCP_NONE) {
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264 | e06fcd75 | aurel32 | gen_update_nip(ctx, ctx->nip); |
265 | e06fcd75 | aurel32 | } |
266 | e06fcd75 | aurel32 | t0 = tcg_const_i32(excp); |
267 | e06fcd75 | aurel32 | t1 = tcg_const_i32(error); |
268 | e06fcd75 | aurel32 | gen_helper_raise_exception_err(t0, t1); |
269 | e06fcd75 | aurel32 | tcg_temp_free_i32(t0); |
270 | e06fcd75 | aurel32 | tcg_temp_free_i32(t1); |
271 | e06fcd75 | aurel32 | ctx->exception = (excp); |
272 | e06fcd75 | aurel32 | } |
273 | e1833e1f | j_mayer | |
274 | e06fcd75 | aurel32 | static always_inline void gen_exception (DisasContext *ctx, uint32_t excp) |
275 | e06fcd75 | aurel32 | { |
276 | e06fcd75 | aurel32 | TCGv_i32 t0; |
277 | e06fcd75 | aurel32 | if (ctx->exception == POWERPC_EXCP_NONE) {
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278 | e06fcd75 | aurel32 | gen_update_nip(ctx, ctx->nip); |
279 | e06fcd75 | aurel32 | } |
280 | e06fcd75 | aurel32 | t0 = tcg_const_i32(excp); |
281 | e06fcd75 | aurel32 | gen_helper_raise_exception(t0); |
282 | e06fcd75 | aurel32 | tcg_temp_free_i32(t0); |
283 | e06fcd75 | aurel32 | ctx->exception = (excp); |
284 | e06fcd75 | aurel32 | } |
285 | e1833e1f | j_mayer | |
286 | e06fcd75 | aurel32 | static always_inline void gen_debug_exception (DisasContext *ctx) |
287 | e06fcd75 | aurel32 | { |
288 | e06fcd75 | aurel32 | TCGv_i32 t0; |
289 | 5518f3a6 | blueswir1 | |
290 | 5518f3a6 | blueswir1 | if (ctx->exception != POWERPC_EXCP_BRANCH)
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291 | 5518f3a6 | blueswir1 | gen_update_nip(ctx, ctx->nip); |
292 | e06fcd75 | aurel32 | t0 = tcg_const_i32(EXCP_DEBUG); |
293 | e06fcd75 | aurel32 | gen_helper_raise_exception(t0); |
294 | e06fcd75 | aurel32 | tcg_temp_free_i32(t0); |
295 | e06fcd75 | aurel32 | } |
296 | 9a64fbe4 | bellard | |
297 | e06fcd75 | aurel32 | static always_inline void gen_inval_exception (DisasContext *ctx, uint32_t error) |
298 | e06fcd75 | aurel32 | { |
299 | e06fcd75 | aurel32 | gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error); |
300 | e06fcd75 | aurel32 | } |
301 | a9d9eb8f | j_mayer | |
302 | f24e5695 | bellard | /* Stop translation */
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303 | e06fcd75 | aurel32 | static always_inline void gen_stop_exception (DisasContext *ctx) |
304 | 3fc6c082 | bellard | { |
305 | d9bce9d9 | j_mayer | gen_update_nip(ctx, ctx->nip); |
306 | e1833e1f | j_mayer | ctx->exception = POWERPC_EXCP_STOP; |
307 | 3fc6c082 | bellard | } |
308 | 3fc6c082 | bellard | |
309 | f24e5695 | bellard | /* No need to update nip here, as execution flow will change */
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310 | e06fcd75 | aurel32 | static always_inline void gen_sync_exception (DisasContext *ctx) |
311 | 2be0071f | bellard | { |
312 | e1833e1f | j_mayer | ctx->exception = POWERPC_EXCP_SYNC; |
313 | 2be0071f | bellard | } |
314 | 2be0071f | bellard | |
315 | 79aceca5 | bellard | #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
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316 | 5c55ff99 | Blue Swirl | GEN_OPCODE(name, opc1, opc2, opc3, inval, type) |
317 | 79aceca5 | bellard | |
318 | c7697e1f | j_mayer | #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
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319 | 5c55ff99 | Blue Swirl | GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type) |
320 | c7697e1f | j_mayer | |
321 | 79aceca5 | bellard | typedef struct opcode_t { |
322 | 79aceca5 | bellard | unsigned char opc1, opc2, opc3; |
323 | 1235fc06 | ths | #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ |
324 | 18fba28c | bellard | unsigned char pad[5]; |
325 | 18fba28c | bellard | #else
|
326 | 18fba28c | bellard | unsigned char pad[1]; |
327 | 18fba28c | bellard | #endif
|
328 | 79aceca5 | bellard | opc_handler_t handler; |
329 | b55266b5 | blueswir1 | const char *oname; |
330 | 79aceca5 | bellard | } opcode_t; |
331 | 79aceca5 | bellard | |
332 | a750fc0b | j_mayer | /*****************************************************************************/
|
333 | 79aceca5 | bellard | /*** Instruction decoding ***/
|
334 | 79aceca5 | bellard | #define EXTRACT_HELPER(name, shift, nb) \
|
335 | b068d6a7 | j_mayer | static always_inline uint32_t name (uint32_t opcode) \
|
336 | 79aceca5 | bellard | { \ |
337 | 79aceca5 | bellard | return (opcode >> (shift)) & ((1 << (nb)) - 1); \ |
338 | 79aceca5 | bellard | } |
339 | 79aceca5 | bellard | |
340 | 79aceca5 | bellard | #define EXTRACT_SHELPER(name, shift, nb) \
|
341 | b068d6a7 | j_mayer | static always_inline int32_t name (uint32_t opcode) \
|
342 | 79aceca5 | bellard | { \ |
343 | 18fba28c | bellard | return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \ |
344 | 79aceca5 | bellard | } |
345 | 79aceca5 | bellard | |
346 | 79aceca5 | bellard | /* Opcode part 1 */
|
347 | 79aceca5 | bellard | EXTRACT_HELPER(opc1, 26, 6); |
348 | 79aceca5 | bellard | /* Opcode part 2 */
|
349 | 79aceca5 | bellard | EXTRACT_HELPER(opc2, 1, 5); |
350 | 79aceca5 | bellard | /* Opcode part 3 */
|
351 | 79aceca5 | bellard | EXTRACT_HELPER(opc3, 6, 5); |
352 | 79aceca5 | bellard | /* Update Cr0 flags */
|
353 | 79aceca5 | bellard | EXTRACT_HELPER(Rc, 0, 1); |
354 | 79aceca5 | bellard | /* Destination */
|
355 | 79aceca5 | bellard | EXTRACT_HELPER(rD, 21, 5); |
356 | 79aceca5 | bellard | /* Source */
|
357 | 79aceca5 | bellard | EXTRACT_HELPER(rS, 21, 5); |
358 | 79aceca5 | bellard | /* First operand */
|
359 | 79aceca5 | bellard | EXTRACT_HELPER(rA, 16, 5); |
360 | 79aceca5 | bellard | /* Second operand */
|
361 | 79aceca5 | bellard | EXTRACT_HELPER(rB, 11, 5); |
362 | 79aceca5 | bellard | /* Third operand */
|
363 | 79aceca5 | bellard | EXTRACT_HELPER(rC, 6, 5); |
364 | 79aceca5 | bellard | /*** Get CRn ***/
|
365 | 79aceca5 | bellard | EXTRACT_HELPER(crfD, 23, 3); |
366 | 79aceca5 | bellard | EXTRACT_HELPER(crfS, 18, 3); |
367 | 79aceca5 | bellard | EXTRACT_HELPER(crbD, 21, 5); |
368 | 79aceca5 | bellard | EXTRACT_HELPER(crbA, 16, 5); |
369 | 79aceca5 | bellard | EXTRACT_HELPER(crbB, 11, 5); |
370 | 79aceca5 | bellard | /* SPR / TBL */
|
371 | 3fc6c082 | bellard | EXTRACT_HELPER(_SPR, 11, 10); |
372 | b068d6a7 | j_mayer | static always_inline uint32_t SPR (uint32_t opcode)
|
373 | 3fc6c082 | bellard | { |
374 | 3fc6c082 | bellard | uint32_t sprn = _SPR(opcode); |
375 | 3fc6c082 | bellard | |
376 | 3fc6c082 | bellard | return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); |
377 | 3fc6c082 | bellard | } |
378 | 79aceca5 | bellard | /*** Get constants ***/
|
379 | 79aceca5 | bellard | EXTRACT_HELPER(IMM, 12, 8); |
380 | 79aceca5 | bellard | /* 16 bits signed immediate value */
|
381 | 79aceca5 | bellard | EXTRACT_SHELPER(SIMM, 0, 16); |
382 | 79aceca5 | bellard | /* 16 bits unsigned immediate value */
|
383 | 79aceca5 | bellard | EXTRACT_HELPER(UIMM, 0, 16); |
384 | 21d21583 | aurel32 | /* 5 bits signed immediate value */
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385 | 21d21583 | aurel32 | EXTRACT_HELPER(SIMM5, 16, 5); |
386 | 27a4edb3 | aurel32 | /* 5 bits signed immediate value */
|
387 | 27a4edb3 | aurel32 | EXTRACT_HELPER(UIMM5, 16, 5); |
388 | 79aceca5 | bellard | /* Bit count */
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389 | 79aceca5 | bellard | EXTRACT_HELPER(NB, 11, 5); |
390 | 79aceca5 | bellard | /* Shift count */
|
391 | 79aceca5 | bellard | EXTRACT_HELPER(SH, 11, 5); |
392 | cd633b10 | aurel32 | /* Vector shift count */
|
393 | cd633b10 | aurel32 | EXTRACT_HELPER(VSH, 6, 4); |
394 | 79aceca5 | bellard | /* Mask start */
|
395 | 79aceca5 | bellard | EXTRACT_HELPER(MB, 6, 5); |
396 | 79aceca5 | bellard | /* Mask end */
|
397 | 79aceca5 | bellard | EXTRACT_HELPER(ME, 1, 5); |
398 | fb0eaffc | bellard | /* Trap operand */
|
399 | fb0eaffc | bellard | EXTRACT_HELPER(TO, 21, 5); |
400 | 79aceca5 | bellard | |
401 | 79aceca5 | bellard | EXTRACT_HELPER(CRM, 12, 8); |
402 | 79aceca5 | bellard | EXTRACT_HELPER(FM, 17, 8); |
403 | 79aceca5 | bellard | EXTRACT_HELPER(SR, 16, 4); |
404 | e4bb997e | aurel32 | EXTRACT_HELPER(FPIMM, 12, 4); |
405 | fb0eaffc | bellard | |
406 | 79aceca5 | bellard | /*** Jump target decoding ***/
|
407 | 79aceca5 | bellard | /* Displacement */
|
408 | 79aceca5 | bellard | EXTRACT_SHELPER(d, 0, 16); |
409 | 79aceca5 | bellard | /* Immediate address */
|
410 | b068d6a7 | j_mayer | static always_inline target_ulong LI (uint32_t opcode)
|
411 | 79aceca5 | bellard | { |
412 | 79aceca5 | bellard | return (opcode >> 0) & 0x03FFFFFC; |
413 | 79aceca5 | bellard | } |
414 | 79aceca5 | bellard | |
415 | b068d6a7 | j_mayer | static always_inline uint32_t BD (uint32_t opcode)
|
416 | 79aceca5 | bellard | { |
417 | 79aceca5 | bellard | return (opcode >> 0) & 0xFFFC; |
418 | 79aceca5 | bellard | } |
419 | 79aceca5 | bellard | |
420 | 79aceca5 | bellard | EXTRACT_HELPER(BO, 21, 5); |
421 | 79aceca5 | bellard | EXTRACT_HELPER(BI, 16, 5); |
422 | 79aceca5 | bellard | /* Absolute/relative address */
|
423 | 79aceca5 | bellard | EXTRACT_HELPER(AA, 1, 1); |
424 | 79aceca5 | bellard | /* Link */
|
425 | 79aceca5 | bellard | EXTRACT_HELPER(LK, 0, 1); |
426 | 79aceca5 | bellard | |
427 | 79aceca5 | bellard | /* Create a mask between <start> and <end> bits */
|
428 | b068d6a7 | j_mayer | static always_inline target_ulong MASK (uint32_t start, uint32_t end)
|
429 | 79aceca5 | bellard | { |
430 | 76a66253 | j_mayer | target_ulong ret; |
431 | 79aceca5 | bellard | |
432 | 76a66253 | j_mayer | #if defined(TARGET_PPC64)
|
433 | 76a66253 | j_mayer | if (likely(start == 0)) { |
434 | 6f2d8978 | j_mayer | ret = UINT64_MAX << (63 - end);
|
435 | 76a66253 | j_mayer | } else if (likely(end == 63)) { |
436 | 6f2d8978 | j_mayer | ret = UINT64_MAX >> start; |
437 | 76a66253 | j_mayer | } |
438 | 76a66253 | j_mayer | #else
|
439 | 76a66253 | j_mayer | if (likely(start == 0)) { |
440 | 6f2d8978 | j_mayer | ret = UINT32_MAX << (31 - end);
|
441 | 76a66253 | j_mayer | } else if (likely(end == 31)) { |
442 | 6f2d8978 | j_mayer | ret = UINT32_MAX >> start; |
443 | 76a66253 | j_mayer | } |
444 | 76a66253 | j_mayer | #endif
|
445 | 76a66253 | j_mayer | else {
|
446 | 76a66253 | j_mayer | ret = (((target_ulong)(-1ULL)) >> (start)) ^
|
447 | 76a66253 | j_mayer | (((target_ulong)(-1ULL) >> (end)) >> 1); |
448 | 76a66253 | j_mayer | if (unlikely(start > end))
|
449 | 76a66253 | j_mayer | return ~ret;
|
450 | 76a66253 | j_mayer | } |
451 | 79aceca5 | bellard | |
452 | 79aceca5 | bellard | return ret;
|
453 | 79aceca5 | bellard | } |
454 | 79aceca5 | bellard | |
455 | a750fc0b | j_mayer | /*****************************************************************************/
|
456 | a750fc0b | j_mayer | /* PowerPC instructions table */
|
457 | 933dc6eb | bellard | |
458 | 76a66253 | j_mayer | #if defined(DO_PPC_STATISTICS)
|
459 | 79aceca5 | bellard | #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
|
460 | 5c55ff99 | Blue Swirl | { \ |
461 | 79aceca5 | bellard | .opc1 = op1, \ |
462 | 79aceca5 | bellard | .opc2 = op2, \ |
463 | 79aceca5 | bellard | .opc3 = op3, \ |
464 | 18fba28c | bellard | .pad = { 0, }, \
|
465 | 79aceca5 | bellard | .handler = { \ |
466 | 79aceca5 | bellard | .inval = invl, \ |
467 | 9a64fbe4 | bellard | .type = _typ, \ |
468 | 79aceca5 | bellard | .handler = &gen_##name, \ |
469 | 76a66253 | j_mayer | .oname = stringify(name), \ |
470 | 79aceca5 | bellard | }, \ |
471 | 3fc6c082 | bellard | .oname = stringify(name), \ |
472 | 79aceca5 | bellard | } |
473 | c7697e1f | j_mayer | #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
|
474 | 5c55ff99 | Blue Swirl | { \ |
475 | c7697e1f | j_mayer | .opc1 = op1, \ |
476 | c7697e1f | j_mayer | .opc2 = op2, \ |
477 | c7697e1f | j_mayer | .opc3 = op3, \ |
478 | c7697e1f | j_mayer | .pad = { 0, }, \
|
479 | c7697e1f | j_mayer | .handler = { \ |
480 | c7697e1f | j_mayer | .inval = invl, \ |
481 | c7697e1f | j_mayer | .type = _typ, \ |
482 | c7697e1f | j_mayer | .handler = &gen_##name, \ |
483 | c7697e1f | j_mayer | .oname = onam, \ |
484 | c7697e1f | j_mayer | }, \ |
485 | c7697e1f | j_mayer | .oname = onam, \ |
486 | c7697e1f | j_mayer | } |
487 | 76a66253 | j_mayer | #else
|
488 | 76a66253 | j_mayer | #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
|
489 | 5c55ff99 | Blue Swirl | { \ |
490 | c7697e1f | j_mayer | .opc1 = op1, \ |
491 | c7697e1f | j_mayer | .opc2 = op2, \ |
492 | c7697e1f | j_mayer | .opc3 = op3, \ |
493 | c7697e1f | j_mayer | .pad = { 0, }, \
|
494 | c7697e1f | j_mayer | .handler = { \ |
495 | c7697e1f | j_mayer | .inval = invl, \ |
496 | c7697e1f | j_mayer | .type = _typ, \ |
497 | c7697e1f | j_mayer | .handler = &gen_##name, \ |
498 | 5c55ff99 | Blue Swirl | }, \ |
499 | 5c55ff99 | Blue Swirl | .oname = stringify(name), \ |
500 | 5c55ff99 | Blue Swirl | } |
501 | 5c55ff99 | Blue Swirl | #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
|
502 | 5c55ff99 | Blue Swirl | { \ |
503 | 5c55ff99 | Blue Swirl | .opc1 = op1, \ |
504 | 5c55ff99 | Blue Swirl | .opc2 = op2, \ |
505 | 5c55ff99 | Blue Swirl | .opc3 = op3, \ |
506 | 5c55ff99 | Blue Swirl | .pad = { 0, }, \
|
507 | 5c55ff99 | Blue Swirl | .handler = { \ |
508 | 5c55ff99 | Blue Swirl | .inval = invl, \ |
509 | 5c55ff99 | Blue Swirl | .type = _typ, \ |
510 | 5c55ff99 | Blue Swirl | .handler = &gen_##name, \ |
511 | 5c55ff99 | Blue Swirl | }, \ |
512 | 5c55ff99 | Blue Swirl | .oname = onam, \ |
513 | 5c55ff99 | Blue Swirl | } |
514 | 5c55ff99 | Blue Swirl | #endif
|
515 | 2e610050 | Blue Swirl | |
516 | 5c55ff99 | Blue Swirl | /* SPR load/store helpers */
|
517 | 5c55ff99 | Blue Swirl | static always_inline void gen_load_spr(TCGv t, int reg) |
518 | 5c55ff99 | Blue Swirl | { |
519 | 5c55ff99 | Blue Swirl | tcg_gen_ld_tl(t, cpu_env, offsetof(CPUState, spr[reg])); |
520 | 5c55ff99 | Blue Swirl | } |
521 | 2e610050 | Blue Swirl | |
522 | 5c55ff99 | Blue Swirl | static always_inline void gen_store_spr(int reg, TCGv t) |
523 | 5c55ff99 | Blue Swirl | { |
524 | 5c55ff99 | Blue Swirl | tcg_gen_st_tl(t, cpu_env, offsetof(CPUState, spr[reg])); |
525 | 5c55ff99 | Blue Swirl | } |
526 | 2e610050 | Blue Swirl | |
527 | 54623277 | Blue Swirl | /* Invalid instruction */
|
528 | 99e300ef | Blue Swirl | static void gen_invalid(DisasContext *ctx) |
529 | 9a64fbe4 | bellard | { |
530 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
531 | 9a64fbe4 | bellard | } |
532 | 9a64fbe4 | bellard | |
533 | 79aceca5 | bellard | static opc_handler_t invalid_handler = {
|
534 | 79aceca5 | bellard | .inval = 0xFFFFFFFF,
|
535 | 9a64fbe4 | bellard | .type = PPC_NONE, |
536 | 79aceca5 | bellard | .handler = gen_invalid, |
537 | 79aceca5 | bellard | }; |
538 | 79aceca5 | bellard | |
539 | e1571908 | aurel32 | /*** Integer comparison ***/
|
540 | e1571908 | aurel32 | |
541 | ea363694 | aurel32 | static always_inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) |
542 | e1571908 | aurel32 | { |
543 | e1571908 | aurel32 | int l1, l2, l3;
|
544 | e1571908 | aurel32 | |
545 | 269f3e95 | aurel32 | tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer); |
546 | 269f3e95 | aurel32 | tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO); |
547 | e1571908 | aurel32 | tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);
|
548 | e1571908 | aurel32 | |
549 | e1571908 | aurel32 | l1 = gen_new_label(); |
550 | e1571908 | aurel32 | l2 = gen_new_label(); |
551 | e1571908 | aurel32 | l3 = gen_new_label(); |
552 | e1571908 | aurel32 | if (s) {
|
553 | ea363694 | aurel32 | tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1); |
554 | ea363694 | aurel32 | tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2); |
555 | e1571908 | aurel32 | } else {
|
556 | ea363694 | aurel32 | tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1); |
557 | ea363694 | aurel32 | tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2); |
558 | e1571908 | aurel32 | } |
559 | e1571908 | aurel32 | tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);
|
560 | e1571908 | aurel32 | tcg_gen_br(l3); |
561 | e1571908 | aurel32 | gen_set_label(l1); |
562 | e1571908 | aurel32 | tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);
|
563 | e1571908 | aurel32 | tcg_gen_br(l3); |
564 | e1571908 | aurel32 | gen_set_label(l2); |
565 | e1571908 | aurel32 | tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);
|
566 | e1571908 | aurel32 | gen_set_label(l3); |
567 | e1571908 | aurel32 | } |
568 | e1571908 | aurel32 | |
569 | ea363694 | aurel32 | static always_inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) |
570 | e1571908 | aurel32 | { |
571 | ea363694 | aurel32 | TCGv t0 = tcg_const_local_tl(arg1); |
572 | ea363694 | aurel32 | gen_op_cmp(arg0, t0, s, crf); |
573 | ea363694 | aurel32 | tcg_temp_free(t0); |
574 | e1571908 | aurel32 | } |
575 | e1571908 | aurel32 | |
576 | e1571908 | aurel32 | #if defined(TARGET_PPC64)
|
577 | ea363694 | aurel32 | static always_inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) |
578 | e1571908 | aurel32 | { |
579 | ea363694 | aurel32 | TCGv t0, t1; |
580 | a7812ae4 | pbrook | t0 = tcg_temp_local_new(); |
581 | a7812ae4 | pbrook | t1 = tcg_temp_local_new(); |
582 | e1571908 | aurel32 | if (s) {
|
583 | ea363694 | aurel32 | tcg_gen_ext32s_tl(t0, arg0); |
584 | ea363694 | aurel32 | tcg_gen_ext32s_tl(t1, arg1); |
585 | e1571908 | aurel32 | } else {
|
586 | ea363694 | aurel32 | tcg_gen_ext32u_tl(t0, arg0); |
587 | ea363694 | aurel32 | tcg_gen_ext32u_tl(t1, arg1); |
588 | e1571908 | aurel32 | } |
589 | ea363694 | aurel32 | gen_op_cmp(t0, t1, s, crf); |
590 | ea363694 | aurel32 | tcg_temp_free(t1); |
591 | ea363694 | aurel32 | tcg_temp_free(t0); |
592 | e1571908 | aurel32 | } |
593 | e1571908 | aurel32 | |
594 | ea363694 | aurel32 | static always_inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) |
595 | e1571908 | aurel32 | { |
596 | ea363694 | aurel32 | TCGv t0 = tcg_const_local_tl(arg1); |
597 | ea363694 | aurel32 | gen_op_cmp32(arg0, t0, s, crf); |
598 | ea363694 | aurel32 | tcg_temp_free(t0); |
599 | e1571908 | aurel32 | } |
600 | e1571908 | aurel32 | #endif
|
601 | e1571908 | aurel32 | |
602 | e1571908 | aurel32 | static always_inline void gen_set_Rc0 (DisasContext *ctx, TCGv reg) |
603 | e1571908 | aurel32 | { |
604 | e1571908 | aurel32 | #if defined(TARGET_PPC64)
|
605 | e1571908 | aurel32 | if (!(ctx->sf_mode))
|
606 | e1571908 | aurel32 | gen_op_cmpi32(reg, 0, 1, 0); |
607 | e1571908 | aurel32 | else
|
608 | e1571908 | aurel32 | #endif
|
609 | e1571908 | aurel32 | gen_op_cmpi(reg, 0, 1, 0); |
610 | e1571908 | aurel32 | } |
611 | e1571908 | aurel32 | |
612 | e1571908 | aurel32 | /* cmp */
|
613 | 99e300ef | Blue Swirl | static void gen_cmp(DisasContext *ctx) |
614 | e1571908 | aurel32 | { |
615 | e1571908 | aurel32 | #if defined(TARGET_PPC64)
|
616 | e1571908 | aurel32 | if (!(ctx->sf_mode && (ctx->opcode & 0x00200000))) |
617 | e1571908 | aurel32 | gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
618 | e1571908 | aurel32 | 1, crfD(ctx->opcode));
|
619 | e1571908 | aurel32 | else
|
620 | e1571908 | aurel32 | #endif
|
621 | e1571908 | aurel32 | gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
622 | e1571908 | aurel32 | 1, crfD(ctx->opcode));
|
623 | e1571908 | aurel32 | } |
624 | e1571908 | aurel32 | |
625 | e1571908 | aurel32 | /* cmpi */
|
626 | 99e300ef | Blue Swirl | static void gen_cmpi(DisasContext *ctx) |
627 | e1571908 | aurel32 | { |
628 | e1571908 | aurel32 | #if defined(TARGET_PPC64)
|
629 | e1571908 | aurel32 | if (!(ctx->sf_mode && (ctx->opcode & 0x00200000))) |
630 | e1571908 | aurel32 | gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), |
631 | e1571908 | aurel32 | 1, crfD(ctx->opcode));
|
632 | e1571908 | aurel32 | else
|
633 | e1571908 | aurel32 | #endif
|
634 | e1571908 | aurel32 | gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), |
635 | e1571908 | aurel32 | 1, crfD(ctx->opcode));
|
636 | e1571908 | aurel32 | } |
637 | e1571908 | aurel32 | |
638 | e1571908 | aurel32 | /* cmpl */
|
639 | 99e300ef | Blue Swirl | static void gen_cmpl(DisasContext *ctx) |
640 | e1571908 | aurel32 | { |
641 | e1571908 | aurel32 | #if defined(TARGET_PPC64)
|
642 | e1571908 | aurel32 | if (!(ctx->sf_mode && (ctx->opcode & 0x00200000))) |
643 | e1571908 | aurel32 | gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
644 | e1571908 | aurel32 | 0, crfD(ctx->opcode));
|
645 | e1571908 | aurel32 | else
|
646 | e1571908 | aurel32 | #endif
|
647 | e1571908 | aurel32 | gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
648 | e1571908 | aurel32 | 0, crfD(ctx->opcode));
|
649 | e1571908 | aurel32 | } |
650 | e1571908 | aurel32 | |
651 | e1571908 | aurel32 | /* cmpli */
|
652 | 99e300ef | Blue Swirl | static void gen_cmpli(DisasContext *ctx) |
653 | e1571908 | aurel32 | { |
654 | e1571908 | aurel32 | #if defined(TARGET_PPC64)
|
655 | e1571908 | aurel32 | if (!(ctx->sf_mode && (ctx->opcode & 0x00200000))) |
656 | e1571908 | aurel32 | gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), |
657 | e1571908 | aurel32 | 0, crfD(ctx->opcode));
|
658 | e1571908 | aurel32 | else
|
659 | e1571908 | aurel32 | #endif
|
660 | e1571908 | aurel32 | gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), |
661 | e1571908 | aurel32 | 0, crfD(ctx->opcode));
|
662 | e1571908 | aurel32 | } |
663 | e1571908 | aurel32 | |
664 | e1571908 | aurel32 | /* isel (PowerPC 2.03 specification) */
|
665 | 99e300ef | Blue Swirl | static void gen_isel(DisasContext *ctx) |
666 | e1571908 | aurel32 | { |
667 | e1571908 | aurel32 | int l1, l2;
|
668 | e1571908 | aurel32 | uint32_t bi = rC(ctx->opcode); |
669 | e1571908 | aurel32 | uint32_t mask; |
670 | a7812ae4 | pbrook | TCGv_i32 t0; |
671 | e1571908 | aurel32 | |
672 | e1571908 | aurel32 | l1 = gen_new_label(); |
673 | e1571908 | aurel32 | l2 = gen_new_label(); |
674 | e1571908 | aurel32 | |
675 | e1571908 | aurel32 | mask = 1 << (3 - (bi & 0x03)); |
676 | a7812ae4 | pbrook | t0 = tcg_temp_new_i32(); |
677 | fea0c503 | aurel32 | tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
|
678 | fea0c503 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
|
679 | e1571908 | aurel32 | if (rA(ctx->opcode) == 0) |
680 | e1571908 | aurel32 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
|
681 | e1571908 | aurel32 | else
|
682 | e1571908 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
683 | e1571908 | aurel32 | tcg_gen_br(l2); |
684 | e1571908 | aurel32 | gen_set_label(l1); |
685 | e1571908 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
686 | e1571908 | aurel32 | gen_set_label(l2); |
687 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); |
688 | e1571908 | aurel32 | } |
689 | e1571908 | aurel32 | |
690 | 79aceca5 | bellard | /*** Integer arithmetic ***/
|
691 | 79aceca5 | bellard | |
692 | 74637406 | aurel32 | static always_inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, TCGv arg1, TCGv arg2, int sub) |
693 | 74637406 | aurel32 | { |
694 | 74637406 | aurel32 | int l1;
|
695 | 74637406 | aurel32 | TCGv t0; |
696 | 79aceca5 | bellard | |
697 | 74637406 | aurel32 | l1 = gen_new_label(); |
698 | 74637406 | aurel32 | /* Start with XER OV disabled, the most likely case */
|
699 | 74637406 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
|
700 | a7812ae4 | pbrook | t0 = tcg_temp_local_new(); |
701 | 74637406 | aurel32 | tcg_gen_xor_tl(t0, arg0, arg1); |
702 | 74637406 | aurel32 | #if defined(TARGET_PPC64)
|
703 | 74637406 | aurel32 | if (!ctx->sf_mode)
|
704 | 74637406 | aurel32 | tcg_gen_ext32s_tl(t0, t0); |
705 | 74637406 | aurel32 | #endif
|
706 | 74637406 | aurel32 | if (sub)
|
707 | 74637406 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
|
708 | 74637406 | aurel32 | else
|
709 | 74637406 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
|
710 | 74637406 | aurel32 | tcg_gen_xor_tl(t0, arg1, arg2); |
711 | 74637406 | aurel32 | #if defined(TARGET_PPC64)
|
712 | 74637406 | aurel32 | if (!ctx->sf_mode)
|
713 | 74637406 | aurel32 | tcg_gen_ext32s_tl(t0, t0); |
714 | 74637406 | aurel32 | #endif
|
715 | 74637406 | aurel32 | if (sub)
|
716 | 74637406 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
|
717 | 74637406 | aurel32 | else
|
718 | 74637406 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
|
719 | 74637406 | aurel32 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); |
720 | 74637406 | aurel32 | gen_set_label(l1); |
721 | 74637406 | aurel32 | tcg_temp_free(t0); |
722 | 79aceca5 | bellard | } |
723 | 79aceca5 | bellard | |
724 | 74637406 | aurel32 | static always_inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1, TCGv arg2, int sub) |
725 | 74637406 | aurel32 | { |
726 | 74637406 | aurel32 | int l1 = gen_new_label();
|
727 | d9bce9d9 | j_mayer | |
728 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
729 | 74637406 | aurel32 | if (!(ctx->sf_mode)) {
|
730 | 74637406 | aurel32 | TCGv t0, t1; |
731 | a7812ae4 | pbrook | t0 = tcg_temp_new(); |
732 | a7812ae4 | pbrook | t1 = tcg_temp_new(); |
733 | d9bce9d9 | j_mayer | |
734 | 74637406 | aurel32 | tcg_gen_ext32u_tl(t0, arg1); |
735 | 74637406 | aurel32 | tcg_gen_ext32u_tl(t1, arg2); |
736 | 74637406 | aurel32 | if (sub) {
|
737 | 74637406 | aurel32 | tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1); |
738 | bdc4e053 | aurel32 | } else {
|
739 | 74637406 | aurel32 | tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); |
740 | 74637406 | aurel32 | } |
741 | a9730017 | aurel32 | tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
|
742 | a9730017 | aurel32 | gen_set_label(l1); |
743 | a9730017 | aurel32 | tcg_temp_free(t0); |
744 | a9730017 | aurel32 | tcg_temp_free(t1); |
745 | 74637406 | aurel32 | } else
|
746 | 74637406 | aurel32 | #endif
|
747 | a9730017 | aurel32 | { |
748 | a9730017 | aurel32 | if (sub) {
|
749 | a9730017 | aurel32 | tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1); |
750 | a9730017 | aurel32 | } else {
|
751 | a9730017 | aurel32 | tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1); |
752 | a9730017 | aurel32 | } |
753 | a9730017 | aurel32 | tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
|
754 | a9730017 | aurel32 | gen_set_label(l1); |
755 | 74637406 | aurel32 | } |
756 | d9bce9d9 | j_mayer | } |
757 | d9bce9d9 | j_mayer | |
758 | 74637406 | aurel32 | /* Common add function */
|
759 | 74637406 | aurel32 | static always_inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2, |
760 | 74637406 | aurel32 | int add_ca, int compute_ca, int compute_ov) |
761 | 74637406 | aurel32 | { |
762 | 74637406 | aurel32 | TCGv t0, t1; |
763 | d9bce9d9 | j_mayer | |
764 | 74637406 | aurel32 | if ((!compute_ca && !compute_ov) ||
|
765 | a7812ae4 | pbrook | (!TCGV_EQUAL(ret,arg1) && !TCGV_EQUAL(ret, arg2))) { |
766 | 74637406 | aurel32 | t0 = ret; |
767 | 74637406 | aurel32 | } else {
|
768 | a7812ae4 | pbrook | t0 = tcg_temp_local_new(); |
769 | 74637406 | aurel32 | } |
770 | 79aceca5 | bellard | |
771 | 74637406 | aurel32 | if (add_ca) {
|
772 | a7812ae4 | pbrook | t1 = tcg_temp_local_new(); |
773 | 74637406 | aurel32 | tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
|
774 | 74637406 | aurel32 | tcg_gen_shri_tl(t1, t1, XER_CA); |
775 | d2e9fd8f | malc | } else {
|
776 | d2e9fd8f | malc | TCGV_UNUSED(t1); |
777 | 74637406 | aurel32 | } |
778 | 79aceca5 | bellard | |
779 | 74637406 | aurel32 | if (compute_ca && compute_ov) {
|
780 | 74637406 | aurel32 | /* Start with XER CA and OV disabled, the most likely case */
|
781 | 74637406 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV))); |
782 | 74637406 | aurel32 | } else if (compute_ca) { |
783 | 74637406 | aurel32 | /* Start with XER CA disabled, the most likely case */
|
784 | 74637406 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
|
785 | 74637406 | aurel32 | } else if (compute_ov) { |
786 | 74637406 | aurel32 | /* Start with XER OV disabled, the most likely case */
|
787 | 74637406 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
|
788 | 74637406 | aurel32 | } |
789 | 79aceca5 | bellard | |
790 | 74637406 | aurel32 | tcg_gen_add_tl(t0, arg1, arg2); |
791 | 74637406 | aurel32 | |
792 | 74637406 | aurel32 | if (compute_ca) {
|
793 | 74637406 | aurel32 | gen_op_arith_compute_ca(ctx, t0, arg1, 0);
|
794 | 74637406 | aurel32 | } |
795 | 74637406 | aurel32 | if (add_ca) {
|
796 | 74637406 | aurel32 | tcg_gen_add_tl(t0, t0, t1); |
797 | 74637406 | aurel32 | gen_op_arith_compute_ca(ctx, t0, t1, 0);
|
798 | 74637406 | aurel32 | tcg_temp_free(t1); |
799 | 74637406 | aurel32 | } |
800 | 74637406 | aurel32 | if (compute_ov) {
|
801 | 74637406 | aurel32 | gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
|
802 | 74637406 | aurel32 | } |
803 | 74637406 | aurel32 | |
804 | 74637406 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
805 | 74637406 | aurel32 | gen_set_Rc0(ctx, t0); |
806 | 74637406 | aurel32 | |
807 | a7812ae4 | pbrook | if (!TCGV_EQUAL(t0, ret)) {
|
808 | 74637406 | aurel32 | tcg_gen_mov_tl(ret, t0); |
809 | 74637406 | aurel32 | tcg_temp_free(t0); |
810 | 74637406 | aurel32 | } |
811 | 39dd32ee | aurel32 | } |
812 | 74637406 | aurel32 | /* Add functions with two operands */
|
813 | 74637406 | aurel32 | #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
|
814 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
815 | 74637406 | aurel32 | { \ |
816 | 74637406 | aurel32 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ |
817 | 74637406 | aurel32 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ |
818 | 74637406 | aurel32 | add_ca, compute_ca, compute_ov); \ |
819 | 74637406 | aurel32 | } |
820 | 74637406 | aurel32 | /* Add functions with one operand and one immediate */
|
821 | 74637406 | aurel32 | #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
|
822 | 74637406 | aurel32 | add_ca, compute_ca, compute_ov) \ |
823 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
824 | 74637406 | aurel32 | { \ |
825 | 74637406 | aurel32 | TCGv t0 = tcg_const_local_tl(const_val); \ |
826 | 74637406 | aurel32 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ |
827 | 74637406 | aurel32 | cpu_gpr[rA(ctx->opcode)], t0, \ |
828 | 74637406 | aurel32 | add_ca, compute_ca, compute_ov); \ |
829 | 74637406 | aurel32 | tcg_temp_free(t0); \ |
830 | 74637406 | aurel32 | } |
831 | 74637406 | aurel32 | |
832 | 74637406 | aurel32 | /* add add. addo addo. */
|
833 | 74637406 | aurel32 | GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) |
834 | 74637406 | aurel32 | GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) |
835 | 74637406 | aurel32 | /* addc addc. addco addco. */
|
836 | 74637406 | aurel32 | GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) |
837 | 74637406 | aurel32 | GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) |
838 | 74637406 | aurel32 | /* adde adde. addeo addeo. */
|
839 | 74637406 | aurel32 | GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) |
840 | 74637406 | aurel32 | GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) |
841 | 74637406 | aurel32 | /* addme addme. addmeo addmeo. */
|
842 | 74637406 | aurel32 | GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) |
843 | 74637406 | aurel32 | GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) |
844 | 74637406 | aurel32 | /* addze addze. addzeo addzeo.*/
|
845 | 74637406 | aurel32 | GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) |
846 | 74637406 | aurel32 | GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) |
847 | 74637406 | aurel32 | /* addi */
|
848 | 99e300ef | Blue Swirl | static void gen_addi(DisasContext *ctx) |
849 | d9bce9d9 | j_mayer | { |
850 | 74637406 | aurel32 | target_long simm = SIMM(ctx->opcode); |
851 | 74637406 | aurel32 | |
852 | 74637406 | aurel32 | if (rA(ctx->opcode) == 0) { |
853 | 74637406 | aurel32 | /* li case */
|
854 | 74637406 | aurel32 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm); |
855 | 74637406 | aurel32 | } else {
|
856 | 74637406 | aurel32 | tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm); |
857 | 74637406 | aurel32 | } |
858 | d9bce9d9 | j_mayer | } |
859 | 74637406 | aurel32 | /* addic addic.*/
|
860 | 74637406 | aurel32 | static always_inline void gen_op_addic (DisasContext *ctx, TCGv ret, TCGv arg1, |
861 | 74637406 | aurel32 | int compute_Rc0)
|
862 | d9bce9d9 | j_mayer | { |
863 | 74637406 | aurel32 | target_long simm = SIMM(ctx->opcode); |
864 | 74637406 | aurel32 | |
865 | 74637406 | aurel32 | /* Start with XER CA and OV disabled, the most likely case */
|
866 | 74637406 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
|
867 | 74637406 | aurel32 | |
868 | 74637406 | aurel32 | if (likely(simm != 0)) { |
869 | a7812ae4 | pbrook | TCGv t0 = tcg_temp_local_new(); |
870 | 74637406 | aurel32 | tcg_gen_addi_tl(t0, arg1, simm); |
871 | 74637406 | aurel32 | gen_op_arith_compute_ca(ctx, t0, arg1, 0);
|
872 | 74637406 | aurel32 | tcg_gen_mov_tl(ret, t0); |
873 | 74637406 | aurel32 | tcg_temp_free(t0); |
874 | 74637406 | aurel32 | } else {
|
875 | 74637406 | aurel32 | tcg_gen_mov_tl(ret, arg1); |
876 | 74637406 | aurel32 | } |
877 | 74637406 | aurel32 | if (compute_Rc0) {
|
878 | 74637406 | aurel32 | gen_set_Rc0(ctx, ret); |
879 | 74637406 | aurel32 | } |
880 | d9bce9d9 | j_mayer | } |
881 | 99e300ef | Blue Swirl | |
882 | 99e300ef | Blue Swirl | static void gen_addic(DisasContext *ctx) |
883 | d9bce9d9 | j_mayer | { |
884 | 74637406 | aurel32 | gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
|
885 | d9bce9d9 | j_mayer | } |
886 | e8eaa2c0 | Blue Swirl | |
887 | e8eaa2c0 | Blue Swirl | static void gen_addic_(DisasContext *ctx) |
888 | d9bce9d9 | j_mayer | { |
889 | 74637406 | aurel32 | gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
|
890 | d9bce9d9 | j_mayer | } |
891 | 99e300ef | Blue Swirl | |
892 | 54623277 | Blue Swirl | /* addis */
|
893 | 99e300ef | Blue Swirl | static void gen_addis(DisasContext *ctx) |
894 | d9bce9d9 | j_mayer | { |
895 | 74637406 | aurel32 | target_long simm = SIMM(ctx->opcode); |
896 | 74637406 | aurel32 | |
897 | 74637406 | aurel32 | if (rA(ctx->opcode) == 0) { |
898 | 74637406 | aurel32 | /* lis case */
|
899 | 74637406 | aurel32 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
|
900 | 74637406 | aurel32 | } else {
|
901 | 74637406 | aurel32 | tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16);
|
902 | 74637406 | aurel32 | } |
903 | d9bce9d9 | j_mayer | } |
904 | 74637406 | aurel32 | |
905 | 74637406 | aurel32 | static always_inline void gen_op_arith_divw (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2, |
906 | 74637406 | aurel32 | int sign, int compute_ov) |
907 | d9bce9d9 | j_mayer | { |
908 | 2ef1b120 | aurel32 | int l1 = gen_new_label();
|
909 | 2ef1b120 | aurel32 | int l2 = gen_new_label();
|
910 | a7812ae4 | pbrook | TCGv_i32 t0 = tcg_temp_local_new_i32(); |
911 | a7812ae4 | pbrook | TCGv_i32 t1 = tcg_temp_local_new_i32(); |
912 | 74637406 | aurel32 | |
913 | 2ef1b120 | aurel32 | tcg_gen_trunc_tl_i32(t0, arg1); |
914 | 2ef1b120 | aurel32 | tcg_gen_trunc_tl_i32(t1, arg2); |
915 | 2ef1b120 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
|
916 | 74637406 | aurel32 | if (sign) {
|
917 | 2ef1b120 | aurel32 | int l3 = gen_new_label();
|
918 | 2ef1b120 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
|
919 | 2ef1b120 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1); |
920 | 74637406 | aurel32 | gen_set_label(l3); |
921 | 2ef1b120 | aurel32 | tcg_gen_div_i32(t0, t0, t1); |
922 | 74637406 | aurel32 | } else {
|
923 | 2ef1b120 | aurel32 | tcg_gen_divu_i32(t0, t0, t1); |
924 | 74637406 | aurel32 | } |
925 | 74637406 | aurel32 | if (compute_ov) {
|
926 | 74637406 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
|
927 | 74637406 | aurel32 | } |
928 | 74637406 | aurel32 | tcg_gen_br(l2); |
929 | 74637406 | aurel32 | gen_set_label(l1); |
930 | 74637406 | aurel32 | if (sign) {
|
931 | 2ef1b120 | aurel32 | tcg_gen_sari_i32(t0, t0, 31);
|
932 | 74637406 | aurel32 | } else {
|
933 | 74637406 | aurel32 | tcg_gen_movi_i32(t0, 0);
|
934 | 74637406 | aurel32 | } |
935 | 74637406 | aurel32 | if (compute_ov) {
|
936 | 74637406 | aurel32 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); |
937 | 74637406 | aurel32 | } |
938 | 74637406 | aurel32 | gen_set_label(l2); |
939 | 2ef1b120 | aurel32 | tcg_gen_extu_i32_tl(ret, t0); |
940 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); |
941 | a7812ae4 | pbrook | tcg_temp_free_i32(t1); |
942 | 74637406 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
943 | 74637406 | aurel32 | gen_set_Rc0(ctx, ret); |
944 | d9bce9d9 | j_mayer | } |
945 | 74637406 | aurel32 | /* Div functions */
|
946 | 74637406 | aurel32 | #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
|
947 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
948 | 74637406 | aurel32 | { \ |
949 | 74637406 | aurel32 | gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ |
950 | 74637406 | aurel32 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ |
951 | 74637406 | aurel32 | sign, compute_ov); \ |
952 | 74637406 | aurel32 | } |
953 | 74637406 | aurel32 | /* divwu divwu. divwuo divwuo. */
|
954 | 74637406 | aurel32 | GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); |
955 | 74637406 | aurel32 | GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); |
956 | 74637406 | aurel32 | /* divw divw. divwo divwo. */
|
957 | 74637406 | aurel32 | GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); |
958 | 74637406 | aurel32 | GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); |
959 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
960 | 2ef1b120 | aurel32 | static always_inline void gen_op_arith_divd (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2, |
961 | 2ef1b120 | aurel32 | int sign, int compute_ov) |
962 | d9bce9d9 | j_mayer | { |
963 | 2ef1b120 | aurel32 | int l1 = gen_new_label();
|
964 | 2ef1b120 | aurel32 | int l2 = gen_new_label();
|
965 | 74637406 | aurel32 | |
966 | 74637406 | aurel32 | tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
|
967 | 74637406 | aurel32 | if (sign) {
|
968 | 2ef1b120 | aurel32 | int l3 = gen_new_label();
|
969 | 74637406 | aurel32 | tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
|
970 | 74637406 | aurel32 | tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1); |
971 | 74637406 | aurel32 | gen_set_label(l3); |
972 | 74637406 | aurel32 | tcg_gen_div_i64(ret, arg1, arg2); |
973 | 74637406 | aurel32 | } else {
|
974 | 74637406 | aurel32 | tcg_gen_divu_i64(ret, arg1, arg2); |
975 | 74637406 | aurel32 | } |
976 | 74637406 | aurel32 | if (compute_ov) {
|
977 | 74637406 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
|
978 | 74637406 | aurel32 | } |
979 | 74637406 | aurel32 | tcg_gen_br(l2); |
980 | 74637406 | aurel32 | gen_set_label(l1); |
981 | 74637406 | aurel32 | if (sign) {
|
982 | 74637406 | aurel32 | tcg_gen_sari_i64(ret, arg1, 63);
|
983 | 74637406 | aurel32 | } else {
|
984 | 74637406 | aurel32 | tcg_gen_movi_i64(ret, 0);
|
985 | 74637406 | aurel32 | } |
986 | 74637406 | aurel32 | if (compute_ov) {
|
987 | 74637406 | aurel32 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); |
988 | 74637406 | aurel32 | } |
989 | 74637406 | aurel32 | gen_set_label(l2); |
990 | 74637406 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
991 | 74637406 | aurel32 | gen_set_Rc0(ctx, ret); |
992 | d9bce9d9 | j_mayer | } |
993 | 74637406 | aurel32 | #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
|
994 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
995 | 74637406 | aurel32 | { \ |
996 | 2ef1b120 | aurel32 | gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ |
997 | 2ef1b120 | aurel32 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ |
998 | 2ef1b120 | aurel32 | sign, compute_ov); \ |
999 | 74637406 | aurel32 | } |
1000 | 74637406 | aurel32 | /* divwu divwu. divwuo divwuo. */
|
1001 | 74637406 | aurel32 | GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); |
1002 | 74637406 | aurel32 | GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); |
1003 | 74637406 | aurel32 | /* divw divw. divwo divwo. */
|
1004 | 74637406 | aurel32 | GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); |
1005 | 74637406 | aurel32 | GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); |
1006 | d9bce9d9 | j_mayer | #endif
|
1007 | 74637406 | aurel32 | |
1008 | 74637406 | aurel32 | /* mulhw mulhw. */
|
1009 | 99e300ef | Blue Swirl | static void gen_mulhw(DisasContext *ctx) |
1010 | d9bce9d9 | j_mayer | { |
1011 | a7812ae4 | pbrook | TCGv_i64 t0, t1; |
1012 | 74637406 | aurel32 | |
1013 | a7812ae4 | pbrook | t0 = tcg_temp_new_i64(); |
1014 | a7812ae4 | pbrook | t1 = tcg_temp_new_i64(); |
1015 | 74637406 | aurel32 | #if defined(TARGET_PPC64)
|
1016 | 74637406 | aurel32 | tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); |
1017 | 74637406 | aurel32 | tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); |
1018 | 74637406 | aurel32 | tcg_gen_mul_i64(t0, t0, t1); |
1019 | 74637406 | aurel32 | tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
|
1020 | 74637406 | aurel32 | #else
|
1021 | 74637406 | aurel32 | tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
1022 | 74637406 | aurel32 | tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); |
1023 | 74637406 | aurel32 | tcg_gen_mul_i64(t0, t0, t1); |
1024 | 74637406 | aurel32 | tcg_gen_shri_i64(t0, t0, 32);
|
1025 | 74637406 | aurel32 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0); |
1026 | 74637406 | aurel32 | #endif
|
1027 | a7812ae4 | pbrook | tcg_temp_free_i64(t0); |
1028 | a7812ae4 | pbrook | tcg_temp_free_i64(t1); |
1029 | 74637406 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1030 | 74637406 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
1031 | d9bce9d9 | j_mayer | } |
1032 | 99e300ef | Blue Swirl | |
1033 | 54623277 | Blue Swirl | /* mulhwu mulhwu. */
|
1034 | 99e300ef | Blue Swirl | static void gen_mulhwu(DisasContext *ctx) |
1035 | d9bce9d9 | j_mayer | { |
1036 | a7812ae4 | pbrook | TCGv_i64 t0, t1; |
1037 | 74637406 | aurel32 | |
1038 | a7812ae4 | pbrook | t0 = tcg_temp_new_i64(); |
1039 | a7812ae4 | pbrook | t1 = tcg_temp_new_i64(); |
1040 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
1041 | 74637406 | aurel32 | tcg_gen_ext32u_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
1042 | 74637406 | aurel32 | tcg_gen_ext32u_i64(t1, cpu_gpr[rB(ctx->opcode)]); |
1043 | 74637406 | aurel32 | tcg_gen_mul_i64(t0, t0, t1); |
1044 | 74637406 | aurel32 | tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
|
1045 | 74637406 | aurel32 | #else
|
1046 | 74637406 | aurel32 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
1047 | 74637406 | aurel32 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); |
1048 | 74637406 | aurel32 | tcg_gen_mul_i64(t0, t0, t1); |
1049 | 74637406 | aurel32 | tcg_gen_shri_i64(t0, t0, 32);
|
1050 | 74637406 | aurel32 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0); |
1051 | 74637406 | aurel32 | #endif
|
1052 | a7812ae4 | pbrook | tcg_temp_free_i64(t0); |
1053 | a7812ae4 | pbrook | tcg_temp_free_i64(t1); |
1054 | 74637406 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1055 | 74637406 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
1056 | d9bce9d9 | j_mayer | } |
1057 | 99e300ef | Blue Swirl | |
1058 | 54623277 | Blue Swirl | /* mullw mullw. */
|
1059 | 99e300ef | Blue Swirl | static void gen_mullw(DisasContext *ctx) |
1060 | d9bce9d9 | j_mayer | { |
1061 | 74637406 | aurel32 | tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1062 | 74637406 | aurel32 | cpu_gpr[rB(ctx->opcode)]); |
1063 | 1e4c090f | aurel32 | tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]); |
1064 | 74637406 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1065 | 74637406 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
1066 | d9bce9d9 | j_mayer | } |
1067 | 99e300ef | Blue Swirl | |
1068 | 54623277 | Blue Swirl | /* mullwo mullwo. */
|
1069 | 99e300ef | Blue Swirl | static void gen_mullwo(DisasContext *ctx) |
1070 | d9bce9d9 | j_mayer | { |
1071 | 74637406 | aurel32 | int l1;
|
1072 | a7812ae4 | pbrook | TCGv_i64 t0, t1; |
1073 | 74637406 | aurel32 | |
1074 | a7812ae4 | pbrook | t0 = tcg_temp_new_i64(); |
1075 | a7812ae4 | pbrook | t1 = tcg_temp_new_i64(); |
1076 | 74637406 | aurel32 | l1 = gen_new_label(); |
1077 | 74637406 | aurel32 | /* Start with XER OV disabled, the most likely case */
|
1078 | 74637406 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
|
1079 | 74637406 | aurel32 | #if defined(TARGET_PPC64)
|
1080 | 74637406 | aurel32 | tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
1081 | 74637406 | aurel32 | tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]); |
1082 | 74637406 | aurel32 | #else
|
1083 | 74637406 | aurel32 | tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
1084 | 74637406 | aurel32 | tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); |
1085 | d9bce9d9 | j_mayer | #endif
|
1086 | 74637406 | aurel32 | tcg_gen_mul_i64(t0, t0, t1); |
1087 | 74637406 | aurel32 | #if defined(TARGET_PPC64)
|
1088 | 74637406 | aurel32 | tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0); |
1089 | 74637406 | aurel32 | tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1); |
1090 | 74637406 | aurel32 | #else
|
1091 | 74637406 | aurel32 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0); |
1092 | 74637406 | aurel32 | tcg_gen_ext32s_i64(t1, t0); |
1093 | 74637406 | aurel32 | tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); |
1094 | 74637406 | aurel32 | #endif
|
1095 | 74637406 | aurel32 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); |
1096 | 74637406 | aurel32 | gen_set_label(l1); |
1097 | a7812ae4 | pbrook | tcg_temp_free_i64(t0); |
1098 | a7812ae4 | pbrook | tcg_temp_free_i64(t1); |
1099 | 74637406 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1100 | 74637406 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
1101 | d9bce9d9 | j_mayer | } |
1102 | 99e300ef | Blue Swirl | |
1103 | 54623277 | Blue Swirl | /* mulli */
|
1104 | 99e300ef | Blue Swirl | static void gen_mulli(DisasContext *ctx) |
1105 | d9bce9d9 | j_mayer | { |
1106 | 74637406 | aurel32 | tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1107 | 74637406 | aurel32 | SIMM(ctx->opcode)); |
1108 | d9bce9d9 | j_mayer | } |
1109 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
1110 | 74637406 | aurel32 | #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
|
1111 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
1112 | 74637406 | aurel32 | { \ |
1113 | a7812ae4 | pbrook | gen_helper_##name (cpu_gpr[rD(ctx->opcode)], \ |
1114 | 74637406 | aurel32 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ |
1115 | 74637406 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) \ |
1116 | 74637406 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ |
1117 | d9bce9d9 | j_mayer | } |
1118 | 74637406 | aurel32 | /* mulhd mulhd. */
|
1119 | 74637406 | aurel32 | GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00);
|
1120 | 74637406 | aurel32 | /* mulhdu mulhdu. */
|
1121 | 74637406 | aurel32 | GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02);
|
1122 | 99e300ef | Blue Swirl | |
1123 | 54623277 | Blue Swirl | /* mulld mulld. */
|
1124 | 99e300ef | Blue Swirl | static void gen_mulld(DisasContext *ctx) |
1125 | d9bce9d9 | j_mayer | { |
1126 | 74637406 | aurel32 | tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1127 | 74637406 | aurel32 | cpu_gpr[rB(ctx->opcode)]); |
1128 | 74637406 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1129 | 74637406 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
1130 | d9bce9d9 | j_mayer | } |
1131 | 74637406 | aurel32 | /* mulldo mulldo. */
|
1132 | 74637406 | aurel32 | GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17);
|
1133 | d9bce9d9 | j_mayer | #endif
|
1134 | 74637406 | aurel32 | |
1135 | 74637406 | aurel32 | /* neg neg. nego nego. */
|
1136 | ec6469a3 | aurel32 | static always_inline void gen_op_arith_neg (DisasContext *ctx, TCGv ret, TCGv arg1, int ov_check) |
1137 | d9bce9d9 | j_mayer | { |
1138 | ec6469a3 | aurel32 | int l1 = gen_new_label();
|
1139 | ec6469a3 | aurel32 | int l2 = gen_new_label();
|
1140 | a7812ae4 | pbrook | TCGv t0 = tcg_temp_local_new(); |
1141 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
1142 | 74637406 | aurel32 | if (ctx->sf_mode) {
|
1143 | 741a7444 | aurel32 | tcg_gen_mov_tl(t0, arg1); |
1144 | ec6469a3 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1); |
1145 | ec6469a3 | aurel32 | } else
|
1146 | ec6469a3 | aurel32 | #endif
|
1147 | ec6469a3 | aurel32 | { |
1148 | ec6469a3 | aurel32 | tcg_gen_ext32s_tl(t0, arg1); |
1149 | 74637406 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1); |
1150 | 74637406 | aurel32 | } |
1151 | 74637406 | aurel32 | tcg_gen_neg_tl(ret, arg1); |
1152 | 74637406 | aurel32 | if (ov_check) {
|
1153 | 74637406 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
|
1154 | 74637406 | aurel32 | } |
1155 | 74637406 | aurel32 | tcg_gen_br(l2); |
1156 | 74637406 | aurel32 | gen_set_label(l1); |
1157 | ec6469a3 | aurel32 | tcg_gen_mov_tl(ret, t0); |
1158 | 74637406 | aurel32 | if (ov_check) {
|
1159 | 74637406 | aurel32 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); |
1160 | 74637406 | aurel32 | } |
1161 | 74637406 | aurel32 | gen_set_label(l2); |
1162 | ec6469a3 | aurel32 | tcg_temp_free(t0); |
1163 | 74637406 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1164 | 74637406 | aurel32 | gen_set_Rc0(ctx, ret); |
1165 | 74637406 | aurel32 | } |
1166 | 99e300ef | Blue Swirl | |
1167 | 99e300ef | Blue Swirl | static void gen_neg(DisasContext *ctx) |
1168 | d9bce9d9 | j_mayer | { |
1169 | ec6469a3 | aurel32 | gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
|
1170 | d9bce9d9 | j_mayer | } |
1171 | 99e300ef | Blue Swirl | |
1172 | 99e300ef | Blue Swirl | static void gen_nego(DisasContext *ctx) |
1173 | 79aceca5 | bellard | { |
1174 | ec6469a3 | aurel32 | gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
|
1175 | 79aceca5 | bellard | } |
1176 | 74637406 | aurel32 | |
1177 | 74637406 | aurel32 | /* Common subf function */
|
1178 | 74637406 | aurel32 | static always_inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2, |
1179 | 74637406 | aurel32 | int add_ca, int compute_ca, int compute_ov) |
1180 | 79aceca5 | bellard | { |
1181 | 74637406 | aurel32 | TCGv t0, t1; |
1182 | 76a66253 | j_mayer | |
1183 | 74637406 | aurel32 | if ((!compute_ca && !compute_ov) ||
|
1184 | a7812ae4 | pbrook | (!TCGV_EQUAL(ret, arg1) && !TCGV_EQUAL(ret, arg2))) { |
1185 | 74637406 | aurel32 | t0 = ret; |
1186 | e864cabd | j_mayer | } else {
|
1187 | a7812ae4 | pbrook | t0 = tcg_temp_local_new(); |
1188 | d9bce9d9 | j_mayer | } |
1189 | 76a66253 | j_mayer | |
1190 | 74637406 | aurel32 | if (add_ca) {
|
1191 | a7812ae4 | pbrook | t1 = tcg_temp_local_new(); |
1192 | 74637406 | aurel32 | tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
|
1193 | 74637406 | aurel32 | tcg_gen_shri_tl(t1, t1, XER_CA); |
1194 | d2e9fd8f | malc | } else {
|
1195 | d2e9fd8f | malc | TCGV_UNUSED(t1); |
1196 | d9bce9d9 | j_mayer | } |
1197 | 79aceca5 | bellard | |
1198 | 74637406 | aurel32 | if (compute_ca && compute_ov) {
|
1199 | 74637406 | aurel32 | /* Start with XER CA and OV disabled, the most likely case */
|
1200 | 74637406 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV))); |
1201 | 74637406 | aurel32 | } else if (compute_ca) { |
1202 | 74637406 | aurel32 | /* Start with XER CA disabled, the most likely case */
|
1203 | 74637406 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
|
1204 | 74637406 | aurel32 | } else if (compute_ov) { |
1205 | 74637406 | aurel32 | /* Start with XER OV disabled, the most likely case */
|
1206 | 74637406 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
|
1207 | 74637406 | aurel32 | } |
1208 | 74637406 | aurel32 | |
1209 | 74637406 | aurel32 | if (add_ca) {
|
1210 | 74637406 | aurel32 | tcg_gen_not_tl(t0, arg1); |
1211 | 74637406 | aurel32 | tcg_gen_add_tl(t0, t0, arg2); |
1212 | 74637406 | aurel32 | gen_op_arith_compute_ca(ctx, t0, arg2, 0);
|
1213 | 74637406 | aurel32 | tcg_gen_add_tl(t0, t0, t1); |
1214 | 74637406 | aurel32 | gen_op_arith_compute_ca(ctx, t0, t1, 0);
|
1215 | 74637406 | aurel32 | tcg_temp_free(t1); |
1216 | 79aceca5 | bellard | } else {
|
1217 | 74637406 | aurel32 | tcg_gen_sub_tl(t0, arg2, arg1); |
1218 | 74637406 | aurel32 | if (compute_ca) {
|
1219 | 74637406 | aurel32 | gen_op_arith_compute_ca(ctx, t0, arg2, 1);
|
1220 | 74637406 | aurel32 | } |
1221 | 74637406 | aurel32 | } |
1222 | 74637406 | aurel32 | if (compute_ov) {
|
1223 | 74637406 | aurel32 | gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
|
1224 | 74637406 | aurel32 | } |
1225 | 74637406 | aurel32 | |
1226 | 74637406 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1227 | 74637406 | aurel32 | gen_set_Rc0(ctx, t0); |
1228 | 74637406 | aurel32 | |
1229 | a7812ae4 | pbrook | if (!TCGV_EQUAL(t0, ret)) {
|
1230 | 74637406 | aurel32 | tcg_gen_mov_tl(ret, t0); |
1231 | 74637406 | aurel32 | tcg_temp_free(t0); |
1232 | 79aceca5 | bellard | } |
1233 | 79aceca5 | bellard | } |
1234 | 74637406 | aurel32 | /* Sub functions with Two operands functions */
|
1235 | 74637406 | aurel32 | #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
|
1236 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
1237 | 74637406 | aurel32 | { \ |
1238 | 74637406 | aurel32 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ |
1239 | 74637406 | aurel32 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ |
1240 | 74637406 | aurel32 | add_ca, compute_ca, compute_ov); \ |
1241 | 74637406 | aurel32 | } |
1242 | 74637406 | aurel32 | /* Sub functions with one operand and one immediate */
|
1243 | 74637406 | aurel32 | #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
|
1244 | 74637406 | aurel32 | add_ca, compute_ca, compute_ov) \ |
1245 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
1246 | 74637406 | aurel32 | { \ |
1247 | 74637406 | aurel32 | TCGv t0 = tcg_const_local_tl(const_val); \ |
1248 | 74637406 | aurel32 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ |
1249 | 74637406 | aurel32 | cpu_gpr[rA(ctx->opcode)], t0, \ |
1250 | 74637406 | aurel32 | add_ca, compute_ca, compute_ov); \ |
1251 | 74637406 | aurel32 | tcg_temp_free(t0); \ |
1252 | 74637406 | aurel32 | } |
1253 | 74637406 | aurel32 | /* subf subf. subfo subfo. */
|
1254 | 74637406 | aurel32 | GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) |
1255 | 74637406 | aurel32 | GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) |
1256 | 74637406 | aurel32 | /* subfc subfc. subfco subfco. */
|
1257 | 74637406 | aurel32 | GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) |
1258 | 74637406 | aurel32 | GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) |
1259 | 74637406 | aurel32 | /* subfe subfe. subfeo subfo. */
|
1260 | 74637406 | aurel32 | GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) |
1261 | 74637406 | aurel32 | GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) |
1262 | 74637406 | aurel32 | /* subfme subfme. subfmeo subfmeo. */
|
1263 | 74637406 | aurel32 | GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) |
1264 | 74637406 | aurel32 | GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) |
1265 | 74637406 | aurel32 | /* subfze subfze. subfzeo subfzeo.*/
|
1266 | 74637406 | aurel32 | GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) |
1267 | 74637406 | aurel32 | GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) |
1268 | 99e300ef | Blue Swirl | |
1269 | 54623277 | Blue Swirl | /* subfic */
|
1270 | 99e300ef | Blue Swirl | static void gen_subfic(DisasContext *ctx) |
1271 | 79aceca5 | bellard | { |
1272 | 74637406 | aurel32 | /* Start with XER CA and OV disabled, the most likely case */
|
1273 | 74637406 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
|
1274 | a7812ae4 | pbrook | TCGv t0 = tcg_temp_local_new(); |
1275 | 74637406 | aurel32 | TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode)); |
1276 | 74637406 | aurel32 | tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]); |
1277 | 74637406 | aurel32 | gen_op_arith_compute_ca(ctx, t0, t1, 1);
|
1278 | 74637406 | aurel32 | tcg_temp_free(t1); |
1279 | 74637406 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); |
1280 | 74637406 | aurel32 | tcg_temp_free(t0); |
1281 | 79aceca5 | bellard | } |
1282 | 79aceca5 | bellard | |
1283 | 79aceca5 | bellard | /*** Integer logical ***/
|
1284 | 26d67362 | aurel32 | #define GEN_LOGICAL2(name, tcg_op, opc, type) \
|
1285 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
1286 | 79aceca5 | bellard | { \ |
1287 | 26d67362 | aurel32 | tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ |
1288 | 26d67362 | aurel32 | cpu_gpr[rB(ctx->opcode)]); \ |
1289 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) \ |
1290 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ |
1291 | 79aceca5 | bellard | } |
1292 | 79aceca5 | bellard | |
1293 | 26d67362 | aurel32 | #define GEN_LOGICAL1(name, tcg_op, opc, type) \
|
1294 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
1295 | 79aceca5 | bellard | { \ |
1296 | 26d67362 | aurel32 | tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ |
1297 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) \ |
1298 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ |
1299 | 79aceca5 | bellard | } |
1300 | 79aceca5 | bellard | |
1301 | 79aceca5 | bellard | /* and & and. */
|
1302 | 26d67362 | aurel32 | GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
|
1303 | 79aceca5 | bellard | /* andc & andc. */
|
1304 | 26d67362 | aurel32 | GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
|
1305 | e8eaa2c0 | Blue Swirl | |
1306 | 54623277 | Blue Swirl | /* andi. */
|
1307 | e8eaa2c0 | Blue Swirl | static void gen_andi_(DisasContext *ctx) |
1308 | 79aceca5 | bellard | { |
1309 | 26d67362 | aurel32 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode)); |
1310 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1311 | 79aceca5 | bellard | } |
1312 | e8eaa2c0 | Blue Swirl | |
1313 | 54623277 | Blue Swirl | /* andis. */
|
1314 | e8eaa2c0 | Blue Swirl | static void gen_andis_(DisasContext *ctx) |
1315 | 79aceca5 | bellard | { |
1316 | 26d67362 | aurel32 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
|
1317 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1318 | 79aceca5 | bellard | } |
1319 | 99e300ef | Blue Swirl | |
1320 | 54623277 | Blue Swirl | /* cntlzw */
|
1321 | 99e300ef | Blue Swirl | static void gen_cntlzw(DisasContext *ctx) |
1322 | 26d67362 | aurel32 | { |
1323 | a7812ae4 | pbrook | gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
1324 | 26d67362 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1325 | 2e31f5d3 | pbrook | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1326 | 26d67362 | aurel32 | } |
1327 | 79aceca5 | bellard | /* eqv & eqv. */
|
1328 | 26d67362 | aurel32 | GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
|
1329 | 79aceca5 | bellard | /* extsb & extsb. */
|
1330 | 26d67362 | aurel32 | GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
|
1331 | 79aceca5 | bellard | /* extsh & extsh. */
|
1332 | 26d67362 | aurel32 | GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
|
1333 | 79aceca5 | bellard | /* nand & nand. */
|
1334 | 26d67362 | aurel32 | GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
|
1335 | 79aceca5 | bellard | /* nor & nor. */
|
1336 | 26d67362 | aurel32 | GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
|
1337 | 99e300ef | Blue Swirl | |
1338 | 54623277 | Blue Swirl | /* or & or. */
|
1339 | 99e300ef | Blue Swirl | static void gen_or(DisasContext *ctx) |
1340 | 9a64fbe4 | bellard | { |
1341 | 76a66253 | j_mayer | int rs, ra, rb;
|
1342 | 76a66253 | j_mayer | |
1343 | 76a66253 | j_mayer | rs = rS(ctx->opcode); |
1344 | 76a66253 | j_mayer | ra = rA(ctx->opcode); |
1345 | 76a66253 | j_mayer | rb = rB(ctx->opcode); |
1346 | 76a66253 | j_mayer | /* Optimisation for mr. ri case */
|
1347 | 76a66253 | j_mayer | if (rs != ra || rs != rb) {
|
1348 | 26d67362 | aurel32 | if (rs != rb)
|
1349 | 26d67362 | aurel32 | tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); |
1350 | 26d67362 | aurel32 | else
|
1351 | 26d67362 | aurel32 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); |
1352 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
1353 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[ra]); |
1354 | 76a66253 | j_mayer | } else if (unlikely(Rc(ctx->opcode) != 0)) { |
1355 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rs]); |
1356 | c80f84e3 | j_mayer | #if defined(TARGET_PPC64)
|
1357 | c80f84e3 | j_mayer | } else {
|
1358 | 26d67362 | aurel32 | int prio = 0; |
1359 | 26d67362 | aurel32 | |
1360 | c80f84e3 | j_mayer | switch (rs) {
|
1361 | c80f84e3 | j_mayer | case 1: |
1362 | c80f84e3 | j_mayer | /* Set process priority to low */
|
1363 | 26d67362 | aurel32 | prio = 2;
|
1364 | c80f84e3 | j_mayer | break;
|
1365 | c80f84e3 | j_mayer | case 6: |
1366 | c80f84e3 | j_mayer | /* Set process priority to medium-low */
|
1367 | 26d67362 | aurel32 | prio = 3;
|
1368 | c80f84e3 | j_mayer | break;
|
1369 | c80f84e3 | j_mayer | case 2: |
1370 | c80f84e3 | j_mayer | /* Set process priority to normal */
|
1371 | 26d67362 | aurel32 | prio = 4;
|
1372 | c80f84e3 | j_mayer | break;
|
1373 | be147d08 | j_mayer | #if !defined(CONFIG_USER_ONLY)
|
1374 | be147d08 | j_mayer | case 31: |
1375 | 76db3ba4 | aurel32 | if (ctx->mem_idx > 0) { |
1376 | be147d08 | j_mayer | /* Set process priority to very low */
|
1377 | 26d67362 | aurel32 | prio = 1;
|
1378 | be147d08 | j_mayer | } |
1379 | be147d08 | j_mayer | break;
|
1380 | be147d08 | j_mayer | case 5: |
1381 | 76db3ba4 | aurel32 | if (ctx->mem_idx > 0) { |
1382 | be147d08 | j_mayer | /* Set process priority to medium-hight */
|
1383 | 26d67362 | aurel32 | prio = 5;
|
1384 | be147d08 | j_mayer | } |
1385 | be147d08 | j_mayer | break;
|
1386 | be147d08 | j_mayer | case 3: |
1387 | 76db3ba4 | aurel32 | if (ctx->mem_idx > 0) { |
1388 | be147d08 | j_mayer | /* Set process priority to high */
|
1389 | 26d67362 | aurel32 | prio = 6;
|
1390 | be147d08 | j_mayer | } |
1391 | be147d08 | j_mayer | break;
|
1392 | be147d08 | j_mayer | case 7: |
1393 | 76db3ba4 | aurel32 | if (ctx->mem_idx > 1) { |
1394 | be147d08 | j_mayer | /* Set process priority to very high */
|
1395 | 26d67362 | aurel32 | prio = 7;
|
1396 | be147d08 | j_mayer | } |
1397 | be147d08 | j_mayer | break;
|
1398 | be147d08 | j_mayer | #endif
|
1399 | c80f84e3 | j_mayer | default:
|
1400 | c80f84e3 | j_mayer | /* nop */
|
1401 | c80f84e3 | j_mayer | break;
|
1402 | c80f84e3 | j_mayer | } |
1403 | 26d67362 | aurel32 | if (prio) {
|
1404 | a7812ae4 | pbrook | TCGv t0 = tcg_temp_new(); |
1405 | 54cdcae6 | aurel32 | gen_load_spr(t0, SPR_PPR); |
1406 | ea363694 | aurel32 | tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
|
1407 | ea363694 | aurel32 | tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
|
1408 | 54cdcae6 | aurel32 | gen_store_spr(SPR_PPR, t0); |
1409 | ea363694 | aurel32 | tcg_temp_free(t0); |
1410 | 26d67362 | aurel32 | } |
1411 | c80f84e3 | j_mayer | #endif
|
1412 | 9a64fbe4 | bellard | } |
1413 | 9a64fbe4 | bellard | } |
1414 | 79aceca5 | bellard | /* orc & orc. */
|
1415 | 26d67362 | aurel32 | GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
|
1416 | 99e300ef | Blue Swirl | |
1417 | 54623277 | Blue Swirl | /* xor & xor. */
|
1418 | 99e300ef | Blue Swirl | static void gen_xor(DisasContext *ctx) |
1419 | 9a64fbe4 | bellard | { |
1420 | 9a64fbe4 | bellard | /* Optimisation for "set to zero" case */
|
1421 | 26d67362 | aurel32 | if (rS(ctx->opcode) != rB(ctx->opcode))
|
1422 | 312179c4 | aurel32 | tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
1423 | 26d67362 | aurel32 | else
|
1424 | 26d67362 | aurel32 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
|
1425 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
1426 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1427 | 9a64fbe4 | bellard | } |
1428 | 99e300ef | Blue Swirl | |
1429 | 54623277 | Blue Swirl | /* ori */
|
1430 | 99e300ef | Blue Swirl | static void gen_ori(DisasContext *ctx) |
1431 | 79aceca5 | bellard | { |
1432 | 76a66253 | j_mayer | target_ulong uimm = UIMM(ctx->opcode); |
1433 | 79aceca5 | bellard | |
1434 | 9a64fbe4 | bellard | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
1435 | 9a64fbe4 | bellard | /* NOP */
|
1436 | 76a66253 | j_mayer | /* XXX: should handle special NOPs for POWER series */
|
1437 | 9a64fbe4 | bellard | return;
|
1438 | 76a66253 | j_mayer | } |
1439 | 26d67362 | aurel32 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); |
1440 | 79aceca5 | bellard | } |
1441 | 99e300ef | Blue Swirl | |
1442 | 54623277 | Blue Swirl | /* oris */
|
1443 | 99e300ef | Blue Swirl | static void gen_oris(DisasContext *ctx) |
1444 | 79aceca5 | bellard | { |
1445 | 76a66253 | j_mayer | target_ulong uimm = UIMM(ctx->opcode); |
1446 | 79aceca5 | bellard | |
1447 | 9a64fbe4 | bellard | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
1448 | 9a64fbe4 | bellard | /* NOP */
|
1449 | 9a64fbe4 | bellard | return;
|
1450 | 76a66253 | j_mayer | } |
1451 | 26d67362 | aurel32 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
|
1452 | 79aceca5 | bellard | } |
1453 | 99e300ef | Blue Swirl | |
1454 | 54623277 | Blue Swirl | /* xori */
|
1455 | 99e300ef | Blue Swirl | static void gen_xori(DisasContext *ctx) |
1456 | 79aceca5 | bellard | { |
1457 | 76a66253 | j_mayer | target_ulong uimm = UIMM(ctx->opcode); |
1458 | 9a64fbe4 | bellard | |
1459 | 9a64fbe4 | bellard | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
1460 | 9a64fbe4 | bellard | /* NOP */
|
1461 | 9a64fbe4 | bellard | return;
|
1462 | 9a64fbe4 | bellard | } |
1463 | 26d67362 | aurel32 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); |
1464 | 79aceca5 | bellard | } |
1465 | 99e300ef | Blue Swirl | |
1466 | 54623277 | Blue Swirl | /* xoris */
|
1467 | 99e300ef | Blue Swirl | static void gen_xoris(DisasContext *ctx) |
1468 | 79aceca5 | bellard | { |
1469 | 76a66253 | j_mayer | target_ulong uimm = UIMM(ctx->opcode); |
1470 | 9a64fbe4 | bellard | |
1471 | 9a64fbe4 | bellard | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
1472 | 9a64fbe4 | bellard | /* NOP */
|
1473 | 9a64fbe4 | bellard | return;
|
1474 | 9a64fbe4 | bellard | } |
1475 | 26d67362 | aurel32 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
|
1476 | 79aceca5 | bellard | } |
1477 | 99e300ef | Blue Swirl | |
1478 | 54623277 | Blue Swirl | /* popcntb : PowerPC 2.03 specification */
|
1479 | 99e300ef | Blue Swirl | static void gen_popcntb(DisasContext *ctx) |
1480 | d9bce9d9 | j_mayer | { |
1481 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
1482 | d9bce9d9 | j_mayer | if (ctx->sf_mode)
|
1483 | a7812ae4 | pbrook | gen_helper_popcntb_64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
1484 | d9bce9d9 | j_mayer | else
|
1485 | d9bce9d9 | j_mayer | #endif
|
1486 | a7812ae4 | pbrook | gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
1487 | d9bce9d9 | j_mayer | } |
1488 | d9bce9d9 | j_mayer | |
1489 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
1490 | d9bce9d9 | j_mayer | /* extsw & extsw. */
|
1491 | 26d67362 | aurel32 | GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
|
1492 | 99e300ef | Blue Swirl | |
1493 | 54623277 | Blue Swirl | /* cntlzd */
|
1494 | 99e300ef | Blue Swirl | static void gen_cntlzd(DisasContext *ctx) |
1495 | 26d67362 | aurel32 | { |
1496 | a7812ae4 | pbrook | gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
1497 | 26d67362 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1498 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1499 | 26d67362 | aurel32 | } |
1500 | d9bce9d9 | j_mayer | #endif
|
1501 | d9bce9d9 | j_mayer | |
1502 | 79aceca5 | bellard | /*** Integer rotate ***/
|
1503 | 99e300ef | Blue Swirl | |
1504 | 54623277 | Blue Swirl | /* rlwimi & rlwimi. */
|
1505 | 99e300ef | Blue Swirl | static void gen_rlwimi(DisasContext *ctx) |
1506 | 79aceca5 | bellard | { |
1507 | 76a66253 | j_mayer | uint32_t mb, me, sh; |
1508 | 79aceca5 | bellard | |
1509 | 79aceca5 | bellard | mb = MB(ctx->opcode); |
1510 | 79aceca5 | bellard | me = ME(ctx->opcode); |
1511 | 76a66253 | j_mayer | sh = SH(ctx->opcode); |
1512 | d03ef511 | aurel32 | if (likely(sh == 0 && mb == 0 && me == 31)) { |
1513 | d03ef511 | aurel32 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
1514 | d03ef511 | aurel32 | } else {
|
1515 | d03ef511 | aurel32 | target_ulong mask; |
1516 | a7812ae4 | pbrook | TCGv t1; |
1517 | a7812ae4 | pbrook | TCGv t0 = tcg_temp_new(); |
1518 | 54843a58 | aurel32 | #if defined(TARGET_PPC64)
|
1519 | a7812ae4 | pbrook | TCGv_i32 t2 = tcg_temp_new_i32(); |
1520 | a7812ae4 | pbrook | tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]); |
1521 | a7812ae4 | pbrook | tcg_gen_rotli_i32(t2, t2, sh); |
1522 | a7812ae4 | pbrook | tcg_gen_extu_i32_i64(t0, t2); |
1523 | a7812ae4 | pbrook | tcg_temp_free_i32(t2); |
1524 | 54843a58 | aurel32 | #else
|
1525 | 54843a58 | aurel32 | tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh); |
1526 | 54843a58 | aurel32 | #endif
|
1527 | 76a66253 | j_mayer | #if defined(TARGET_PPC64)
|
1528 | d03ef511 | aurel32 | mb += 32;
|
1529 | d03ef511 | aurel32 | me += 32;
|
1530 | 76a66253 | j_mayer | #endif
|
1531 | d03ef511 | aurel32 | mask = MASK(mb, me); |
1532 | a7812ae4 | pbrook | t1 = tcg_temp_new(); |
1533 | d03ef511 | aurel32 | tcg_gen_andi_tl(t0, t0, mask); |
1534 | d03ef511 | aurel32 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask); |
1535 | d03ef511 | aurel32 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
1536 | d03ef511 | aurel32 | tcg_temp_free(t0); |
1537 | d03ef511 | aurel32 | tcg_temp_free(t1); |
1538 | d03ef511 | aurel32 | } |
1539 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
1540 | d03ef511 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1541 | 79aceca5 | bellard | } |
1542 | 99e300ef | Blue Swirl | |
1543 | 54623277 | Blue Swirl | /* rlwinm & rlwinm. */
|
1544 | 99e300ef | Blue Swirl | static void gen_rlwinm(DisasContext *ctx) |
1545 | 79aceca5 | bellard | { |
1546 | 79aceca5 | bellard | uint32_t mb, me, sh; |
1547 | 3b46e624 | ths | |
1548 | 79aceca5 | bellard | sh = SH(ctx->opcode); |
1549 | 79aceca5 | bellard | mb = MB(ctx->opcode); |
1550 | 79aceca5 | bellard | me = ME(ctx->opcode); |
1551 | d03ef511 | aurel32 | |
1552 | d03ef511 | aurel32 | if (likely(mb == 0 && me == (31 - sh))) { |
1553 | d03ef511 | aurel32 | if (likely(sh == 0)) { |
1554 | d03ef511 | aurel32 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
1555 | d03ef511 | aurel32 | } else {
|
1556 | a7812ae4 | pbrook | TCGv t0 = tcg_temp_new(); |
1557 | d03ef511 | aurel32 | tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]); |
1558 | d03ef511 | aurel32 | tcg_gen_shli_tl(t0, t0, sh); |
1559 | d03ef511 | aurel32 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0); |
1560 | d03ef511 | aurel32 | tcg_temp_free(t0); |
1561 | 79aceca5 | bellard | } |
1562 | d03ef511 | aurel32 | } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) { |
1563 | a7812ae4 | pbrook | TCGv t0 = tcg_temp_new(); |
1564 | d03ef511 | aurel32 | tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]); |
1565 | d03ef511 | aurel32 | tcg_gen_shri_tl(t0, t0, mb); |
1566 | d03ef511 | aurel32 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0); |
1567 | d03ef511 | aurel32 | tcg_temp_free(t0); |
1568 | d03ef511 | aurel32 | } else {
|
1569 | a7812ae4 | pbrook | TCGv t0 = tcg_temp_new(); |
1570 | 54843a58 | aurel32 | #if defined(TARGET_PPC64)
|
1571 | a7812ae4 | pbrook | TCGv_i32 t1 = tcg_temp_new_i32(); |
1572 | 54843a58 | aurel32 | tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]); |
1573 | 54843a58 | aurel32 | tcg_gen_rotli_i32(t1, t1, sh); |
1574 | 54843a58 | aurel32 | tcg_gen_extu_i32_i64(t0, t1); |
1575 | a7812ae4 | pbrook | tcg_temp_free_i32(t1); |
1576 | 54843a58 | aurel32 | #else
|
1577 | 54843a58 | aurel32 | tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh); |
1578 | 54843a58 | aurel32 | #endif
|
1579 | 76a66253 | j_mayer | #if defined(TARGET_PPC64)
|
1580 | d03ef511 | aurel32 | mb += 32;
|
1581 | d03ef511 | aurel32 | me += 32;
|
1582 | 76a66253 | j_mayer | #endif
|
1583 | d03ef511 | aurel32 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); |
1584 | d03ef511 | aurel32 | tcg_temp_free(t0); |
1585 | d03ef511 | aurel32 | } |
1586 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
1587 | d03ef511 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1588 | 79aceca5 | bellard | } |
1589 | 99e300ef | Blue Swirl | |
1590 | 54623277 | Blue Swirl | /* rlwnm & rlwnm. */
|
1591 | 99e300ef | Blue Swirl | static void gen_rlwnm(DisasContext *ctx) |
1592 | 79aceca5 | bellard | { |
1593 | 79aceca5 | bellard | uint32_t mb, me; |
1594 | 54843a58 | aurel32 | TCGv t0; |
1595 | 54843a58 | aurel32 | #if defined(TARGET_PPC64)
|
1596 | a7812ae4 | pbrook | TCGv_i32 t1, t2; |
1597 | 54843a58 | aurel32 | #endif
|
1598 | 79aceca5 | bellard | |
1599 | 79aceca5 | bellard | mb = MB(ctx->opcode); |
1600 | 79aceca5 | bellard | me = ME(ctx->opcode); |
1601 | a7812ae4 | pbrook | t0 = tcg_temp_new(); |
1602 | d03ef511 | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
|
1603 | 54843a58 | aurel32 | #if defined(TARGET_PPC64)
|
1604 | a7812ae4 | pbrook | t1 = tcg_temp_new_i32(); |
1605 | a7812ae4 | pbrook | t2 = tcg_temp_new_i32(); |
1606 | 54843a58 | aurel32 | tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]); |
1607 | 54843a58 | aurel32 | tcg_gen_trunc_i64_i32(t2, t0); |
1608 | 54843a58 | aurel32 | tcg_gen_rotl_i32(t1, t1, t2); |
1609 | 54843a58 | aurel32 | tcg_gen_extu_i32_i64(t0, t1); |
1610 | a7812ae4 | pbrook | tcg_temp_free_i32(t1); |
1611 | a7812ae4 | pbrook | tcg_temp_free_i32(t2); |
1612 | 54843a58 | aurel32 | #else
|
1613 | 54843a58 | aurel32 | tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0); |
1614 | 54843a58 | aurel32 | #endif
|
1615 | 76a66253 | j_mayer | if (unlikely(mb != 0 || me != 31)) { |
1616 | 76a66253 | j_mayer | #if defined(TARGET_PPC64)
|
1617 | 76a66253 | j_mayer | mb += 32;
|
1618 | 76a66253 | j_mayer | me += 32;
|
1619 | 76a66253 | j_mayer | #endif
|
1620 | 54843a58 | aurel32 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); |
1621 | d03ef511 | aurel32 | } else {
|
1622 | 54843a58 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
1623 | 79aceca5 | bellard | } |
1624 | 54843a58 | aurel32 | tcg_temp_free(t0); |
1625 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
1626 | d03ef511 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1627 | 79aceca5 | bellard | } |
1628 | 79aceca5 | bellard | |
1629 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
1630 | d9bce9d9 | j_mayer | #define GEN_PPC64_R2(name, opc1, opc2) \
|
1631 | e8eaa2c0 | Blue Swirl | static void glue(gen_, name##0)(DisasContext *ctx) \ |
1632 | d9bce9d9 | j_mayer | { \ |
1633 | d9bce9d9 | j_mayer | gen_##name(ctx, 0); \ |
1634 | d9bce9d9 | j_mayer | } \ |
1635 | e8eaa2c0 | Blue Swirl | \ |
1636 | e8eaa2c0 | Blue Swirl | static void glue(gen_, name##1)(DisasContext *ctx) \ |
1637 | d9bce9d9 | j_mayer | { \ |
1638 | d9bce9d9 | j_mayer | gen_##name(ctx, 1); \ |
1639 | d9bce9d9 | j_mayer | } |
1640 | d9bce9d9 | j_mayer | #define GEN_PPC64_R4(name, opc1, opc2) \
|
1641 | e8eaa2c0 | Blue Swirl | static void glue(gen_, name##0)(DisasContext *ctx) \ |
1642 | d9bce9d9 | j_mayer | { \ |
1643 | d9bce9d9 | j_mayer | gen_##name(ctx, 0, 0); \ |
1644 | d9bce9d9 | j_mayer | } \ |
1645 | e8eaa2c0 | Blue Swirl | \ |
1646 | e8eaa2c0 | Blue Swirl | static void glue(gen_, name##1)(DisasContext *ctx) \ |
1647 | d9bce9d9 | j_mayer | { \ |
1648 | d9bce9d9 | j_mayer | gen_##name(ctx, 0, 1); \ |
1649 | d9bce9d9 | j_mayer | } \ |
1650 | e8eaa2c0 | Blue Swirl | \ |
1651 | e8eaa2c0 | Blue Swirl | static void glue(gen_, name##2)(DisasContext *ctx) \ |
1652 | d9bce9d9 | j_mayer | { \ |
1653 | d9bce9d9 | j_mayer | gen_##name(ctx, 1, 0); \ |
1654 | d9bce9d9 | j_mayer | } \ |
1655 | e8eaa2c0 | Blue Swirl | \ |
1656 | e8eaa2c0 | Blue Swirl | static void glue(gen_, name##3)(DisasContext *ctx) \ |
1657 | d9bce9d9 | j_mayer | { \ |
1658 | d9bce9d9 | j_mayer | gen_##name(ctx, 1, 1); \ |
1659 | d9bce9d9 | j_mayer | } |
1660 | 51789c41 | j_mayer | |
1661 | b068d6a7 | j_mayer | static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb, |
1662 | b068d6a7 | j_mayer | uint32_t me, uint32_t sh) |
1663 | 51789c41 | j_mayer | { |
1664 | d03ef511 | aurel32 | if (likely(sh != 0 && mb == 0 && me == (63 - sh))) { |
1665 | d03ef511 | aurel32 | tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); |
1666 | d03ef511 | aurel32 | } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) { |
1667 | d03ef511 | aurel32 | tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb); |
1668 | d03ef511 | aurel32 | } else {
|
1669 | a7812ae4 | pbrook | TCGv t0 = tcg_temp_new(); |
1670 | 54843a58 | aurel32 | tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
1671 | d03ef511 | aurel32 | if (likely(mb == 0 && me == 63)) { |
1672 | 54843a58 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
1673 | d03ef511 | aurel32 | } else {
|
1674 | d03ef511 | aurel32 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); |
1675 | 51789c41 | j_mayer | } |
1676 | d03ef511 | aurel32 | tcg_temp_free(t0); |
1677 | 51789c41 | j_mayer | } |
1678 | 51789c41 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
1679 | d03ef511 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1680 | 51789c41 | j_mayer | } |
1681 | d9bce9d9 | j_mayer | /* rldicl - rldicl. */
|
1682 | b068d6a7 | j_mayer | static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn) |
1683 | d9bce9d9 | j_mayer | { |
1684 | 51789c41 | j_mayer | uint32_t sh, mb; |
1685 | d9bce9d9 | j_mayer | |
1686 | 9d53c753 | j_mayer | sh = SH(ctx->opcode) | (shn << 5);
|
1687 | 9d53c753 | j_mayer | mb = MB(ctx->opcode) | (mbn << 5);
|
1688 | 51789c41 | j_mayer | gen_rldinm(ctx, mb, 63, sh);
|
1689 | d9bce9d9 | j_mayer | } |
1690 | 51789c41 | j_mayer | GEN_PPC64_R4(rldicl, 0x1E, 0x00); |
1691 | d9bce9d9 | j_mayer | /* rldicr - rldicr. */
|
1692 | b068d6a7 | j_mayer | static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn) |
1693 | d9bce9d9 | j_mayer | { |
1694 | 51789c41 | j_mayer | uint32_t sh, me; |
1695 | d9bce9d9 | j_mayer | |
1696 | 9d53c753 | j_mayer | sh = SH(ctx->opcode) | (shn << 5);
|
1697 | 9d53c753 | j_mayer | me = MB(ctx->opcode) | (men << 5);
|
1698 | 51789c41 | j_mayer | gen_rldinm(ctx, 0, me, sh);
|
1699 | d9bce9d9 | j_mayer | } |
1700 | 51789c41 | j_mayer | GEN_PPC64_R4(rldicr, 0x1E, 0x02); |
1701 | d9bce9d9 | j_mayer | /* rldic - rldic. */
|
1702 | b068d6a7 | j_mayer | static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn) |
1703 | d9bce9d9 | j_mayer | { |
1704 | 51789c41 | j_mayer | uint32_t sh, mb; |
1705 | d9bce9d9 | j_mayer | |
1706 | 9d53c753 | j_mayer | sh = SH(ctx->opcode) | (shn << 5);
|
1707 | 9d53c753 | j_mayer | mb = MB(ctx->opcode) | (mbn << 5);
|
1708 | 51789c41 | j_mayer | gen_rldinm(ctx, mb, 63 - sh, sh);
|
1709 | 51789c41 | j_mayer | } |
1710 | 51789c41 | j_mayer | GEN_PPC64_R4(rldic, 0x1E, 0x04); |
1711 | 51789c41 | j_mayer | |
1712 | b068d6a7 | j_mayer | static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb, |
1713 | b068d6a7 | j_mayer | uint32_t me) |
1714 | 51789c41 | j_mayer | { |
1715 | 54843a58 | aurel32 | TCGv t0; |
1716 | d03ef511 | aurel32 | |
1717 | d03ef511 | aurel32 | mb = MB(ctx->opcode); |
1718 | d03ef511 | aurel32 | me = ME(ctx->opcode); |
1719 | a7812ae4 | pbrook | t0 = tcg_temp_new(); |
1720 | d03ef511 | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
|
1721 | 54843a58 | aurel32 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
1722 | 51789c41 | j_mayer | if (unlikely(mb != 0 || me != 63)) { |
1723 | 54843a58 | aurel32 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); |
1724 | 54843a58 | aurel32 | } else {
|
1725 | 54843a58 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
1726 | 54843a58 | aurel32 | } |
1727 | 54843a58 | aurel32 | tcg_temp_free(t0); |
1728 | 51789c41 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
1729 | d03ef511 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1730 | d9bce9d9 | j_mayer | } |
1731 | 51789c41 | j_mayer | |
1732 | d9bce9d9 | j_mayer | /* rldcl - rldcl. */
|
1733 | b068d6a7 | j_mayer | static always_inline void gen_rldcl (DisasContext *ctx, int mbn) |
1734 | d9bce9d9 | j_mayer | { |
1735 | 51789c41 | j_mayer | uint32_t mb; |
1736 | d9bce9d9 | j_mayer | |
1737 | 9d53c753 | j_mayer | mb = MB(ctx->opcode) | (mbn << 5);
|
1738 | 51789c41 | j_mayer | gen_rldnm(ctx, mb, 63);
|
1739 | d9bce9d9 | j_mayer | } |
1740 | 36081602 | j_mayer | GEN_PPC64_R2(rldcl, 0x1E, 0x08); |
1741 | d9bce9d9 | j_mayer | /* rldcr - rldcr. */
|
1742 | b068d6a7 | j_mayer | static always_inline void gen_rldcr (DisasContext *ctx, int men) |
1743 | d9bce9d9 | j_mayer | { |
1744 | 51789c41 | j_mayer | uint32_t me; |
1745 | d9bce9d9 | j_mayer | |
1746 | 9d53c753 | j_mayer | me = MB(ctx->opcode) | (men << 5);
|
1747 | 51789c41 | j_mayer | gen_rldnm(ctx, 0, me);
|
1748 | d9bce9d9 | j_mayer | } |
1749 | 36081602 | j_mayer | GEN_PPC64_R2(rldcr, 0x1E, 0x09); |
1750 | d9bce9d9 | j_mayer | /* rldimi - rldimi. */
|
1751 | b068d6a7 | j_mayer | static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn) |
1752 | d9bce9d9 | j_mayer | { |
1753 | 271a916e | j_mayer | uint32_t sh, mb, me; |
1754 | d9bce9d9 | j_mayer | |
1755 | 9d53c753 | j_mayer | sh = SH(ctx->opcode) | (shn << 5);
|
1756 | 9d53c753 | j_mayer | mb = MB(ctx->opcode) | (mbn << 5);
|
1757 | 271a916e | j_mayer | me = 63 - sh;
|
1758 | d03ef511 | aurel32 | if (unlikely(sh == 0 && mb == 0)) { |
1759 | d03ef511 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
1760 | d03ef511 | aurel32 | } else {
|
1761 | d03ef511 | aurel32 | TCGv t0, t1; |
1762 | d03ef511 | aurel32 | target_ulong mask; |
1763 | d03ef511 | aurel32 | |
1764 | a7812ae4 | pbrook | t0 = tcg_temp_new(); |
1765 | 54843a58 | aurel32 | tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
1766 | a7812ae4 | pbrook | t1 = tcg_temp_new(); |
1767 | d03ef511 | aurel32 | mask = MASK(mb, me); |
1768 | d03ef511 | aurel32 | tcg_gen_andi_tl(t0, t0, mask); |
1769 | d03ef511 | aurel32 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask); |
1770 | d03ef511 | aurel32 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
1771 | d03ef511 | aurel32 | tcg_temp_free(t0); |
1772 | d03ef511 | aurel32 | tcg_temp_free(t1); |
1773 | 51789c41 | j_mayer | } |
1774 | 51789c41 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
1775 | d03ef511 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1776 | d9bce9d9 | j_mayer | } |
1777 | 36081602 | j_mayer | GEN_PPC64_R4(rldimi, 0x1E, 0x06); |
1778 | d9bce9d9 | j_mayer | #endif
|
1779 | d9bce9d9 | j_mayer | |
1780 | 79aceca5 | bellard | /*** Integer shift ***/
|
1781 | 99e300ef | Blue Swirl | |
1782 | 54623277 | Blue Swirl | /* slw & slw. */
|
1783 | 99e300ef | Blue Swirl | static void gen_slw(DisasContext *ctx) |
1784 | 26d67362 | aurel32 | { |
1785 | fea0c503 | aurel32 | TCGv t0; |
1786 | 26d67362 | aurel32 | int l1, l2;
|
1787 | 26d67362 | aurel32 | l1 = gen_new_label(); |
1788 | 26d67362 | aurel32 | l2 = gen_new_label(); |
1789 | 26d67362 | aurel32 | |
1790 | a7812ae4 | pbrook | t0 = tcg_temp_local_new(); |
1791 | 0cfe58cd | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
|
1792 | 0cfe58cd | aurel32 | tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
|
1793 | 26d67362 | aurel32 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
|
1794 | 26d67362 | aurel32 | tcg_gen_br(l2); |
1795 | 26d67362 | aurel32 | gen_set_label(l1); |
1796 | fea0c503 | aurel32 | tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0); |
1797 | 26d67362 | aurel32 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
1798 | 26d67362 | aurel32 | gen_set_label(l2); |
1799 | fea0c503 | aurel32 | tcg_temp_free(t0); |
1800 | 26d67362 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1801 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1802 | 26d67362 | aurel32 | } |
1803 | 99e300ef | Blue Swirl | |
1804 | 54623277 | Blue Swirl | /* sraw & sraw. */
|
1805 | 99e300ef | Blue Swirl | static void gen_sraw(DisasContext *ctx) |
1806 | 26d67362 | aurel32 | { |
1807 | a7812ae4 | pbrook | gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], |
1808 | a7812ae4 | pbrook | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
1809 | 26d67362 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1810 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1811 | 26d67362 | aurel32 | } |
1812 | 99e300ef | Blue Swirl | |
1813 | 54623277 | Blue Swirl | /* srawi & srawi. */
|
1814 | 99e300ef | Blue Swirl | static void gen_srawi(DisasContext *ctx) |
1815 | 79aceca5 | bellard | { |
1816 | 26d67362 | aurel32 | int sh = SH(ctx->opcode);
|
1817 | 26d67362 | aurel32 | if (sh != 0) { |
1818 | 26d67362 | aurel32 | int l1, l2;
|
1819 | fea0c503 | aurel32 | TCGv t0; |
1820 | 26d67362 | aurel32 | l1 = gen_new_label(); |
1821 | 26d67362 | aurel32 | l2 = gen_new_label(); |
1822 | a7812ae4 | pbrook | t0 = tcg_temp_local_new(); |
1823 | fea0c503 | aurel32 | tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]); |
1824 | fea0c503 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
|
1825 | fea0c503 | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1); |
1826 | fea0c503 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
|
1827 | 269f3e95 | aurel32 | tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
|
1828 | 26d67362 | aurel32 | tcg_gen_br(l2); |
1829 | 26d67362 | aurel32 | gen_set_label(l1); |
1830 | 269f3e95 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
|
1831 | 26d67362 | aurel32 | gen_set_label(l2); |
1832 | fea0c503 | aurel32 | tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]); |
1833 | fea0c503 | aurel32 | tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh); |
1834 | fea0c503 | aurel32 | tcg_temp_free(t0); |
1835 | 26d67362 | aurel32 | } else {
|
1836 | 26d67362 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
1837 | 269f3e95 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
|
1838 | d9bce9d9 | j_mayer | } |
1839 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
1840 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1841 | 79aceca5 | bellard | } |
1842 | 99e300ef | Blue Swirl | |
1843 | 54623277 | Blue Swirl | /* srw & srw. */
|
1844 | 99e300ef | Blue Swirl | static void gen_srw(DisasContext *ctx) |
1845 | 26d67362 | aurel32 | { |
1846 | fea0c503 | aurel32 | TCGv t0, t1; |
1847 | 26d67362 | aurel32 | int l1, l2;
|
1848 | 26d67362 | aurel32 | l1 = gen_new_label(); |
1849 | 26d67362 | aurel32 | l2 = gen_new_label(); |
1850 | d9bce9d9 | j_mayer | |
1851 | a7812ae4 | pbrook | t0 = tcg_temp_local_new(); |
1852 | 0cfe58cd | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
|
1853 | 0cfe58cd | aurel32 | tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
|
1854 | 26d67362 | aurel32 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
|
1855 | 26d67362 | aurel32 | tcg_gen_br(l2); |
1856 | 26d67362 | aurel32 | gen_set_label(l1); |
1857 | a7812ae4 | pbrook | t1 = tcg_temp_new(); |
1858 | fea0c503 | aurel32 | tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]); |
1859 | fea0c503 | aurel32 | tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t1, t0); |
1860 | fea0c503 | aurel32 | tcg_temp_free(t1); |
1861 | 26d67362 | aurel32 | gen_set_label(l2); |
1862 | fea0c503 | aurel32 | tcg_temp_free(t0); |
1863 | 26d67362 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1864 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1865 | 26d67362 | aurel32 | } |
1866 | 54623277 | Blue Swirl | |
1867 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
1868 | d9bce9d9 | j_mayer | /* sld & sld. */
|
1869 | 99e300ef | Blue Swirl | static void gen_sld(DisasContext *ctx) |
1870 | 26d67362 | aurel32 | { |
1871 | fea0c503 | aurel32 | TCGv t0; |
1872 | 26d67362 | aurel32 | int l1, l2;
|
1873 | 26d67362 | aurel32 | l1 = gen_new_label(); |
1874 | 26d67362 | aurel32 | l2 = gen_new_label(); |
1875 | 26d67362 | aurel32 | |
1876 | a7812ae4 | pbrook | t0 = tcg_temp_local_new(); |
1877 | 0cfe58cd | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
|
1878 | 0cfe58cd | aurel32 | tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
|
1879 | 26d67362 | aurel32 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
|
1880 | 26d67362 | aurel32 | tcg_gen_br(l2); |
1881 | 26d67362 | aurel32 | gen_set_label(l1); |
1882 | fea0c503 | aurel32 | tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0); |
1883 | 26d67362 | aurel32 | gen_set_label(l2); |
1884 | fea0c503 | aurel32 | tcg_temp_free(t0); |
1885 | 26d67362 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1886 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1887 | 26d67362 | aurel32 | } |
1888 | 99e300ef | Blue Swirl | |
1889 | 54623277 | Blue Swirl | /* srad & srad. */
|
1890 | 99e300ef | Blue Swirl | static void gen_srad(DisasContext *ctx) |
1891 | 26d67362 | aurel32 | { |
1892 | a7812ae4 | pbrook | gen_helper_srad(cpu_gpr[rA(ctx->opcode)], |
1893 | a7812ae4 | pbrook | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
1894 | 26d67362 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1895 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1896 | 26d67362 | aurel32 | } |
1897 | d9bce9d9 | j_mayer | /* sradi & sradi. */
|
1898 | b068d6a7 | j_mayer | static always_inline void gen_sradi (DisasContext *ctx, int n) |
1899 | d9bce9d9 | j_mayer | { |
1900 | 26d67362 | aurel32 | int sh = SH(ctx->opcode) + (n << 5); |
1901 | d9bce9d9 | j_mayer | if (sh != 0) { |
1902 | 26d67362 | aurel32 | int l1, l2;
|
1903 | fea0c503 | aurel32 | TCGv t0; |
1904 | 26d67362 | aurel32 | l1 = gen_new_label(); |
1905 | 26d67362 | aurel32 | l2 = gen_new_label(); |
1906 | a7812ae4 | pbrook | t0 = tcg_temp_local_new(); |
1907 | 26d67362 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
|
1908 | fea0c503 | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1); |
1909 | fea0c503 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
|
1910 | 269f3e95 | aurel32 | tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
|
1911 | 26d67362 | aurel32 | tcg_gen_br(l2); |
1912 | 26d67362 | aurel32 | gen_set_label(l1); |
1913 | 269f3e95 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
|
1914 | 26d67362 | aurel32 | gen_set_label(l2); |
1915 | a9730017 | aurel32 | tcg_temp_free(t0); |
1916 | 26d67362 | aurel32 | tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); |
1917 | 26d67362 | aurel32 | } else {
|
1918 | 26d67362 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
1919 | 269f3e95 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
|
1920 | d9bce9d9 | j_mayer | } |
1921 | d9bce9d9 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
1922 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1923 | d9bce9d9 | j_mayer | } |
1924 | e8eaa2c0 | Blue Swirl | |
1925 | e8eaa2c0 | Blue Swirl | static void gen_sradi0(DisasContext *ctx) |
1926 | d9bce9d9 | j_mayer | { |
1927 | d9bce9d9 | j_mayer | gen_sradi(ctx, 0);
|
1928 | d9bce9d9 | j_mayer | } |
1929 | e8eaa2c0 | Blue Swirl | |
1930 | e8eaa2c0 | Blue Swirl | static void gen_sradi1(DisasContext *ctx) |
1931 | d9bce9d9 | j_mayer | { |
1932 | d9bce9d9 | j_mayer | gen_sradi(ctx, 1);
|
1933 | d9bce9d9 | j_mayer | } |
1934 | 99e300ef | Blue Swirl | |
1935 | 54623277 | Blue Swirl | /* srd & srd. */
|
1936 | 99e300ef | Blue Swirl | static void gen_srd(DisasContext *ctx) |
1937 | 26d67362 | aurel32 | { |
1938 | fea0c503 | aurel32 | TCGv t0; |
1939 | 26d67362 | aurel32 | int l1, l2;
|
1940 | 26d67362 | aurel32 | l1 = gen_new_label(); |
1941 | 26d67362 | aurel32 | l2 = gen_new_label(); |
1942 | 26d67362 | aurel32 | |
1943 | a7812ae4 | pbrook | t0 = tcg_temp_local_new(); |
1944 | 0cfe58cd | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
|
1945 | 0cfe58cd | aurel32 | tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
|
1946 | 26d67362 | aurel32 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
|
1947 | 26d67362 | aurel32 | tcg_gen_br(l2); |
1948 | 26d67362 | aurel32 | gen_set_label(l1); |
1949 | fea0c503 | aurel32 | tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0); |
1950 | 26d67362 | aurel32 | gen_set_label(l2); |
1951 | fea0c503 | aurel32 | tcg_temp_free(t0); |
1952 | 26d67362 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1953 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1954 | 26d67362 | aurel32 | } |
1955 | d9bce9d9 | j_mayer | #endif
|
1956 | 79aceca5 | bellard | |
1957 | 79aceca5 | bellard | /*** Floating-Point arithmetic ***/
|
1958 | 7c58044c | j_mayer | #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
|
1959 | 99e300ef | Blue Swirl | static void gen_f##name(DisasContext *ctx) \ |
1960 | 9a64fbe4 | bellard | { \ |
1961 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
1962 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
1963 | 3cc62370 | bellard | return; \
|
1964 | 3cc62370 | bellard | } \ |
1965 | eb44b959 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */ \
|
1966 | eb44b959 | aurel32 | gen_update_nip(ctx, ctx->nip - 4); \
|
1967 | 7c58044c | j_mayer | gen_reset_fpstatus(); \ |
1968 | af12906f | aurel32 | gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \ |
1969 | af12906f | aurel32 | cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \ |
1970 | 4ecc3190 | bellard | if (isfloat) { \
|
1971 | af12906f | aurel32 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \ |
1972 | 4ecc3190 | bellard | } \ |
1973 | af12906f | aurel32 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \ |
1974 | af12906f | aurel32 | Rc(ctx->opcode) != 0); \
|
1975 | 9a64fbe4 | bellard | } |
1976 | 9a64fbe4 | bellard | |
1977 | 7c58044c | j_mayer | #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
|
1978 | 7c58044c | j_mayer | _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \ |
1979 | 7c58044c | j_mayer | _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type); |
1980 | 9a64fbe4 | bellard | |
1981 | 7c58044c | j_mayer | #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
|
1982 | 99e300ef | Blue Swirl | static void gen_f##name(DisasContext *ctx) \ |
1983 | 9a64fbe4 | bellard | { \ |
1984 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
1985 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
1986 | 3cc62370 | bellard | return; \
|
1987 | 3cc62370 | bellard | } \ |
1988 | eb44b959 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */ \
|
1989 | eb44b959 | aurel32 | gen_update_nip(ctx, ctx->nip - 4); \
|
1990 | 7c58044c | j_mayer | gen_reset_fpstatus(); \ |
1991 | af12906f | aurel32 | gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \ |
1992 | af12906f | aurel32 | cpu_fpr[rB(ctx->opcode)]); \ |
1993 | 4ecc3190 | bellard | if (isfloat) { \
|
1994 | af12906f | aurel32 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \ |
1995 | 4ecc3190 | bellard | } \ |
1996 | af12906f | aurel32 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ |
1997 | af12906f | aurel32 | set_fprf, Rc(ctx->opcode) != 0); \
|
1998 | 9a64fbe4 | bellard | } |
1999 | 7c58044c | j_mayer | #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
|
2000 | 7c58044c | j_mayer | _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ |
2001 | 7c58044c | j_mayer | _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type); |
2002 | 9a64fbe4 | bellard | |
2003 | 7c58044c | j_mayer | #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
|
2004 | 99e300ef | Blue Swirl | static void gen_f##name(DisasContext *ctx) \ |
2005 | 9a64fbe4 | bellard | { \ |
2006 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
2007 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
2008 | 3cc62370 | bellard | return; \
|
2009 | 3cc62370 | bellard | } \ |
2010 | eb44b959 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */ \
|
2011 | eb44b959 | aurel32 | gen_update_nip(ctx, ctx->nip - 4); \
|
2012 | 7c58044c | j_mayer | gen_reset_fpstatus(); \ |
2013 | af12906f | aurel32 | gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \ |
2014 | af12906f | aurel32 | cpu_fpr[rC(ctx->opcode)]); \ |
2015 | 4ecc3190 | bellard | if (isfloat) { \
|
2016 | af12906f | aurel32 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \ |
2017 | 4ecc3190 | bellard | } \ |
2018 | af12906f | aurel32 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ |
2019 | af12906f | aurel32 | set_fprf, Rc(ctx->opcode) != 0); \
|
2020 | 9a64fbe4 | bellard | } |
2021 | 7c58044c | j_mayer | #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
|
2022 | 7c58044c | j_mayer | _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ |
2023 | 7c58044c | j_mayer | _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type); |
2024 | 9a64fbe4 | bellard | |
2025 | 7c58044c | j_mayer | #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
|
2026 | 99e300ef | Blue Swirl | static void gen_f##name(DisasContext *ctx) \ |
2027 | 9a64fbe4 | bellard | { \ |
2028 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
2029 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
2030 | 3cc62370 | bellard | return; \
|
2031 | 3cc62370 | bellard | } \ |
2032 | eb44b959 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */ \
|
2033 | eb44b959 | aurel32 | gen_update_nip(ctx, ctx->nip - 4); \
|
2034 | 7c58044c | j_mayer | gen_reset_fpstatus(); \ |
2035 | af12906f | aurel32 | gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \ |
2036 | af12906f | aurel32 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ |
2037 | af12906f | aurel32 | set_fprf, Rc(ctx->opcode) != 0); \
|
2038 | 79aceca5 | bellard | } |
2039 | 79aceca5 | bellard | |
2040 | 7c58044c | j_mayer | #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
|
2041 | 99e300ef | Blue Swirl | static void gen_f##name(DisasContext *ctx) \ |
2042 | 9a64fbe4 | bellard | { \ |
2043 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
2044 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
2045 | 3cc62370 | bellard | return; \
|
2046 | 3cc62370 | bellard | } \ |
2047 | eb44b959 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */ \
|
2048 | eb44b959 | aurel32 | gen_update_nip(ctx, ctx->nip - 4); \
|
2049 | 7c58044c | j_mayer | gen_reset_fpstatus(); \ |
2050 | af12906f | aurel32 | gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \ |
2051 | af12906f | aurel32 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ |
2052 | af12906f | aurel32 | set_fprf, Rc(ctx->opcode) != 0); \
|
2053 | 79aceca5 | bellard | } |
2054 | 79aceca5 | bellard | |
2055 | 9a64fbe4 | bellard | /* fadd - fadds */
|
2056 | 7c58044c | j_mayer | GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT); |
2057 | 4ecc3190 | bellard | /* fdiv - fdivs */
|
2058 | 7c58044c | j_mayer | GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT); |
2059 | 4ecc3190 | bellard | /* fmul - fmuls */
|
2060 | 7c58044c | j_mayer | GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT); |
2061 | 79aceca5 | bellard | |
2062 | d7e4b87e | j_mayer | /* fre */
|
2063 | 7c58044c | j_mayer | GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT); |
2064 | d7e4b87e | j_mayer | |
2065 | a750fc0b | j_mayer | /* fres */
|
2066 | 7c58044c | j_mayer | GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES); |
2067 | 79aceca5 | bellard | |
2068 | a750fc0b | j_mayer | /* frsqrte */
|
2069 | 7c58044c | j_mayer | GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE); |
2070 | 7c58044c | j_mayer | |
2071 | 7c58044c | j_mayer | /* frsqrtes */
|
2072 | 99e300ef | Blue Swirl | static void gen_frsqrtes(DisasContext *ctx) |
2073 | 7c58044c | j_mayer | { |
2074 | af12906f | aurel32 | if (unlikely(!ctx->fpu_enabled)) {
|
2075 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); |
2076 | af12906f | aurel32 | return;
|
2077 | af12906f | aurel32 | } |
2078 | eb44b959 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
2079 | eb44b959 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
2080 | af12906f | aurel32 | gen_reset_fpstatus(); |
2081 | af12906f | aurel32 | gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); |
2082 | af12906f | aurel32 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); |
2083 | af12906f | aurel32 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0); |
2084 | 7c58044c | j_mayer | } |
2085 | 79aceca5 | bellard | |
2086 | a750fc0b | j_mayer | /* fsel */
|
2087 | 7c58044c | j_mayer | _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL); |
2088 | 4ecc3190 | bellard | /* fsub - fsubs */
|
2089 | 7c58044c | j_mayer | GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT); |
2090 | 79aceca5 | bellard | /* Optional: */
|
2091 | 99e300ef | Blue Swirl | |
2092 | 54623277 | Blue Swirl | /* fsqrt */
|
2093 | 99e300ef | Blue Swirl | static void gen_fsqrt(DisasContext *ctx) |
2094 | c7d344af | bellard | { |
2095 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) {
|
2096 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); |
2097 | c7d344af | bellard | return;
|
2098 | c7d344af | bellard | } |
2099 | eb44b959 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
2100 | eb44b959 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
2101 | 7c58044c | j_mayer | gen_reset_fpstatus(); |
2102 | af12906f | aurel32 | gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); |
2103 | af12906f | aurel32 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0); |
2104 | c7d344af | bellard | } |
2105 | 79aceca5 | bellard | |
2106 | 99e300ef | Blue Swirl | static void gen_fsqrts(DisasContext *ctx) |
2107 | 79aceca5 | bellard | { |
2108 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) {
|
2109 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); |
2110 | 3cc62370 | bellard | return;
|
2111 | 3cc62370 | bellard | } |
2112 | eb44b959 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
2113 | eb44b959 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
2114 | 7c58044c | j_mayer | gen_reset_fpstatus(); |
2115 | af12906f | aurel32 | gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); |
2116 | af12906f | aurel32 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); |
2117 | af12906f | aurel32 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0); |
2118 | 79aceca5 | bellard | } |
2119 | 79aceca5 | bellard | |
2120 | 79aceca5 | bellard | /*** Floating-Point multiply-and-add ***/
|
2121 | 4ecc3190 | bellard | /* fmadd - fmadds */
|
2122 | 7c58044c | j_mayer | GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT); |
2123 | 4ecc3190 | bellard | /* fmsub - fmsubs */
|
2124 | 7c58044c | j_mayer | GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT); |
2125 | 4ecc3190 | bellard | /* fnmadd - fnmadds */
|
2126 | 7c58044c | j_mayer | GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT); |
2127 | 4ecc3190 | bellard | /* fnmsub - fnmsubs */
|
2128 | 7c58044c | j_mayer | GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT); |
2129 | 79aceca5 | bellard | |
2130 | 79aceca5 | bellard | /*** Floating-Point round & convert ***/
|
2131 | 79aceca5 | bellard | /* fctiw */
|
2132 | 7c58044c | j_mayer | GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT); |
2133 | 79aceca5 | bellard | /* fctiwz */
|
2134 | 7c58044c | j_mayer | GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT); |
2135 | 79aceca5 | bellard | /* frsp */
|
2136 | 7c58044c | j_mayer | GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT); |
2137 | 426613db | j_mayer | #if defined(TARGET_PPC64)
|
2138 | 426613db | j_mayer | /* fcfid */
|
2139 | 7c58044c | j_mayer | GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B); |
2140 | 426613db | j_mayer | /* fctid */
|
2141 | 7c58044c | j_mayer | GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B); |
2142 | 426613db | j_mayer | /* fctidz */
|
2143 | 7c58044c | j_mayer | GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B); |
2144 | 426613db | j_mayer | #endif
|
2145 | 79aceca5 | bellard | |
2146 | d7e4b87e | j_mayer | /* frin */
|
2147 | 7c58044c | j_mayer | GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT); |
2148 | d7e4b87e | j_mayer | /* friz */
|
2149 | 7c58044c | j_mayer | GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT); |
2150 | d7e4b87e | j_mayer | /* frip */
|
2151 | 7c58044c | j_mayer | GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT); |
2152 | d7e4b87e | j_mayer | /* frim */
|
2153 | 7c58044c | j_mayer | GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT); |
2154 | d7e4b87e | j_mayer | |
2155 | 79aceca5 | bellard | /*** Floating-Point compare ***/
|
2156 | 99e300ef | Blue Swirl | |
2157 | 54623277 | Blue Swirl | /* fcmpo */
|
2158 | 99e300ef | Blue Swirl | static void gen_fcmpo(DisasContext *ctx) |
2159 | 79aceca5 | bellard | { |
2160 | 330c483b | aurel32 | TCGv_i32 crf; |
2161 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) {
|
2162 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); |
2163 | 3cc62370 | bellard | return;
|
2164 | 3cc62370 | bellard | } |
2165 | eb44b959 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
2166 | eb44b959 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
2167 | 7c58044c | j_mayer | gen_reset_fpstatus(); |
2168 | 9a819377 | aurel32 | crf = tcg_const_i32(crfD(ctx->opcode)); |
2169 | 9a819377 | aurel32 | gen_helper_fcmpo(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf); |
2170 | 330c483b | aurel32 | tcg_temp_free_i32(crf); |
2171 | af12906f | aurel32 | gen_helper_float_check_status(); |
2172 | 79aceca5 | bellard | } |
2173 | 79aceca5 | bellard | |
2174 | 79aceca5 | bellard | /* fcmpu */
|
2175 | 99e300ef | Blue Swirl | static void gen_fcmpu(DisasContext *ctx) |
2176 | 79aceca5 | bellard | { |
2177 | 330c483b | aurel32 | TCGv_i32 crf; |
2178 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) {
|
2179 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); |
2180 | 3cc62370 | bellard | return;
|
2181 | 3cc62370 | bellard | } |
2182 | eb44b959 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
2183 | eb44b959 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
2184 | 7c58044c | j_mayer | gen_reset_fpstatus(); |
2185 | 9a819377 | aurel32 | crf = tcg_const_i32(crfD(ctx->opcode)); |
2186 | 9a819377 | aurel32 | gen_helper_fcmpu(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf); |
2187 | 330c483b | aurel32 | tcg_temp_free_i32(crf); |
2188 | af12906f | aurel32 | gen_helper_float_check_status(); |
2189 | 79aceca5 | bellard | } |
2190 | 79aceca5 | bellard | |
2191 | 9a64fbe4 | bellard | /*** Floating-point move ***/
|
2192 | 9a64fbe4 | bellard | /* fabs */
|
2193 | 7c58044c | j_mayer | /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
|
2194 | 7c58044c | j_mayer | GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT); |
2195 | 9a64fbe4 | bellard | |
2196 | 9a64fbe4 | bellard | /* fmr - fmr. */
|
2197 | 7c58044c | j_mayer | /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
|
2198 | 99e300ef | Blue Swirl | static void gen_fmr(DisasContext *ctx) |
2199 | 9a64fbe4 | bellard | { |
2200 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) {
|
2201 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); |
2202 | 3cc62370 | bellard | return;
|
2203 | 3cc62370 | bellard | } |
2204 | af12906f | aurel32 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); |
2205 | af12906f | aurel32 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); |
2206 | 9a64fbe4 | bellard | } |
2207 | 9a64fbe4 | bellard | |
2208 | 9a64fbe4 | bellard | /* fnabs */
|
2209 | 7c58044c | j_mayer | /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
|
2210 | 7c58044c | j_mayer | GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT); |
2211 | 9a64fbe4 | bellard | /* fneg */
|
2212 | 7c58044c | j_mayer | /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
|
2213 | 7c58044c | j_mayer | GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT); |
2214 | 9a64fbe4 | bellard | |
2215 | 79aceca5 | bellard | /*** Floating-Point status & ctrl register ***/
|
2216 | 99e300ef | Blue Swirl | |
2217 | 54623277 | Blue Swirl | /* mcrfs */
|
2218 | 99e300ef | Blue Swirl | static void gen_mcrfs(DisasContext *ctx) |
2219 | 79aceca5 | bellard | { |
2220 | 7c58044c | j_mayer | int bfa;
|
2221 | 7c58044c | j_mayer | |
2222 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) {
|
2223 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); |
2224 | 3cc62370 | bellard | return;
|
2225 | 3cc62370 | bellard | } |
2226 | 7c58044c | j_mayer | bfa = 4 * (7 - crfS(ctx->opcode)); |
2227 | e1571908 | aurel32 | tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa); |
2228 | e1571908 | aurel32 | tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
|
2229 | af12906f | aurel32 | tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
|
2230 | 79aceca5 | bellard | } |
2231 | 79aceca5 | bellard | |
2232 | 79aceca5 | bellard | /* mffs */
|
2233 | 99e300ef | Blue Swirl | static void gen_mffs(DisasContext *ctx) |
2234 | 79aceca5 | bellard | { |
2235 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) {
|
2236 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); |
2237 | 3cc62370 | bellard | return;
|
2238 | 3cc62370 | bellard | } |
2239 | 7c58044c | j_mayer | gen_reset_fpstatus(); |
2240 | af12906f | aurel32 | tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr); |
2241 | af12906f | aurel32 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); |
2242 | 79aceca5 | bellard | } |
2243 | 79aceca5 | bellard | |
2244 | 79aceca5 | bellard | /* mtfsb0 */
|
2245 | 99e300ef | Blue Swirl | static void gen_mtfsb0(DisasContext *ctx) |
2246 | 79aceca5 | bellard | { |
2247 | fb0eaffc | bellard | uint8_t crb; |
2248 | 3b46e624 | ths | |
2249 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) {
|
2250 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); |
2251 | 3cc62370 | bellard | return;
|
2252 | 3cc62370 | bellard | } |
2253 | 6e35d524 | aurel32 | crb = 31 - crbD(ctx->opcode);
|
2254 | 7c58044c | j_mayer | gen_reset_fpstatus(); |
2255 | 6e35d524 | aurel32 | if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
|
2256 | eb44b959 | aurel32 | TCGv_i32 t0; |
2257 | eb44b959 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
2258 | eb44b959 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
2259 | eb44b959 | aurel32 | t0 = tcg_const_i32(crb); |
2260 | 6e35d524 | aurel32 | gen_helper_fpscr_clrbit(t0); |
2261 | 6e35d524 | aurel32 | tcg_temp_free_i32(t0); |
2262 | 6e35d524 | aurel32 | } |
2263 | 7c58044c | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) { |
2264 | e1571908 | aurel32 | tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
|
2265 | 7c58044c | j_mayer | } |
2266 | 79aceca5 | bellard | } |
2267 | 79aceca5 | bellard | |
2268 | 79aceca5 | bellard | /* mtfsb1 */
|
2269 | 99e300ef | Blue Swirl | static void gen_mtfsb1(DisasContext *ctx) |
2270 | 79aceca5 | bellard | { |
2271 | fb0eaffc | bellard | uint8_t crb; |
2272 | 3b46e624 | ths | |
2273 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) {
|
2274 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); |
2275 | 3cc62370 | bellard | return;
|
2276 | 3cc62370 | bellard | } |
2277 | 6e35d524 | aurel32 | crb = 31 - crbD(ctx->opcode);
|
2278 | 7c58044c | j_mayer | gen_reset_fpstatus(); |
2279 | 7c58044c | j_mayer | /* XXX: we pretend we can only do IEEE floating-point computations */
|
2280 | af12906f | aurel32 | if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
|
2281 | eb44b959 | aurel32 | TCGv_i32 t0; |
2282 | eb44b959 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
2283 | eb44b959 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
2284 | eb44b959 | aurel32 | t0 = tcg_const_i32(crb); |
2285 | af12906f | aurel32 | gen_helper_fpscr_setbit(t0); |
2286 | 0f2f39c2 | aurel32 | tcg_temp_free_i32(t0); |
2287 | af12906f | aurel32 | } |
2288 | 7c58044c | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) { |
2289 | e1571908 | aurel32 | tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
|
2290 | 7c58044c | j_mayer | } |
2291 | 7c58044c | j_mayer | /* We can raise a differed exception */
|
2292 | af12906f | aurel32 | gen_helper_float_check_status(); |
2293 | 79aceca5 | bellard | } |
2294 | 79aceca5 | bellard | |
2295 | 79aceca5 | bellard | /* mtfsf */
|
2296 | 99e300ef | Blue Swirl | static void gen_mtfsf(DisasContext *ctx) |
2297 | 79aceca5 | bellard | { |
2298 | 0f2f39c2 | aurel32 | TCGv_i32 t0; |
2299 | 4911012d | blueswir1 | int L = ctx->opcode & 0x02000000; |
2300 | af12906f | aurel32 | |
2301 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) {
|
2302 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); |
2303 | 3cc62370 | bellard | return;
|
2304 | 3cc62370 | bellard | } |
2305 | eb44b959 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
2306 | eb44b959 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
2307 | 7c58044c | j_mayer | gen_reset_fpstatus(); |
2308 | 4911012d | blueswir1 | if (L)
|
2309 | 4911012d | blueswir1 | t0 = tcg_const_i32(0xff);
|
2310 | 4911012d | blueswir1 | else
|
2311 | 4911012d | blueswir1 | t0 = tcg_const_i32(FM(ctx->opcode)); |
2312 | af12906f | aurel32 | gen_helper_store_fpscr(cpu_fpr[rB(ctx->opcode)], t0); |
2313 | 0f2f39c2 | aurel32 | tcg_temp_free_i32(t0); |
2314 | 7c58044c | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) { |
2315 | e1571908 | aurel32 | tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
|
2316 | 7c58044c | j_mayer | } |
2317 | 7c58044c | j_mayer | /* We can raise a differed exception */
|
2318 | af12906f | aurel32 | gen_helper_float_check_status(); |
2319 | 79aceca5 | bellard | } |
2320 | 79aceca5 | bellard | |
2321 | 79aceca5 | bellard | /* mtfsfi */
|
2322 | 99e300ef | Blue Swirl | static void gen_mtfsfi(DisasContext *ctx) |
2323 | 79aceca5 | bellard | { |
2324 | 7c58044c | j_mayer | int bf, sh;
|
2325 | 0f2f39c2 | aurel32 | TCGv_i64 t0; |
2326 | 0f2f39c2 | aurel32 | TCGv_i32 t1; |
2327 | 7c58044c | j_mayer | |
2328 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) {
|
2329 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); |
2330 | 3cc62370 | bellard | return;
|
2331 | 3cc62370 | bellard | } |
2332 | 7c58044c | j_mayer | bf = crbD(ctx->opcode) >> 2;
|
2333 | 7c58044c | j_mayer | sh = 7 - bf;
|
2334 | eb44b959 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
2335 | eb44b959 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
2336 | 7c58044c | j_mayer | gen_reset_fpstatus(); |
2337 | 0f2f39c2 | aurel32 | t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
|
2338 | af12906f | aurel32 | t1 = tcg_const_i32(1 << sh);
|
2339 | af12906f | aurel32 | gen_helper_store_fpscr(t0, t1); |
2340 | 0f2f39c2 | aurel32 | tcg_temp_free_i64(t0); |
2341 | 0f2f39c2 | aurel32 | tcg_temp_free_i32(t1); |
2342 | 7c58044c | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) { |
2343 | e1571908 | aurel32 | tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
|
2344 | 7c58044c | j_mayer | } |
2345 | 7c58044c | j_mayer | /* We can raise a differed exception */
|
2346 | af12906f | aurel32 | gen_helper_float_check_status(); |
2347 | 79aceca5 | bellard | } |
2348 | 79aceca5 | bellard | |
2349 | 76a66253 | j_mayer | /*** Addressing modes ***/
|
2350 | 76a66253 | j_mayer | /* Register indirect with immediate index : EA = (rA|0) + SIMM */
|
2351 | 76db3ba4 | aurel32 | static always_inline void gen_addr_imm_index (DisasContext *ctx, TCGv EA, target_long maskl) |
2352 | 76a66253 | j_mayer | { |
2353 | 76a66253 | j_mayer | target_long simm = SIMM(ctx->opcode); |
2354 | 76a66253 | j_mayer | |
2355 | be147d08 | j_mayer | simm &= ~maskl; |
2356 | 76db3ba4 | aurel32 | if (rA(ctx->opcode) == 0) { |
2357 | 76db3ba4 | aurel32 | #if defined(TARGET_PPC64)
|
2358 | 76db3ba4 | aurel32 | if (!ctx->sf_mode) {
|
2359 | 76db3ba4 | aurel32 | tcg_gen_movi_tl(EA, (uint32_t)simm); |
2360 | 76db3ba4 | aurel32 | } else
|
2361 | 76db3ba4 | aurel32 | #endif
|
2362 | e2be8d8d | aurel32 | tcg_gen_movi_tl(EA, simm); |
2363 | 76db3ba4 | aurel32 | } else if (likely(simm != 0)) { |
2364 | e2be8d8d | aurel32 | tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); |
2365 | 76db3ba4 | aurel32 | #if defined(TARGET_PPC64)
|
2366 | 76db3ba4 | aurel32 | if (!ctx->sf_mode) {
|
2367 | 76db3ba4 | aurel32 | tcg_gen_ext32u_tl(EA, EA); |
2368 | 76db3ba4 | aurel32 | } |
2369 | 76db3ba4 | aurel32 | #endif
|
2370 | 76db3ba4 | aurel32 | } else {
|
2371 | 76db3ba4 | aurel32 | #if defined(TARGET_PPC64)
|
2372 | 76db3ba4 | aurel32 | if (!ctx->sf_mode) {
|
2373 | 76db3ba4 | aurel32 | tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
2374 | 76db3ba4 | aurel32 | } else
|
2375 | 76db3ba4 | aurel32 | #endif
|
2376 | e2be8d8d | aurel32 | tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
2377 | 76db3ba4 | aurel32 | } |
2378 | 76a66253 | j_mayer | } |
2379 | 76a66253 | j_mayer | |
2380 | 76db3ba4 | aurel32 | static always_inline void gen_addr_reg_index (DisasContext *ctx, TCGv EA) |
2381 | 76a66253 | j_mayer | { |
2382 | 76db3ba4 | aurel32 | if (rA(ctx->opcode) == 0) { |
2383 | 76db3ba4 | aurel32 | #if defined(TARGET_PPC64)
|
2384 | 76db3ba4 | aurel32 | if (!ctx->sf_mode) {
|
2385 | 76db3ba4 | aurel32 | tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); |
2386 | 76db3ba4 | aurel32 | } else
|
2387 | 76db3ba4 | aurel32 | #endif
|
2388 | e2be8d8d | aurel32 | tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); |
2389 | 76db3ba4 | aurel32 | } else {
|
2390 | e2be8d8d | aurel32 | tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
2391 | 76db3ba4 | aurel32 | #if defined(TARGET_PPC64)
|
2392 | 76db3ba4 | aurel32 | if (!ctx->sf_mode) {
|
2393 | 76db3ba4 | aurel32 | tcg_gen_ext32u_tl(EA, EA); |
2394 | 76db3ba4 | aurel32 | } |
2395 | 76db3ba4 | aurel32 | #endif
|
2396 | 76db3ba4 | aurel32 | } |
2397 | 76a66253 | j_mayer | } |
2398 | 76a66253 | j_mayer | |
2399 | 76db3ba4 | aurel32 | static always_inline void gen_addr_register (DisasContext *ctx, TCGv EA) |
2400 | 76a66253 | j_mayer | { |
2401 | 76db3ba4 | aurel32 | if (rA(ctx->opcode) == 0) { |
2402 | e2be8d8d | aurel32 | tcg_gen_movi_tl(EA, 0);
|
2403 | 76db3ba4 | aurel32 | } else {
|
2404 | 76db3ba4 | aurel32 | #if defined(TARGET_PPC64)
|
2405 | 76db3ba4 | aurel32 | if (!ctx->sf_mode) {
|
2406 | 76db3ba4 | aurel32 | tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
2407 | 76db3ba4 | aurel32 | } else
|
2408 | 76db3ba4 | aurel32 | #endif
|
2409 | 76db3ba4 | aurel32 | tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
2410 | 76db3ba4 | aurel32 | } |
2411 | 76db3ba4 | aurel32 | } |
2412 | 76db3ba4 | aurel32 | |
2413 | 76db3ba4 | aurel32 | static always_inline void gen_addr_add (DisasContext *ctx, TCGv ret, TCGv arg1, target_long val) |
2414 | 76db3ba4 | aurel32 | { |
2415 | 76db3ba4 | aurel32 | tcg_gen_addi_tl(ret, arg1, val); |
2416 | 76db3ba4 | aurel32 | #if defined(TARGET_PPC64)
|
2417 | 76db3ba4 | aurel32 | if (!ctx->sf_mode) {
|
2418 | 76db3ba4 | aurel32 | tcg_gen_ext32u_tl(ret, ret); |
2419 | 76db3ba4 | aurel32 | } |
2420 | 76db3ba4 | aurel32 | #endif
|
2421 | 76a66253 | j_mayer | } |
2422 | 76a66253 | j_mayer | |
2423 | cf360a32 | aurel32 | static always_inline void gen_check_align (DisasContext *ctx, TCGv EA, int mask) |
2424 | cf360a32 | aurel32 | { |
2425 | cf360a32 | aurel32 | int l1 = gen_new_label();
|
2426 | cf360a32 | aurel32 | TCGv t0 = tcg_temp_new(); |
2427 | cf360a32 | aurel32 | TCGv_i32 t1, t2; |
2428 | cf360a32 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
2429 | cf360a32 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
2430 | cf360a32 | aurel32 | tcg_gen_andi_tl(t0, EA, mask); |
2431 | cf360a32 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
|
2432 | cf360a32 | aurel32 | t1 = tcg_const_i32(POWERPC_EXCP_ALIGN); |
2433 | cf360a32 | aurel32 | t2 = tcg_const_i32(0);
|
2434 | cf360a32 | aurel32 | gen_helper_raise_exception_err(t1, t2); |
2435 | cf360a32 | aurel32 | tcg_temp_free_i32(t1); |
2436 | cf360a32 | aurel32 | tcg_temp_free_i32(t2); |
2437 | cf360a32 | aurel32 | gen_set_label(l1); |
2438 | cf360a32 | aurel32 | tcg_temp_free(t0); |
2439 | cf360a32 | aurel32 | } |
2440 | cf360a32 | aurel32 | |
2441 | 7863667f | j_mayer | /*** Integer load ***/
|
2442 | 76db3ba4 | aurel32 | static always_inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2) |
2443 | 76db3ba4 | aurel32 | { |
2444 | 76db3ba4 | aurel32 | tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx); |
2445 | 76db3ba4 | aurel32 | } |
2446 | 76db3ba4 | aurel32 | |
2447 | 76db3ba4 | aurel32 | static always_inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2) |
2448 | 76db3ba4 | aurel32 | { |
2449 | 76db3ba4 | aurel32 | tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx); |
2450 | 76db3ba4 | aurel32 | } |
2451 | 76db3ba4 | aurel32 | |
2452 | 76db3ba4 | aurel32 | static always_inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2) |
2453 | 76db3ba4 | aurel32 | { |
2454 | 76db3ba4 | aurel32 | tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx); |
2455 | 76db3ba4 | aurel32 | if (unlikely(ctx->le_mode)) {
|
2456 | fa3966a3 | aurel32 | tcg_gen_bswap16_tl(arg1, arg1); |
2457 | 76db3ba4 | aurel32 | } |
2458 | b61f2753 | aurel32 | } |
2459 | b61f2753 | aurel32 | |
2460 | 76db3ba4 | aurel32 | static always_inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2) |
2461 | b61f2753 | aurel32 | { |
2462 | 76db3ba4 | aurel32 | if (unlikely(ctx->le_mode)) {
|
2463 | 76db3ba4 | aurel32 | tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx); |
2464 | fa3966a3 | aurel32 | tcg_gen_bswap16_tl(arg1, arg1); |
2465 | 76db3ba4 | aurel32 | tcg_gen_ext16s_tl(arg1, arg1); |
2466 | 76db3ba4 | aurel32 | } else {
|
2467 | 76db3ba4 | aurel32 | tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx); |
2468 | 76db3ba4 | aurel32 | } |
2469 | b61f2753 | aurel32 | } |
2470 | b61f2753 | aurel32 | |
2471 | 76db3ba4 | aurel32 | static always_inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2) |
2472 | b61f2753 | aurel32 | { |
2473 | 76db3ba4 | aurel32 | tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx); |
2474 | 76db3ba4 | aurel32 | if (unlikely(ctx->le_mode)) {
|
2475 | fa3966a3 | aurel32 | tcg_gen_bswap32_tl(arg1, arg1); |
2476 | 76db3ba4 | aurel32 | } |
2477 | b61f2753 | aurel32 | } |
2478 | b61f2753 | aurel32 | |
2479 | 76db3ba4 | aurel32 | #if defined(TARGET_PPC64)
|
2480 | 76db3ba4 | aurel32 | static always_inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2) |
2481 | b61f2753 | aurel32 | { |
2482 | a457e7ee | blueswir1 | if (unlikely(ctx->le_mode)) {
|
2483 | 76db3ba4 | aurel32 | tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx); |
2484 | fa3966a3 | aurel32 | tcg_gen_bswap32_tl(arg1, arg1); |
2485 | fa3966a3 | aurel32 | tcg_gen_ext32s_tl(arg1, arg1); |
2486 | b61f2753 | aurel32 | } else
|
2487 | 76db3ba4 | aurel32 | tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx); |
2488 | b61f2753 | aurel32 | } |
2489 | 76db3ba4 | aurel32 | #endif
|
2490 | b61f2753 | aurel32 | |
2491 | 76db3ba4 | aurel32 | static always_inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
2492 | b61f2753 | aurel32 | { |
2493 | 76db3ba4 | aurel32 | tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx); |
2494 | 76db3ba4 | aurel32 | if (unlikely(ctx->le_mode)) {
|
2495 | 66896cb8 | aurel32 | tcg_gen_bswap64_i64(arg1, arg1); |
2496 | 76db3ba4 | aurel32 | } |
2497 | b61f2753 | aurel32 | } |
2498 | b61f2753 | aurel32 | |
2499 | 76db3ba4 | aurel32 | static always_inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2) |
2500 | b61f2753 | aurel32 | { |
2501 | 76db3ba4 | aurel32 | tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx); |
2502 | b61f2753 | aurel32 | } |
2503 | b61f2753 | aurel32 | |
2504 | 76db3ba4 | aurel32 | static always_inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2) |
2505 | b61f2753 | aurel32 | { |
2506 | 76db3ba4 | aurel32 | if (unlikely(ctx->le_mode)) {
|
2507 | 76db3ba4 | aurel32 | TCGv t0 = tcg_temp_new(); |
2508 | 76db3ba4 | aurel32 | tcg_gen_ext16u_tl(t0, arg1); |
2509 | fa3966a3 | aurel32 | tcg_gen_bswap16_tl(t0, t0); |
2510 | 76db3ba4 | aurel32 | tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx); |
2511 | 76db3ba4 | aurel32 | tcg_temp_free(t0); |
2512 | 76db3ba4 | aurel32 | } else {
|
2513 | 76db3ba4 | aurel32 | tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx); |
2514 | 76db3ba4 | aurel32 | } |
2515 | b61f2753 | aurel32 | } |
2516 | b61f2753 | aurel32 | |
2517 | 76db3ba4 | aurel32 | static always_inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2) |
2518 | b61f2753 | aurel32 | { |
2519 | 76db3ba4 | aurel32 | if (unlikely(ctx->le_mode)) {
|
2520 | fa3966a3 | aurel32 | TCGv t0 = tcg_temp_new(); |
2521 | fa3966a3 | aurel32 | tcg_gen_ext32u_tl(t0, arg1); |
2522 | fa3966a3 | aurel32 | tcg_gen_bswap32_tl(t0, t0); |
2523 | 76db3ba4 | aurel32 | tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx); |
2524 | 76db3ba4 | aurel32 | tcg_temp_free(t0); |
2525 | 76db3ba4 | aurel32 | } else {
|
2526 | 76db3ba4 | aurel32 | tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx); |
2527 | 76db3ba4 | aurel32 | } |
2528 | b61f2753 | aurel32 | } |
2529 | b61f2753 | aurel32 | |
2530 | 76db3ba4 | aurel32 | static always_inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
2531 | b61f2753 | aurel32 | { |
2532 | 76db3ba4 | aurel32 | if (unlikely(ctx->le_mode)) {
|
2533 | a7812ae4 | pbrook | TCGv_i64 t0 = tcg_temp_new_i64(); |
2534 | 66896cb8 | aurel32 | tcg_gen_bswap64_i64(t0, arg1); |
2535 | 76db3ba4 | aurel32 | tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx); |
2536 | a7812ae4 | pbrook | tcg_temp_free_i64(t0); |
2537 | b61f2753 | aurel32 | } else
|
2538 | 76db3ba4 | aurel32 | tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx); |
2539 | b61f2753 | aurel32 | } |
2540 | b61f2753 | aurel32 | |
2541 | 0c8aacd4 | aurel32 | #define GEN_LD(name, ldop, opc, type) \
|
2542 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
2543 | 79aceca5 | bellard | { \ |
2544 | 76db3ba4 | aurel32 | TCGv EA; \ |
2545 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); \ |
2546 | 76db3ba4 | aurel32 | EA = tcg_temp_new(); \ |
2547 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, EA, 0); \
|
2548 | 76db3ba4 | aurel32 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ |
2549 | b61f2753 | aurel32 | tcg_temp_free(EA); \ |
2550 | 79aceca5 | bellard | } |
2551 | 79aceca5 | bellard | |
2552 | 0c8aacd4 | aurel32 | #define GEN_LDU(name, ldop, opc, type) \
|
2553 | 99e300ef | Blue Swirl | static void glue(gen_, name##u)(DisasContext *ctx) \ |
2554 | 79aceca5 | bellard | { \ |
2555 | b61f2753 | aurel32 | TCGv EA; \ |
2556 | 76a66253 | j_mayer | if (unlikely(rA(ctx->opcode) == 0 || \ |
2557 | 76a66253 | j_mayer | rA(ctx->opcode) == rD(ctx->opcode))) { \ |
2558 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
2559 | 9fddaa0c | bellard | return; \
|
2560 | 9a64fbe4 | bellard | } \ |
2561 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); \ |
2562 | 0c8aacd4 | aurel32 | EA = tcg_temp_new(); \ |
2563 | 9d53c753 | j_mayer | if (type == PPC_64B) \
|
2564 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, EA, 0x03); \
|
2565 | 9d53c753 | j_mayer | else \
|
2566 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, EA, 0); \
|
2567 | 76db3ba4 | aurel32 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ |
2568 | b61f2753 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2569 | b61f2753 | aurel32 | tcg_temp_free(EA); \ |
2570 | 79aceca5 | bellard | } |
2571 | 79aceca5 | bellard | |
2572 | 0c8aacd4 | aurel32 | #define GEN_LDUX(name, ldop, opc2, opc3, type) \
|
2573 | 99e300ef | Blue Swirl | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
2574 | 79aceca5 | bellard | { \ |
2575 | b61f2753 | aurel32 | TCGv EA; \ |
2576 | 76a66253 | j_mayer | if (unlikely(rA(ctx->opcode) == 0 || \ |
2577 | 76a66253 | j_mayer | rA(ctx->opcode) == rD(ctx->opcode))) { \ |
2578 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
2579 | 9fddaa0c | bellard | return; \
|
2580 | 9a64fbe4 | bellard | } \ |
2581 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); \ |
2582 | 0c8aacd4 | aurel32 | EA = tcg_temp_new(); \ |
2583 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, EA); \ |
2584 | 76db3ba4 | aurel32 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ |
2585 | b61f2753 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2586 | b61f2753 | aurel32 | tcg_temp_free(EA); \ |
2587 | 79aceca5 | bellard | } |
2588 | 79aceca5 | bellard | |
2589 | 0c8aacd4 | aurel32 | #define GEN_LDX(name, ldop, opc2, opc3, type) \
|
2590 | 99e300ef | Blue Swirl | static void glue(gen_, name##x)(DisasContext *ctx) \ |
2591 | 79aceca5 | bellard | { \ |
2592 | 76db3ba4 | aurel32 | TCGv EA; \ |
2593 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); \ |
2594 | 76db3ba4 | aurel32 | EA = tcg_temp_new(); \ |
2595 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, EA); \ |
2596 | 76db3ba4 | aurel32 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ |
2597 | b61f2753 | aurel32 | tcg_temp_free(EA); \ |
2598 | 79aceca5 | bellard | } |
2599 | 79aceca5 | bellard | |
2600 | 0c8aacd4 | aurel32 | #define GEN_LDS(name, ldop, op, type) \
|
2601 | 0c8aacd4 | aurel32 | GEN_LD(name, ldop, op | 0x20, type); \
|
2602 | 0c8aacd4 | aurel32 | GEN_LDU(name, ldop, op | 0x21, type); \
|
2603 | 0c8aacd4 | aurel32 | GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \ |
2604 | 0c8aacd4 | aurel32 | GEN_LDX(name, ldop, 0x17, op | 0x00, type) |
2605 | 79aceca5 | bellard | |
2606 | 79aceca5 | bellard | /* lbz lbzu lbzux lbzx */
|
2607 | 0c8aacd4 | aurel32 | GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
|
2608 | 79aceca5 | bellard | /* lha lhau lhaux lhax */
|
2609 | 0c8aacd4 | aurel32 | GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
|
2610 | 79aceca5 | bellard | /* lhz lhzu lhzux lhzx */
|
2611 | 0c8aacd4 | aurel32 | GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
|
2612 | 79aceca5 | bellard | /* lwz lwzu lwzux lwzx */
|
2613 | 0c8aacd4 | aurel32 | GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
|
2614 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
2615 | d9bce9d9 | j_mayer | /* lwaux */
|
2616 | 0c8aacd4 | aurel32 | GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B); |
2617 | d9bce9d9 | j_mayer | /* lwax */
|
2618 | 0c8aacd4 | aurel32 | GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B); |
2619 | d9bce9d9 | j_mayer | /* ldux */
|
2620 | 0c8aacd4 | aurel32 | GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B); |
2621 | d9bce9d9 | j_mayer | /* ldx */
|
2622 | 0c8aacd4 | aurel32 | GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B); |
2623 | 99e300ef | Blue Swirl | |
2624 | 99e300ef | Blue Swirl | static void gen_ld(DisasContext *ctx) |
2625 | d9bce9d9 | j_mayer | { |
2626 | b61f2753 | aurel32 | TCGv EA; |
2627 | d9bce9d9 | j_mayer | if (Rc(ctx->opcode)) {
|
2628 | d9bce9d9 | j_mayer | if (unlikely(rA(ctx->opcode) == 0 || |
2629 | d9bce9d9 | j_mayer | rA(ctx->opcode) == rD(ctx->opcode))) { |
2630 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
2631 | d9bce9d9 | j_mayer | return;
|
2632 | d9bce9d9 | j_mayer | } |
2633 | d9bce9d9 | j_mayer | } |
2634 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); |
2635 | a7812ae4 | pbrook | EA = tcg_temp_new(); |
2636 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, EA, 0x03);
|
2637 | d9bce9d9 | j_mayer | if (ctx->opcode & 0x02) { |
2638 | d9bce9d9 | j_mayer | /* lwa (lwau is undefined) */
|
2639 | 76db3ba4 | aurel32 | gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA); |
2640 | d9bce9d9 | j_mayer | } else {
|
2641 | d9bce9d9 | j_mayer | /* ld - ldu */
|
2642 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA); |
2643 | d9bce9d9 | j_mayer | } |
2644 | d9bce9d9 | j_mayer | if (Rc(ctx->opcode))
|
2645 | b61f2753 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); |
2646 | b61f2753 | aurel32 | tcg_temp_free(EA); |
2647 | d9bce9d9 | j_mayer | } |
2648 | 99e300ef | Blue Swirl | |
2649 | 54623277 | Blue Swirl | /* lq */
|
2650 | 99e300ef | Blue Swirl | static void gen_lq(DisasContext *ctx) |
2651 | be147d08 | j_mayer | { |
2652 | be147d08 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
2653 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
2654 | be147d08 | j_mayer | #else
|
2655 | be147d08 | j_mayer | int ra, rd;
|
2656 | b61f2753 | aurel32 | TCGv EA; |
2657 | be147d08 | j_mayer | |
2658 | be147d08 | j_mayer | /* Restore CPU state */
|
2659 | 76db3ba4 | aurel32 | if (unlikely(ctx->mem_idx == 0)) { |
2660 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
2661 | be147d08 | j_mayer | return;
|
2662 | be147d08 | j_mayer | } |
2663 | be147d08 | j_mayer | ra = rA(ctx->opcode); |
2664 | be147d08 | j_mayer | rd = rD(ctx->opcode); |
2665 | be147d08 | j_mayer | if (unlikely((rd & 1) || rd == ra)) { |
2666 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
2667 | be147d08 | j_mayer | return;
|
2668 | be147d08 | j_mayer | } |
2669 | 76db3ba4 | aurel32 | if (unlikely(ctx->le_mode)) {
|
2670 | be147d08 | j_mayer | /* Little-endian mode is not handled */
|
2671 | e06fcd75 | aurel32 | gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE); |
2672 | be147d08 | j_mayer | return;
|
2673 | be147d08 | j_mayer | } |
2674 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); |
2675 | a7812ae4 | pbrook | EA = tcg_temp_new(); |
2676 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, EA, 0x0F);
|
2677 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_gpr[rd], EA); |
2678 | 76db3ba4 | aurel32 | gen_addr_add(ctx, EA, EA, 8);
|
2679 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
|
2680 | b61f2753 | aurel32 | tcg_temp_free(EA); |
2681 | be147d08 | j_mayer | #endif
|
2682 | be147d08 | j_mayer | } |
2683 | d9bce9d9 | j_mayer | #endif
|
2684 | 79aceca5 | bellard | |
2685 | 79aceca5 | bellard | /*** Integer store ***/
|
2686 | 0c8aacd4 | aurel32 | #define GEN_ST(name, stop, opc, type) \
|
2687 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
2688 | 79aceca5 | bellard | { \ |
2689 | 76db3ba4 | aurel32 | TCGv EA; \ |
2690 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); \ |
2691 | 76db3ba4 | aurel32 | EA = tcg_temp_new(); \ |
2692 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, EA, 0); \
|
2693 | 76db3ba4 | aurel32 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ |
2694 | b61f2753 | aurel32 | tcg_temp_free(EA); \ |
2695 | 79aceca5 | bellard | } |
2696 | 79aceca5 | bellard | |
2697 | 0c8aacd4 | aurel32 | #define GEN_STU(name, stop, opc, type) \
|
2698 | 99e300ef | Blue Swirl | static void glue(gen_, stop##u)(DisasContext *ctx) \ |
2699 | 79aceca5 | bellard | { \ |
2700 | b61f2753 | aurel32 | TCGv EA; \ |
2701 | 76a66253 | j_mayer | if (unlikely(rA(ctx->opcode) == 0)) { \ |
2702 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
2703 | 9fddaa0c | bellard | return; \
|
2704 | 9a64fbe4 | bellard | } \ |
2705 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); \ |
2706 | 0c8aacd4 | aurel32 | EA = tcg_temp_new(); \ |
2707 | 9d53c753 | j_mayer | if (type == PPC_64B) \
|
2708 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, EA, 0x03); \
|
2709 | 9d53c753 | j_mayer | else \
|
2710 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, EA, 0); \
|
2711 | 76db3ba4 | aurel32 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ |
2712 | b61f2753 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2713 | b61f2753 | aurel32 | tcg_temp_free(EA); \ |
2714 | 79aceca5 | bellard | } |
2715 | 79aceca5 | bellard | |
2716 | 0c8aacd4 | aurel32 | #define GEN_STUX(name, stop, opc2, opc3, type) \
|
2717 | 99e300ef | Blue Swirl | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
2718 | 79aceca5 | bellard | { \ |
2719 | b61f2753 | aurel32 | TCGv EA; \ |
2720 | 76a66253 | j_mayer | if (unlikely(rA(ctx->opcode) == 0)) { \ |
2721 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
2722 | 9fddaa0c | bellard | return; \
|
2723 | 9a64fbe4 | bellard | } \ |
2724 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); \ |
2725 | 0c8aacd4 | aurel32 | EA = tcg_temp_new(); \ |
2726 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, EA); \ |
2727 | 76db3ba4 | aurel32 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ |
2728 | b61f2753 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2729 | b61f2753 | aurel32 | tcg_temp_free(EA); \ |
2730 | 79aceca5 | bellard | } |
2731 | 79aceca5 | bellard | |
2732 | 0c8aacd4 | aurel32 | #define GEN_STX(name, stop, opc2, opc3, type) \
|
2733 | 99e300ef | Blue Swirl | static void glue(gen_, name##x)(DisasContext *ctx) \ |
2734 | 79aceca5 | bellard | { \ |
2735 | 76db3ba4 | aurel32 | TCGv EA; \ |
2736 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); \ |
2737 | 76db3ba4 | aurel32 | EA = tcg_temp_new(); \ |
2738 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, EA); \ |
2739 | 76db3ba4 | aurel32 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ |
2740 | b61f2753 | aurel32 | tcg_temp_free(EA); \ |
2741 | 79aceca5 | bellard | } |
2742 | 79aceca5 | bellard | |
2743 | 0c8aacd4 | aurel32 | #define GEN_STS(name, stop, op, type) \
|
2744 | 0c8aacd4 | aurel32 | GEN_ST(name, stop, op | 0x20, type); \
|
2745 | 0c8aacd4 | aurel32 | GEN_STU(name, stop, op | 0x21, type); \
|
2746 | 0c8aacd4 | aurel32 | GEN_STUX(name, stop, 0x17, op | 0x01, type); \ |
2747 | 0c8aacd4 | aurel32 | GEN_STX(name, stop, 0x17, op | 0x00, type) |
2748 | 79aceca5 | bellard | |
2749 | 79aceca5 | bellard | /* stb stbu stbux stbx */
|
2750 | 0c8aacd4 | aurel32 | GEN_STS(stb, st8, 0x06, PPC_INTEGER);
|
2751 | 79aceca5 | bellard | /* sth sthu sthux sthx */
|
2752 | 0c8aacd4 | aurel32 | GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
|
2753 | 79aceca5 | bellard | /* stw stwu stwux stwx */
|
2754 | 0c8aacd4 | aurel32 | GEN_STS(stw, st32, 0x04, PPC_INTEGER);
|
2755 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
2756 | 0c8aacd4 | aurel32 | GEN_STUX(std, st64, 0x15, 0x05, PPC_64B); |
2757 | 0c8aacd4 | aurel32 | GEN_STX(std, st64, 0x15, 0x04, PPC_64B); |
2758 | 99e300ef | Blue Swirl | |
2759 | 99e300ef | Blue Swirl | static void gen_std(DisasContext *ctx) |
2760 | d9bce9d9 | j_mayer | { |
2761 | be147d08 | j_mayer | int rs;
|
2762 | b61f2753 | aurel32 | TCGv EA; |
2763 | be147d08 | j_mayer | |
2764 | be147d08 | j_mayer | rs = rS(ctx->opcode); |
2765 | be147d08 | j_mayer | if ((ctx->opcode & 0x3) == 0x2) { |
2766 | be147d08 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
2767 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
2768 | be147d08 | j_mayer | #else
|
2769 | be147d08 | j_mayer | /* stq */
|
2770 | 76db3ba4 | aurel32 | if (unlikely(ctx->mem_idx == 0)) { |
2771 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
2772 | be147d08 | j_mayer | return;
|
2773 | be147d08 | j_mayer | } |
2774 | be147d08 | j_mayer | if (unlikely(rs & 1)) { |
2775 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
2776 | d9bce9d9 | j_mayer | return;
|
2777 | d9bce9d9 | j_mayer | } |
2778 | 76db3ba4 | aurel32 | if (unlikely(ctx->le_mode)) {
|
2779 | be147d08 | j_mayer | /* Little-endian mode is not handled */
|
2780 | e06fcd75 | aurel32 | gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE); |
2781 | be147d08 | j_mayer | return;
|
2782 | be147d08 | j_mayer | } |
2783 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); |
2784 | a7812ae4 | pbrook | EA = tcg_temp_new(); |
2785 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, EA, 0x03);
|
2786 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_gpr[rs], EA); |
2787 | 76db3ba4 | aurel32 | gen_addr_add(ctx, EA, EA, 8);
|
2788 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
|
2789 | b61f2753 | aurel32 | tcg_temp_free(EA); |
2790 | be147d08 | j_mayer | #endif
|
2791 | be147d08 | j_mayer | } else {
|
2792 | be147d08 | j_mayer | /* std / stdu */
|
2793 | be147d08 | j_mayer | if (Rc(ctx->opcode)) {
|
2794 | be147d08 | j_mayer | if (unlikely(rA(ctx->opcode) == 0)) { |
2795 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
2796 | be147d08 | j_mayer | return;
|
2797 | be147d08 | j_mayer | } |
2798 | be147d08 | j_mayer | } |
2799 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); |
2800 | a7812ae4 | pbrook | EA = tcg_temp_new(); |
2801 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, EA, 0x03);
|
2802 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_gpr[rs], EA); |
2803 | be147d08 | j_mayer | if (Rc(ctx->opcode))
|
2804 | b61f2753 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); |
2805 | b61f2753 | aurel32 | tcg_temp_free(EA); |
2806 | d9bce9d9 | j_mayer | } |
2807 | d9bce9d9 | j_mayer | } |
2808 | d9bce9d9 | j_mayer | #endif
|
2809 | 79aceca5 | bellard | /*** Integer load and store with byte reverse ***/
|
2810 | 79aceca5 | bellard | /* lhbrx */
|
2811 | 76db3ba4 | aurel32 | static void always_inline gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2) |
2812 | b61f2753 | aurel32 | { |
2813 | 76db3ba4 | aurel32 | tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx); |
2814 | 76db3ba4 | aurel32 | if (likely(!ctx->le_mode)) {
|
2815 | fa3966a3 | aurel32 | tcg_gen_bswap16_tl(arg1, arg1); |
2816 | 76db3ba4 | aurel32 | } |
2817 | b61f2753 | aurel32 | } |
2818 | 0c8aacd4 | aurel32 | GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); |
2819 | b61f2753 | aurel32 | |
2820 | 79aceca5 | bellard | /* lwbrx */
|
2821 | 76db3ba4 | aurel32 | static void always_inline gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2) |
2822 | b61f2753 | aurel32 | { |
2823 | 76db3ba4 | aurel32 | tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx); |
2824 | 76db3ba4 | aurel32 | if (likely(!ctx->le_mode)) {
|
2825 | fa3966a3 | aurel32 | tcg_gen_bswap32_tl(arg1, arg1); |
2826 | 76db3ba4 | aurel32 | } |
2827 | b61f2753 | aurel32 | } |
2828 | 0c8aacd4 | aurel32 | GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); |
2829 | b61f2753 | aurel32 | |
2830 | 79aceca5 | bellard | /* sthbrx */
|
2831 | 76db3ba4 | aurel32 | static void always_inline gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2) |
2832 | b61f2753 | aurel32 | { |
2833 | 76db3ba4 | aurel32 | if (likely(!ctx->le_mode)) {
|
2834 | 76db3ba4 | aurel32 | TCGv t0 = tcg_temp_new(); |
2835 | 76db3ba4 | aurel32 | tcg_gen_ext16u_tl(t0, arg1); |
2836 | fa3966a3 | aurel32 | tcg_gen_bswap16_tl(t0, t0); |
2837 | 76db3ba4 | aurel32 | tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx); |
2838 | 76db3ba4 | aurel32 | tcg_temp_free(t0); |
2839 | 76db3ba4 | aurel32 | } else {
|
2840 | 76db3ba4 | aurel32 | tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx); |
2841 | 76db3ba4 | aurel32 | } |
2842 | b61f2753 | aurel32 | } |
2843 | 0c8aacd4 | aurel32 | GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); |
2844 | b61f2753 | aurel32 | |
2845 | 79aceca5 | bellard | /* stwbrx */
|
2846 | 76db3ba4 | aurel32 | static void always_inline gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2) |
2847 | b61f2753 | aurel32 | { |
2848 | 76db3ba4 | aurel32 | if (likely(!ctx->le_mode)) {
|
2849 | fa3966a3 | aurel32 | TCGv t0 = tcg_temp_new(); |
2850 | fa3966a3 | aurel32 | tcg_gen_ext32u_tl(t0, arg1); |
2851 | fa3966a3 | aurel32 | tcg_gen_bswap32_tl(t0, t0); |
2852 | 76db3ba4 | aurel32 | tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx); |
2853 | 76db3ba4 | aurel32 | tcg_temp_free(t0); |
2854 | 76db3ba4 | aurel32 | } else {
|
2855 | 76db3ba4 | aurel32 | tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx); |
2856 | 76db3ba4 | aurel32 | } |
2857 | b61f2753 | aurel32 | } |
2858 | 0c8aacd4 | aurel32 | GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); |
2859 | 79aceca5 | bellard | |
2860 | 79aceca5 | bellard | /*** Integer load and store multiple ***/
|
2861 | 99e300ef | Blue Swirl | |
2862 | 54623277 | Blue Swirl | /* lmw */
|
2863 | 99e300ef | Blue Swirl | static void gen_lmw(DisasContext *ctx) |
2864 | 79aceca5 | bellard | { |
2865 | 76db3ba4 | aurel32 | TCGv t0; |
2866 | 76db3ba4 | aurel32 | TCGv_i32 t1; |
2867 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); |
2868 | 76a66253 | j_mayer | /* NIP cannot be restored if the memory exception comes from an helper */
|
2869 | d9bce9d9 | j_mayer | gen_update_nip(ctx, ctx->nip - 4);
|
2870 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
2871 | 76db3ba4 | aurel32 | t1 = tcg_const_i32(rD(ctx->opcode)); |
2872 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, t0, 0);
|
2873 | ff4a62cd | aurel32 | gen_helper_lmw(t0, t1); |
2874 | ff4a62cd | aurel32 | tcg_temp_free(t0); |
2875 | ff4a62cd | aurel32 | tcg_temp_free_i32(t1); |
2876 | 79aceca5 | bellard | } |
2877 | 79aceca5 | bellard | |
2878 | 79aceca5 | bellard | /* stmw */
|
2879 | 99e300ef | Blue Swirl | static void gen_stmw(DisasContext *ctx) |
2880 | 79aceca5 | bellard | { |
2881 | 76db3ba4 | aurel32 | TCGv t0; |
2882 | 76db3ba4 | aurel32 | TCGv_i32 t1; |
2883 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); |
2884 | 76a66253 | j_mayer | /* NIP cannot be restored if the memory exception comes from an helper */
|
2885 | d9bce9d9 | j_mayer | gen_update_nip(ctx, ctx->nip - 4);
|
2886 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
2887 | 76db3ba4 | aurel32 | t1 = tcg_const_i32(rS(ctx->opcode)); |
2888 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, t0, 0);
|
2889 | ff4a62cd | aurel32 | gen_helper_stmw(t0, t1); |
2890 | ff4a62cd | aurel32 | tcg_temp_free(t0); |
2891 | ff4a62cd | aurel32 | tcg_temp_free_i32(t1); |
2892 | 79aceca5 | bellard | } |
2893 | 79aceca5 | bellard | |
2894 | 79aceca5 | bellard | /*** Integer load and store strings ***/
|
2895 | 54623277 | Blue Swirl | |
2896 | 79aceca5 | bellard | /* lswi */
|
2897 | 3fc6c082 | bellard | /* PowerPC32 specification says we must generate an exception if
|
2898 | 9a64fbe4 | bellard | * rA is in the range of registers to be loaded.
|
2899 | 9a64fbe4 | bellard | * In an other hand, IBM says this is valid, but rA won't be loaded.
|
2900 | 9a64fbe4 | bellard | * For now, I'll follow the spec...
|
2901 | 9a64fbe4 | bellard | */
|
2902 | 99e300ef | Blue Swirl | static void gen_lswi(DisasContext *ctx) |
2903 | 79aceca5 | bellard | { |
2904 | dfbc799d | aurel32 | TCGv t0; |
2905 | dfbc799d | aurel32 | TCGv_i32 t1, t2; |
2906 | 79aceca5 | bellard | int nb = NB(ctx->opcode);
|
2907 | 79aceca5 | bellard | int start = rD(ctx->opcode);
|
2908 | 9a64fbe4 | bellard | int ra = rA(ctx->opcode);
|
2909 | 79aceca5 | bellard | int nr;
|
2910 | 79aceca5 | bellard | |
2911 | 79aceca5 | bellard | if (nb == 0) |
2912 | 79aceca5 | bellard | nb = 32;
|
2913 | 79aceca5 | bellard | nr = nb / 4;
|
2914 | 76a66253 | j_mayer | if (unlikely(((start + nr) > 32 && |
2915 | 76a66253 | j_mayer | start <= ra && (start + nr - 32) > ra) ||
|
2916 | 76a66253 | j_mayer | ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
|
2917 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); |
2918 | 9fddaa0c | bellard | return;
|
2919 | 297d8e62 | bellard | } |
2920 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); |
2921 | 8dd4983c | bellard | /* NIP cannot be restored if the memory exception comes from an helper */
|
2922 | d9bce9d9 | j_mayer | gen_update_nip(ctx, ctx->nip - 4);
|
2923 | dfbc799d | aurel32 | t0 = tcg_temp_new(); |
2924 | 76db3ba4 | aurel32 | gen_addr_register(ctx, t0); |
2925 | dfbc799d | aurel32 | t1 = tcg_const_i32(nb); |
2926 | dfbc799d | aurel32 | t2 = tcg_const_i32(start); |
2927 | dfbc799d | aurel32 | gen_helper_lsw(t0, t1, t2); |
2928 | dfbc799d | aurel32 | tcg_temp_free(t0); |
2929 | dfbc799d | aurel32 | tcg_temp_free_i32(t1); |
2930 | dfbc799d | aurel32 | tcg_temp_free_i32(t2); |
2931 | 79aceca5 | bellard | } |
2932 | 79aceca5 | bellard | |
2933 | 79aceca5 | bellard | /* lswx */
|
2934 | 99e300ef | Blue Swirl | static void gen_lswx(DisasContext *ctx) |
2935 | 79aceca5 | bellard | { |
2936 | 76db3ba4 | aurel32 | TCGv t0; |
2937 | 76db3ba4 | aurel32 | TCGv_i32 t1, t2, t3; |
2938 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); |
2939 | 76a66253 | j_mayer | /* NIP cannot be restored if the memory exception comes from an helper */
|
2940 | d9bce9d9 | j_mayer | gen_update_nip(ctx, ctx->nip - 4);
|
2941 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
2942 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
2943 | 76db3ba4 | aurel32 | t1 = tcg_const_i32(rD(ctx->opcode)); |
2944 | 76db3ba4 | aurel32 | t2 = tcg_const_i32(rA(ctx->opcode)); |
2945 | 76db3ba4 | aurel32 | t3 = tcg_const_i32(rB(ctx->opcode)); |
2946 | dfbc799d | aurel32 | gen_helper_lswx(t0, t1, t2, t3); |
2947 | dfbc799d | aurel32 | tcg_temp_free(t0); |
2948 | dfbc799d | aurel32 | tcg_temp_free_i32(t1); |
2949 | dfbc799d | aurel32 | tcg_temp_free_i32(t2); |
2950 | dfbc799d | aurel32 | tcg_temp_free_i32(t3); |
2951 | 79aceca5 | bellard | } |
2952 | 79aceca5 | bellard | |
2953 | 79aceca5 | bellard | /* stswi */
|
2954 | 99e300ef | Blue Swirl | static void gen_stswi(DisasContext *ctx) |
2955 | 79aceca5 | bellard | { |
2956 | 76db3ba4 | aurel32 | TCGv t0; |
2957 | 76db3ba4 | aurel32 | TCGv_i32 t1, t2; |
2958 | 4b3686fa | bellard | int nb = NB(ctx->opcode);
|
2959 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); |
2960 | 76a66253 | j_mayer | /* NIP cannot be restored if the memory exception comes from an helper */
|
2961 | d9bce9d9 | j_mayer | gen_update_nip(ctx, ctx->nip - 4);
|
2962 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
2963 | 76db3ba4 | aurel32 | gen_addr_register(ctx, t0); |
2964 | 4b3686fa | bellard | if (nb == 0) |
2965 | 4b3686fa | bellard | nb = 32;
|
2966 | dfbc799d | aurel32 | t1 = tcg_const_i32(nb); |
2967 | 76db3ba4 | aurel32 | t2 = tcg_const_i32(rS(ctx->opcode)); |
2968 | dfbc799d | aurel32 | gen_helper_stsw(t0, t1, t2); |
2969 | dfbc799d | aurel32 | tcg_temp_free(t0); |
2970 | dfbc799d | aurel32 | tcg_temp_free_i32(t1); |
2971 | dfbc799d | aurel32 | tcg_temp_free_i32(t2); |
2972 | 79aceca5 | bellard | } |
2973 | 79aceca5 | bellard | |
2974 | 79aceca5 | bellard | /* stswx */
|
2975 | 99e300ef | Blue Swirl | static void gen_stswx(DisasContext *ctx) |
2976 | 79aceca5 | bellard | { |
2977 | 76db3ba4 | aurel32 | TCGv t0; |
2978 | 76db3ba4 | aurel32 | TCGv_i32 t1, t2; |
2979 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); |
2980 | 8dd4983c | bellard | /* NIP cannot be restored if the memory exception comes from an helper */
|
2981 | 5fafdf24 | ths | gen_update_nip(ctx, ctx->nip - 4);
|
2982 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
2983 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
2984 | 76db3ba4 | aurel32 | t1 = tcg_temp_new_i32(); |
2985 | dfbc799d | aurel32 | tcg_gen_trunc_tl_i32(t1, cpu_xer); |
2986 | dfbc799d | aurel32 | tcg_gen_andi_i32(t1, t1, 0x7F);
|
2987 | 76db3ba4 | aurel32 | t2 = tcg_const_i32(rS(ctx->opcode)); |
2988 | dfbc799d | aurel32 | gen_helper_stsw(t0, t1, t2); |
2989 | dfbc799d | aurel32 | tcg_temp_free(t0); |
2990 | dfbc799d | aurel32 | tcg_temp_free_i32(t1); |
2991 | dfbc799d | aurel32 | tcg_temp_free_i32(t2); |
2992 | 79aceca5 | bellard | } |
2993 | 79aceca5 | bellard | |
2994 | 79aceca5 | bellard | /*** Memory synchronisation ***/
|
2995 | 79aceca5 | bellard | /* eieio */
|
2996 | 99e300ef | Blue Swirl | static void gen_eieio(DisasContext *ctx) |
2997 | 79aceca5 | bellard | { |
2998 | 79aceca5 | bellard | } |
2999 | 79aceca5 | bellard | |
3000 | 79aceca5 | bellard | /* isync */
|
3001 | 99e300ef | Blue Swirl | static void gen_isync(DisasContext *ctx) |
3002 | 79aceca5 | bellard | { |
3003 | e06fcd75 | aurel32 | gen_stop_exception(ctx); |
3004 | 79aceca5 | bellard | } |
3005 | 79aceca5 | bellard | |
3006 | 111bfab3 | bellard | /* lwarx */
|
3007 | 99e300ef | Blue Swirl | static void gen_lwarx(DisasContext *ctx) |
3008 | 79aceca5 | bellard | { |
3009 | 76db3ba4 | aurel32 | TCGv t0; |
3010 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_RES); |
3011 | 76db3ba4 | aurel32 | t0 = tcg_temp_local_new(); |
3012 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
3013 | cf360a32 | aurel32 | gen_check_align(ctx, t0, 0x03);
|
3014 | 76db3ba4 | aurel32 | gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0); |
3015 | cf360a32 | aurel32 | tcg_gen_mov_tl(cpu_reserve, t0); |
3016 | cf360a32 | aurel32 | tcg_temp_free(t0); |
3017 | 79aceca5 | bellard | } |
3018 | 79aceca5 | bellard | |
3019 | 79aceca5 | bellard | /* stwcx. */
|
3020 | e8eaa2c0 | Blue Swirl | static void gen_stwcx_(DisasContext *ctx) |
3021 | 79aceca5 | bellard | { |
3022 | 76db3ba4 | aurel32 | int l1;
|
3023 | 76db3ba4 | aurel32 | TCGv t0; |
3024 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_RES); |
3025 | 76db3ba4 | aurel32 | t0 = tcg_temp_local_new(); |
3026 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
3027 | cf360a32 | aurel32 | gen_check_align(ctx, t0, 0x03);
|
3028 | cf360a32 | aurel32 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
|
3029 | cf360a32 | aurel32 | tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO); |
3030 | cf360a32 | aurel32 | tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1); |
3031 | 76db3ba4 | aurel32 | l1 = gen_new_label(); |
3032 | cf360a32 | aurel32 | tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); |
3033 | cf360a32 | aurel32 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ); |
3034 | 76db3ba4 | aurel32 | gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0); |
3035 | cf360a32 | aurel32 | gen_set_label(l1); |
3036 | cf360a32 | aurel32 | tcg_gen_movi_tl(cpu_reserve, -1);
|
3037 | cf360a32 | aurel32 | tcg_temp_free(t0); |
3038 | 79aceca5 | bellard | } |
3039 | 79aceca5 | bellard | |
3040 | 426613db | j_mayer | #if defined(TARGET_PPC64)
|
3041 | 426613db | j_mayer | /* ldarx */
|
3042 | 99e300ef | Blue Swirl | static void gen_ldarx(DisasContext *ctx) |
3043 | 426613db | j_mayer | { |
3044 | 76db3ba4 | aurel32 | TCGv t0; |
3045 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_RES); |
3046 | 76db3ba4 | aurel32 | t0 = tcg_temp_local_new(); |
3047 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
3048 | cf360a32 | aurel32 | gen_check_align(ctx, t0, 0x07);
|
3049 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], t0); |
3050 | cf360a32 | aurel32 | tcg_gen_mov_tl(cpu_reserve, t0); |
3051 | cf360a32 | aurel32 | tcg_temp_free(t0); |
3052 | 426613db | j_mayer | } |
3053 | 426613db | j_mayer | |
3054 | 426613db | j_mayer | /* stdcx. */
|
3055 | e8eaa2c0 | Blue Swirl | static void gen_stdcx_(DisasContext *ctx) |
3056 | 426613db | j_mayer | { |
3057 | 76db3ba4 | aurel32 | int l1;
|
3058 | 76db3ba4 | aurel32 | TCGv t0; |
3059 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_RES); |
3060 | 76db3ba4 | aurel32 | t0 = tcg_temp_local_new(); |
3061 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
3062 | cf360a32 | aurel32 | gen_check_align(ctx, t0, 0x07);
|
3063 | cf360a32 | aurel32 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
|
3064 | cf360a32 | aurel32 | tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO); |
3065 | cf360a32 | aurel32 | tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1); |
3066 | 76db3ba4 | aurel32 | l1 = gen_new_label(); |
3067 | cf360a32 | aurel32 | tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); |
3068 | cf360a32 | aurel32 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ); |
3069 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0); |
3070 | cf360a32 | aurel32 | gen_set_label(l1); |
3071 | cf360a32 | aurel32 | tcg_gen_movi_tl(cpu_reserve, -1);
|
3072 | cf360a32 | aurel32 | tcg_temp_free(t0); |
3073 | 426613db | j_mayer | } |
3074 | 426613db | j_mayer | #endif /* defined(TARGET_PPC64) */ |
3075 | 426613db | j_mayer | |
3076 | 79aceca5 | bellard | /* sync */
|
3077 | 99e300ef | Blue Swirl | static void gen_sync(DisasContext *ctx) |
3078 | 79aceca5 | bellard | { |
3079 | 79aceca5 | bellard | } |
3080 | 79aceca5 | bellard | |
3081 | 0db1b20e | j_mayer | /* wait */
|
3082 | 99e300ef | Blue Swirl | static void gen_wait(DisasContext *ctx) |
3083 | 0db1b20e | j_mayer | { |
3084 | 931ff272 | aurel32 | TCGv_i32 t0 = tcg_temp_new_i32(); |
3085 | 931ff272 | aurel32 | tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, halted)); |
3086 | 931ff272 | aurel32 | tcg_temp_free_i32(t0); |
3087 | 0db1b20e | j_mayer | /* Stop translation, as the CPU is supposed to sleep from now */
|
3088 | e06fcd75 | aurel32 | gen_exception_err(ctx, EXCP_HLT, 1);
|
3089 | 0db1b20e | j_mayer | } |
3090 | 0db1b20e | j_mayer | |
3091 | 79aceca5 | bellard | /*** Floating-point load ***/
|
3092 | a0d7d5a7 | aurel32 | #define GEN_LDF(name, ldop, opc, type) \
|
3093 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
3094 | 79aceca5 | bellard | { \ |
3095 | a0d7d5a7 | aurel32 | TCGv EA; \ |
3096 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
3097 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3098 | 4ecc3190 | bellard | return; \
|
3099 | 4ecc3190 | bellard | } \ |
3100 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
3101 | a0d7d5a7 | aurel32 | EA = tcg_temp_new(); \ |
3102 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, EA, 0); \
|
3103 | 76db3ba4 | aurel32 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ |
3104 | a0d7d5a7 | aurel32 | tcg_temp_free(EA); \ |
3105 | 79aceca5 | bellard | } |
3106 | 79aceca5 | bellard | |
3107 | a0d7d5a7 | aurel32 | #define GEN_LDUF(name, ldop, opc, type) \
|
3108 | 99e300ef | Blue Swirl | static void glue(gen_, name##u)(DisasContext *ctx) \ |
3109 | 79aceca5 | bellard | { \ |
3110 | a0d7d5a7 | aurel32 | TCGv EA; \ |
3111 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
3112 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3113 | 4ecc3190 | bellard | return; \
|
3114 | 4ecc3190 | bellard | } \ |
3115 | 76a66253 | j_mayer | if (unlikely(rA(ctx->opcode) == 0)) { \ |
3116 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
3117 | 9fddaa0c | bellard | return; \
|
3118 | 9a64fbe4 | bellard | } \ |
3119 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
3120 | a0d7d5a7 | aurel32 | EA = tcg_temp_new(); \ |
3121 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, EA, 0); \
|
3122 | 76db3ba4 | aurel32 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ |
3123 | a0d7d5a7 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3124 | a0d7d5a7 | aurel32 | tcg_temp_free(EA); \ |
3125 | 79aceca5 | bellard | } |
3126 | 79aceca5 | bellard | |
3127 | a0d7d5a7 | aurel32 | #define GEN_LDUXF(name, ldop, opc, type) \
|
3128 | 99e300ef | Blue Swirl | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
3129 | 79aceca5 | bellard | { \ |
3130 | a0d7d5a7 | aurel32 | TCGv EA; \ |
3131 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
3132 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3133 | 4ecc3190 | bellard | return; \
|
3134 | 4ecc3190 | bellard | } \ |
3135 | 76a66253 | j_mayer | if (unlikely(rA(ctx->opcode) == 0)) { \ |
3136 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
3137 | 9fddaa0c | bellard | return; \
|
3138 | 9a64fbe4 | bellard | } \ |
3139 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
3140 | a0d7d5a7 | aurel32 | EA = tcg_temp_new(); \ |
3141 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, EA); \ |
3142 | 76db3ba4 | aurel32 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ |
3143 | a0d7d5a7 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3144 | a0d7d5a7 | aurel32 | tcg_temp_free(EA); \ |
3145 | 79aceca5 | bellard | } |
3146 | 79aceca5 | bellard | |
3147 | a0d7d5a7 | aurel32 | #define GEN_LDXF(name, ldop, opc2, opc3, type) \
|
3148 | 99e300ef | Blue Swirl | static void glue(gen_, name##x)(DisasContext *ctx) \ |
3149 | 79aceca5 | bellard | { \ |
3150 | a0d7d5a7 | aurel32 | TCGv EA; \ |
3151 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
3152 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3153 | 4ecc3190 | bellard | return; \
|
3154 | 4ecc3190 | bellard | } \ |
3155 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
3156 | a0d7d5a7 | aurel32 | EA = tcg_temp_new(); \ |
3157 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, EA); \ |
3158 | 76db3ba4 | aurel32 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ |
3159 | a0d7d5a7 | aurel32 | tcg_temp_free(EA); \ |
3160 | 79aceca5 | bellard | } |
3161 | 79aceca5 | bellard | |
3162 | a0d7d5a7 | aurel32 | #define GEN_LDFS(name, ldop, op, type) \
|
3163 | a0d7d5a7 | aurel32 | GEN_LDF(name, ldop, op | 0x20, type); \
|
3164 | a0d7d5a7 | aurel32 | GEN_LDUF(name, ldop, op | 0x21, type); \
|
3165 | a0d7d5a7 | aurel32 | GEN_LDUXF(name, ldop, op | 0x01, type); \
|
3166 | a0d7d5a7 | aurel32 | GEN_LDXF(name, ldop, 0x17, op | 0x00, type) |
3167 | a0d7d5a7 | aurel32 | |
3168 | 76db3ba4 | aurel32 | static always_inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
3169 | a0d7d5a7 | aurel32 | { |
3170 | a0d7d5a7 | aurel32 | TCGv t0 = tcg_temp_new(); |
3171 | a0d7d5a7 | aurel32 | TCGv_i32 t1 = tcg_temp_new_i32(); |
3172 | 76db3ba4 | aurel32 | gen_qemu_ld32u(ctx, t0, arg2); |
3173 | a0d7d5a7 | aurel32 | tcg_gen_trunc_tl_i32(t1, t0); |
3174 | a0d7d5a7 | aurel32 | tcg_temp_free(t0); |
3175 | a0d7d5a7 | aurel32 | gen_helper_float32_to_float64(arg1, t1); |
3176 | a0d7d5a7 | aurel32 | tcg_temp_free_i32(t1); |
3177 | a0d7d5a7 | aurel32 | } |
3178 | 79aceca5 | bellard | |
3179 | a0d7d5a7 | aurel32 | /* lfd lfdu lfdux lfdx */
|
3180 | a0d7d5a7 | aurel32 | GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
|
3181 | a0d7d5a7 | aurel32 | /* lfs lfsu lfsux lfsx */
|
3182 | a0d7d5a7 | aurel32 | GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
|
3183 | 79aceca5 | bellard | |
3184 | 79aceca5 | bellard | /*** Floating-point store ***/
|
3185 | a0d7d5a7 | aurel32 | #define GEN_STF(name, stop, opc, type) \
|
3186 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
3187 | 79aceca5 | bellard | { \ |
3188 | a0d7d5a7 | aurel32 | TCGv EA; \ |
3189 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
3190 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3191 | 4ecc3190 | bellard | return; \
|
3192 | 4ecc3190 | bellard | } \ |
3193 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
3194 | a0d7d5a7 | aurel32 | EA = tcg_temp_new(); \ |
3195 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, EA, 0); \
|
3196 | 76db3ba4 | aurel32 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ |
3197 | a0d7d5a7 | aurel32 | tcg_temp_free(EA); \ |
3198 | 79aceca5 | bellard | } |
3199 | 79aceca5 | bellard | |
3200 | a0d7d5a7 | aurel32 | #define GEN_STUF(name, stop, opc, type) \
|
3201 | 99e300ef | Blue Swirl | static void glue(gen_, name##u)(DisasContext *ctx) \ |
3202 | 79aceca5 | bellard | { \ |
3203 | a0d7d5a7 | aurel32 | TCGv EA; \ |
3204 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
3205 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3206 | 4ecc3190 | bellard | return; \
|
3207 | 4ecc3190 | bellard | } \ |
3208 | 76a66253 | j_mayer | if (unlikely(rA(ctx->opcode) == 0)) { \ |
3209 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
3210 | 9fddaa0c | bellard | return; \
|
3211 | 9a64fbe4 | bellard | } \ |
3212 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
3213 | a0d7d5a7 | aurel32 | EA = tcg_temp_new(); \ |
3214 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, EA, 0); \
|
3215 | 76db3ba4 | aurel32 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ |
3216 | a0d7d5a7 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3217 | a0d7d5a7 | aurel32 | tcg_temp_free(EA); \ |
3218 | 79aceca5 | bellard | } |
3219 | 79aceca5 | bellard | |
3220 | a0d7d5a7 | aurel32 | #define GEN_STUXF(name, stop, opc, type) \
|
3221 | 99e300ef | Blue Swirl | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
3222 | 79aceca5 | bellard | { \ |
3223 | a0d7d5a7 | aurel32 | TCGv EA; \ |
3224 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
3225 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3226 | 4ecc3190 | bellard | return; \
|
3227 | 4ecc3190 | bellard | } \ |
3228 | 76a66253 | j_mayer | if (unlikely(rA(ctx->opcode) == 0)) { \ |
3229 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
3230 | 9fddaa0c | bellard | return; \
|
3231 | 9a64fbe4 | bellard | } \ |
3232 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
3233 | a0d7d5a7 | aurel32 | EA = tcg_temp_new(); \ |
3234 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, EA); \ |
3235 | 76db3ba4 | aurel32 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ |
3236 | a0d7d5a7 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3237 | a0d7d5a7 | aurel32 | tcg_temp_free(EA); \ |
3238 | 79aceca5 | bellard | } |
3239 | 79aceca5 | bellard | |
3240 | a0d7d5a7 | aurel32 | #define GEN_STXF(name, stop, opc2, opc3, type) \
|
3241 | 99e300ef | Blue Swirl | static void glue(gen_, name##x)(DisasContext *ctx) \ |
3242 | 79aceca5 | bellard | { \ |
3243 | a0d7d5a7 | aurel32 | TCGv EA; \ |
3244 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
3245 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3246 | 4ecc3190 | bellard | return; \
|
3247 | 4ecc3190 | bellard | } \ |
3248 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
3249 | a0d7d5a7 | aurel32 | EA = tcg_temp_new(); \ |
3250 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, EA); \ |
3251 | 76db3ba4 | aurel32 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ |
3252 | a0d7d5a7 | aurel32 | tcg_temp_free(EA); \ |
3253 | 79aceca5 | bellard | } |
3254 | 79aceca5 | bellard | |
3255 | a0d7d5a7 | aurel32 | #define GEN_STFS(name, stop, op, type) \
|
3256 | a0d7d5a7 | aurel32 | GEN_STF(name, stop, op | 0x20, type); \
|
3257 | a0d7d5a7 | aurel32 | GEN_STUF(name, stop, op | 0x21, type); \
|
3258 | a0d7d5a7 | aurel32 | GEN_STUXF(name, stop, op | 0x01, type); \
|
3259 | a0d7d5a7 | aurel32 | GEN_STXF(name, stop, 0x17, op | 0x00, type) |
3260 | a0d7d5a7 | aurel32 | |
3261 | 76db3ba4 | aurel32 | static always_inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
3262 | a0d7d5a7 | aurel32 | { |
3263 | a0d7d5a7 | aurel32 | TCGv_i32 t0 = tcg_temp_new_i32(); |
3264 | a0d7d5a7 | aurel32 | TCGv t1 = tcg_temp_new(); |
3265 | a0d7d5a7 | aurel32 | gen_helper_float64_to_float32(t0, arg1); |
3266 | a0d7d5a7 | aurel32 | tcg_gen_extu_i32_tl(t1, t0); |
3267 | a0d7d5a7 | aurel32 | tcg_temp_free_i32(t0); |
3268 | 76db3ba4 | aurel32 | gen_qemu_st32(ctx, t1, arg2); |
3269 | a0d7d5a7 | aurel32 | tcg_temp_free(t1); |
3270 | a0d7d5a7 | aurel32 | } |
3271 | 79aceca5 | bellard | |
3272 | 79aceca5 | bellard | /* stfd stfdu stfdux stfdx */
|
3273 | a0d7d5a7 | aurel32 | GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
|
3274 | 79aceca5 | bellard | /* stfs stfsu stfsux stfsx */
|
3275 | a0d7d5a7 | aurel32 | GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
|
3276 | 79aceca5 | bellard | |
3277 | 79aceca5 | bellard | /* Optional: */
|
3278 | 76db3ba4 | aurel32 | static always_inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
3279 | a0d7d5a7 | aurel32 | { |
3280 | a0d7d5a7 | aurel32 | TCGv t0 = tcg_temp_new(); |
3281 | a0d7d5a7 | aurel32 | tcg_gen_trunc_i64_tl(t0, arg1), |
3282 | 76db3ba4 | aurel32 | gen_qemu_st32(ctx, t0, arg2); |
3283 | a0d7d5a7 | aurel32 | tcg_temp_free(t0); |
3284 | a0d7d5a7 | aurel32 | } |
3285 | 79aceca5 | bellard | /* stfiwx */
|
3286 | a0d7d5a7 | aurel32 | GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX); |
3287 | 79aceca5 | bellard | |
3288 | 79aceca5 | bellard | /*** Branch ***/
|
3289 | b068d6a7 | j_mayer | static always_inline void gen_goto_tb (DisasContext *ctx, int n, |
3290 | b068d6a7 | j_mayer | target_ulong dest) |
3291 | c1942362 | bellard | { |
3292 | c1942362 | bellard | TranslationBlock *tb; |
3293 | c1942362 | bellard | tb = ctx->tb; |
3294 | a2ffb812 | aurel32 | #if defined(TARGET_PPC64)
|
3295 | a2ffb812 | aurel32 | if (!ctx->sf_mode)
|
3296 | a2ffb812 | aurel32 | dest = (uint32_t) dest; |
3297 | a2ffb812 | aurel32 | #endif
|
3298 | 57fec1fe | bellard | if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
|
3299 | 8cbcb4fa | aurel32 | likely(!ctx->singlestep_enabled)) { |
3300 | 57fec1fe | bellard | tcg_gen_goto_tb(n); |
3301 | a2ffb812 | aurel32 | tcg_gen_movi_tl(cpu_nip, dest & ~3);
|
3302 | 57fec1fe | bellard | tcg_gen_exit_tb((long)tb + n);
|
3303 | c1942362 | bellard | } else {
|
3304 | a2ffb812 | aurel32 | tcg_gen_movi_tl(cpu_nip, dest & ~3);
|
3305 | 8cbcb4fa | aurel32 | if (unlikely(ctx->singlestep_enabled)) {
|
3306 | 8cbcb4fa | aurel32 | if ((ctx->singlestep_enabled &
|
3307 | bdc4e053 | aurel32 | (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) && |
3308 | 8cbcb4fa | aurel32 | ctx->exception == POWERPC_EXCP_BRANCH) { |
3309 | 8cbcb4fa | aurel32 | target_ulong tmp = ctx->nip; |
3310 | 8cbcb4fa | aurel32 | ctx->nip = dest; |
3311 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_TRACE); |
3312 | 8cbcb4fa | aurel32 | ctx->nip = tmp; |
3313 | 8cbcb4fa | aurel32 | } |
3314 | 8cbcb4fa | aurel32 | if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
|
3315 | e06fcd75 | aurel32 | gen_debug_exception(ctx); |
3316 | 8cbcb4fa | aurel32 | } |
3317 | 8cbcb4fa | aurel32 | } |
3318 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
3319 | c1942362 | bellard | } |
3320 | c53be334 | bellard | } |
3321 | c53be334 | bellard | |
3322 | b068d6a7 | j_mayer | static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip) |
3323 | e1833e1f | j_mayer | { |
3324 | e1833e1f | j_mayer | #if defined(TARGET_PPC64)
|
3325 | a2ffb812 | aurel32 | if (ctx->sf_mode == 0) |
3326 | a2ffb812 | aurel32 | tcg_gen_movi_tl(cpu_lr, (uint32_t)nip); |
3327 | e1833e1f | j_mayer | else
|
3328 | e1833e1f | j_mayer | #endif
|
3329 | a2ffb812 | aurel32 | tcg_gen_movi_tl(cpu_lr, nip); |
3330 | e1833e1f | j_mayer | } |
3331 | e1833e1f | j_mayer | |
3332 | 79aceca5 | bellard | /* b ba bl bla */
|
3333 | 99e300ef | Blue Swirl | static void gen_b(DisasContext *ctx) |
3334 | 79aceca5 | bellard | { |
3335 | 76a66253 | j_mayer | target_ulong li, target; |
3336 | 38a64f9d | bellard | |
3337 | 8cbcb4fa | aurel32 | ctx->exception = POWERPC_EXCP_BRANCH; |
3338 | 38a64f9d | bellard | /* sign extend LI */
|
3339 | 76a66253 | j_mayer | #if defined(TARGET_PPC64)
|
3340 | d9bce9d9 | j_mayer | if (ctx->sf_mode)
|
3341 | d9bce9d9 | j_mayer | li = ((int64_t)LI(ctx->opcode) << 38) >> 38; |
3342 | d9bce9d9 | j_mayer | else
|
3343 | 76a66253 | j_mayer | #endif
|
3344 | d9bce9d9 | j_mayer | li = ((int32_t)LI(ctx->opcode) << 6) >> 6; |
3345 | 76a66253 | j_mayer | if (likely(AA(ctx->opcode) == 0)) |
3346 | 046d6672 | bellard | target = ctx->nip + li - 4;
|
3347 | 79aceca5 | bellard | else
|
3348 | 9a64fbe4 | bellard | target = li; |
3349 | e1833e1f | j_mayer | if (LK(ctx->opcode))
|
3350 | e1833e1f | j_mayer | gen_setlr(ctx, ctx->nip); |
3351 | c1942362 | bellard | gen_goto_tb(ctx, 0, target);
|
3352 | 79aceca5 | bellard | } |
3353 | 79aceca5 | bellard | |
3354 | e98a6e40 | bellard | #define BCOND_IM 0 |
3355 | e98a6e40 | bellard | #define BCOND_LR 1 |
3356 | e98a6e40 | bellard | #define BCOND_CTR 2 |
3357 | e98a6e40 | bellard | |
3358 | b068d6a7 | j_mayer | static always_inline void gen_bcond (DisasContext *ctx, int type) |
3359 | d9bce9d9 | j_mayer | { |
3360 | d9bce9d9 | j_mayer | uint32_t bo = BO(ctx->opcode); |
3361 | a2ffb812 | aurel32 | int l1 = gen_new_label();
|
3362 | a2ffb812 | aurel32 | TCGv target; |
3363 | e98a6e40 | bellard | |
3364 | 8cbcb4fa | aurel32 | ctx->exception = POWERPC_EXCP_BRANCH; |
3365 | a2ffb812 | aurel32 | if (type == BCOND_LR || type == BCOND_CTR) {
|
3366 | a7812ae4 | pbrook | target = tcg_temp_local_new(); |
3367 | a2ffb812 | aurel32 | if (type == BCOND_CTR)
|
3368 | a2ffb812 | aurel32 | tcg_gen_mov_tl(target, cpu_ctr); |
3369 | a2ffb812 | aurel32 | else
|
3370 | a2ffb812 | aurel32 | tcg_gen_mov_tl(target, cpu_lr); |
3371 | d2e9fd8f | malc | } else {
|
3372 | d2e9fd8f | malc | TCGV_UNUSED(target); |
3373 | e98a6e40 | bellard | } |
3374 | e1833e1f | j_mayer | if (LK(ctx->opcode))
|
3375 | e1833e1f | j_mayer | gen_setlr(ctx, ctx->nip); |
3376 | a2ffb812 | aurel32 | l1 = gen_new_label(); |
3377 | a2ffb812 | aurel32 | if ((bo & 0x4) == 0) { |
3378 | a2ffb812 | aurel32 | /* Decrement and test CTR */
|
3379 | a7812ae4 | pbrook | TCGv temp = tcg_temp_new(); |
3380 | a2ffb812 | aurel32 | if (unlikely(type == BCOND_CTR)) {
|
3381 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
3382 | a2ffb812 | aurel32 | return;
|
3383 | a2ffb812 | aurel32 | } |
3384 | a2ffb812 | aurel32 | tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
|
3385 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
3386 | a2ffb812 | aurel32 | if (!ctx->sf_mode)
|
3387 | a2ffb812 | aurel32 | tcg_gen_ext32u_tl(temp, cpu_ctr); |
3388 | a2ffb812 | aurel32 | else
|
3389 | d9bce9d9 | j_mayer | #endif
|
3390 | a2ffb812 | aurel32 | tcg_gen_mov_tl(temp, cpu_ctr); |
3391 | a2ffb812 | aurel32 | if (bo & 0x2) { |
3392 | a2ffb812 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
|
3393 | a2ffb812 | aurel32 | } else {
|
3394 | a2ffb812 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
|
3395 | e98a6e40 | bellard | } |
3396 | a7812ae4 | pbrook | tcg_temp_free(temp); |
3397 | a2ffb812 | aurel32 | } |
3398 | a2ffb812 | aurel32 | if ((bo & 0x10) == 0) { |
3399 | a2ffb812 | aurel32 | /* Test CR */
|
3400 | a2ffb812 | aurel32 | uint32_t bi = BI(ctx->opcode); |
3401 | a2ffb812 | aurel32 | uint32_t mask = 1 << (3 - (bi & 0x03)); |
3402 | a7812ae4 | pbrook | TCGv_i32 temp = tcg_temp_new_i32(); |
3403 | a2ffb812 | aurel32 | |
3404 | d9bce9d9 | j_mayer | if (bo & 0x8) { |
3405 | a2ffb812 | aurel32 | tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
|
3406 | a2ffb812 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
|
3407 | d9bce9d9 | j_mayer | } else {
|
3408 | a2ffb812 | aurel32 | tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
|
3409 | a2ffb812 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
|
3410 | d9bce9d9 | j_mayer | } |
3411 | a7812ae4 | pbrook | tcg_temp_free_i32(temp); |
3412 | d9bce9d9 | j_mayer | } |
3413 | e98a6e40 | bellard | if (type == BCOND_IM) {
|
3414 | a2ffb812 | aurel32 | target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); |
3415 | a2ffb812 | aurel32 | if (likely(AA(ctx->opcode) == 0)) { |
3416 | a2ffb812 | aurel32 | gen_goto_tb(ctx, 0, ctx->nip + li - 4); |
3417 | a2ffb812 | aurel32 | } else {
|
3418 | a2ffb812 | aurel32 | gen_goto_tb(ctx, 0, li);
|
3419 | a2ffb812 | aurel32 | } |
3420 | c53be334 | bellard | gen_set_label(l1); |
3421 | c1942362 | bellard | gen_goto_tb(ctx, 1, ctx->nip);
|
3422 | e98a6e40 | bellard | } else {
|
3423 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
3424 | a2ffb812 | aurel32 | if (!(ctx->sf_mode))
|
3425 | a2ffb812 | aurel32 | tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
|
3426 | a2ffb812 | aurel32 | else
|
3427 | a2ffb812 | aurel32 | #endif
|
3428 | a2ffb812 | aurel32 | tcg_gen_andi_tl(cpu_nip, target, ~3);
|
3429 | a2ffb812 | aurel32 | tcg_gen_exit_tb(0);
|
3430 | a2ffb812 | aurel32 | gen_set_label(l1); |
3431 | a2ffb812 | aurel32 | #if defined(TARGET_PPC64)
|
3432 | a2ffb812 | aurel32 | if (!(ctx->sf_mode))
|
3433 | a2ffb812 | aurel32 | tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip); |
3434 | d9bce9d9 | j_mayer | else
|
3435 | d9bce9d9 | j_mayer | #endif
|
3436 | a2ffb812 | aurel32 | tcg_gen_movi_tl(cpu_nip, ctx->nip); |
3437 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
3438 | 08e46e54 | j_mayer | } |
3439 | e98a6e40 | bellard | } |
3440 | e98a6e40 | bellard | |
3441 | 99e300ef | Blue Swirl | static void gen_bc(DisasContext *ctx) |
3442 | 3b46e624 | ths | { |
3443 | e98a6e40 | bellard | gen_bcond(ctx, BCOND_IM); |
3444 | e98a6e40 | bellard | } |
3445 | e98a6e40 | bellard | |
3446 | 99e300ef | Blue Swirl | static void gen_bcctr(DisasContext *ctx) |
3447 | 3b46e624 | ths | { |
3448 | e98a6e40 | bellard | gen_bcond(ctx, BCOND_CTR); |
3449 | e98a6e40 | bellard | } |
3450 | e98a6e40 | bellard | |
3451 | 99e300ef | Blue Swirl | static void gen_bclr(DisasContext *ctx) |
3452 | 3b46e624 | ths | { |
3453 | e98a6e40 | bellard | gen_bcond(ctx, BCOND_LR); |
3454 | e98a6e40 | bellard | } |
3455 | 79aceca5 | bellard | |
3456 | 79aceca5 | bellard | /*** Condition register logical ***/
|
3457 | e1571908 | aurel32 | #define GEN_CRLOGIC(name, tcg_op, opc) \
|
3458 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
3459 | 79aceca5 | bellard | { \ |
3460 | fc0d441e | j_mayer | uint8_t bitmask; \ |
3461 | fc0d441e | j_mayer | int sh; \
|
3462 | a7812ae4 | pbrook | TCGv_i32 t0, t1; \ |
3463 | fc0d441e | j_mayer | sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ |
3464 | a7812ae4 | pbrook | t0 = tcg_temp_new_i32(); \ |
3465 | fc0d441e | j_mayer | if (sh > 0) \ |
3466 | fea0c503 | aurel32 | tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
|
3467 | fc0d441e | j_mayer | else if (sh < 0) \ |
3468 | fea0c503 | aurel32 | tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
|
3469 | e1571908 | aurel32 | else \
|
3470 | fea0c503 | aurel32 | tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
|
3471 | a7812ae4 | pbrook | t1 = tcg_temp_new_i32(); \ |
3472 | fc0d441e | j_mayer | sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ |
3473 | fc0d441e | j_mayer | if (sh > 0) \ |
3474 | fea0c503 | aurel32 | tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
|
3475 | fc0d441e | j_mayer | else if (sh < 0) \ |
3476 | fea0c503 | aurel32 | tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
|
3477 | e1571908 | aurel32 | else \
|
3478 | fea0c503 | aurel32 | tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
|
3479 | fea0c503 | aurel32 | tcg_op(t0, t0, t1); \ |
3480 | fc0d441e | j_mayer | bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \ |
3481 | fea0c503 | aurel32 | tcg_gen_andi_i32(t0, t0, bitmask); \ |
3482 | fea0c503 | aurel32 | tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
|
3483 | fea0c503 | aurel32 | tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
|
3484 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); \ |
3485 | a7812ae4 | pbrook | tcg_temp_free_i32(t1); \ |
3486 | 79aceca5 | bellard | } |
3487 | 79aceca5 | bellard | |
3488 | 79aceca5 | bellard | /* crand */
|
3489 | e1571908 | aurel32 | GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
|
3490 | 79aceca5 | bellard | /* crandc */
|
3491 | e1571908 | aurel32 | GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
|
3492 | 79aceca5 | bellard | /* creqv */
|
3493 | e1571908 | aurel32 | GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
|
3494 | 79aceca5 | bellard | /* crnand */
|
3495 | e1571908 | aurel32 | GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
|
3496 | 79aceca5 | bellard | /* crnor */
|
3497 | e1571908 | aurel32 | GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
|
3498 | 79aceca5 | bellard | /* cror */
|
3499 | e1571908 | aurel32 | GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
|
3500 | 79aceca5 | bellard | /* crorc */
|
3501 | e1571908 | aurel32 | GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
|
3502 | 79aceca5 | bellard | /* crxor */
|
3503 | e1571908 | aurel32 | GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
|
3504 | 99e300ef | Blue Swirl | |
3505 | 54623277 | Blue Swirl | /* mcrf */
|
3506 | 99e300ef | Blue Swirl | static void gen_mcrf(DisasContext *ctx) |
3507 | 79aceca5 | bellard | { |
3508 | 47e4661c | aurel32 | tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); |
3509 | 79aceca5 | bellard | } |
3510 | 79aceca5 | bellard | |
3511 | 79aceca5 | bellard | /*** System linkage ***/
|
3512 | 99e300ef | Blue Swirl | |
3513 | 54623277 | Blue Swirl | /* rfi (mem_idx only) */
|
3514 | 99e300ef | Blue Swirl | static void gen_rfi(DisasContext *ctx) |
3515 | 79aceca5 | bellard | { |
3516 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
3517 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
3518 | 9a64fbe4 | bellard | #else
|
3519 | 9a64fbe4 | bellard | /* Restore CPU state */
|
3520 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
3521 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
3522 | 9fddaa0c | bellard | return;
|
3523 | 9a64fbe4 | bellard | } |
3524 | d72a19f7 | aurel32 | gen_helper_rfi(); |
3525 | e06fcd75 | aurel32 | gen_sync_exception(ctx); |
3526 | 9a64fbe4 | bellard | #endif
|
3527 | 79aceca5 | bellard | } |
3528 | 79aceca5 | bellard | |
3529 | 426613db | j_mayer | #if defined(TARGET_PPC64)
|
3530 | 99e300ef | Blue Swirl | static void gen_rfid(DisasContext *ctx) |
3531 | 426613db | j_mayer | { |
3532 | 426613db | j_mayer | #if defined(CONFIG_USER_ONLY)
|
3533 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
3534 | 426613db | j_mayer | #else
|
3535 | 426613db | j_mayer | /* Restore CPU state */
|
3536 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
3537 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
3538 | 426613db | j_mayer | return;
|
3539 | 426613db | j_mayer | } |
3540 | d72a19f7 | aurel32 | gen_helper_rfid(); |
3541 | e06fcd75 | aurel32 | gen_sync_exception(ctx); |
3542 | 426613db | j_mayer | #endif
|
3543 | 426613db | j_mayer | } |
3544 | 426613db | j_mayer | |
3545 | 99e300ef | Blue Swirl | static void gen_hrfid(DisasContext *ctx) |
3546 | be147d08 | j_mayer | { |
3547 | be147d08 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
3548 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
3549 | be147d08 | j_mayer | #else
|
3550 | be147d08 | j_mayer | /* Restore CPU state */
|
3551 | 76db3ba4 | aurel32 | if (unlikely(ctx->mem_idx <= 1)) { |
3552 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
3553 | be147d08 | j_mayer | return;
|
3554 | be147d08 | j_mayer | } |
3555 | d72a19f7 | aurel32 | gen_helper_hrfid(); |
3556 | e06fcd75 | aurel32 | gen_sync_exception(ctx); |
3557 | be147d08 | j_mayer | #endif
|
3558 | be147d08 | j_mayer | } |
3559 | be147d08 | j_mayer | #endif
|
3560 | be147d08 | j_mayer | |
3561 | 79aceca5 | bellard | /* sc */
|
3562 | 417bf010 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
3563 | 417bf010 | j_mayer | #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
|
3564 | 417bf010 | j_mayer | #else
|
3565 | 417bf010 | j_mayer | #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
|
3566 | 417bf010 | j_mayer | #endif
|
3567 | 99e300ef | Blue Swirl | static void gen_sc(DisasContext *ctx) |
3568 | 79aceca5 | bellard | { |
3569 | e1833e1f | j_mayer | uint32_t lev; |
3570 | e1833e1f | j_mayer | |
3571 | e1833e1f | j_mayer | lev = (ctx->opcode >> 5) & 0x7F; |
3572 | e06fcd75 | aurel32 | gen_exception_err(ctx, POWERPC_SYSCALL, lev); |
3573 | 79aceca5 | bellard | } |
3574 | 79aceca5 | bellard | |
3575 | 79aceca5 | bellard | /*** Trap ***/
|
3576 | 99e300ef | Blue Swirl | |
3577 | 54623277 | Blue Swirl | /* tw */
|
3578 | 99e300ef | Blue Swirl | static void gen_tw(DisasContext *ctx) |
3579 | 79aceca5 | bellard | { |
3580 | cab3bee2 | aurel32 | TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode)); |
3581 | a0ae05aa | ths | /* Update the nip since this might generate a trap exception */
|
3582 | d9bce9d9 | j_mayer | gen_update_nip(ctx, ctx->nip); |
3583 | cab3bee2 | aurel32 | gen_helper_tw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); |
3584 | cab3bee2 | aurel32 | tcg_temp_free_i32(t0); |
3585 | 79aceca5 | bellard | } |
3586 | 79aceca5 | bellard | |
3587 | 79aceca5 | bellard | /* twi */
|
3588 | 99e300ef | Blue Swirl | static void gen_twi(DisasContext *ctx) |
3589 | 79aceca5 | bellard | { |
3590 | cab3bee2 | aurel32 | TCGv t0 = tcg_const_tl(SIMM(ctx->opcode)); |
3591 | cab3bee2 | aurel32 | TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode)); |
3592 | d9bce9d9 | j_mayer | /* Update the nip since this might generate a trap exception */
|
3593 | d9bce9d9 | j_mayer | gen_update_nip(ctx, ctx->nip); |
3594 | cab3bee2 | aurel32 | gen_helper_tw(cpu_gpr[rA(ctx->opcode)], t0, t1); |
3595 | cab3bee2 | aurel32 | tcg_temp_free(t0); |
3596 | cab3bee2 | aurel32 | tcg_temp_free_i32(t1); |
3597 | 79aceca5 | bellard | } |
3598 | 79aceca5 | bellard | |
3599 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
3600 | d9bce9d9 | j_mayer | /* td */
|
3601 | 99e300ef | Blue Swirl | static void gen_td(DisasContext *ctx) |
3602 | d9bce9d9 | j_mayer | { |
3603 | cab3bee2 | aurel32 | TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode)); |
3604 | d9bce9d9 | j_mayer | /* Update the nip since this might generate a trap exception */
|
3605 | d9bce9d9 | j_mayer | gen_update_nip(ctx, ctx->nip); |
3606 | cab3bee2 | aurel32 | gen_helper_td(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); |
3607 | cab3bee2 | aurel32 | tcg_temp_free_i32(t0); |
3608 | d9bce9d9 | j_mayer | } |
3609 | d9bce9d9 | j_mayer | |
3610 | d9bce9d9 | j_mayer | /* tdi */
|
3611 | 99e300ef | Blue Swirl | static void gen_tdi(DisasContext *ctx) |
3612 | d9bce9d9 | j_mayer | { |
3613 | cab3bee2 | aurel32 | TCGv t0 = tcg_const_tl(SIMM(ctx->opcode)); |
3614 | cab3bee2 | aurel32 | TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode)); |
3615 | d9bce9d9 | j_mayer | /* Update the nip since this might generate a trap exception */
|
3616 | d9bce9d9 | j_mayer | gen_update_nip(ctx, ctx->nip); |
3617 | cab3bee2 | aurel32 | gen_helper_td(cpu_gpr[rA(ctx->opcode)], t0, t1); |
3618 | cab3bee2 | aurel32 | tcg_temp_free(t0); |
3619 | cab3bee2 | aurel32 | tcg_temp_free_i32(t1); |
3620 | d9bce9d9 | j_mayer | } |
3621 | d9bce9d9 | j_mayer | #endif
|
3622 | d9bce9d9 | j_mayer | |
3623 | 79aceca5 | bellard | /*** Processor control ***/
|
3624 | 99e300ef | Blue Swirl | |
3625 | 54623277 | Blue Swirl | /* mcrxr */
|
3626 | 99e300ef | Blue Swirl | static void gen_mcrxr(DisasContext *ctx) |
3627 | 79aceca5 | bellard | { |
3628 | 3d7b417e | aurel32 | tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer); |
3629 | 3d7b417e | aurel32 | tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA); |
3630 | 269f3e95 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA)); |
3631 | 79aceca5 | bellard | } |
3632 | 79aceca5 | bellard | |
3633 | 0cfe11ea | aurel32 | /* mfcr mfocrf */
|
3634 | 99e300ef | Blue Swirl | static void gen_mfcr(DisasContext *ctx) |
3635 | 79aceca5 | bellard | { |
3636 | 76a66253 | j_mayer | uint32_t crm, crn; |
3637 | 3b46e624 | ths | |
3638 | 76a66253 | j_mayer | if (likely(ctx->opcode & 0x00100000)) { |
3639 | 76a66253 | j_mayer | crm = CRM(ctx->opcode); |
3640 | 8dd640e4 | malc | if (likely(crm && ((crm & (crm - 1)) == 0))) { |
3641 | 0cfe11ea | aurel32 | crn = ctz32 (crm); |
3642 | e1571908 | aurel32 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
|
3643 | 0497d2f4 | aurel32 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], |
3644 | 0497d2f4 | aurel32 | cpu_gpr[rD(ctx->opcode)], crn * 4);
|
3645 | 76a66253 | j_mayer | } |
3646 | d9bce9d9 | j_mayer | } else {
|
3647 | 651721b2 | aurel32 | TCGv_i32 t0 = tcg_temp_new_i32(); |
3648 | 651721b2 | aurel32 | tcg_gen_mov_i32(t0, cpu_crf[0]);
|
3649 | 651721b2 | aurel32 | tcg_gen_shli_i32(t0, t0, 4);
|
3650 | 651721b2 | aurel32 | tcg_gen_or_i32(t0, t0, cpu_crf[1]);
|
3651 | 651721b2 | aurel32 | tcg_gen_shli_i32(t0, t0, 4);
|
3652 | 651721b2 | aurel32 | tcg_gen_or_i32(t0, t0, cpu_crf[2]);
|
3653 | 651721b2 | aurel32 | tcg_gen_shli_i32(t0, t0, 4);
|
3654 | 651721b2 | aurel32 | tcg_gen_or_i32(t0, t0, cpu_crf[3]);
|
3655 | 651721b2 | aurel32 | tcg_gen_shli_i32(t0, t0, 4);
|
3656 | 651721b2 | aurel32 | tcg_gen_or_i32(t0, t0, cpu_crf[4]);
|
3657 | 651721b2 | aurel32 | tcg_gen_shli_i32(t0, t0, 4);
|
3658 | 651721b2 | aurel32 | tcg_gen_or_i32(t0, t0, cpu_crf[5]);
|
3659 | 651721b2 | aurel32 | tcg_gen_shli_i32(t0, t0, 4);
|
3660 | 651721b2 | aurel32 | tcg_gen_or_i32(t0, t0, cpu_crf[6]);
|
3661 | 651721b2 | aurel32 | tcg_gen_shli_i32(t0, t0, 4);
|
3662 | 651721b2 | aurel32 | tcg_gen_or_i32(t0, t0, cpu_crf[7]);
|
3663 | 651721b2 | aurel32 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); |
3664 | 651721b2 | aurel32 | tcg_temp_free_i32(t0); |
3665 | d9bce9d9 | j_mayer | } |
3666 | 79aceca5 | bellard | } |
3667 | 79aceca5 | bellard | |
3668 | 79aceca5 | bellard | /* mfmsr */
|
3669 | 99e300ef | Blue Swirl | static void gen_mfmsr(DisasContext *ctx) |
3670 | 79aceca5 | bellard | { |
3671 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
3672 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
3673 | 9a64fbe4 | bellard | #else
|
3674 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
3675 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
3676 | 9fddaa0c | bellard | return;
|
3677 | 9a64fbe4 | bellard | } |
3678 | 6527f6ea | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); |
3679 | 9a64fbe4 | bellard | #endif
|
3680 | 79aceca5 | bellard | } |
3681 | 79aceca5 | bellard | |
3682 | a11b8151 | j_mayer | #if 1 |
3683 | 6f2d8978 | j_mayer | #define SPR_NOACCESS ((void *)(-1UL)) |
3684 | 3fc6c082 | bellard | #else
|
3685 | 3fc6c082 | bellard | static void spr_noaccess (void *opaque, int sprn) |
3686 | 3fc6c082 | bellard | { |
3687 | 3fc6c082 | bellard | sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); |
3688 | 3fc6c082 | bellard | printf("ERROR: try to access SPR %d !\n", sprn);
|
3689 | 3fc6c082 | bellard | } |
3690 | 3fc6c082 | bellard | #define SPR_NOACCESS (&spr_noaccess)
|
3691 | 3fc6c082 | bellard | #endif
|
3692 | 3fc6c082 | bellard | |
3693 | 79aceca5 | bellard | /* mfspr */
|
3694 | b068d6a7 | j_mayer | static always_inline void gen_op_mfspr (DisasContext *ctx) |
3695 | 79aceca5 | bellard | { |
3696 | 45d827d2 | aurel32 | void (*read_cb)(void *opaque, int gprn, int sprn); |
3697 | 79aceca5 | bellard | uint32_t sprn = SPR(ctx->opcode); |
3698 | 79aceca5 | bellard | |
3699 | 3fc6c082 | bellard | #if !defined(CONFIG_USER_ONLY)
|
3700 | 76db3ba4 | aurel32 | if (ctx->mem_idx == 2) |
3701 | be147d08 | j_mayer | read_cb = ctx->spr_cb[sprn].hea_read; |
3702 | 76db3ba4 | aurel32 | else if (ctx->mem_idx) |
3703 | 3fc6c082 | bellard | read_cb = ctx->spr_cb[sprn].oea_read; |
3704 | 3fc6c082 | bellard | else
|
3705 | 9a64fbe4 | bellard | #endif
|
3706 | 3fc6c082 | bellard | read_cb = ctx->spr_cb[sprn].uea_read; |
3707 | 76a66253 | j_mayer | if (likely(read_cb != NULL)) { |
3708 | 76a66253 | j_mayer | if (likely(read_cb != SPR_NOACCESS)) {
|
3709 | 45d827d2 | aurel32 | (*read_cb)(ctx, rD(ctx->opcode), sprn); |
3710 | 3fc6c082 | bellard | } else {
|
3711 | 3fc6c082 | bellard | /* Privilege exception */
|
3712 | 9fceefa7 | j_mayer | /* This is a hack to avoid warnings when running Linux:
|
3713 | 9fceefa7 | j_mayer | * this OS breaks the PowerPC virtualisation model,
|
3714 | 9fceefa7 | j_mayer | * allowing userland application to read the PVR
|
3715 | 9fceefa7 | j_mayer | */
|
3716 | 9fceefa7 | j_mayer | if (sprn != SPR_PVR) {
|
3717 | 93fcfe39 | aliguori | qemu_log("Trying to read privileged spr %d %03x at "
|
3718 | 077fc206 | j_mayer | ADDRX "\n", sprn, sprn, ctx->nip);
|
3719 | 077fc206 | j_mayer | printf("Trying to read privileged spr %d %03x at " ADDRX "\n", |
3720 | 077fc206 | j_mayer | sprn, sprn, ctx->nip); |
3721 | f24e5695 | bellard | } |
3722 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
3723 | 79aceca5 | bellard | } |
3724 | 3fc6c082 | bellard | } else {
|
3725 | 3fc6c082 | bellard | /* Not defined */
|
3726 | 93fcfe39 | aliguori | qemu_log("Trying to read invalid spr %d %03x at "
|
3727 | 077fc206 | j_mayer | ADDRX "\n", sprn, sprn, ctx->nip);
|
3728 | 077fc206 | j_mayer | printf("Trying to read invalid spr %d %03x at " ADDRX "\n", |
3729 | 077fc206 | j_mayer | sprn, sprn, ctx->nip); |
3730 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR); |
3731 | 79aceca5 | bellard | } |
3732 | 79aceca5 | bellard | } |
3733 | 79aceca5 | bellard | |
3734 | 99e300ef | Blue Swirl | static void gen_mfspr(DisasContext *ctx) |
3735 | 79aceca5 | bellard | { |
3736 | 3fc6c082 | bellard | gen_op_mfspr(ctx); |
3737 | 76a66253 | j_mayer | } |
3738 | 3fc6c082 | bellard | |
3739 | 3fc6c082 | bellard | /* mftb */
|
3740 | 99e300ef | Blue Swirl | static void gen_mftb(DisasContext *ctx) |
3741 | 3fc6c082 | bellard | { |
3742 | 3fc6c082 | bellard | gen_op_mfspr(ctx); |
3743 | 79aceca5 | bellard | } |
3744 | 79aceca5 | bellard | |
3745 | 0cfe11ea | aurel32 | /* mtcrf mtocrf*/
|
3746 | 99e300ef | Blue Swirl | static void gen_mtcrf(DisasContext *ctx) |
3747 | 79aceca5 | bellard | { |
3748 | 76a66253 | j_mayer | uint32_t crm, crn; |
3749 | 3b46e624 | ths | |
3750 | 76a66253 | j_mayer | crm = CRM(ctx->opcode); |
3751 | 8dd640e4 | malc | if (likely((ctx->opcode & 0x00100000))) { |
3752 | 8dd640e4 | malc | if (crm && ((crm & (crm - 1)) == 0)) { |
3753 | 8dd640e4 | malc | TCGv_i32 temp = tcg_temp_new_i32(); |
3754 | 0cfe11ea | aurel32 | crn = ctz32 (crm); |
3755 | 8dd640e4 | malc | tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); |
3756 | 0cfe11ea | aurel32 | tcg_gen_shri_i32(temp, temp, crn * 4);
|
3757 | 0cfe11ea | aurel32 | tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); |
3758 | 8dd640e4 | malc | tcg_temp_free_i32(temp); |
3759 | 8dd640e4 | malc | } |
3760 | 76a66253 | j_mayer | } else {
|
3761 | 651721b2 | aurel32 | TCGv_i32 temp = tcg_temp_new_i32(); |
3762 | 651721b2 | aurel32 | tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); |
3763 | 651721b2 | aurel32 | for (crn = 0 ; crn < 8 ; crn++) { |
3764 | 651721b2 | aurel32 | if (crm & (1 << crn)) { |
3765 | 651721b2 | aurel32 | tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); |
3766 | 651721b2 | aurel32 | tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); |
3767 | 651721b2 | aurel32 | } |
3768 | 651721b2 | aurel32 | } |
3769 | a7812ae4 | pbrook | tcg_temp_free_i32(temp); |
3770 | 76a66253 | j_mayer | } |
3771 | 79aceca5 | bellard | } |
3772 | 79aceca5 | bellard | |
3773 | 79aceca5 | bellard | /* mtmsr */
|
3774 | 426613db | j_mayer | #if defined(TARGET_PPC64)
|
3775 | 99e300ef | Blue Swirl | static void gen_mtmsrd(DisasContext *ctx) |
3776 | 426613db | j_mayer | { |
3777 | 426613db | j_mayer | #if defined(CONFIG_USER_ONLY)
|
3778 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
3779 | 426613db | j_mayer | #else
|
3780 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
3781 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
3782 | 426613db | j_mayer | return;
|
3783 | 426613db | j_mayer | } |
3784 | be147d08 | j_mayer | if (ctx->opcode & 0x00010000) { |
3785 | be147d08 | j_mayer | /* Special form that does not need any synchronisation */
|
3786 | 6527f6ea | aurel32 | TCGv t0 = tcg_temp_new(); |
3787 | 6527f6ea | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); |
3788 | 6527f6ea | aurel32 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE))); |
3789 | 6527f6ea | aurel32 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); |
3790 | 6527f6ea | aurel32 | tcg_temp_free(t0); |
3791 | be147d08 | j_mayer | } else {
|
3792 | 056b05f8 | j_mayer | /* XXX: we need to update nip before the store
|
3793 | 056b05f8 | j_mayer | * if we enter power saving mode, we will exit the loop
|
3794 | 056b05f8 | j_mayer | * directly from ppc_store_msr
|
3795 | 056b05f8 | j_mayer | */
|
3796 | be147d08 | j_mayer | gen_update_nip(ctx, ctx->nip); |
3797 | 6527f6ea | aurel32 | gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]); |
3798 | be147d08 | j_mayer | /* Must stop the translation as machine state (may have) changed */
|
3799 | be147d08 | j_mayer | /* Note that mtmsr is not always defined as context-synchronizing */
|
3800 | e06fcd75 | aurel32 | gen_stop_exception(ctx); |
3801 | be147d08 | j_mayer | } |
3802 | 426613db | j_mayer | #endif
|
3803 | 426613db | j_mayer | } |
3804 | 426613db | j_mayer | #endif
|
3805 | 426613db | j_mayer | |
3806 | 99e300ef | Blue Swirl | static void gen_mtmsr(DisasContext *ctx) |
3807 | 79aceca5 | bellard | { |
3808 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
3809 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
3810 | 9a64fbe4 | bellard | #else
|
3811 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
3812 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
3813 | 9fddaa0c | bellard | return;
|
3814 | 9a64fbe4 | bellard | } |
3815 | be147d08 | j_mayer | if (ctx->opcode & 0x00010000) { |
3816 | be147d08 | j_mayer | /* Special form that does not need any synchronisation */
|
3817 | 6527f6ea | aurel32 | TCGv t0 = tcg_temp_new(); |
3818 | 6527f6ea | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); |
3819 | 6527f6ea | aurel32 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE))); |
3820 | 6527f6ea | aurel32 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); |
3821 | 6527f6ea | aurel32 | tcg_temp_free(t0); |
3822 | be147d08 | j_mayer | } else {
|
3823 | 056b05f8 | j_mayer | /* XXX: we need to update nip before the store
|
3824 | 056b05f8 | j_mayer | * if we enter power saving mode, we will exit the loop
|
3825 | 056b05f8 | j_mayer | * directly from ppc_store_msr
|
3826 | 056b05f8 | j_mayer | */
|
3827 | be147d08 | j_mayer | gen_update_nip(ctx, ctx->nip); |
3828 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
3829 | 6527f6ea | aurel32 | if (!ctx->sf_mode) {
|
3830 | 6527f6ea | aurel32 | TCGv t0 = tcg_temp_new(); |
3831 | 6527f6ea | aurel32 | TCGv t1 = tcg_temp_new(); |
3832 | 6527f6ea | aurel32 | tcg_gen_andi_tl(t0, cpu_msr, 0xFFFFFFFF00000000ULL);
|
3833 | 6527f6ea | aurel32 | tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]); |
3834 | 6527f6ea | aurel32 | tcg_gen_or_tl(t0, t0, t1); |
3835 | 6527f6ea | aurel32 | tcg_temp_free(t1); |
3836 | 6527f6ea | aurel32 | gen_helper_store_msr(t0); |
3837 | 6527f6ea | aurel32 | tcg_temp_free(t0); |
3838 | 6527f6ea | aurel32 | } else
|
3839 | d9bce9d9 | j_mayer | #endif
|
3840 | 6527f6ea | aurel32 | gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]); |
3841 | be147d08 | j_mayer | /* Must stop the translation as machine state (may have) changed */
|
3842 | 6527f6ea | aurel32 | /* Note that mtmsr is not always defined as context-synchronizing */
|
3843 | e06fcd75 | aurel32 | gen_stop_exception(ctx); |
3844 | be147d08 | j_mayer | } |
3845 | 9a64fbe4 | bellard | #endif
|
3846 | 79aceca5 | bellard | } |
3847 | 79aceca5 | bellard | |
3848 | 79aceca5 | bellard | /* mtspr */
|
3849 | 99e300ef | Blue Swirl | static void gen_mtspr(DisasContext *ctx) |
3850 | 79aceca5 | bellard | { |
3851 | 45d827d2 | aurel32 | void (*write_cb)(void *opaque, int sprn, int gprn); |
3852 | 79aceca5 | bellard | uint32_t sprn = SPR(ctx->opcode); |
3853 | 79aceca5 | bellard | |
3854 | 3fc6c082 | bellard | #if !defined(CONFIG_USER_ONLY)
|
3855 | 76db3ba4 | aurel32 | if (ctx->mem_idx == 2) |
3856 | be147d08 | j_mayer | write_cb = ctx->spr_cb[sprn].hea_write; |
3857 | 76db3ba4 | aurel32 | else if (ctx->mem_idx) |
3858 | 3fc6c082 | bellard | write_cb = ctx->spr_cb[sprn].oea_write; |
3859 | 3fc6c082 | bellard | else
|
3860 | 9a64fbe4 | bellard | #endif
|
3861 | 3fc6c082 | bellard | write_cb = ctx->spr_cb[sprn].uea_write; |
3862 | 76a66253 | j_mayer | if (likely(write_cb != NULL)) { |
3863 | 76a66253 | j_mayer | if (likely(write_cb != SPR_NOACCESS)) {
|
3864 | 45d827d2 | aurel32 | (*write_cb)(ctx, sprn, rS(ctx->opcode)); |
3865 | 3fc6c082 | bellard | } else {
|
3866 | 3fc6c082 | bellard | /* Privilege exception */
|
3867 | 93fcfe39 | aliguori | qemu_log("Trying to write privileged spr %d %03x at "
|
3868 | 077fc206 | j_mayer | ADDRX "\n", sprn, sprn, ctx->nip);
|
3869 | 077fc206 | j_mayer | printf("Trying to write privileged spr %d %03x at " ADDRX "\n", |
3870 | 077fc206 | j_mayer | sprn, sprn, ctx->nip); |
3871 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
3872 | 76a66253 | j_mayer | } |
3873 | 3fc6c082 | bellard | } else {
|
3874 | 3fc6c082 | bellard | /* Not defined */
|
3875 | 93fcfe39 | aliguori | qemu_log("Trying to write invalid spr %d %03x at "
|
3876 | 077fc206 | j_mayer | ADDRX "\n", sprn, sprn, ctx->nip);
|
3877 | 077fc206 | j_mayer | printf("Trying to write invalid spr %d %03x at " ADDRX "\n", |
3878 | 077fc206 | j_mayer | sprn, sprn, ctx->nip); |
3879 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR); |
3880 | 79aceca5 | bellard | } |
3881 | 79aceca5 | bellard | } |
3882 | 79aceca5 | bellard | |
3883 | 79aceca5 | bellard | /*** Cache management ***/
|
3884 | 99e300ef | Blue Swirl | |
3885 | 54623277 | Blue Swirl | /* dcbf */
|
3886 | 99e300ef | Blue Swirl | static void gen_dcbf(DisasContext *ctx) |
3887 | 79aceca5 | bellard | { |
3888 | dac454af | j_mayer | /* XXX: specification says this is treated as a load by the MMU */
|
3889 | 76db3ba4 | aurel32 | TCGv t0; |
3890 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_CACHE); |
3891 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
3892 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
3893 | 76db3ba4 | aurel32 | gen_qemu_ld8u(ctx, t0, t0); |
3894 | fea0c503 | aurel32 | tcg_temp_free(t0); |
3895 | 79aceca5 | bellard | } |
3896 | 79aceca5 | bellard | |
3897 | 79aceca5 | bellard | /* dcbi (Supervisor only) */
|
3898 | 99e300ef | Blue Swirl | static void gen_dcbi(DisasContext *ctx) |
3899 | 79aceca5 | bellard | { |
3900 | a541f297 | bellard | #if defined(CONFIG_USER_ONLY)
|
3901 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
3902 | a541f297 | bellard | #else
|
3903 | b61f2753 | aurel32 | TCGv EA, val; |
3904 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
3905 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
3906 | 9fddaa0c | bellard | return;
|
3907 | 9a64fbe4 | bellard | } |
3908 | a7812ae4 | pbrook | EA = tcg_temp_new(); |
3909 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_CACHE); |
3910 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, EA); |
3911 | a7812ae4 | pbrook | val = tcg_temp_new(); |
3912 | 76a66253 | j_mayer | /* XXX: specification says this should be treated as a store by the MMU */
|
3913 | 76db3ba4 | aurel32 | gen_qemu_ld8u(ctx, val, EA); |
3914 | 76db3ba4 | aurel32 | gen_qemu_st8(ctx, val, EA); |
3915 | b61f2753 | aurel32 | tcg_temp_free(val); |
3916 | b61f2753 | aurel32 | tcg_temp_free(EA); |
3917 | a541f297 | bellard | #endif
|
3918 | 79aceca5 | bellard | } |
3919 | 79aceca5 | bellard | |
3920 | 79aceca5 | bellard | /* dcdst */
|
3921 | 99e300ef | Blue Swirl | static void gen_dcbst(DisasContext *ctx) |
3922 | 79aceca5 | bellard | { |
3923 | 76a66253 | j_mayer | /* XXX: specification say this is treated as a load by the MMU */
|
3924 | 76db3ba4 | aurel32 | TCGv t0; |
3925 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_CACHE); |
3926 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
3927 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
3928 | 76db3ba4 | aurel32 | gen_qemu_ld8u(ctx, t0, t0); |
3929 | fea0c503 | aurel32 | tcg_temp_free(t0); |
3930 | 79aceca5 | bellard | } |
3931 | 79aceca5 | bellard | |
3932 | 79aceca5 | bellard | /* dcbt */
|
3933 | 99e300ef | Blue Swirl | static void gen_dcbt(DisasContext *ctx) |
3934 | 79aceca5 | bellard | { |
3935 | 0db1b20e | j_mayer | /* interpreted as no-op */
|
3936 | 76a66253 | j_mayer | /* XXX: specification say this is treated as a load by the MMU
|
3937 | 76a66253 | j_mayer | * but does not generate any exception
|
3938 | 76a66253 | j_mayer | */
|
3939 | 79aceca5 | bellard | } |
3940 | 79aceca5 | bellard | |
3941 | 79aceca5 | bellard | /* dcbtst */
|
3942 | 99e300ef | Blue Swirl | static void gen_dcbtst(DisasContext *ctx) |
3943 | 79aceca5 | bellard | { |
3944 | 0db1b20e | j_mayer | /* interpreted as no-op */
|
3945 | 76a66253 | j_mayer | /* XXX: specification say this is treated as a load by the MMU
|
3946 | 76a66253 | j_mayer | * but does not generate any exception
|
3947 | 76a66253 | j_mayer | */
|
3948 | 79aceca5 | bellard | } |
3949 | 79aceca5 | bellard | |
3950 | 79aceca5 | bellard | /* dcbz */
|
3951 | 99e300ef | Blue Swirl | static void gen_dcbz(DisasContext *ctx) |
3952 | 79aceca5 | bellard | { |
3953 | 76db3ba4 | aurel32 | TCGv t0; |
3954 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_CACHE); |
3955 | 799a8c8d | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
3956 | 799a8c8d | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
3957 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
3958 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
3959 | 799a8c8d | aurel32 | gen_helper_dcbz(t0); |
3960 | 799a8c8d | aurel32 | tcg_temp_free(t0); |
3961 | d63001d1 | j_mayer | } |
3962 | d63001d1 | j_mayer | |
3963 | e8eaa2c0 | Blue Swirl | static void gen_dcbz_970(DisasContext *ctx) |
3964 | d63001d1 | j_mayer | { |
3965 | 76db3ba4 | aurel32 | TCGv t0; |
3966 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_CACHE); |
3967 | 799a8c8d | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
3968 | 799a8c8d | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
3969 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
3970 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
3971 | d63001d1 | j_mayer | if (ctx->opcode & 0x00200000) |
3972 | 799a8c8d | aurel32 | gen_helper_dcbz(t0); |
3973 | d63001d1 | j_mayer | else
|
3974 | 799a8c8d | aurel32 | gen_helper_dcbz_970(t0); |
3975 | 799a8c8d | aurel32 | tcg_temp_free(t0); |
3976 | 79aceca5 | bellard | } |
3977 | 79aceca5 | bellard | |
3978 | ae1c1a3d | aurel32 | /* dst / dstt */
|
3979 | 99e300ef | Blue Swirl | static void gen_dst(DisasContext *ctx) |
3980 | ae1c1a3d | aurel32 | { |
3981 | ae1c1a3d | aurel32 | if (rA(ctx->opcode) == 0) { |
3982 | ae1c1a3d | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); |
3983 | ae1c1a3d | aurel32 | } else {
|
3984 | ae1c1a3d | aurel32 | /* interpreted as no-op */
|
3985 | ae1c1a3d | aurel32 | } |
3986 | ae1c1a3d | aurel32 | } |
3987 | ae1c1a3d | aurel32 | |
3988 | ae1c1a3d | aurel32 | /* dstst /dststt */
|
3989 | 99e300ef | Blue Swirl | static void gen_dstst(DisasContext *ctx) |
3990 | ae1c1a3d | aurel32 | { |
3991 | ae1c1a3d | aurel32 | if (rA(ctx->opcode) == 0) { |
3992 | ae1c1a3d | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); |
3993 | ae1c1a3d | aurel32 | } else {
|
3994 | ae1c1a3d | aurel32 | /* interpreted as no-op */
|
3995 | ae1c1a3d | aurel32 | } |
3996 | ae1c1a3d | aurel32 | |
3997 | ae1c1a3d | aurel32 | } |
3998 | ae1c1a3d | aurel32 | |
3999 | ae1c1a3d | aurel32 | /* dss / dssall */
|
4000 | 99e300ef | Blue Swirl | static void gen_dss(DisasContext *ctx) |
4001 | ae1c1a3d | aurel32 | { |
4002 | ae1c1a3d | aurel32 | /* interpreted as no-op */
|
4003 | ae1c1a3d | aurel32 | } |
4004 | ae1c1a3d | aurel32 | |
4005 | 79aceca5 | bellard | /* icbi */
|
4006 | 99e300ef | Blue Swirl | static void gen_icbi(DisasContext *ctx) |
4007 | 79aceca5 | bellard | { |
4008 | 76db3ba4 | aurel32 | TCGv t0; |
4009 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_CACHE); |
4010 | 30032c94 | j_mayer | /* NIP cannot be restored if the memory exception comes from an helper */
|
4011 | 30032c94 | j_mayer | gen_update_nip(ctx, ctx->nip - 4);
|
4012 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
4013 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
4014 | 37d269df | aurel32 | gen_helper_icbi(t0); |
4015 | 37d269df | aurel32 | tcg_temp_free(t0); |
4016 | 79aceca5 | bellard | } |
4017 | 79aceca5 | bellard | |
4018 | 79aceca5 | bellard | /* Optional: */
|
4019 | 79aceca5 | bellard | /* dcba */
|
4020 | 99e300ef | Blue Swirl | static void gen_dcba(DisasContext *ctx) |
4021 | 79aceca5 | bellard | { |
4022 | 0db1b20e | j_mayer | /* interpreted as no-op */
|
4023 | 0db1b20e | j_mayer | /* XXX: specification say this is treated as a store by the MMU
|
4024 | 0db1b20e | j_mayer | * but does not generate any exception
|
4025 | 0db1b20e | j_mayer | */
|
4026 | 79aceca5 | bellard | } |
4027 | 79aceca5 | bellard | |
4028 | 79aceca5 | bellard | /*** Segment register manipulation ***/
|
4029 | 79aceca5 | bellard | /* Supervisor only: */
|
4030 | 99e300ef | Blue Swirl | |
4031 | 54623277 | Blue Swirl | /* mfsr */
|
4032 | 99e300ef | Blue Swirl | static void gen_mfsr(DisasContext *ctx) |
4033 | 79aceca5 | bellard | { |
4034 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
4035 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4036 | 9a64fbe4 | bellard | #else
|
4037 | 74d37793 | aurel32 | TCGv t0; |
4038 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
4039 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4040 | 9fddaa0c | bellard | return;
|
4041 | 9a64fbe4 | bellard | } |
4042 | 74d37793 | aurel32 | t0 = tcg_const_tl(SR(ctx->opcode)); |
4043 | 74d37793 | aurel32 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0); |
4044 | 74d37793 | aurel32 | tcg_temp_free(t0); |
4045 | 9a64fbe4 | bellard | #endif
|
4046 | 79aceca5 | bellard | } |
4047 | 79aceca5 | bellard | |
4048 | 79aceca5 | bellard | /* mfsrin */
|
4049 | 99e300ef | Blue Swirl | static void gen_mfsrin(DisasContext *ctx) |
4050 | 79aceca5 | bellard | { |
4051 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
4052 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4053 | 9a64fbe4 | bellard | #else
|
4054 | 74d37793 | aurel32 | TCGv t0; |
4055 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
4056 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4057 | 9fddaa0c | bellard | return;
|
4058 | 9a64fbe4 | bellard | } |
4059 | 74d37793 | aurel32 | t0 = tcg_temp_new(); |
4060 | 74d37793 | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
|
4061 | 74d37793 | aurel32 | tcg_gen_andi_tl(t0, t0, 0xF);
|
4062 | 74d37793 | aurel32 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0); |
4063 | 74d37793 | aurel32 | tcg_temp_free(t0); |
4064 | 9a64fbe4 | bellard | #endif
|
4065 | 79aceca5 | bellard | } |
4066 | 79aceca5 | bellard | |
4067 | 79aceca5 | bellard | /* mtsr */
|
4068 | 99e300ef | Blue Swirl | static void gen_mtsr(DisasContext *ctx) |
4069 | 79aceca5 | bellard | { |
4070 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
4071 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4072 | 9a64fbe4 | bellard | #else
|
4073 | 74d37793 | aurel32 | TCGv t0; |
4074 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
4075 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4076 | 9fddaa0c | bellard | return;
|
4077 | 9a64fbe4 | bellard | } |
4078 | 74d37793 | aurel32 | t0 = tcg_const_tl(SR(ctx->opcode)); |
4079 | 74d37793 | aurel32 | gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]); |
4080 | 74d37793 | aurel32 | tcg_temp_free(t0); |
4081 | 9a64fbe4 | bellard | #endif
|
4082 | 79aceca5 | bellard | } |
4083 | 79aceca5 | bellard | |
4084 | 79aceca5 | bellard | /* mtsrin */
|
4085 | 99e300ef | Blue Swirl | static void gen_mtsrin(DisasContext *ctx) |
4086 | 79aceca5 | bellard | { |
4087 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
4088 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4089 | 9a64fbe4 | bellard | #else
|
4090 | 74d37793 | aurel32 | TCGv t0; |
4091 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
4092 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4093 | 9fddaa0c | bellard | return;
|
4094 | 9a64fbe4 | bellard | } |
4095 | 74d37793 | aurel32 | t0 = tcg_temp_new(); |
4096 | 74d37793 | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
|
4097 | 74d37793 | aurel32 | tcg_gen_andi_tl(t0, t0, 0xF);
|
4098 | 74d37793 | aurel32 | gen_helper_store_sr(t0, cpu_gpr[rD(ctx->opcode)]); |
4099 | 74d37793 | aurel32 | tcg_temp_free(t0); |
4100 | 9a64fbe4 | bellard | #endif
|
4101 | 79aceca5 | bellard | } |
4102 | 79aceca5 | bellard | |
4103 | 12de9a39 | j_mayer | #if defined(TARGET_PPC64)
|
4104 | 12de9a39 | j_mayer | /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
|
4105 | e8eaa2c0 | Blue Swirl | |
4106 | 54623277 | Blue Swirl | /* mfsr */
|
4107 | e8eaa2c0 | Blue Swirl | static void gen_mfsr_64b(DisasContext *ctx) |
4108 | 12de9a39 | j_mayer | { |
4109 | 12de9a39 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
4110 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4111 | 12de9a39 | j_mayer | #else
|
4112 | 74d37793 | aurel32 | TCGv t0; |
4113 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
4114 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4115 | 12de9a39 | j_mayer | return;
|
4116 | 12de9a39 | j_mayer | } |
4117 | 74d37793 | aurel32 | t0 = tcg_const_tl(SR(ctx->opcode)); |
4118 | f6b868fc | blueswir1 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0); |
4119 | 74d37793 | aurel32 | tcg_temp_free(t0); |
4120 | 12de9a39 | j_mayer | #endif
|
4121 | 12de9a39 | j_mayer | } |
4122 | 12de9a39 | j_mayer | |
4123 | 12de9a39 | j_mayer | /* mfsrin */
|
4124 | e8eaa2c0 | Blue Swirl | static void gen_mfsrin_64b(DisasContext *ctx) |
4125 | 12de9a39 | j_mayer | { |
4126 | 12de9a39 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
4127 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4128 | 12de9a39 | j_mayer | #else
|
4129 | 74d37793 | aurel32 | TCGv t0; |
4130 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
4131 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4132 | 12de9a39 | j_mayer | return;
|
4133 | 12de9a39 | j_mayer | } |
4134 | 74d37793 | aurel32 | t0 = tcg_temp_new(); |
4135 | 74d37793 | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
|
4136 | 74d37793 | aurel32 | tcg_gen_andi_tl(t0, t0, 0xF);
|
4137 | f6b868fc | blueswir1 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0); |
4138 | 74d37793 | aurel32 | tcg_temp_free(t0); |
4139 | 12de9a39 | j_mayer | #endif
|
4140 | 12de9a39 | j_mayer | } |
4141 | 12de9a39 | j_mayer | |
4142 | 12de9a39 | j_mayer | /* mtsr */
|
4143 | e8eaa2c0 | Blue Swirl | static void gen_mtsr_64b(DisasContext *ctx) |
4144 | 12de9a39 | j_mayer | { |
4145 | 12de9a39 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
4146 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4147 | 12de9a39 | j_mayer | #else
|
4148 | 74d37793 | aurel32 | TCGv t0; |
4149 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
4150 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4151 | 12de9a39 | j_mayer | return;
|
4152 | 12de9a39 | j_mayer | } |
4153 | 74d37793 | aurel32 | t0 = tcg_const_tl(SR(ctx->opcode)); |
4154 | f6b868fc | blueswir1 | gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]); |
4155 | 74d37793 | aurel32 | tcg_temp_free(t0); |
4156 | 12de9a39 | j_mayer | #endif
|
4157 | 12de9a39 | j_mayer | } |
4158 | 12de9a39 | j_mayer | |
4159 | 12de9a39 | j_mayer | /* mtsrin */
|
4160 | e8eaa2c0 | Blue Swirl | static void gen_mtsrin_64b(DisasContext *ctx) |
4161 | 12de9a39 | j_mayer | { |
4162 | 12de9a39 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
4163 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4164 | 12de9a39 | j_mayer | #else
|
4165 | 74d37793 | aurel32 | TCGv t0; |
4166 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
4167 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4168 | 12de9a39 | j_mayer | return;
|
4169 | 12de9a39 | j_mayer | } |
4170 | 74d37793 | aurel32 | t0 = tcg_temp_new(); |
4171 | 74d37793 | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
|
4172 | 74d37793 | aurel32 | tcg_gen_andi_tl(t0, t0, 0xF);
|
4173 | f6b868fc | blueswir1 | gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]); |
4174 | 74d37793 | aurel32 | tcg_temp_free(t0); |
4175 | 12de9a39 | j_mayer | #endif
|
4176 | 12de9a39 | j_mayer | } |
4177 | f6b868fc | blueswir1 | |
4178 | f6b868fc | blueswir1 | /* slbmte */
|
4179 | e8eaa2c0 | Blue Swirl | static void gen_slbmte(DisasContext *ctx) |
4180 | f6b868fc | blueswir1 | { |
4181 | f6b868fc | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
4182 | f6b868fc | blueswir1 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4183 | f6b868fc | blueswir1 | #else
|
4184 | f6b868fc | blueswir1 | if (unlikely(!ctx->mem_idx)) {
|
4185 | f6b868fc | blueswir1 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4186 | f6b868fc | blueswir1 | return;
|
4187 | f6b868fc | blueswir1 | } |
4188 | f6b868fc | blueswir1 | gen_helper_store_slb(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
4189 | f6b868fc | blueswir1 | #endif
|
4190 | f6b868fc | blueswir1 | } |
4191 | f6b868fc | blueswir1 | |
4192 | 12de9a39 | j_mayer | #endif /* defined(TARGET_PPC64) */ |
4193 | 12de9a39 | j_mayer | |
4194 | 79aceca5 | bellard | /*** Lookaside buffer management ***/
|
4195 | 76db3ba4 | aurel32 | /* Optional & mem_idx only: */
|
4196 | 99e300ef | Blue Swirl | |
4197 | 54623277 | Blue Swirl | /* tlbia */
|
4198 | 99e300ef | Blue Swirl | static void gen_tlbia(DisasContext *ctx) |
4199 | 79aceca5 | bellard | { |
4200 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
4201 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
4202 | 9a64fbe4 | bellard | #else
|
4203 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
4204 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
4205 | 9fddaa0c | bellard | return;
|
4206 | 9a64fbe4 | bellard | } |
4207 | 74d37793 | aurel32 | gen_helper_tlbia(); |
4208 | 9a64fbe4 | bellard | #endif
|
4209 | 79aceca5 | bellard | } |
4210 | 79aceca5 | bellard | |
4211 | bf14b1ce | blueswir1 | /* tlbiel */
|
4212 | 99e300ef | Blue Swirl | static void gen_tlbiel(DisasContext *ctx) |
4213 | bf14b1ce | blueswir1 | { |
4214 | bf14b1ce | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
4215 | bf14b1ce | blueswir1 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
4216 | bf14b1ce | blueswir1 | #else
|
4217 | bf14b1ce | blueswir1 | if (unlikely(!ctx->mem_idx)) {
|
4218 | bf14b1ce | blueswir1 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
4219 | bf14b1ce | blueswir1 | return;
|
4220 | bf14b1ce | blueswir1 | } |
4221 | bf14b1ce | blueswir1 | gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]); |
4222 | bf14b1ce | blueswir1 | #endif
|
4223 | bf14b1ce | blueswir1 | } |
4224 | bf14b1ce | blueswir1 | |
4225 | 79aceca5 | bellard | /* tlbie */
|
4226 | 99e300ef | Blue Swirl | static void gen_tlbie(DisasContext *ctx) |
4227 | 79aceca5 | bellard | { |
4228 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
4229 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
4230 | 9a64fbe4 | bellard | #else
|
4231 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
4232 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
4233 | 9fddaa0c | bellard | return;
|
4234 | 9a64fbe4 | bellard | } |
4235 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
4236 | 74d37793 | aurel32 | if (!ctx->sf_mode) {
|
4237 | 74d37793 | aurel32 | TCGv t0 = tcg_temp_new(); |
4238 | 74d37793 | aurel32 | tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); |
4239 | 74d37793 | aurel32 | gen_helper_tlbie(t0); |
4240 | 74d37793 | aurel32 | tcg_temp_free(t0); |
4241 | 74d37793 | aurel32 | } else
|
4242 | d9bce9d9 | j_mayer | #endif
|
4243 | 74d37793 | aurel32 | gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]); |
4244 | 9a64fbe4 | bellard | #endif
|
4245 | 79aceca5 | bellard | } |
4246 | 79aceca5 | bellard | |
4247 | 79aceca5 | bellard | /* tlbsync */
|
4248 | 99e300ef | Blue Swirl | static void gen_tlbsync(DisasContext *ctx) |
4249 | 79aceca5 | bellard | { |
4250 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
4251 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
4252 | 9a64fbe4 | bellard | #else
|
4253 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
4254 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
4255 | 9fddaa0c | bellard | return;
|
4256 | 9a64fbe4 | bellard | } |
4257 | 9a64fbe4 | bellard | /* This has no effect: it should ensure that all previous
|
4258 | 9a64fbe4 | bellard | * tlbie have completed
|
4259 | 9a64fbe4 | bellard | */
|
4260 | e06fcd75 | aurel32 | gen_stop_exception(ctx); |
4261 | 9a64fbe4 | bellard | #endif
|
4262 | 79aceca5 | bellard | } |
4263 | 79aceca5 | bellard | |
4264 | 426613db | j_mayer | #if defined(TARGET_PPC64)
|
4265 | 426613db | j_mayer | /* slbia */
|
4266 | 99e300ef | Blue Swirl | static void gen_slbia(DisasContext *ctx) |
4267 | 426613db | j_mayer | { |
4268 | 426613db | j_mayer | #if defined(CONFIG_USER_ONLY)
|
4269 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
4270 | 426613db | j_mayer | #else
|
4271 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
4272 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
4273 | 426613db | j_mayer | return;
|
4274 | 426613db | j_mayer | } |
4275 | 74d37793 | aurel32 | gen_helper_slbia(); |
4276 | 426613db | j_mayer | #endif
|
4277 | 426613db | j_mayer | } |
4278 | 426613db | j_mayer | |
4279 | 426613db | j_mayer | /* slbie */
|
4280 | 99e300ef | Blue Swirl | static void gen_slbie(DisasContext *ctx) |
4281 | 426613db | j_mayer | { |
4282 | 426613db | j_mayer | #if defined(CONFIG_USER_ONLY)
|
4283 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
4284 | 426613db | j_mayer | #else
|
4285 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
4286 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
4287 | 426613db | j_mayer | return;
|
4288 | 426613db | j_mayer | } |
4289 | 74d37793 | aurel32 | gen_helper_slbie(cpu_gpr[rB(ctx->opcode)]); |
4290 | 426613db | j_mayer | #endif
|
4291 | 426613db | j_mayer | } |
4292 | 426613db | j_mayer | #endif
|
4293 | 426613db | j_mayer | |
4294 | 79aceca5 | bellard | /*** External control ***/
|
4295 | 79aceca5 | bellard | /* Optional: */
|
4296 | 99e300ef | Blue Swirl | |
4297 | 54623277 | Blue Swirl | /* eciwx */
|
4298 | 99e300ef | Blue Swirl | static void gen_eciwx(DisasContext *ctx) |
4299 | 79aceca5 | bellard | { |
4300 | 76db3ba4 | aurel32 | TCGv t0; |
4301 | fa407c03 | aurel32 | /* Should check EAR[E] ! */
|
4302 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_EXT); |
4303 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
4304 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
4305 | fa407c03 | aurel32 | gen_check_align(ctx, t0, 0x03);
|
4306 | 76db3ba4 | aurel32 | gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0); |
4307 | fa407c03 | aurel32 | tcg_temp_free(t0); |
4308 | 76a66253 | j_mayer | } |
4309 | 76a66253 | j_mayer | |
4310 | 76a66253 | j_mayer | /* ecowx */
|
4311 | 99e300ef | Blue Swirl | static void gen_ecowx(DisasContext *ctx) |
4312 | 76a66253 | j_mayer | { |
4313 | 76db3ba4 | aurel32 | TCGv t0; |
4314 | fa407c03 | aurel32 | /* Should check EAR[E] ! */
|
4315 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_EXT); |
4316 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
4317 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
4318 | fa407c03 | aurel32 | gen_check_align(ctx, t0, 0x03);
|
4319 | 76db3ba4 | aurel32 | gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0); |
4320 | fa407c03 | aurel32 | tcg_temp_free(t0); |
4321 | 76a66253 | j_mayer | } |
4322 | 76a66253 | j_mayer | |
4323 | 76a66253 | j_mayer | /* PowerPC 601 specific instructions */
|
4324 | 99e300ef | Blue Swirl | |
4325 | 54623277 | Blue Swirl | /* abs - abs. */
|
4326 | 99e300ef | Blue Swirl | static void gen_abs(DisasContext *ctx) |
4327 | 76a66253 | j_mayer | { |
4328 | 22e0e173 | aurel32 | int l1 = gen_new_label();
|
4329 | 22e0e173 | aurel32 | int l2 = gen_new_label();
|
4330 | 22e0e173 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
|
4331 | 22e0e173 | aurel32 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
4332 | 22e0e173 | aurel32 | tcg_gen_br(l2); |
4333 | 22e0e173 | aurel32 | gen_set_label(l1); |
4334 | 22e0e173 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
4335 | 22e0e173 | aurel32 | gen_set_label(l2); |
4336 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4337 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
4338 | 76a66253 | j_mayer | } |
4339 | 76a66253 | j_mayer | |
4340 | 76a66253 | j_mayer | /* abso - abso. */
|
4341 | 99e300ef | Blue Swirl | static void gen_abso(DisasContext *ctx) |
4342 | 76a66253 | j_mayer | { |
4343 | 22e0e173 | aurel32 | int l1 = gen_new_label();
|
4344 | 22e0e173 | aurel32 | int l2 = gen_new_label();
|
4345 | 22e0e173 | aurel32 | int l3 = gen_new_label();
|
4346 | 22e0e173 | aurel32 | /* Start with XER OV disabled, the most likely case */
|
4347 | 22e0e173 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
|
4348 | 22e0e173 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
|
4349 | 22e0e173 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
|
4350 | 22e0e173 | aurel32 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); |
4351 | 22e0e173 | aurel32 | tcg_gen_br(l2); |
4352 | 22e0e173 | aurel32 | gen_set_label(l1); |
4353 | 22e0e173 | aurel32 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
4354 | 22e0e173 | aurel32 | tcg_gen_br(l3); |
4355 | 22e0e173 | aurel32 | gen_set_label(l2); |
4356 | 22e0e173 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
4357 | 22e0e173 | aurel32 | gen_set_label(l3); |
4358 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4359 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
4360 | 76a66253 | j_mayer | } |
4361 | 76a66253 | j_mayer | |
4362 | 76a66253 | j_mayer | /* clcs */
|
4363 | 99e300ef | Blue Swirl | static void gen_clcs(DisasContext *ctx) |
4364 | 76a66253 | j_mayer | { |
4365 | 22e0e173 | aurel32 | TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); |
4366 | 22e0e173 | aurel32 | gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], t0); |
4367 | 22e0e173 | aurel32 | tcg_temp_free_i32(t0); |
4368 | c7697e1f | j_mayer | /* Rc=1 sets CR0 to an undefined state */
|
4369 | 76a66253 | j_mayer | } |
4370 | 76a66253 | j_mayer | |
4371 | 76a66253 | j_mayer | /* div - div. */
|
4372 | 99e300ef | Blue Swirl | static void gen_div(DisasContext *ctx) |
4373 | 76a66253 | j_mayer | { |
4374 | 22e0e173 | aurel32 | gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
4375 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4376 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
4377 | 76a66253 | j_mayer | } |
4378 | 76a66253 | j_mayer | |
4379 | 76a66253 | j_mayer | /* divo - divo. */
|
4380 | 99e300ef | Blue Swirl | static void gen_divo(DisasContext *ctx) |
4381 | 76a66253 | j_mayer | { |
4382 | 22e0e173 | aurel32 | gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
4383 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4384 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
4385 | 76a66253 | j_mayer | } |
4386 | 76a66253 | j_mayer | |
4387 | 76a66253 | j_mayer | /* divs - divs. */
|
4388 | 99e300ef | Blue Swirl | static void gen_divs(DisasContext *ctx) |
4389 | 76a66253 | j_mayer | { |
4390 | 22e0e173 | aurel32 | gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
4391 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4392 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
4393 | 76a66253 | j_mayer | } |
4394 | 76a66253 | j_mayer | |
4395 | 76a66253 | j_mayer | /* divso - divso. */
|
4396 | 99e300ef | Blue Swirl | static void gen_divso(DisasContext *ctx) |
4397 | 76a66253 | j_mayer | { |
4398 | 22e0e173 | aurel32 | gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
4399 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4400 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
4401 | 76a66253 | j_mayer | } |
4402 | 76a66253 | j_mayer | |
4403 | 76a66253 | j_mayer | /* doz - doz. */
|
4404 | 99e300ef | Blue Swirl | static void gen_doz(DisasContext *ctx) |
4405 | 76a66253 | j_mayer | { |
4406 | 22e0e173 | aurel32 | int l1 = gen_new_label();
|
4407 | 22e0e173 | aurel32 | int l2 = gen_new_label();
|
4408 | 22e0e173 | aurel32 | tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); |
4409 | 22e0e173 | aurel32 | tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
4410 | 22e0e173 | aurel32 | tcg_gen_br(l2); |
4411 | 22e0e173 | aurel32 | gen_set_label(l1); |
4412 | 22e0e173 | aurel32 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
|
4413 | 22e0e173 | aurel32 | gen_set_label(l2); |
4414 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4415 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
4416 | 76a66253 | j_mayer | } |
4417 | 76a66253 | j_mayer | |
4418 | 76a66253 | j_mayer | /* dozo - dozo. */
|
4419 | 99e300ef | Blue Swirl | static void gen_dozo(DisasContext *ctx) |
4420 | 76a66253 | j_mayer | { |
4421 | 22e0e173 | aurel32 | int l1 = gen_new_label();
|
4422 | 22e0e173 | aurel32 | int l2 = gen_new_label();
|
4423 | 22e0e173 | aurel32 | TCGv t0 = tcg_temp_new(); |
4424 | 22e0e173 | aurel32 | TCGv t1 = tcg_temp_new(); |
4425 | 22e0e173 | aurel32 | TCGv t2 = tcg_temp_new(); |
4426 | 22e0e173 | aurel32 | /* Start with XER OV disabled, the most likely case */
|
4427 | 22e0e173 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
|
4428 | 22e0e173 | aurel32 | tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); |
4429 | 22e0e173 | aurel32 | tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
4430 | 22e0e173 | aurel32 | tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
4431 | 22e0e173 | aurel32 | tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0); |
4432 | 22e0e173 | aurel32 | tcg_gen_andc_tl(t1, t1, t2); |
4433 | 22e0e173 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); |
4434 | 22e0e173 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
|
4435 | 22e0e173 | aurel32 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); |
4436 | 22e0e173 | aurel32 | tcg_gen_br(l2); |
4437 | 22e0e173 | aurel32 | gen_set_label(l1); |
4438 | 22e0e173 | aurel32 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
|
4439 | 22e0e173 | aurel32 | gen_set_label(l2); |
4440 | 22e0e173 | aurel32 | tcg_temp_free(t0); |
4441 | 22e0e173 | aurel32 | tcg_temp_free(t1); |
4442 | 22e0e173 | aurel32 | tcg_temp_free(t2); |
4443 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4444 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
4445 | 76a66253 | j_mayer | } |
4446 | 76a66253 | j_mayer | |
4447 | 76a66253 | j_mayer | /* dozi */
|
4448 | 99e300ef | Blue Swirl | static void gen_dozi(DisasContext *ctx) |
4449 | 76a66253 | j_mayer | { |
4450 | 22e0e173 | aurel32 | target_long simm = SIMM(ctx->opcode); |
4451 | 22e0e173 | aurel32 | int l1 = gen_new_label();
|
4452 | 22e0e173 | aurel32 | int l2 = gen_new_label();
|
4453 | 22e0e173 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1); |
4454 | 22e0e173 | aurel32 | tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]); |
4455 | 22e0e173 | aurel32 | tcg_gen_br(l2); |
4456 | 22e0e173 | aurel32 | gen_set_label(l1); |
4457 | 22e0e173 | aurel32 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
|
4458 | 22e0e173 | aurel32 | gen_set_label(l2); |
4459 | 22e0e173 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
4460 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
4461 | 76a66253 | j_mayer | } |
4462 | 76a66253 | j_mayer | |
4463 | 76a66253 | j_mayer | /* lscbx - lscbx. */
|
4464 | 99e300ef | Blue Swirl | static void gen_lscbx(DisasContext *ctx) |
4465 | 76a66253 | j_mayer | { |
4466 | bdb4b689 | aurel32 | TCGv t0 = tcg_temp_new(); |
4467 | bdb4b689 | aurel32 | TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); |
4468 | bdb4b689 | aurel32 | TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); |
4469 | bdb4b689 | aurel32 | TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); |
4470 | 76a66253 | j_mayer | |
4471 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
4472 | 76a66253 | j_mayer | /* NIP cannot be restored if the memory exception comes from an helper */
|
4473 | d9bce9d9 | j_mayer | gen_update_nip(ctx, ctx->nip - 4);
|
4474 | bdb4b689 | aurel32 | gen_helper_lscbx(t0, t0, t1, t2, t3); |
4475 | bdb4b689 | aurel32 | tcg_temp_free_i32(t1); |
4476 | bdb4b689 | aurel32 | tcg_temp_free_i32(t2); |
4477 | bdb4b689 | aurel32 | tcg_temp_free_i32(t3); |
4478 | 3d7b417e | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
|
4479 | bdb4b689 | aurel32 | tcg_gen_or_tl(cpu_xer, cpu_xer, t0); |
4480 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4481 | bdb4b689 | aurel32 | gen_set_Rc0(ctx, t0); |
4482 | bdb4b689 | aurel32 | tcg_temp_free(t0); |
4483 | 76a66253 | j_mayer | } |
4484 | 76a66253 | j_mayer | |
4485 | 76a66253 | j_mayer | /* maskg - maskg. */
|
4486 | 99e300ef | Blue Swirl | static void gen_maskg(DisasContext *ctx) |
4487 | 76a66253 | j_mayer | { |
4488 | 22e0e173 | aurel32 | int l1 = gen_new_label();
|
4489 | 22e0e173 | aurel32 | TCGv t0 = tcg_temp_new(); |
4490 | 22e0e173 | aurel32 | TCGv t1 = tcg_temp_new(); |
4491 | 22e0e173 | aurel32 | TCGv t2 = tcg_temp_new(); |
4492 | 22e0e173 | aurel32 | TCGv t3 = tcg_temp_new(); |
4493 | 22e0e173 | aurel32 | tcg_gen_movi_tl(t3, 0xFFFFFFFF);
|
4494 | 22e0e173 | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
|
4495 | 22e0e173 | aurel32 | tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
|
4496 | 22e0e173 | aurel32 | tcg_gen_addi_tl(t2, t0, 1);
|
4497 | 22e0e173 | aurel32 | tcg_gen_shr_tl(t2, t3, t2); |
4498 | 22e0e173 | aurel32 | tcg_gen_shr_tl(t3, t3, t1); |
4499 | 22e0e173 | aurel32 | tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3); |
4500 | 22e0e173 | aurel32 | tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); |
4501 | 22e0e173 | aurel32 | tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
4502 | 22e0e173 | aurel32 | gen_set_label(l1); |
4503 | 22e0e173 | aurel32 | tcg_temp_free(t0); |
4504 | 22e0e173 | aurel32 | tcg_temp_free(t1); |
4505 | 22e0e173 | aurel32 | tcg_temp_free(t2); |
4506 | 22e0e173 | aurel32 | tcg_temp_free(t3); |
4507 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4508 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
4509 | 76a66253 | j_mayer | } |
4510 | 76a66253 | j_mayer | |
4511 | 76a66253 | j_mayer | /* maskir - maskir. */
|
4512 | 99e300ef | Blue Swirl | static void gen_maskir(DisasContext *ctx) |
4513 | 76a66253 | j_mayer | { |
4514 | 22e0e173 | aurel32 | TCGv t0 = tcg_temp_new(); |
4515 | 22e0e173 | aurel32 | TCGv t1 = tcg_temp_new(); |
4516 | 22e0e173 | aurel32 | tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
4517 | 22e0e173 | aurel32 | tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
4518 | 22e0e173 | aurel32 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
4519 | 22e0e173 | aurel32 | tcg_temp_free(t0); |
4520 | 22e0e173 | aurel32 | tcg_temp_free(t1); |
4521 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4522 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
4523 | 76a66253 | j_mayer | } |
4524 | 76a66253 | j_mayer | |
4525 | 76a66253 | j_mayer | /* mul - mul. */
|
4526 | 99e300ef | Blue Swirl | static void gen_mul(DisasContext *ctx) |
4527 | 76a66253 | j_mayer | { |
4528 | 22e0e173 | aurel32 | TCGv_i64 t0 = tcg_temp_new_i64(); |
4529 | 22e0e173 | aurel32 | TCGv_i64 t1 = tcg_temp_new_i64(); |
4530 | 22e0e173 | aurel32 | TCGv t2 = tcg_temp_new(); |
4531 | 22e0e173 | aurel32 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
4532 | 22e0e173 | aurel32 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); |
4533 | 22e0e173 | aurel32 | tcg_gen_mul_i64(t0, t0, t1); |
4534 | 22e0e173 | aurel32 | tcg_gen_trunc_i64_tl(t2, t0); |
4535 | 22e0e173 | aurel32 | gen_store_spr(SPR_MQ, t2); |
4536 | 22e0e173 | aurel32 | tcg_gen_shri_i64(t1, t0, 32);
|
4537 | 22e0e173 | aurel32 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); |
4538 | 22e0e173 | aurel32 | tcg_temp_free_i64(t0); |
4539 | 22e0e173 | aurel32 | tcg_temp_free_i64(t1); |
4540 | 22e0e173 | aurel32 | tcg_temp_free(t2); |
4541 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4542 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
4543 | 76a66253 | j_mayer | } |
4544 | 76a66253 | j_mayer | |
4545 | 76a66253 | j_mayer | /* mulo - mulo. */
|
4546 | 99e300ef | Blue Swirl | static void gen_mulo(DisasContext *ctx) |
4547 | 76a66253 | j_mayer | { |
4548 | 22e0e173 | aurel32 | int l1 = gen_new_label();
|
4549 | 22e0e173 | aurel32 | TCGv_i64 t0 = tcg_temp_new_i64(); |
4550 | 22e0e173 | aurel32 | TCGv_i64 t1 = tcg_temp_new_i64(); |
4551 | 22e0e173 | aurel32 | TCGv t2 = tcg_temp_new(); |
4552 | 22e0e173 | aurel32 | /* Start with XER OV disabled, the most likely case */
|
4553 | 22e0e173 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
|
4554 | 22e0e173 | aurel32 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
4555 | 22e0e173 | aurel32 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); |
4556 | 22e0e173 | aurel32 | tcg_gen_mul_i64(t0, t0, t1); |
4557 | 22e0e173 | aurel32 | tcg_gen_trunc_i64_tl(t2, t0); |
4558 | 22e0e173 | aurel32 | gen_store_spr(SPR_MQ, t2); |
4559 | 22e0e173 | aurel32 | tcg_gen_shri_i64(t1, t0, 32);
|
4560 | 22e0e173 | aurel32 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); |
4561 | 22e0e173 | aurel32 | tcg_gen_ext32s_i64(t1, t0); |
4562 | 22e0e173 | aurel32 | tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); |
4563 | 22e0e173 | aurel32 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); |
4564 | 22e0e173 | aurel32 | gen_set_label(l1); |
4565 | 22e0e173 | aurel32 | tcg_temp_free_i64(t0); |
4566 | 22e0e173 | aurel32 | tcg_temp_free_i64(t1); |
4567 | 22e0e173 | aurel32 | tcg_temp_free(t2); |
4568 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4569 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
4570 | 76a66253 | j_mayer | } |
4571 | 76a66253 | j_mayer | |
4572 | 76a66253 | j_mayer | /* nabs - nabs. */
|
4573 | 99e300ef | Blue Swirl | static void gen_nabs(DisasContext *ctx) |
4574 | 76a66253 | j_mayer | { |
4575 | 22e0e173 | aurel32 | int l1 = gen_new_label();
|
4576 | 22e0e173 | aurel32 | int l2 = gen_new_label();
|
4577 | 22e0e173 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
|
4578 | 22e0e173 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
4579 | 22e0e173 | aurel32 | tcg_gen_br(l2); |
4580 | 22e0e173 | aurel32 | gen_set_label(l1); |
4581 | 22e0e173 | aurel32 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
4582 | 22e0e173 | aurel32 | gen_set_label(l2); |
4583 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4584 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
4585 | 76a66253 | j_mayer | } |
4586 | 76a66253 | j_mayer | |
4587 | 76a66253 | j_mayer | /* nabso - nabso. */
|
4588 | 99e300ef | Blue Swirl | static void gen_nabso(DisasContext *ctx) |
4589 | 76a66253 | j_mayer | { |
4590 | 22e0e173 | aurel32 | int l1 = gen_new_label();
|
4591 | 22e0e173 | aurel32 | int l2 = gen_new_label();
|
4592 | 22e0e173 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
|
4593 | 22e0e173 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
4594 | 22e0e173 | aurel32 | tcg_gen_br(l2); |
4595 | 22e0e173 | aurel32 | gen_set_label(l1); |
4596 | 22e0e173 | aurel32 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
4597 | 22e0e173 | aurel32 | gen_set_label(l2); |
4598 | 22e0e173 | aurel32 | /* nabs never overflows */
|
4599 | 22e0e173 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
|
4600 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4601 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
4602 | 76a66253 | j_mayer | } |
4603 | 76a66253 | j_mayer | |
4604 | 76a66253 | j_mayer | /* rlmi - rlmi. */
|
4605 | 99e300ef | Blue Swirl | static void gen_rlmi(DisasContext *ctx) |
4606 | 76a66253 | j_mayer | { |
4607 | 7487953d | aurel32 | uint32_t mb = MB(ctx->opcode); |
4608 | 7487953d | aurel32 | uint32_t me = ME(ctx->opcode); |
4609 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
4610 | 7487953d | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
|
4611 | 7487953d | aurel32 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
4612 | 7487953d | aurel32 | tcg_gen_andi_tl(t0, t0, MASK(mb, me)); |
4613 | 7487953d | aurel32 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me)); |
4614 | 7487953d | aurel32 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0); |
4615 | 7487953d | aurel32 | tcg_temp_free(t0); |
4616 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4617 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
4618 | 76a66253 | j_mayer | } |
4619 | 76a66253 | j_mayer | |
4620 | 76a66253 | j_mayer | /* rrib - rrib. */
|
4621 | 99e300ef | Blue Swirl | static void gen_rrib(DisasContext *ctx) |
4622 | 76a66253 | j_mayer | { |
4623 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
4624 | 7487953d | aurel32 | TCGv t1 = tcg_temp_new(); |
4625 | 7487953d | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
|
4626 | 7487953d | aurel32 | tcg_gen_movi_tl(t1, 0x80000000);
|
4627 | 7487953d | aurel32 | tcg_gen_shr_tl(t1, t1, t0); |
4628 | 7487953d | aurel32 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
4629 | 7487953d | aurel32 | tcg_gen_and_tl(t0, t0, t1); |
4630 | 7487953d | aurel32 | tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1); |
4631 | 7487953d | aurel32 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
4632 | 7487953d | aurel32 | tcg_temp_free(t0); |
4633 | 7487953d | aurel32 | tcg_temp_free(t1); |
4634 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4635 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
4636 | 76a66253 | j_mayer | } |
4637 | 76a66253 | j_mayer | |
4638 | 76a66253 | j_mayer | /* sle - sle. */
|
4639 | 99e300ef | Blue Swirl | static void gen_sle(DisasContext *ctx) |
4640 | 76a66253 | j_mayer | { |
4641 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
4642 | 7487953d | aurel32 | TCGv t1 = tcg_temp_new(); |
4643 | 7487953d | aurel32 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
|
4644 | 7487953d | aurel32 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); |
4645 | 7487953d | aurel32 | tcg_gen_subfi_tl(t1, 32, t1);
|
4646 | 7487953d | aurel32 | tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); |
4647 | 7487953d | aurel32 | tcg_gen_or_tl(t1, t0, t1); |
4648 | 7487953d | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
4649 | 7487953d | aurel32 | gen_store_spr(SPR_MQ, t1); |
4650 | 7487953d | aurel32 | tcg_temp_free(t0); |
4651 | 7487953d | aurel32 | tcg_temp_free(t1); |
4652 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4653 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
4654 | 76a66253 | j_mayer | } |
4655 | 76a66253 | j_mayer | |
4656 | 76a66253 | j_mayer | /* sleq - sleq. */
|
4657 | 99e300ef | Blue Swirl | static void gen_sleq(DisasContext *ctx) |
4658 | 76a66253 | j_mayer | { |
4659 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
4660 | 7487953d | aurel32 | TCGv t1 = tcg_temp_new(); |
4661 | 7487953d | aurel32 | TCGv t2 = tcg_temp_new(); |
4662 | 7487953d | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
|
4663 | 7487953d | aurel32 | tcg_gen_movi_tl(t2, 0xFFFFFFFF);
|
4664 | 7487953d | aurel32 | tcg_gen_shl_tl(t2, t2, t0); |
4665 | 7487953d | aurel32 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
4666 | 7487953d | aurel32 | gen_load_spr(t1, SPR_MQ); |
4667 | 7487953d | aurel32 | gen_store_spr(SPR_MQ, t0); |
4668 | 7487953d | aurel32 | tcg_gen_and_tl(t0, t0, t2); |
4669 | 7487953d | aurel32 | tcg_gen_andc_tl(t1, t1, t2); |
4670 | 7487953d | aurel32 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
4671 | 7487953d | aurel32 | tcg_temp_free(t0); |
4672 | 7487953d | aurel32 | tcg_temp_free(t1); |
4673 | 7487953d | aurel32 | tcg_temp_free(t2); |
4674 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4675 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
4676 | 76a66253 | j_mayer | } |
4677 | 76a66253 | j_mayer | |
4678 | 76a66253 | j_mayer | /* sliq - sliq. */
|
4679 | 99e300ef | Blue Swirl | static void gen_sliq(DisasContext *ctx) |
4680 | 76a66253 | j_mayer | { |
4681 | 7487953d | aurel32 | int sh = SH(ctx->opcode);
|
4682 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
4683 | 7487953d | aurel32 | TCGv t1 = tcg_temp_new(); |
4684 | 7487953d | aurel32 | tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
4685 | 7487953d | aurel32 | tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
|
4686 | 7487953d | aurel32 | tcg_gen_or_tl(t1, t0, t1); |
4687 | 7487953d | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
4688 | 7487953d | aurel32 | gen_store_spr(SPR_MQ, t1); |
4689 | 7487953d | aurel32 | tcg_temp_free(t0); |
4690 | 7487953d | aurel32 | tcg_temp_free(t1); |
4691 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4692 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
4693 | 76a66253 | j_mayer | } |
4694 | 76a66253 | j_mayer | |
4695 | 76a66253 | j_mayer | /* slliq - slliq. */
|
4696 | 99e300ef | Blue Swirl | static void gen_slliq(DisasContext *ctx) |
4697 | 76a66253 | j_mayer | { |
4698 | 7487953d | aurel32 | int sh = SH(ctx->opcode);
|
4699 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
4700 | 7487953d | aurel32 | TCGv t1 = tcg_temp_new(); |
4701 | 7487953d | aurel32 | tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
4702 | 7487953d | aurel32 | gen_load_spr(t1, SPR_MQ); |
4703 | 7487953d | aurel32 | gen_store_spr(SPR_MQ, t0); |
4704 | 7487953d | aurel32 | tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
|
4705 | 7487953d | aurel32 | tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
|
4706 | 7487953d | aurel32 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
4707 | 7487953d | aurel32 | tcg_temp_free(t0); |
4708 | 7487953d | aurel32 | tcg_temp_free(t1); |
4709 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4710 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
4711 | 76a66253 | j_mayer | } |
4712 | 76a66253 | j_mayer | |
4713 | 76a66253 | j_mayer | /* sllq - sllq. */
|
4714 | 99e300ef | Blue Swirl | static void gen_sllq(DisasContext *ctx) |
4715 | 76a66253 | j_mayer | { |
4716 | 7487953d | aurel32 | int l1 = gen_new_label();
|
4717 | 7487953d | aurel32 | int l2 = gen_new_label();
|
4718 | 7487953d | aurel32 | TCGv t0 = tcg_temp_local_new(); |
4719 | 7487953d | aurel32 | TCGv t1 = tcg_temp_local_new(); |
4720 | 7487953d | aurel32 | TCGv t2 = tcg_temp_local_new(); |
4721 | 7487953d | aurel32 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
|
4722 | 7487953d | aurel32 | tcg_gen_movi_tl(t1, 0xFFFFFFFF);
|
4723 | 7487953d | aurel32 | tcg_gen_shl_tl(t1, t1, t2); |
4724 | 7487953d | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
|
4725 | 7487953d | aurel32 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
|
4726 | 7487953d | aurel32 | gen_load_spr(t0, SPR_MQ); |
4727 | 7487953d | aurel32 | tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
4728 | 7487953d | aurel32 | tcg_gen_br(l2); |
4729 | 7487953d | aurel32 | gen_set_label(l1); |
4730 | 7487953d | aurel32 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); |
4731 | 7487953d | aurel32 | gen_load_spr(t2, SPR_MQ); |
4732 | 7487953d | aurel32 | tcg_gen_andc_tl(t1, t2, t1); |
4733 | 7487953d | aurel32 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
4734 | 7487953d | aurel32 | gen_set_label(l2); |
4735 | 7487953d | aurel32 | tcg_temp_free(t0); |
4736 | 7487953d | aurel32 | tcg_temp_free(t1); |
4737 | 7487953d | aurel32 | tcg_temp_free(t2); |
4738 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4739 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
4740 | 76a66253 | j_mayer | } |
4741 | 76a66253 | j_mayer | |
4742 | 76a66253 | j_mayer | /* slq - slq. */
|
4743 | 99e300ef | Blue Swirl | static void gen_slq(DisasContext *ctx) |
4744 | 76a66253 | j_mayer | { |
4745 | 7487953d | aurel32 | int l1 = gen_new_label();
|
4746 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
4747 | 7487953d | aurel32 | TCGv t1 = tcg_temp_new(); |
4748 | 7487953d | aurel32 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
|
4749 | 7487953d | aurel32 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); |
4750 | 7487953d | aurel32 | tcg_gen_subfi_tl(t1, 32, t1);
|
4751 | 7487953d | aurel32 | tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); |
4752 | 7487953d | aurel32 | tcg_gen_or_tl(t1, t0, t1); |
4753 | 7487953d | aurel32 | gen_store_spr(SPR_MQ, t1); |
4754 | 7487953d | aurel32 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
|
4755 | 7487953d | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
4756 | 7487953d | aurel32 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
|
4757 | 7487953d | aurel32 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
|
4758 | 7487953d | aurel32 | gen_set_label(l1); |
4759 | 7487953d | aurel32 | tcg_temp_free(t0); |
4760 | 7487953d | aurel32 | tcg_temp_free(t1); |
4761 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4762 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
4763 | 76a66253 | j_mayer | } |
4764 | 76a66253 | j_mayer | |
4765 | d9bce9d9 | j_mayer | /* sraiq - sraiq. */
|
4766 | 99e300ef | Blue Swirl | static void gen_sraiq(DisasContext *ctx) |
4767 | 76a66253 | j_mayer | { |
4768 | 7487953d | aurel32 | int sh = SH(ctx->opcode);
|
4769 | 7487953d | aurel32 | int l1 = gen_new_label();
|
4770 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
4771 | 7487953d | aurel32 | TCGv t1 = tcg_temp_new(); |
4772 | 7487953d | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
4773 | 7487953d | aurel32 | tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
|
4774 | 7487953d | aurel32 | tcg_gen_or_tl(t0, t0, t1); |
4775 | 7487953d | aurel32 | gen_store_spr(SPR_MQ, t0); |
4776 | 7487953d | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
|
4777 | 7487953d | aurel32 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
|
4778 | 7487953d | aurel32 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
|
4779 | 7487953d | aurel32 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
|
4780 | 7487953d | aurel32 | gen_set_label(l1); |
4781 | 7487953d | aurel32 | tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); |
4782 | 7487953d | aurel32 | tcg_temp_free(t0); |
4783 | 7487953d | aurel32 | tcg_temp_free(t1); |
4784 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4785 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
4786 | 76a66253 | j_mayer | } |
4787 | 76a66253 | j_mayer | |
4788 | 76a66253 | j_mayer | /* sraq - sraq. */
|
4789 | 99e300ef | Blue Swirl | static void gen_sraq(DisasContext *ctx) |
4790 | 76a66253 | j_mayer | { |
4791 | 7487953d | aurel32 | int l1 = gen_new_label();
|
4792 | 7487953d | aurel32 | int l2 = gen_new_label();
|
4793 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
4794 | 7487953d | aurel32 | TCGv t1 = tcg_temp_local_new(); |
4795 | 7487953d | aurel32 | TCGv t2 = tcg_temp_local_new(); |
4796 | 7487953d | aurel32 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
|
4797 | 7487953d | aurel32 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); |
4798 | 7487953d | aurel32 | tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2); |
4799 | 7487953d | aurel32 | tcg_gen_subfi_tl(t2, 32, t2);
|
4800 | 7487953d | aurel32 | tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2); |
4801 | 7487953d | aurel32 | tcg_gen_or_tl(t0, t0, t2); |
4802 | 7487953d | aurel32 | gen_store_spr(SPR_MQ, t0); |
4803 | 7487953d | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
|
4804 | 7487953d | aurel32 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
|
4805 | 7487953d | aurel32 | tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]); |
4806 | 7487953d | aurel32 | tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
|
4807 | 7487953d | aurel32 | gen_set_label(l1); |
4808 | 7487953d | aurel32 | tcg_temp_free(t0); |
4809 | 7487953d | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); |
4810 | 7487953d | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
|
4811 | 7487953d | aurel32 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
|
4812 | 7487953d | aurel32 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
|
4813 | 7487953d | aurel32 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
|
4814 | 7487953d | aurel32 | gen_set_label(l2); |
4815 | 7487953d | aurel32 | tcg_temp_free(t1); |
4816 | 7487953d | aurel32 | tcg_temp_free(t2); |
4817 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4818 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
4819 | 76a66253 | j_mayer | } |
4820 | 76a66253 | j_mayer | |
4821 | 76a66253 | j_mayer | /* sre - sre. */
|
4822 | 99e300ef | Blue Swirl | static void gen_sre(DisasContext *ctx) |
4823 | 76a66253 | j_mayer | { |
4824 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
4825 | 7487953d | aurel32 | TCGv t1 = tcg_temp_new(); |
4826 | 7487953d | aurel32 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
|
4827 | 7487953d | aurel32 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); |
4828 | 7487953d | aurel32 | tcg_gen_subfi_tl(t1, 32, t1);
|
4829 | 7487953d | aurel32 | tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); |
4830 | 7487953d | aurel32 | tcg_gen_or_tl(t1, t0, t1); |
4831 | 7487953d | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
4832 | 7487953d | aurel32 | gen_store_spr(SPR_MQ, t1); |
4833 | 7487953d | aurel32 | tcg_temp_free(t0); |
4834 | 7487953d | aurel32 | tcg_temp_free(t1); |
4835 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4836 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
4837 | 76a66253 | j_mayer | } |
4838 | 76a66253 | j_mayer | |
4839 | 76a66253 | j_mayer | /* srea - srea. */
|
4840 | 99e300ef | Blue Swirl | static void gen_srea(DisasContext *ctx) |
4841 | 76a66253 | j_mayer | { |
4842 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
4843 | 7487953d | aurel32 | TCGv t1 = tcg_temp_new(); |
4844 | 7487953d | aurel32 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
|
4845 | 7487953d | aurel32 | tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); |
4846 | 7487953d | aurel32 | gen_store_spr(SPR_MQ, t0); |
4847 | 7487953d | aurel32 | tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1); |
4848 | 7487953d | aurel32 | tcg_temp_free(t0); |
4849 | 7487953d | aurel32 | tcg_temp_free(t1); |
4850 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4851 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
4852 | 76a66253 | j_mayer | } |
4853 | 76a66253 | j_mayer | |
4854 | 76a66253 | j_mayer | /* sreq */
|
4855 | 99e300ef | Blue Swirl | static void gen_sreq(DisasContext *ctx) |
4856 | 76a66253 | j_mayer | { |
4857 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
4858 | 7487953d | aurel32 | TCGv t1 = tcg_temp_new(); |
4859 | 7487953d | aurel32 | TCGv t2 = tcg_temp_new(); |
4860 | 7487953d | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
|
4861 | 7487953d | aurel32 | tcg_gen_movi_tl(t1, 0xFFFFFFFF);
|
4862 | 7487953d | aurel32 | tcg_gen_shr_tl(t1, t1, t0); |
4863 | 7487953d | aurel32 | tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
4864 | 7487953d | aurel32 | gen_load_spr(t2, SPR_MQ); |
4865 | 7487953d | aurel32 | gen_store_spr(SPR_MQ, t0); |
4866 | 7487953d | aurel32 | tcg_gen_and_tl(t0, t0, t1); |
4867 | 7487953d | aurel32 | tcg_gen_andc_tl(t2, t2, t1); |
4868 | 7487953d | aurel32 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); |
4869 | 7487953d | aurel32 | tcg_temp_free(t0); |
4870 | 7487953d | aurel32 | tcg_temp_free(t1); |
4871 | 7487953d | aurel32 | tcg_temp_free(t2); |
4872 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4873 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
4874 | 76a66253 | j_mayer | } |
4875 | 76a66253 | j_mayer | |
4876 | 76a66253 | j_mayer | /* sriq */
|
4877 | 99e300ef | Blue Swirl | static void gen_sriq(DisasContext *ctx) |
4878 | 76a66253 | j_mayer | { |
4879 | 7487953d | aurel32 | int sh = SH(ctx->opcode);
|
4880 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
4881 | 7487953d | aurel32 | TCGv t1 = tcg_temp_new(); |
4882 | 7487953d | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
4883 | 7487953d | aurel32 | tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
|
4884 | 7487953d | aurel32 | tcg_gen_or_tl(t1, t0, t1); |
4885 | 7487953d | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
4886 | 7487953d | aurel32 | gen_store_spr(SPR_MQ, t1); |
4887 | 7487953d | aurel32 | tcg_temp_free(t0); |
4888 | 7487953d | aurel32 | tcg_temp_free(t1); |
4889 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4890 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
4891 | 76a66253 | j_mayer | } |
4892 | 76a66253 | j_mayer | |
4893 | 76a66253 | j_mayer | /* srliq */
|
4894 | 99e300ef | Blue Swirl | static void gen_srliq(DisasContext *ctx) |
4895 | 76a66253 | j_mayer | { |
4896 | 7487953d | aurel32 | int sh = SH(ctx->opcode);
|
4897 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
4898 | 7487953d | aurel32 | TCGv t1 = tcg_temp_new(); |
4899 | 7487953d | aurel32 | tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
4900 | 7487953d | aurel32 | gen_load_spr(t1, SPR_MQ); |
4901 | 7487953d | aurel32 | gen_store_spr(SPR_MQ, t0); |
4902 | 7487953d | aurel32 | tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
|
4903 | 7487953d | aurel32 | tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
|
4904 | 7487953d | aurel32 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
4905 | 7487953d | aurel32 | tcg_temp_free(t0); |
4906 | 7487953d | aurel32 | tcg_temp_free(t1); |
4907 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4908 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
4909 | 76a66253 | j_mayer | } |
4910 | 76a66253 | j_mayer | |
4911 | 76a66253 | j_mayer | /* srlq */
|
4912 | 99e300ef | Blue Swirl | static void gen_srlq(DisasContext *ctx) |
4913 | 76a66253 | j_mayer | { |
4914 | 7487953d | aurel32 | int l1 = gen_new_label();
|
4915 | 7487953d | aurel32 | int l2 = gen_new_label();
|
4916 | 7487953d | aurel32 | TCGv t0 = tcg_temp_local_new(); |
4917 | 7487953d | aurel32 | TCGv t1 = tcg_temp_local_new(); |
4918 | 7487953d | aurel32 | TCGv t2 = tcg_temp_local_new(); |
4919 | 7487953d | aurel32 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
|
4920 | 7487953d | aurel32 | tcg_gen_movi_tl(t1, 0xFFFFFFFF);
|
4921 | 7487953d | aurel32 | tcg_gen_shr_tl(t2, t1, t2); |
4922 | 7487953d | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
|
4923 | 7487953d | aurel32 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
|
4924 | 7487953d | aurel32 | gen_load_spr(t0, SPR_MQ); |
4925 | 7487953d | aurel32 | tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); |
4926 | 7487953d | aurel32 | tcg_gen_br(l2); |
4927 | 7487953d | aurel32 | gen_set_label(l1); |
4928 | 7487953d | aurel32 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); |
4929 | 7487953d | aurel32 | tcg_gen_and_tl(t0, t0, t2); |
4930 | 7487953d | aurel32 | gen_load_spr(t1, SPR_MQ); |
4931 | 7487953d | aurel32 | tcg_gen_andc_tl(t1, t1, t2); |
4932 | 7487953d | aurel32 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
4933 | 7487953d | aurel32 | gen_set_label(l2); |
4934 | 7487953d | aurel32 | tcg_temp_free(t0); |
4935 | 7487953d | aurel32 | tcg_temp_free(t1); |
4936 | 7487953d | aurel32 | tcg_temp_free(t2); |
4937 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4938 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
4939 | 76a66253 | j_mayer | } |
4940 | 76a66253 | j_mayer | |
4941 | 76a66253 | j_mayer | /* srq */
|
4942 | 99e300ef | Blue Swirl | static void gen_srq(DisasContext *ctx) |
4943 | 76a66253 | j_mayer | { |
4944 | 7487953d | aurel32 | int l1 = gen_new_label();
|
4945 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
4946 | 7487953d | aurel32 | TCGv t1 = tcg_temp_new(); |
4947 | 7487953d | aurel32 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
|
4948 | 7487953d | aurel32 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); |
4949 | 7487953d | aurel32 | tcg_gen_subfi_tl(t1, 32, t1);
|
4950 | 7487953d | aurel32 | tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); |
4951 | 7487953d | aurel32 | tcg_gen_or_tl(t1, t0, t1); |
4952 | 7487953d | aurel32 | gen_store_spr(SPR_MQ, t1); |
4953 | 7487953d | aurel32 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
|
4954 | 7487953d | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
4955 | 7487953d | aurel32 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
|
4956 | 7487953d | aurel32 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
|
4957 | 7487953d | aurel32 | gen_set_label(l1); |
4958 | 7487953d | aurel32 | tcg_temp_free(t0); |
4959 | 7487953d | aurel32 | tcg_temp_free(t1); |
4960 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4961 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
4962 | 76a66253 | j_mayer | } |
4963 | 76a66253 | j_mayer | |
4964 | 76a66253 | j_mayer | /* PowerPC 602 specific instructions */
|
4965 | 99e300ef | Blue Swirl | |
4966 | 54623277 | Blue Swirl | /* dsa */
|
4967 | 99e300ef | Blue Swirl | static void gen_dsa(DisasContext *ctx) |
4968 | 76a66253 | j_mayer | { |
4969 | 76a66253 | j_mayer | /* XXX: TODO */
|
4970 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
4971 | 76a66253 | j_mayer | } |
4972 | 76a66253 | j_mayer | |
4973 | 76a66253 | j_mayer | /* esa */
|
4974 | 99e300ef | Blue Swirl | static void gen_esa(DisasContext *ctx) |
4975 | 76a66253 | j_mayer | { |
4976 | 76a66253 | j_mayer | /* XXX: TODO */
|
4977 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
4978 | 76a66253 | j_mayer | } |
4979 | 76a66253 | j_mayer | |
4980 | 76a66253 | j_mayer | /* mfrom */
|
4981 | 99e300ef | Blue Swirl | static void gen_mfrom(DisasContext *ctx) |
4982 | 76a66253 | j_mayer | { |
4983 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
4984 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
4985 | 76a66253 | j_mayer | #else
|
4986 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
4987 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
4988 | 76a66253 | j_mayer | return;
|
4989 | 76a66253 | j_mayer | } |
4990 | cf02a65c | aurel32 | gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
4991 | 76a66253 | j_mayer | #endif
|
4992 | 76a66253 | j_mayer | } |
4993 | 76a66253 | j_mayer | |
4994 | 76a66253 | j_mayer | /* 602 - 603 - G2 TLB management */
|
4995 | e8eaa2c0 | Blue Swirl | |
4996 | 54623277 | Blue Swirl | /* tlbld */
|
4997 | e8eaa2c0 | Blue Swirl | static void gen_tlbld_6xx(DisasContext *ctx) |
4998 | 76a66253 | j_mayer | { |
4999 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5000 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5001 | 76a66253 | j_mayer | #else
|
5002 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5003 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5004 | 76a66253 | j_mayer | return;
|
5005 | 76a66253 | j_mayer | } |
5006 | 74d37793 | aurel32 | gen_helper_6xx_tlbd(cpu_gpr[rB(ctx->opcode)]); |
5007 | 76a66253 | j_mayer | #endif
|
5008 | 76a66253 | j_mayer | } |
5009 | 76a66253 | j_mayer | |
5010 | 76a66253 | j_mayer | /* tlbli */
|
5011 | e8eaa2c0 | Blue Swirl | static void gen_tlbli_6xx(DisasContext *ctx) |
5012 | 76a66253 | j_mayer | { |
5013 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5014 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5015 | 76a66253 | j_mayer | #else
|
5016 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5017 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5018 | 76a66253 | j_mayer | return;
|
5019 | 76a66253 | j_mayer | } |
5020 | 74d37793 | aurel32 | gen_helper_6xx_tlbi(cpu_gpr[rB(ctx->opcode)]); |
5021 | 76a66253 | j_mayer | #endif
|
5022 | 76a66253 | j_mayer | } |
5023 | 76a66253 | j_mayer | |
5024 | 7dbe11ac | j_mayer | /* 74xx TLB management */
|
5025 | e8eaa2c0 | Blue Swirl | |
5026 | 54623277 | Blue Swirl | /* tlbld */
|
5027 | e8eaa2c0 | Blue Swirl | static void gen_tlbld_74xx(DisasContext *ctx) |
5028 | 7dbe11ac | j_mayer | { |
5029 | 7dbe11ac | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5030 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5031 | 7dbe11ac | j_mayer | #else
|
5032 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5033 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5034 | 7dbe11ac | j_mayer | return;
|
5035 | 7dbe11ac | j_mayer | } |
5036 | 74d37793 | aurel32 | gen_helper_74xx_tlbd(cpu_gpr[rB(ctx->opcode)]); |
5037 | 7dbe11ac | j_mayer | #endif
|
5038 | 7dbe11ac | j_mayer | } |
5039 | 7dbe11ac | j_mayer | |
5040 | 7dbe11ac | j_mayer | /* tlbli */
|
5041 | e8eaa2c0 | Blue Swirl | static void gen_tlbli_74xx(DisasContext *ctx) |
5042 | 7dbe11ac | j_mayer | { |
5043 | 7dbe11ac | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5044 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5045 | 7dbe11ac | j_mayer | #else
|
5046 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5047 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5048 | 7dbe11ac | j_mayer | return;
|
5049 | 7dbe11ac | j_mayer | } |
5050 | 74d37793 | aurel32 | gen_helper_74xx_tlbi(cpu_gpr[rB(ctx->opcode)]); |
5051 | 7dbe11ac | j_mayer | #endif
|
5052 | 7dbe11ac | j_mayer | } |
5053 | 7dbe11ac | j_mayer | |
5054 | 76a66253 | j_mayer | /* POWER instructions not in PowerPC 601 */
|
5055 | 99e300ef | Blue Swirl | |
5056 | 54623277 | Blue Swirl | /* clf */
|
5057 | 99e300ef | Blue Swirl | static void gen_clf(DisasContext *ctx) |
5058 | 76a66253 | j_mayer | { |
5059 | 76a66253 | j_mayer | /* Cache line flush: implemented as no-op */
|
5060 | 76a66253 | j_mayer | } |
5061 | 76a66253 | j_mayer | |
5062 | 76a66253 | j_mayer | /* cli */
|
5063 | 99e300ef | Blue Swirl | static void gen_cli(DisasContext *ctx) |
5064 | 76a66253 | j_mayer | { |
5065 | 7f75ffd3 | blueswir1 | /* Cache line invalidate: privileged and treated as no-op */
|
5066 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5067 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5068 | 76a66253 | j_mayer | #else
|
5069 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5070 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5071 | 76a66253 | j_mayer | return;
|
5072 | 76a66253 | j_mayer | } |
5073 | 76a66253 | j_mayer | #endif
|
5074 | 76a66253 | j_mayer | } |
5075 | 76a66253 | j_mayer | |
5076 | 76a66253 | j_mayer | /* dclst */
|
5077 | 99e300ef | Blue Swirl | static void gen_dclst(DisasContext *ctx) |
5078 | 76a66253 | j_mayer | { |
5079 | 76a66253 | j_mayer | /* Data cache line store: treated as no-op */
|
5080 | 76a66253 | j_mayer | } |
5081 | 76a66253 | j_mayer | |
5082 | 99e300ef | Blue Swirl | static void gen_mfsri(DisasContext *ctx) |
5083 | 76a66253 | j_mayer | { |
5084 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5085 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5086 | 76a66253 | j_mayer | #else
|
5087 | 74d37793 | aurel32 | int ra = rA(ctx->opcode);
|
5088 | 74d37793 | aurel32 | int rd = rD(ctx->opcode);
|
5089 | 74d37793 | aurel32 | TCGv t0; |
5090 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5091 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5092 | 76a66253 | j_mayer | return;
|
5093 | 76a66253 | j_mayer | } |
5094 | 74d37793 | aurel32 | t0 = tcg_temp_new(); |
5095 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
5096 | 74d37793 | aurel32 | tcg_gen_shri_tl(t0, t0, 28);
|
5097 | 74d37793 | aurel32 | tcg_gen_andi_tl(t0, t0, 0xF);
|
5098 | 74d37793 | aurel32 | gen_helper_load_sr(cpu_gpr[rd], t0); |
5099 | 74d37793 | aurel32 | tcg_temp_free(t0); |
5100 | 76a66253 | j_mayer | if (ra != 0 && ra != rd) |
5101 | 74d37793 | aurel32 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]); |
5102 | 76a66253 | j_mayer | #endif
|
5103 | 76a66253 | j_mayer | } |
5104 | 76a66253 | j_mayer | |
5105 | 99e300ef | Blue Swirl | static void gen_rac(DisasContext *ctx) |
5106 | 76a66253 | j_mayer | { |
5107 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5108 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5109 | 76a66253 | j_mayer | #else
|
5110 | 22e0e173 | aurel32 | TCGv t0; |
5111 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5112 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5113 | 76a66253 | j_mayer | return;
|
5114 | 76a66253 | j_mayer | } |
5115 | 22e0e173 | aurel32 | t0 = tcg_temp_new(); |
5116 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
5117 | 22e0e173 | aurel32 | gen_helper_rac(cpu_gpr[rD(ctx->opcode)], t0); |
5118 | 22e0e173 | aurel32 | tcg_temp_free(t0); |
5119 | 76a66253 | j_mayer | #endif
|
5120 | 76a66253 | j_mayer | } |
5121 | 76a66253 | j_mayer | |
5122 | 99e300ef | Blue Swirl | static void gen_rfsvc(DisasContext *ctx) |
5123 | 76a66253 | j_mayer | { |
5124 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5125 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5126 | 76a66253 | j_mayer | #else
|
5127 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5128 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5129 | 76a66253 | j_mayer | return;
|
5130 | 76a66253 | j_mayer | } |
5131 | d72a19f7 | aurel32 | gen_helper_rfsvc(); |
5132 | e06fcd75 | aurel32 | gen_sync_exception(ctx); |
5133 | 76a66253 | j_mayer | #endif
|
5134 | 76a66253 | j_mayer | } |
5135 | 76a66253 | j_mayer | |
5136 | 76a66253 | j_mayer | /* svc is not implemented for now */
|
5137 | 76a66253 | j_mayer | |
5138 | 76a66253 | j_mayer | /* POWER2 specific instructions */
|
5139 | 76a66253 | j_mayer | /* Quad manipulation (load/store two floats at a time) */
|
5140 | 76a66253 | j_mayer | |
5141 | 76a66253 | j_mayer | /* lfq */
|
5142 | 99e300ef | Blue Swirl | static void gen_lfq(DisasContext *ctx) |
5143 | 76a66253 | j_mayer | { |
5144 | 01a4afeb | aurel32 | int rd = rD(ctx->opcode);
|
5145 | 76db3ba4 | aurel32 | TCGv t0; |
5146 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); |
5147 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
5148 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, t0, 0);
|
5149 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); |
5150 | 76db3ba4 | aurel32 | gen_addr_add(ctx, t0, t0, 8);
|
5151 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0); |
5152 | 01a4afeb | aurel32 | tcg_temp_free(t0); |
5153 | 76a66253 | j_mayer | } |
5154 | 76a66253 | j_mayer | |
5155 | 76a66253 | j_mayer | /* lfqu */
|
5156 | 99e300ef | Blue Swirl | static void gen_lfqu(DisasContext *ctx) |
5157 | 76a66253 | j_mayer | { |
5158 | 76a66253 | j_mayer | int ra = rA(ctx->opcode);
|
5159 | 01a4afeb | aurel32 | int rd = rD(ctx->opcode);
|
5160 | 76db3ba4 | aurel32 | TCGv t0, t1; |
5161 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); |
5162 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
5163 | 76db3ba4 | aurel32 | t1 = tcg_temp_new(); |
5164 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, t0, 0);
|
5165 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); |
5166 | 76db3ba4 | aurel32 | gen_addr_add(ctx, t1, t0, 8);
|
5167 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1); |
5168 | 76a66253 | j_mayer | if (ra != 0) |
5169 | 01a4afeb | aurel32 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5170 | 01a4afeb | aurel32 | tcg_temp_free(t0); |
5171 | 01a4afeb | aurel32 | tcg_temp_free(t1); |
5172 | 76a66253 | j_mayer | } |
5173 | 76a66253 | j_mayer | |
5174 | 76a66253 | j_mayer | /* lfqux */
|
5175 | 99e300ef | Blue Swirl | static void gen_lfqux(DisasContext *ctx) |
5176 | 76a66253 | j_mayer | { |
5177 | 76a66253 | j_mayer | int ra = rA(ctx->opcode);
|
5178 | 01a4afeb | aurel32 | int rd = rD(ctx->opcode);
|
5179 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); |
5180 | 76db3ba4 | aurel32 | TCGv t0, t1; |
5181 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
5182 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
5183 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); |
5184 | 76db3ba4 | aurel32 | t1 = tcg_temp_new(); |
5185 | 76db3ba4 | aurel32 | gen_addr_add(ctx, t1, t0, 8);
|
5186 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1); |
5187 | 76db3ba4 | aurel32 | tcg_temp_free(t1); |
5188 | 76a66253 | j_mayer | if (ra != 0) |
5189 | 01a4afeb | aurel32 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5190 | 01a4afeb | aurel32 | tcg_temp_free(t0); |
5191 | 76a66253 | j_mayer | } |
5192 | 76a66253 | j_mayer | |
5193 | 76a66253 | j_mayer | /* lfqx */
|
5194 | 99e300ef | Blue Swirl | static void gen_lfqx(DisasContext *ctx) |
5195 | 76a66253 | j_mayer | { |
5196 | 01a4afeb | aurel32 | int rd = rD(ctx->opcode);
|
5197 | 76db3ba4 | aurel32 | TCGv t0; |
5198 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); |
5199 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
5200 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
5201 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); |
5202 | 76db3ba4 | aurel32 | gen_addr_add(ctx, t0, t0, 8);
|
5203 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0); |
5204 | 01a4afeb | aurel32 | tcg_temp_free(t0); |
5205 | 76a66253 | j_mayer | } |
5206 | 76a66253 | j_mayer | |
5207 | 76a66253 | j_mayer | /* stfq */
|
5208 | 99e300ef | Blue Swirl | static void gen_stfq(DisasContext *ctx) |
5209 | 76a66253 | j_mayer | { |
5210 | 01a4afeb | aurel32 | int rd = rD(ctx->opcode);
|
5211 | 76db3ba4 | aurel32 | TCGv t0; |
5212 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); |
5213 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
5214 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, t0, 0);
|
5215 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); |
5216 | 76db3ba4 | aurel32 | gen_addr_add(ctx, t0, t0, 8);
|
5217 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0); |
5218 | 01a4afeb | aurel32 | tcg_temp_free(t0); |
5219 | 76a66253 | j_mayer | } |
5220 | 76a66253 | j_mayer | |
5221 | 76a66253 | j_mayer | /* stfqu */
|
5222 | 99e300ef | Blue Swirl | static void gen_stfqu(DisasContext *ctx) |
5223 | 76a66253 | j_mayer | { |
5224 | 76a66253 | j_mayer | int ra = rA(ctx->opcode);
|
5225 | 01a4afeb | aurel32 | int rd = rD(ctx->opcode);
|
5226 | 76db3ba4 | aurel32 | TCGv t0, t1; |
5227 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); |
5228 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
5229 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, t0, 0);
|
5230 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); |
5231 | 76db3ba4 | aurel32 | t1 = tcg_temp_new(); |
5232 | 76db3ba4 | aurel32 | gen_addr_add(ctx, t1, t0, 8);
|
5233 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1); |
5234 | 76db3ba4 | aurel32 | tcg_temp_free(t1); |
5235 | 76a66253 | j_mayer | if (ra != 0) |
5236 | 01a4afeb | aurel32 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5237 | 01a4afeb | aurel32 | tcg_temp_free(t0); |
5238 | 76a66253 | j_mayer | } |
5239 | 76a66253 | j_mayer | |
5240 | 76a66253 | j_mayer | /* stfqux */
|
5241 | 99e300ef | Blue Swirl | static void gen_stfqux(DisasContext *ctx) |
5242 | 76a66253 | j_mayer | { |
5243 | 76a66253 | j_mayer | int ra = rA(ctx->opcode);
|
5244 | 01a4afeb | aurel32 | int rd = rD(ctx->opcode);
|
5245 | 76db3ba4 | aurel32 | TCGv t0, t1; |
5246 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); |
5247 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
5248 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
5249 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); |
5250 | 76db3ba4 | aurel32 | t1 = tcg_temp_new(); |
5251 | 76db3ba4 | aurel32 | gen_addr_add(ctx, t1, t0, 8);
|
5252 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1); |
5253 | 76db3ba4 | aurel32 | tcg_temp_free(t1); |
5254 | 76a66253 | j_mayer | if (ra != 0) |
5255 | 01a4afeb | aurel32 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5256 | 01a4afeb | aurel32 | tcg_temp_free(t0); |
5257 | 76a66253 | j_mayer | } |
5258 | 76a66253 | j_mayer | |
5259 | 76a66253 | j_mayer | /* stfqx */
|
5260 | 99e300ef | Blue Swirl | static void gen_stfqx(DisasContext *ctx) |
5261 | 76a66253 | j_mayer | { |
5262 | 01a4afeb | aurel32 | int rd = rD(ctx->opcode);
|
5263 | 76db3ba4 | aurel32 | TCGv t0; |
5264 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); |
5265 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
5266 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
5267 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); |
5268 | 76db3ba4 | aurel32 | gen_addr_add(ctx, t0, t0, 8);
|
5269 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0); |
5270 | 01a4afeb | aurel32 | tcg_temp_free(t0); |
5271 | 76a66253 | j_mayer | } |
5272 | 76a66253 | j_mayer | |
5273 | 76a66253 | j_mayer | /* BookE specific instructions */
|
5274 | 99e300ef | Blue Swirl | |
5275 | 54623277 | Blue Swirl | /* XXX: not implemented on 440 ? */
|
5276 | 99e300ef | Blue Swirl | static void gen_mfapidi(DisasContext *ctx) |
5277 | 76a66253 | j_mayer | { |
5278 | 76a66253 | j_mayer | /* XXX: TODO */
|
5279 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5280 | 76a66253 | j_mayer | } |
5281 | 76a66253 | j_mayer | |
5282 | 2662a059 | j_mayer | /* XXX: not implemented on 440 ? */
|
5283 | 99e300ef | Blue Swirl | static void gen_tlbiva(DisasContext *ctx) |
5284 | 76a66253 | j_mayer | { |
5285 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5286 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5287 | 76a66253 | j_mayer | #else
|
5288 | 74d37793 | aurel32 | TCGv t0; |
5289 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5290 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5291 | 76a66253 | j_mayer | return;
|
5292 | 76a66253 | j_mayer | } |
5293 | ec72e276 | aurel32 | t0 = tcg_temp_new(); |
5294 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
5295 | 74d37793 | aurel32 | gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]); |
5296 | 74d37793 | aurel32 | tcg_temp_free(t0); |
5297 | 76a66253 | j_mayer | #endif
|
5298 | 76a66253 | j_mayer | } |
5299 | 76a66253 | j_mayer | |
5300 | 76a66253 | j_mayer | /* All 405 MAC instructions are translated here */
|
5301 | b068d6a7 | j_mayer | static always_inline void gen_405_mulladd_insn (DisasContext *ctx, |
5302 | b068d6a7 | j_mayer | int opc2, int opc3, |
5303 | b068d6a7 | j_mayer | int ra, int rb, int rt, int Rc) |
5304 | 76a66253 | j_mayer | { |
5305 | 182608d4 | aurel32 | TCGv t0, t1; |
5306 | 182608d4 | aurel32 | |
5307 | a7812ae4 | pbrook | t0 = tcg_temp_local_new(); |
5308 | a7812ae4 | pbrook | t1 = tcg_temp_local_new(); |
5309 | 182608d4 | aurel32 | |
5310 | 76a66253 | j_mayer | switch (opc3 & 0x0D) { |
5311 | 76a66253 | j_mayer | case 0x05: |
5312 | 76a66253 | j_mayer | /* macchw - macchw. - macchwo - macchwo. */
|
5313 | 76a66253 | j_mayer | /* macchws - macchws. - macchwso - macchwso. */
|
5314 | 76a66253 | j_mayer | /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
|
5315 | 76a66253 | j_mayer | /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
|
5316 | 76a66253 | j_mayer | /* mulchw - mulchw. */
|
5317 | 182608d4 | aurel32 | tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); |
5318 | 182608d4 | aurel32 | tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
|
5319 | 182608d4 | aurel32 | tcg_gen_ext16s_tl(t1, t1); |
5320 | 76a66253 | j_mayer | break;
|
5321 | 76a66253 | j_mayer | case 0x04: |
5322 | 76a66253 | j_mayer | /* macchwu - macchwu. - macchwuo - macchwuo. */
|
5323 | 76a66253 | j_mayer | /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
|
5324 | 76a66253 | j_mayer | /* mulchwu - mulchwu. */
|
5325 | 182608d4 | aurel32 | tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); |
5326 | 182608d4 | aurel32 | tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
|
5327 | 182608d4 | aurel32 | tcg_gen_ext16u_tl(t1, t1); |
5328 | 76a66253 | j_mayer | break;
|
5329 | 76a66253 | j_mayer | case 0x01: |
5330 | 76a66253 | j_mayer | /* machhw - machhw. - machhwo - machhwo. */
|
5331 | 76a66253 | j_mayer | /* machhws - machhws. - machhwso - machhwso. */
|
5332 | 76a66253 | j_mayer | /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
|
5333 | 76a66253 | j_mayer | /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
|
5334 | 76a66253 | j_mayer | /* mulhhw - mulhhw. */
|
5335 | 182608d4 | aurel32 | tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
|
5336 | 182608d4 | aurel32 | tcg_gen_ext16s_tl(t0, t0); |
5337 | 182608d4 | aurel32 | tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
|
5338 | 182608d4 | aurel32 | tcg_gen_ext16s_tl(t1, t1); |
5339 | 76a66253 | j_mayer | break;
|
5340 | 76a66253 | j_mayer | case 0x00: |
5341 | 76a66253 | j_mayer | /* machhwu - machhwu. - machhwuo - machhwuo. */
|
5342 | 76a66253 | j_mayer | /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
|
5343 | 76a66253 | j_mayer | /* mulhhwu - mulhhwu. */
|
5344 | 182608d4 | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
|
5345 | 182608d4 | aurel32 | tcg_gen_ext16u_tl(t0, t0); |
5346 | 182608d4 | aurel32 | tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
|
5347 | 182608d4 | aurel32 | tcg_gen_ext16u_tl(t1, t1); |
5348 | 76a66253 | j_mayer | break;
|
5349 | 76a66253 | j_mayer | case 0x0D: |
5350 | 76a66253 | j_mayer | /* maclhw - maclhw. - maclhwo - maclhwo. */
|
5351 | 76a66253 | j_mayer | /* maclhws - maclhws. - maclhwso - maclhwso. */
|
5352 | 76a66253 | j_mayer | /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
|
5353 | 76a66253 | j_mayer | /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
|
5354 | 76a66253 | j_mayer | /* mullhw - mullhw. */
|
5355 | 182608d4 | aurel32 | tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); |
5356 | 182608d4 | aurel32 | tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); |
5357 | 76a66253 | j_mayer | break;
|
5358 | 76a66253 | j_mayer | case 0x0C: |
5359 | 76a66253 | j_mayer | /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
|
5360 | 76a66253 | j_mayer | /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
|
5361 | 76a66253 | j_mayer | /* mullhwu - mullhwu. */
|
5362 | 182608d4 | aurel32 | tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); |
5363 | 182608d4 | aurel32 | tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); |
5364 | 76a66253 | j_mayer | break;
|
5365 | 76a66253 | j_mayer | } |
5366 | 76a66253 | j_mayer | if (opc2 & 0x04) { |
5367 | 182608d4 | aurel32 | /* (n)multiply-and-accumulate (0x0C / 0x0E) */
|
5368 | 182608d4 | aurel32 | tcg_gen_mul_tl(t1, t0, t1); |
5369 | 182608d4 | aurel32 | if (opc2 & 0x02) { |
5370 | 182608d4 | aurel32 | /* nmultiply-and-accumulate (0x0E) */
|
5371 | 182608d4 | aurel32 | tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); |
5372 | 182608d4 | aurel32 | } else {
|
5373 | 182608d4 | aurel32 | /* multiply-and-accumulate (0x0C) */
|
5374 | 182608d4 | aurel32 | tcg_gen_add_tl(t0, cpu_gpr[rt], t1); |
5375 | 182608d4 | aurel32 | } |
5376 | 182608d4 | aurel32 | |
5377 | 182608d4 | aurel32 | if (opc3 & 0x12) { |
5378 | 182608d4 | aurel32 | /* Check overflow and/or saturate */
|
5379 | 182608d4 | aurel32 | int l1 = gen_new_label();
|
5380 | 182608d4 | aurel32 | |
5381 | 182608d4 | aurel32 | if (opc3 & 0x10) { |
5382 | 182608d4 | aurel32 | /* Start with XER OV disabled, the most likely case */
|
5383 | 182608d4 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
|
5384 | 182608d4 | aurel32 | } |
5385 | 182608d4 | aurel32 | if (opc3 & 0x01) { |
5386 | 182608d4 | aurel32 | /* Signed */
|
5387 | 182608d4 | aurel32 | tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); |
5388 | 182608d4 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
|
5389 | 182608d4 | aurel32 | tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); |
5390 | 182608d4 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
|
5391 | bdc4e053 | aurel32 | if (opc3 & 0x02) { |
5392 | 182608d4 | aurel32 | /* Saturate */
|
5393 | 182608d4 | aurel32 | tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
|
5394 | 182608d4 | aurel32 | tcg_gen_xori_tl(t0, t0, 0x7fffffff);
|
5395 | 182608d4 | aurel32 | } |
5396 | 182608d4 | aurel32 | } else {
|
5397 | 182608d4 | aurel32 | /* Unsigned */
|
5398 | 182608d4 | aurel32 | tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); |
5399 | bdc4e053 | aurel32 | if (opc3 & 0x02) { |
5400 | 182608d4 | aurel32 | /* Saturate */
|
5401 | 182608d4 | aurel32 | tcg_gen_movi_tl(t0, UINT32_MAX); |
5402 | 182608d4 | aurel32 | } |
5403 | 182608d4 | aurel32 | } |
5404 | 182608d4 | aurel32 | if (opc3 & 0x10) { |
5405 | 182608d4 | aurel32 | /* Check overflow */
|
5406 | 182608d4 | aurel32 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); |
5407 | 182608d4 | aurel32 | } |
5408 | 182608d4 | aurel32 | gen_set_label(l1); |
5409 | 182608d4 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rt], t0); |
5410 | 182608d4 | aurel32 | } |
5411 | 182608d4 | aurel32 | } else {
|
5412 | 182608d4 | aurel32 | tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); |
5413 | 76a66253 | j_mayer | } |
5414 | 182608d4 | aurel32 | tcg_temp_free(t0); |
5415 | 182608d4 | aurel32 | tcg_temp_free(t1); |
5416 | 76a66253 | j_mayer | if (unlikely(Rc) != 0) { |
5417 | 76a66253 | j_mayer | /* Update Rc0 */
|
5418 | 182608d4 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rt]); |
5419 | 76a66253 | j_mayer | } |
5420 | 76a66253 | j_mayer | } |
5421 | 76a66253 | j_mayer | |
5422 | a750fc0b | j_mayer | #define GEN_MAC_HANDLER(name, opc2, opc3) \
|
5423 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
5424 | 76a66253 | j_mayer | { \ |
5425 | 76a66253 | j_mayer | gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ |
5426 | 76a66253 | j_mayer | rD(ctx->opcode), Rc(ctx->opcode)); \ |
5427 | 76a66253 | j_mayer | } |
5428 | 76a66253 | j_mayer | |
5429 | 76a66253 | j_mayer | /* macchw - macchw. */
|
5430 | a750fc0b | j_mayer | GEN_MAC_HANDLER(macchw, 0x0C, 0x05); |
5431 | 76a66253 | j_mayer | /* macchwo - macchwo. */
|
5432 | a750fc0b | j_mayer | GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); |
5433 | 76a66253 | j_mayer | /* macchws - macchws. */
|
5434 | a750fc0b | j_mayer | GEN_MAC_HANDLER(macchws, 0x0C, 0x07); |
5435 | 76a66253 | j_mayer | /* macchwso - macchwso. */
|
5436 | a750fc0b | j_mayer | GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); |
5437 | 76a66253 | j_mayer | /* macchwsu - macchwsu. */
|
5438 | a750fc0b | j_mayer | GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); |
5439 | 76a66253 | j_mayer | /* macchwsuo - macchwsuo. */
|
5440 | a750fc0b | j_mayer | GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); |
5441 | 76a66253 | j_mayer | /* macchwu - macchwu. */
|
5442 | a750fc0b | j_mayer | GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); |
5443 | 76a66253 | j_mayer | /* macchwuo - macchwuo. */
|
5444 | a750fc0b | j_mayer | GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); |
5445 | 76a66253 | j_mayer | /* machhw - machhw. */
|
5446 | a750fc0b | j_mayer | GEN_MAC_HANDLER(machhw, 0x0C, 0x01); |
5447 | 76a66253 | j_mayer | /* machhwo - machhwo. */
|
5448 | a750fc0b | j_mayer | GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); |
5449 | 76a66253 | j_mayer | /* machhws - machhws. */
|
5450 | a750fc0b | j_mayer | GEN_MAC_HANDLER(machhws, 0x0C, 0x03); |
5451 | 76a66253 | j_mayer | /* machhwso - machhwso. */
|
5452 | a750fc0b | j_mayer | GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); |
5453 | 76a66253 | j_mayer | /* machhwsu - machhwsu. */
|
5454 | a750fc0b | j_mayer | GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); |
5455 | 76a66253 | j_mayer | /* machhwsuo - machhwsuo. */
|
5456 | a750fc0b | j_mayer | GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); |
5457 | 76a66253 | j_mayer | /* machhwu - machhwu. */
|
5458 | a750fc0b | j_mayer | GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); |
5459 | 76a66253 | j_mayer | /* machhwuo - machhwuo. */
|
5460 | a750fc0b | j_mayer | GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); |
5461 | 76a66253 | j_mayer | /* maclhw - maclhw. */
|
5462 | a750fc0b | j_mayer | GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); |
5463 | 76a66253 | j_mayer | /* maclhwo - maclhwo. */
|
5464 | a750fc0b | j_mayer | GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); |
5465 | 76a66253 | j_mayer | /* maclhws - maclhws. */
|
5466 | a750fc0b | j_mayer | GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); |
5467 | 76a66253 | j_mayer | /* maclhwso - maclhwso. */
|
5468 | a750fc0b | j_mayer | GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); |
5469 | 76a66253 | j_mayer | /* maclhwu - maclhwu. */
|
5470 | a750fc0b | j_mayer | GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); |
5471 | 76a66253 | j_mayer | /* maclhwuo - maclhwuo. */
|
5472 | a750fc0b | j_mayer | GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); |
5473 | 76a66253 | j_mayer | /* maclhwsu - maclhwsu. */
|
5474 | a750fc0b | j_mayer | GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); |
5475 | 76a66253 | j_mayer | /* maclhwsuo - maclhwsuo. */
|
5476 | a750fc0b | j_mayer | GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); |
5477 | 76a66253 | j_mayer | /* nmacchw - nmacchw. */
|
5478 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); |
5479 | 76a66253 | j_mayer | /* nmacchwo - nmacchwo. */
|
5480 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); |
5481 | 76a66253 | j_mayer | /* nmacchws - nmacchws. */
|
5482 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); |
5483 | 76a66253 | j_mayer | /* nmacchwso - nmacchwso. */
|
5484 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); |
5485 | 76a66253 | j_mayer | /* nmachhw - nmachhw. */
|
5486 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); |
5487 | 76a66253 | j_mayer | /* nmachhwo - nmachhwo. */
|
5488 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); |
5489 | 76a66253 | j_mayer | /* nmachhws - nmachhws. */
|
5490 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); |
5491 | 76a66253 | j_mayer | /* nmachhwso - nmachhwso. */
|
5492 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); |
5493 | 76a66253 | j_mayer | /* nmaclhw - nmaclhw. */
|
5494 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); |
5495 | 76a66253 | j_mayer | /* nmaclhwo - nmaclhwo. */
|
5496 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); |
5497 | 76a66253 | j_mayer | /* nmaclhws - nmaclhws. */
|
5498 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); |
5499 | 76a66253 | j_mayer | /* nmaclhwso - nmaclhwso. */
|
5500 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); |
5501 | 76a66253 | j_mayer | |
5502 | 76a66253 | j_mayer | /* mulchw - mulchw. */
|
5503 | a750fc0b | j_mayer | GEN_MAC_HANDLER(mulchw, 0x08, 0x05); |
5504 | 76a66253 | j_mayer | /* mulchwu - mulchwu. */
|
5505 | a750fc0b | j_mayer | GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); |
5506 | 76a66253 | j_mayer | /* mulhhw - mulhhw. */
|
5507 | a750fc0b | j_mayer | GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); |
5508 | 76a66253 | j_mayer | /* mulhhwu - mulhhwu. */
|
5509 | a750fc0b | j_mayer | GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); |
5510 | 76a66253 | j_mayer | /* mullhw - mullhw. */
|
5511 | a750fc0b | j_mayer | GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); |
5512 | 76a66253 | j_mayer | /* mullhwu - mullhwu. */
|
5513 | a750fc0b | j_mayer | GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); |
5514 | 76a66253 | j_mayer | |
5515 | 76a66253 | j_mayer | /* mfdcr */
|
5516 | 99e300ef | Blue Swirl | static void gen_mfdcr(DisasContext *ctx) |
5517 | 76a66253 | j_mayer | { |
5518 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5519 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
5520 | 76a66253 | j_mayer | #else
|
5521 | 06dca6a7 | aurel32 | TCGv dcrn; |
5522 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5523 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
5524 | 76a66253 | j_mayer | return;
|
5525 | 76a66253 | j_mayer | } |
5526 | 06dca6a7 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
5527 | 06dca6a7 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
5528 | 06dca6a7 | aurel32 | dcrn = tcg_const_tl(SPR(ctx->opcode)); |
5529 | 06dca6a7 | aurel32 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], dcrn); |
5530 | 06dca6a7 | aurel32 | tcg_temp_free(dcrn); |
5531 | 76a66253 | j_mayer | #endif
|
5532 | 76a66253 | j_mayer | } |
5533 | 76a66253 | j_mayer | |
5534 | 76a66253 | j_mayer | /* mtdcr */
|
5535 | 99e300ef | Blue Swirl | static void gen_mtdcr(DisasContext *ctx) |
5536 | 76a66253 | j_mayer | { |
5537 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5538 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
5539 | 76a66253 | j_mayer | #else
|
5540 | 06dca6a7 | aurel32 | TCGv dcrn; |
5541 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5542 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
5543 | 76a66253 | j_mayer | return;
|
5544 | 76a66253 | j_mayer | } |
5545 | 06dca6a7 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
5546 | 06dca6a7 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
5547 | 06dca6a7 | aurel32 | dcrn = tcg_const_tl(SPR(ctx->opcode)); |
5548 | 06dca6a7 | aurel32 | gen_helper_store_dcr(dcrn, cpu_gpr[rS(ctx->opcode)]); |
5549 | 06dca6a7 | aurel32 | tcg_temp_free(dcrn); |
5550 | a42bd6cc | j_mayer | #endif
|
5551 | a42bd6cc | j_mayer | } |
5552 | a42bd6cc | j_mayer | |
5553 | a42bd6cc | j_mayer | /* mfdcrx */
|
5554 | 2662a059 | j_mayer | /* XXX: not implemented on 440 ? */
|
5555 | 99e300ef | Blue Swirl | static void gen_mfdcrx(DisasContext *ctx) |
5556 | a42bd6cc | j_mayer | { |
5557 | a42bd6cc | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5558 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
5559 | a42bd6cc | j_mayer | #else
|
5560 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5561 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
5562 | a42bd6cc | j_mayer | return;
|
5563 | a42bd6cc | j_mayer | } |
5564 | 06dca6a7 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
5565 | 06dca6a7 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
5566 | 06dca6a7 | aurel32 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
5567 | a750fc0b | j_mayer | /* Note: Rc update flag set leads to undefined state of Rc0 */
|
5568 | a42bd6cc | j_mayer | #endif
|
5569 | a42bd6cc | j_mayer | } |
5570 | a42bd6cc | j_mayer | |
5571 | a42bd6cc | j_mayer | /* mtdcrx */
|
5572 | 2662a059 | j_mayer | /* XXX: not implemented on 440 ? */
|
5573 | 99e300ef | Blue Swirl | static void gen_mtdcrx(DisasContext *ctx) |
5574 | a42bd6cc | j_mayer | { |
5575 | a42bd6cc | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5576 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
5577 | a42bd6cc | j_mayer | #else
|
5578 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5579 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
5580 | a42bd6cc | j_mayer | return;
|
5581 | a42bd6cc | j_mayer | } |
5582 | 06dca6a7 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
5583 | 06dca6a7 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
5584 | 06dca6a7 | aurel32 | gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
5585 | a750fc0b | j_mayer | /* Note: Rc update flag set leads to undefined state of Rc0 */
|
5586 | 76a66253 | j_mayer | #endif
|
5587 | 76a66253 | j_mayer | } |
5588 | 76a66253 | j_mayer | |
5589 | a750fc0b | j_mayer | /* mfdcrux (PPC 460) : user-mode access to DCR */
|
5590 | 99e300ef | Blue Swirl | static void gen_mfdcrux(DisasContext *ctx) |
5591 | a750fc0b | j_mayer | { |
5592 | 06dca6a7 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
5593 | 06dca6a7 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
5594 | 06dca6a7 | aurel32 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
5595 | a750fc0b | j_mayer | /* Note: Rc update flag set leads to undefined state of Rc0 */
|
5596 | a750fc0b | j_mayer | } |
5597 | a750fc0b | j_mayer | |
5598 | a750fc0b | j_mayer | /* mtdcrux (PPC 460) : user-mode access to DCR */
|
5599 | 99e300ef | Blue Swirl | static void gen_mtdcrux(DisasContext *ctx) |
5600 | a750fc0b | j_mayer | { |
5601 | 06dca6a7 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
5602 | 06dca6a7 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
5603 | 06dca6a7 | aurel32 | gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
5604 | a750fc0b | j_mayer | /* Note: Rc update flag set leads to undefined state of Rc0 */
|
5605 | a750fc0b | j_mayer | } |
5606 | a750fc0b | j_mayer | |
5607 | 76a66253 | j_mayer | /* dccci */
|
5608 | 99e300ef | Blue Swirl | static void gen_dccci(DisasContext *ctx) |
5609 | 76a66253 | j_mayer | { |
5610 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5611 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5612 | 76a66253 | j_mayer | #else
|
5613 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5614 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5615 | 76a66253 | j_mayer | return;
|
5616 | 76a66253 | j_mayer | } |
5617 | 76a66253 | j_mayer | /* interpreted as no-op */
|
5618 | 76a66253 | j_mayer | #endif
|
5619 | 76a66253 | j_mayer | } |
5620 | 76a66253 | j_mayer | |
5621 | 76a66253 | j_mayer | /* dcread */
|
5622 | 99e300ef | Blue Swirl | static void gen_dcread(DisasContext *ctx) |
5623 | 76a66253 | j_mayer | { |
5624 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5625 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5626 | 76a66253 | j_mayer | #else
|
5627 | b61f2753 | aurel32 | TCGv EA, val; |
5628 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5629 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5630 | 76a66253 | j_mayer | return;
|
5631 | 76a66253 | j_mayer | } |
5632 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_CACHE); |
5633 | a7812ae4 | pbrook | EA = tcg_temp_new(); |
5634 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, EA); |
5635 | a7812ae4 | pbrook | val = tcg_temp_new(); |
5636 | 76db3ba4 | aurel32 | gen_qemu_ld32u(ctx, val, EA); |
5637 | b61f2753 | aurel32 | tcg_temp_free(val); |
5638 | b61f2753 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); |
5639 | b61f2753 | aurel32 | tcg_temp_free(EA); |
5640 | 76a66253 | j_mayer | #endif
|
5641 | 76a66253 | j_mayer | } |
5642 | 76a66253 | j_mayer | |
5643 | 76a66253 | j_mayer | /* icbt */
|
5644 | e8eaa2c0 | Blue Swirl | static void gen_icbt_40x(DisasContext *ctx) |
5645 | 76a66253 | j_mayer | { |
5646 | 76a66253 | j_mayer | /* interpreted as no-op */
|
5647 | 76a66253 | j_mayer | /* XXX: specification say this is treated as a load by the MMU
|
5648 | 76a66253 | j_mayer | * but does not generate any exception
|
5649 | 76a66253 | j_mayer | */
|
5650 | 76a66253 | j_mayer | } |
5651 | 76a66253 | j_mayer | |
5652 | 76a66253 | j_mayer | /* iccci */
|
5653 | 99e300ef | Blue Swirl | static void gen_iccci(DisasContext *ctx) |
5654 | 76a66253 | j_mayer | { |
5655 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5656 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5657 | 76a66253 | j_mayer | #else
|
5658 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5659 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5660 | 76a66253 | j_mayer | return;
|
5661 | 76a66253 | j_mayer | } |
5662 | 76a66253 | j_mayer | /* interpreted as no-op */
|
5663 | 76a66253 | j_mayer | #endif
|
5664 | 76a66253 | j_mayer | } |
5665 | 76a66253 | j_mayer | |
5666 | 76a66253 | j_mayer | /* icread */
|
5667 | 99e300ef | Blue Swirl | static void gen_icread(DisasContext *ctx) |
5668 | 76a66253 | j_mayer | { |
5669 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5670 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5671 | 76a66253 | j_mayer | #else
|
5672 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5673 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5674 | 76a66253 | j_mayer | return;
|
5675 | 76a66253 | j_mayer | } |
5676 | 76a66253 | j_mayer | /* interpreted as no-op */
|
5677 | 76a66253 | j_mayer | #endif
|
5678 | 76a66253 | j_mayer | } |
5679 | 76a66253 | j_mayer | |
5680 | 76db3ba4 | aurel32 | /* rfci (mem_idx only) */
|
5681 | e8eaa2c0 | Blue Swirl | static void gen_rfci_40x(DisasContext *ctx) |
5682 | a42bd6cc | j_mayer | { |
5683 | a42bd6cc | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5684 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5685 | a42bd6cc | j_mayer | #else
|
5686 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5687 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5688 | a42bd6cc | j_mayer | return;
|
5689 | a42bd6cc | j_mayer | } |
5690 | a42bd6cc | j_mayer | /* Restore CPU state */
|
5691 | d72a19f7 | aurel32 | gen_helper_40x_rfci(); |
5692 | e06fcd75 | aurel32 | gen_sync_exception(ctx); |
5693 | a42bd6cc | j_mayer | #endif
|
5694 | a42bd6cc | j_mayer | } |
5695 | a42bd6cc | j_mayer | |
5696 | 99e300ef | Blue Swirl | static void gen_rfci(DisasContext *ctx) |
5697 | a42bd6cc | j_mayer | { |
5698 | a42bd6cc | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5699 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5700 | a42bd6cc | j_mayer | #else
|
5701 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5702 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5703 | a42bd6cc | j_mayer | return;
|
5704 | a42bd6cc | j_mayer | } |
5705 | a42bd6cc | j_mayer | /* Restore CPU state */
|
5706 | d72a19f7 | aurel32 | gen_helper_rfci(); |
5707 | e06fcd75 | aurel32 | gen_sync_exception(ctx); |
5708 | a42bd6cc | j_mayer | #endif
|
5709 | a42bd6cc | j_mayer | } |
5710 | a42bd6cc | j_mayer | |
5711 | a42bd6cc | j_mayer | /* BookE specific */
|
5712 | 99e300ef | Blue Swirl | |
5713 | 54623277 | Blue Swirl | /* XXX: not implemented on 440 ? */
|
5714 | 99e300ef | Blue Swirl | static void gen_rfdi(DisasContext *ctx) |
5715 | 76a66253 | j_mayer | { |
5716 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5717 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5718 | 76a66253 | j_mayer | #else
|
5719 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5720 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5721 | 76a66253 | j_mayer | return;
|
5722 | 76a66253 | j_mayer | } |
5723 | 76a66253 | j_mayer | /* Restore CPU state */
|
5724 | d72a19f7 | aurel32 | gen_helper_rfdi(); |
5725 | e06fcd75 | aurel32 | gen_sync_exception(ctx); |
5726 | 76a66253 | j_mayer | #endif
|
5727 | 76a66253 | j_mayer | } |
5728 | 76a66253 | j_mayer | |
5729 | 2662a059 | j_mayer | /* XXX: not implemented on 440 ? */
|
5730 | 99e300ef | Blue Swirl | static void gen_rfmci(DisasContext *ctx) |
5731 | a42bd6cc | j_mayer | { |
5732 | a42bd6cc | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5733 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5734 | a42bd6cc | j_mayer | #else
|
5735 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5736 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5737 | a42bd6cc | j_mayer | return;
|
5738 | a42bd6cc | j_mayer | } |
5739 | a42bd6cc | j_mayer | /* Restore CPU state */
|
5740 | d72a19f7 | aurel32 | gen_helper_rfmci(); |
5741 | e06fcd75 | aurel32 | gen_sync_exception(ctx); |
5742 | a42bd6cc | j_mayer | #endif
|
5743 | a42bd6cc | j_mayer | } |
5744 | 5eb7995e | j_mayer | |
5745 | d9bce9d9 | j_mayer | /* TLB management - PowerPC 405 implementation */
|
5746 | e8eaa2c0 | Blue Swirl | |
5747 | 54623277 | Blue Swirl | /* tlbre */
|
5748 | e8eaa2c0 | Blue Swirl | static void gen_tlbre_40x(DisasContext *ctx) |
5749 | 76a66253 | j_mayer | { |
5750 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5751 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5752 | 76a66253 | j_mayer | #else
|
5753 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5754 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5755 | 76a66253 | j_mayer | return;
|
5756 | 76a66253 | j_mayer | } |
5757 | 76a66253 | j_mayer | switch (rB(ctx->opcode)) {
|
5758 | 76a66253 | j_mayer | case 0: |
5759 | 74d37793 | aurel32 | gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
5760 | 76a66253 | j_mayer | break;
|
5761 | 76a66253 | j_mayer | case 1: |
5762 | 74d37793 | aurel32 | gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
5763 | 76a66253 | j_mayer | break;
|
5764 | 76a66253 | j_mayer | default:
|
5765 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5766 | 76a66253 | j_mayer | break;
|
5767 | 9a64fbe4 | bellard | } |
5768 | 76a66253 | j_mayer | #endif
|
5769 | 76a66253 | j_mayer | } |
5770 | 76a66253 | j_mayer | |
5771 | d9bce9d9 | j_mayer | /* tlbsx - tlbsx. */
|
5772 | e8eaa2c0 | Blue Swirl | static void gen_tlbsx_40x(DisasContext *ctx) |
5773 | 76a66253 | j_mayer | { |
5774 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5775 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5776 | 76a66253 | j_mayer | #else
|
5777 | 74d37793 | aurel32 | TCGv t0; |
5778 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5779 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5780 | 76a66253 | j_mayer | return;
|
5781 | 76a66253 | j_mayer | } |
5782 | 74d37793 | aurel32 | t0 = tcg_temp_new(); |
5783 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
5784 | 74d37793 | aurel32 | gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], t0); |
5785 | 74d37793 | aurel32 | tcg_temp_free(t0); |
5786 | 74d37793 | aurel32 | if (Rc(ctx->opcode)) {
|
5787 | 74d37793 | aurel32 | int l1 = gen_new_label();
|
5788 | 74d37793 | aurel32 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
|
5789 | 74d37793 | aurel32 | tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO); |
5790 | 74d37793 | aurel32 | tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1); |
5791 | 74d37793 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
|
5792 | 74d37793 | aurel32 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); |
5793 | 74d37793 | aurel32 | gen_set_label(l1); |
5794 | 74d37793 | aurel32 | } |
5795 | 76a66253 | j_mayer | #endif
|
5796 | 79aceca5 | bellard | } |
5797 | 79aceca5 | bellard | |
5798 | 76a66253 | j_mayer | /* tlbwe */
|
5799 | e8eaa2c0 | Blue Swirl | static void gen_tlbwe_40x(DisasContext *ctx) |
5800 | 79aceca5 | bellard | { |
5801 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5802 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5803 | 76a66253 | j_mayer | #else
|
5804 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5805 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5806 | 76a66253 | j_mayer | return;
|
5807 | 76a66253 | j_mayer | } |
5808 | 76a66253 | j_mayer | switch (rB(ctx->opcode)) {
|
5809 | 76a66253 | j_mayer | case 0: |
5810 | 74d37793 | aurel32 | gen_helper_4xx_tlbwe_hi(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
5811 | 76a66253 | j_mayer | break;
|
5812 | 76a66253 | j_mayer | case 1: |
5813 | 74d37793 | aurel32 | gen_helper_4xx_tlbwe_lo(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
5814 | 76a66253 | j_mayer | break;
|
5815 | 76a66253 | j_mayer | default:
|
5816 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5817 | 76a66253 | j_mayer | break;
|
5818 | 9a64fbe4 | bellard | } |
5819 | 76a66253 | j_mayer | #endif
|
5820 | 76a66253 | j_mayer | } |
5821 | 76a66253 | j_mayer | |
5822 | a4bb6c3e | j_mayer | /* TLB management - PowerPC 440 implementation */
|
5823 | e8eaa2c0 | Blue Swirl | |
5824 | 54623277 | Blue Swirl | /* tlbre */
|
5825 | e8eaa2c0 | Blue Swirl | static void gen_tlbre_440(DisasContext *ctx) |
5826 | 5eb7995e | j_mayer | { |
5827 | 5eb7995e | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5828 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5829 | 5eb7995e | j_mayer | #else
|
5830 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5831 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5832 | 5eb7995e | j_mayer | return;
|
5833 | 5eb7995e | j_mayer | } |
5834 | 5eb7995e | j_mayer | switch (rB(ctx->opcode)) {
|
5835 | 5eb7995e | j_mayer | case 0: |
5836 | 5eb7995e | j_mayer | case 1: |
5837 | 5eb7995e | j_mayer | case 2: |
5838 | 74d37793 | aurel32 | { |
5839 | 74d37793 | aurel32 | TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); |
5840 | 74d37793 | aurel32 | gen_helper_440_tlbwe(t0, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
5841 | 74d37793 | aurel32 | tcg_temp_free_i32(t0); |
5842 | 74d37793 | aurel32 | } |
5843 | 5eb7995e | j_mayer | break;
|
5844 | 5eb7995e | j_mayer | default:
|
5845 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5846 | 5eb7995e | j_mayer | break;
|
5847 | 5eb7995e | j_mayer | } |
5848 | 5eb7995e | j_mayer | #endif
|
5849 | 5eb7995e | j_mayer | } |
5850 | 5eb7995e | j_mayer | |
5851 | 5eb7995e | j_mayer | /* tlbsx - tlbsx. */
|
5852 | e8eaa2c0 | Blue Swirl | static void gen_tlbsx_440(DisasContext *ctx) |
5853 | 5eb7995e | j_mayer | { |
5854 | 5eb7995e | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5855 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5856 | 5eb7995e | j_mayer | #else
|
5857 | 74d37793 | aurel32 | TCGv t0; |
5858 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5859 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5860 | 5eb7995e | j_mayer | return;
|
5861 | 5eb7995e | j_mayer | } |
5862 | 74d37793 | aurel32 | t0 = tcg_temp_new(); |
5863 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
5864 | 74d37793 | aurel32 | gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], t0); |
5865 | 74d37793 | aurel32 | tcg_temp_free(t0); |
5866 | 74d37793 | aurel32 | if (Rc(ctx->opcode)) {
|
5867 | 74d37793 | aurel32 | int l1 = gen_new_label();
|
5868 | 74d37793 | aurel32 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
|
5869 | 74d37793 | aurel32 | tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO); |
5870 | 74d37793 | aurel32 | tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1); |
5871 | 74d37793 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
|
5872 | 74d37793 | aurel32 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); |
5873 | 74d37793 | aurel32 | gen_set_label(l1); |
5874 | 74d37793 | aurel32 | } |
5875 | 5eb7995e | j_mayer | #endif
|
5876 | 5eb7995e | j_mayer | } |
5877 | 5eb7995e | j_mayer | |
5878 | 5eb7995e | j_mayer | /* tlbwe */
|
5879 | e8eaa2c0 | Blue Swirl | static void gen_tlbwe_440(DisasContext *ctx) |
5880 | 5eb7995e | j_mayer | { |
5881 | 5eb7995e | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5882 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5883 | 5eb7995e | j_mayer | #else
|
5884 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5885 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5886 | 5eb7995e | j_mayer | return;
|
5887 | 5eb7995e | j_mayer | } |
5888 | 5eb7995e | j_mayer | switch (rB(ctx->opcode)) {
|
5889 | 5eb7995e | j_mayer | case 0: |
5890 | 5eb7995e | j_mayer | case 1: |
5891 | 5eb7995e | j_mayer | case 2: |
5892 | 74d37793 | aurel32 | { |
5893 | 74d37793 | aurel32 | TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); |
5894 | 74d37793 | aurel32 | gen_helper_440_tlbwe(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
5895 | 74d37793 | aurel32 | tcg_temp_free_i32(t0); |
5896 | 74d37793 | aurel32 | } |
5897 | 5eb7995e | j_mayer | break;
|
5898 | 5eb7995e | j_mayer | default:
|
5899 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5900 | 5eb7995e | j_mayer | break;
|
5901 | 5eb7995e | j_mayer | } |
5902 | 5eb7995e | j_mayer | #endif
|
5903 | 5eb7995e | j_mayer | } |
5904 | 5eb7995e | j_mayer | |
5905 | 76a66253 | j_mayer | /* wrtee */
|
5906 | 99e300ef | Blue Swirl | static void gen_wrtee(DisasContext *ctx) |
5907 | 76a66253 | j_mayer | { |
5908 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5909 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5910 | 76a66253 | j_mayer | #else
|
5911 | 6527f6ea | aurel32 | TCGv t0; |
5912 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5913 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5914 | 76a66253 | j_mayer | return;
|
5915 | 76a66253 | j_mayer | } |
5916 | 6527f6ea | aurel32 | t0 = tcg_temp_new(); |
5917 | 6527f6ea | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
|
5918 | 6527f6ea | aurel32 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
|
5919 | 6527f6ea | aurel32 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); |
5920 | 6527f6ea | aurel32 | tcg_temp_free(t0); |
5921 | dee96f6c | j_mayer | /* Stop translation to have a chance to raise an exception
|
5922 | dee96f6c | j_mayer | * if we just set msr_ee to 1
|
5923 | dee96f6c | j_mayer | */
|
5924 | e06fcd75 | aurel32 | gen_stop_exception(ctx); |
5925 | 76a66253 | j_mayer | #endif
|
5926 | 76a66253 | j_mayer | } |
5927 | 76a66253 | j_mayer | |
5928 | 76a66253 | j_mayer | /* wrteei */
|
5929 | 99e300ef | Blue Swirl | static void gen_wrteei(DisasContext *ctx) |
5930 | 76a66253 | j_mayer | { |
5931 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5932 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5933 | 76a66253 | j_mayer | #else
|
5934 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5935 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5936 | 76a66253 | j_mayer | return;
|
5937 | 76a66253 | j_mayer | } |
5938 | 6527f6ea | aurel32 | if (ctx->opcode & 0x00010000) { |
5939 | 6527f6ea | aurel32 | tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
|
5940 | 6527f6ea | aurel32 | /* Stop translation to have a chance to raise an exception */
|
5941 | e06fcd75 | aurel32 | gen_stop_exception(ctx); |
5942 | 6527f6ea | aurel32 | } else {
|
5943 | 1b6e5f99 | aurel32 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
|
5944 | 6527f6ea | aurel32 | } |
5945 | 76a66253 | j_mayer | #endif
|
5946 | 76a66253 | j_mayer | } |
5947 | 76a66253 | j_mayer | |
5948 | 08e46e54 | j_mayer | /* PowerPC 440 specific instructions */
|
5949 | 99e300ef | Blue Swirl | |
5950 | 54623277 | Blue Swirl | /* dlmzb */
|
5951 | 99e300ef | Blue Swirl | static void gen_dlmzb(DisasContext *ctx) |
5952 | 76a66253 | j_mayer | { |
5953 | ef0d51af | aurel32 | TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); |
5954 | ef0d51af | aurel32 | gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], |
5955 | ef0d51af | aurel32 | cpu_gpr[rB(ctx->opcode)], t0); |
5956 | ef0d51af | aurel32 | tcg_temp_free_i32(t0); |
5957 | 76a66253 | j_mayer | } |
5958 | 76a66253 | j_mayer | |
5959 | 76a66253 | j_mayer | /* mbar replaces eieio on 440 */
|
5960 | 99e300ef | Blue Swirl | static void gen_mbar(DisasContext *ctx) |
5961 | 76a66253 | j_mayer | { |
5962 | 76a66253 | j_mayer | /* interpreted as no-op */
|
5963 | 76a66253 | j_mayer | } |
5964 | 76a66253 | j_mayer | |
5965 | 76a66253 | j_mayer | /* msync replaces sync on 440 */
|
5966 | 99e300ef | Blue Swirl | static void gen_msync(DisasContext *ctx) |
5967 | 76a66253 | j_mayer | { |
5968 | 76a66253 | j_mayer | /* interpreted as no-op */
|
5969 | 76a66253 | j_mayer | } |
5970 | 76a66253 | j_mayer | |
5971 | 76a66253 | j_mayer | /* icbt */
|
5972 | e8eaa2c0 | Blue Swirl | static void gen_icbt_440(DisasContext *ctx) |
5973 | 76a66253 | j_mayer | { |
5974 | 76a66253 | j_mayer | /* interpreted as no-op */
|
5975 | 76a66253 | j_mayer | /* XXX: specification say this is treated as a load by the MMU
|
5976 | 76a66253 | j_mayer | * but does not generate any exception
|
5977 | 76a66253 | j_mayer | */
|
5978 | 79aceca5 | bellard | } |
5979 | 79aceca5 | bellard | |
5980 | a9d9eb8f | j_mayer | /*** Altivec vector extension ***/
|
5981 | a9d9eb8f | j_mayer | /* Altivec registers moves */
|
5982 | a9d9eb8f | j_mayer | |
5983 | 564e571a | aurel32 | static always_inline TCGv_ptr gen_avr_ptr(int reg) |
5984 | 564e571a | aurel32 | { |
5985 | e4704b3b | aurel32 | TCGv_ptr r = tcg_temp_new_ptr(); |
5986 | 564e571a | aurel32 | tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg])); |
5987 | 564e571a | aurel32 | return r;
|
5988 | 564e571a | aurel32 | } |
5989 | 564e571a | aurel32 | |
5990 | a9d9eb8f | j_mayer | #define GEN_VR_LDX(name, opc2, opc3) \
|
5991 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
5992 | a9d9eb8f | j_mayer | { \ |
5993 | fe1e5c53 | aurel32 | TCGv EA; \ |
5994 | a9d9eb8f | j_mayer | if (unlikely(!ctx->altivec_enabled)) { \
|
5995 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
5996 | a9d9eb8f | j_mayer | return; \
|
5997 | a9d9eb8f | j_mayer | } \ |
5998 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); \ |
5999 | fe1e5c53 | aurel32 | EA = tcg_temp_new(); \ |
6000 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, EA); \ |
6001 | fe1e5c53 | aurel32 | tcg_gen_andi_tl(EA, EA, ~0xf); \
|
6002 | 76db3ba4 | aurel32 | if (ctx->le_mode) { \
|
6003 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ |
6004 | fe1e5c53 | aurel32 | tcg_gen_addi_tl(EA, EA, 8); \
|
6005 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
6006 | fe1e5c53 | aurel32 | } else { \
|
6007 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
6008 | fe1e5c53 | aurel32 | tcg_gen_addi_tl(EA, EA, 8); \
|
6009 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ |
6010 | fe1e5c53 | aurel32 | } \ |
6011 | fe1e5c53 | aurel32 | tcg_temp_free(EA); \ |
6012 | a9d9eb8f | j_mayer | } |
6013 | a9d9eb8f | j_mayer | |
6014 | a9d9eb8f | j_mayer | #define GEN_VR_STX(name, opc2, opc3) \
|
6015 | 99e300ef | Blue Swirl | static void gen_st##name(DisasContext *ctx) \ |
6016 | a9d9eb8f | j_mayer | { \ |
6017 | fe1e5c53 | aurel32 | TCGv EA; \ |
6018 | a9d9eb8f | j_mayer | if (unlikely(!ctx->altivec_enabled)) { \
|
6019 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
6020 | a9d9eb8f | j_mayer | return; \
|
6021 | a9d9eb8f | j_mayer | } \ |
6022 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); \ |
6023 | fe1e5c53 | aurel32 | EA = tcg_temp_new(); \ |
6024 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, EA); \ |
6025 | fe1e5c53 | aurel32 | tcg_gen_andi_tl(EA, EA, ~0xf); \
|
6026 | 76db3ba4 | aurel32 | if (ctx->le_mode) { \
|
6027 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ |
6028 | fe1e5c53 | aurel32 | tcg_gen_addi_tl(EA, EA, 8); \
|
6029 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
6030 | fe1e5c53 | aurel32 | } else { \
|
6031 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
6032 | fe1e5c53 | aurel32 | tcg_gen_addi_tl(EA, EA, 8); \
|
6033 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ |
6034 | fe1e5c53 | aurel32 | } \ |
6035 | fe1e5c53 | aurel32 | tcg_temp_free(EA); \ |
6036 | a9d9eb8f | j_mayer | } |
6037 | a9d9eb8f | j_mayer | |
6038 | cbfb6ae9 | aurel32 | #define GEN_VR_LVE(name, opc2, opc3) \
|
6039 | 99e300ef | Blue Swirl | static void gen_lve##name(DisasContext *ctx) \ |
6040 | cbfb6ae9 | aurel32 | { \ |
6041 | cbfb6ae9 | aurel32 | TCGv EA; \ |
6042 | cbfb6ae9 | aurel32 | TCGv_ptr rs; \ |
6043 | cbfb6ae9 | aurel32 | if (unlikely(!ctx->altivec_enabled)) { \
|
6044 | cbfb6ae9 | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
6045 | cbfb6ae9 | aurel32 | return; \
|
6046 | cbfb6ae9 | aurel32 | } \ |
6047 | cbfb6ae9 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); \ |
6048 | cbfb6ae9 | aurel32 | EA = tcg_temp_new(); \ |
6049 | cbfb6ae9 | aurel32 | gen_addr_reg_index(ctx, EA); \ |
6050 | cbfb6ae9 | aurel32 | rs = gen_avr_ptr(rS(ctx->opcode)); \ |
6051 | cbfb6ae9 | aurel32 | gen_helper_lve##name (rs, EA); \ |
6052 | cbfb6ae9 | aurel32 | tcg_temp_free(EA); \ |
6053 | cbfb6ae9 | aurel32 | tcg_temp_free_ptr(rs); \ |
6054 | cbfb6ae9 | aurel32 | } |
6055 | cbfb6ae9 | aurel32 | |
6056 | cbfb6ae9 | aurel32 | #define GEN_VR_STVE(name, opc2, opc3) \
|
6057 | 99e300ef | Blue Swirl | static void gen_stve##name(DisasContext *ctx) \ |
6058 | cbfb6ae9 | aurel32 | { \ |
6059 | cbfb6ae9 | aurel32 | TCGv EA; \ |
6060 | cbfb6ae9 | aurel32 | TCGv_ptr rs; \ |
6061 | cbfb6ae9 | aurel32 | if (unlikely(!ctx->altivec_enabled)) { \
|
6062 | cbfb6ae9 | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
6063 | cbfb6ae9 | aurel32 | return; \
|
6064 | cbfb6ae9 | aurel32 | } \ |
6065 | cbfb6ae9 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); \ |
6066 | cbfb6ae9 | aurel32 | EA = tcg_temp_new(); \ |
6067 | cbfb6ae9 | aurel32 | gen_addr_reg_index(ctx, EA); \ |
6068 | cbfb6ae9 | aurel32 | rs = gen_avr_ptr(rS(ctx->opcode)); \ |
6069 | cbfb6ae9 | aurel32 | gen_helper_stve##name (rs, EA); \ |
6070 | cbfb6ae9 | aurel32 | tcg_temp_free(EA); \ |
6071 | cbfb6ae9 | aurel32 | tcg_temp_free_ptr(rs); \ |
6072 | cbfb6ae9 | aurel32 | } |
6073 | cbfb6ae9 | aurel32 | |
6074 | fe1e5c53 | aurel32 | GEN_VR_LDX(lvx, 0x07, 0x03); |
6075 | a9d9eb8f | j_mayer | /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
|
6076 | fe1e5c53 | aurel32 | GEN_VR_LDX(lvxl, 0x07, 0x0B); |
6077 | a9d9eb8f | j_mayer | |
6078 | cbfb6ae9 | aurel32 | GEN_VR_LVE(bx, 0x07, 0x00); |
6079 | cbfb6ae9 | aurel32 | GEN_VR_LVE(hx, 0x07, 0x01); |
6080 | cbfb6ae9 | aurel32 | GEN_VR_LVE(wx, 0x07, 0x02); |
6081 | cbfb6ae9 | aurel32 | |
6082 | fe1e5c53 | aurel32 | GEN_VR_STX(svx, 0x07, 0x07); |
6083 | a9d9eb8f | j_mayer | /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
|
6084 | fe1e5c53 | aurel32 | GEN_VR_STX(svxl, 0x07, 0x0F); |
6085 | a9d9eb8f | j_mayer | |
6086 | cbfb6ae9 | aurel32 | GEN_VR_STVE(bx, 0x07, 0x04); |
6087 | cbfb6ae9 | aurel32 | GEN_VR_STVE(hx, 0x07, 0x05); |
6088 | cbfb6ae9 | aurel32 | GEN_VR_STVE(wx, 0x07, 0x06); |
6089 | cbfb6ae9 | aurel32 | |
6090 | 99e300ef | Blue Swirl | static void gen_lvsl(DisasContext *ctx) |
6091 | bf8d8ded | aurel32 | { |
6092 | bf8d8ded | aurel32 | TCGv_ptr rd; |
6093 | bf8d8ded | aurel32 | TCGv EA; |
6094 | bf8d8ded | aurel32 | if (unlikely(!ctx->altivec_enabled)) {
|
6095 | bf8d8ded | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); |
6096 | bf8d8ded | aurel32 | return;
|
6097 | bf8d8ded | aurel32 | } |
6098 | bf8d8ded | aurel32 | EA = tcg_temp_new(); |
6099 | bf8d8ded | aurel32 | gen_addr_reg_index(ctx, EA); |
6100 | bf8d8ded | aurel32 | rd = gen_avr_ptr(rD(ctx->opcode)); |
6101 | bf8d8ded | aurel32 | gen_helper_lvsl(rd, EA); |
6102 | bf8d8ded | aurel32 | tcg_temp_free(EA); |
6103 | bf8d8ded | aurel32 | tcg_temp_free_ptr(rd); |
6104 | bf8d8ded | aurel32 | } |
6105 | bf8d8ded | aurel32 | |
6106 | 99e300ef | Blue Swirl | static void gen_lvsr(DisasContext *ctx) |
6107 | bf8d8ded | aurel32 | { |
6108 | bf8d8ded | aurel32 | TCGv_ptr rd; |
6109 | bf8d8ded | aurel32 | TCGv EA; |
6110 | bf8d8ded | aurel32 | if (unlikely(!ctx->altivec_enabled)) {
|
6111 | bf8d8ded | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); |
6112 | bf8d8ded | aurel32 | return;
|
6113 | bf8d8ded | aurel32 | } |
6114 | bf8d8ded | aurel32 | EA = tcg_temp_new(); |
6115 | bf8d8ded | aurel32 | gen_addr_reg_index(ctx, EA); |
6116 | bf8d8ded | aurel32 | rd = gen_avr_ptr(rD(ctx->opcode)); |
6117 | bf8d8ded | aurel32 | gen_helper_lvsr(rd, EA); |
6118 | bf8d8ded | aurel32 | tcg_temp_free(EA); |
6119 | bf8d8ded | aurel32 | tcg_temp_free_ptr(rd); |
6120 | bf8d8ded | aurel32 | } |
6121 | bf8d8ded | aurel32 | |
6122 | 99e300ef | Blue Swirl | static void gen_mfvscr(DisasContext *ctx) |
6123 | 785f451b | aurel32 | { |
6124 | 785f451b | aurel32 | TCGv_i32 t; |
6125 | 785f451b | aurel32 | if (unlikely(!ctx->altivec_enabled)) {
|
6126 | 785f451b | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); |
6127 | 785f451b | aurel32 | return;
|
6128 | 785f451b | aurel32 | } |
6129 | 785f451b | aurel32 | tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
|
6130 | 785f451b | aurel32 | t = tcg_temp_new_i32(); |
6131 | 785f451b | aurel32 | tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, vscr)); |
6132 | 785f451b | aurel32 | tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t); |
6133 | fce5ecb7 | aurel32 | tcg_temp_free_i32(t); |
6134 | 785f451b | aurel32 | } |
6135 | 785f451b | aurel32 | |
6136 | 99e300ef | Blue Swirl | static void gen_mtvscr(DisasContext *ctx) |
6137 | 785f451b | aurel32 | { |
6138 | 6e87b7c7 | aurel32 | TCGv_ptr p; |
6139 | 785f451b | aurel32 | if (unlikely(!ctx->altivec_enabled)) {
|
6140 | 785f451b | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); |
6141 | 785f451b | aurel32 | return;
|
6142 | 785f451b | aurel32 | } |
6143 | 6e87b7c7 | aurel32 | p = gen_avr_ptr(rD(ctx->opcode)); |
6144 | 6e87b7c7 | aurel32 | gen_helper_mtvscr(p); |
6145 | 6e87b7c7 | aurel32 | tcg_temp_free_ptr(p); |
6146 | 785f451b | aurel32 | } |
6147 | 785f451b | aurel32 | |
6148 | 7a9b96cf | aurel32 | /* Logical operations */
|
6149 | 7a9b96cf | aurel32 | #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
|
6150 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
6151 | 7a9b96cf | aurel32 | { \ |
6152 | 7a9b96cf | aurel32 | if (unlikely(!ctx->altivec_enabled)) { \
|
6153 | 7a9b96cf | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
6154 | 7a9b96cf | aurel32 | return; \
|
6155 | 7a9b96cf | aurel32 | } \ |
6156 | 7a9b96cf | aurel32 | tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \ |
6157 | 7a9b96cf | aurel32 | tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \ |
6158 | 7a9b96cf | aurel32 | } |
6159 | 7a9b96cf | aurel32 | |
6160 | 7a9b96cf | aurel32 | GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16); |
6161 | 7a9b96cf | aurel32 | GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17); |
6162 | 7a9b96cf | aurel32 | GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18); |
6163 | 7a9b96cf | aurel32 | GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19); |
6164 | 7a9b96cf | aurel32 | GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20); |
6165 | 7a9b96cf | aurel32 | |
6166 | 8e27dd6f | aurel32 | #define GEN_VXFORM(name, opc2, opc3) \
|
6167 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
6168 | 8e27dd6f | aurel32 | { \ |
6169 | 8e27dd6f | aurel32 | TCGv_ptr ra, rb, rd; \ |
6170 | 8e27dd6f | aurel32 | if (unlikely(!ctx->altivec_enabled)) { \
|
6171 | 8e27dd6f | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
6172 | 8e27dd6f | aurel32 | return; \
|
6173 | 8e27dd6f | aurel32 | } \ |
6174 | 8e27dd6f | aurel32 | ra = gen_avr_ptr(rA(ctx->opcode)); \ |
6175 | 8e27dd6f | aurel32 | rb = gen_avr_ptr(rB(ctx->opcode)); \ |
6176 | 8e27dd6f | aurel32 | rd = gen_avr_ptr(rD(ctx->opcode)); \ |
6177 | 8e27dd6f | aurel32 | gen_helper_##name (rd, ra, rb); \ |
6178 | 8e27dd6f | aurel32 | tcg_temp_free_ptr(ra); \ |
6179 | 8e27dd6f | aurel32 | tcg_temp_free_ptr(rb); \ |
6180 | 8e27dd6f | aurel32 | tcg_temp_free_ptr(rd); \ |
6181 | 8e27dd6f | aurel32 | } |
6182 | 8e27dd6f | aurel32 | |
6183 | 7872c51c | aurel32 | GEN_VXFORM(vaddubm, 0, 0); |
6184 | 7872c51c | aurel32 | GEN_VXFORM(vadduhm, 0, 1); |
6185 | 7872c51c | aurel32 | GEN_VXFORM(vadduwm, 0, 2); |
6186 | 7872c51c | aurel32 | GEN_VXFORM(vsububm, 0, 16); |
6187 | 7872c51c | aurel32 | GEN_VXFORM(vsubuhm, 0, 17); |
6188 | 7872c51c | aurel32 | GEN_VXFORM(vsubuwm, 0, 18); |
6189 | e4039339 | aurel32 | GEN_VXFORM(vmaxub, 1, 0); |
6190 | e4039339 | aurel32 | GEN_VXFORM(vmaxuh, 1, 1); |
6191 | e4039339 | aurel32 | GEN_VXFORM(vmaxuw, 1, 2); |
6192 | e4039339 | aurel32 | GEN_VXFORM(vmaxsb, 1, 4); |
6193 | e4039339 | aurel32 | GEN_VXFORM(vmaxsh, 1, 5); |
6194 | e4039339 | aurel32 | GEN_VXFORM(vmaxsw, 1, 6); |
6195 | e4039339 | aurel32 | GEN_VXFORM(vminub, 1, 8); |
6196 | e4039339 | aurel32 | GEN_VXFORM(vminuh, 1, 9); |
6197 | e4039339 | aurel32 | GEN_VXFORM(vminuw, 1, 10); |
6198 | e4039339 | aurel32 | GEN_VXFORM(vminsb, 1, 12); |
6199 | e4039339 | aurel32 | GEN_VXFORM(vminsh, 1, 13); |
6200 | e4039339 | aurel32 | GEN_VXFORM(vminsw, 1, 14); |
6201 | fab3cbe9 | aurel32 | GEN_VXFORM(vavgub, 1, 16); |
6202 | fab3cbe9 | aurel32 | GEN_VXFORM(vavguh, 1, 17); |
6203 | fab3cbe9 | aurel32 | GEN_VXFORM(vavguw, 1, 18); |
6204 | fab3cbe9 | aurel32 | GEN_VXFORM(vavgsb, 1, 20); |
6205 | fab3cbe9 | aurel32 | GEN_VXFORM(vavgsh, 1, 21); |
6206 | fab3cbe9 | aurel32 | GEN_VXFORM(vavgsw, 1, 22); |
6207 | 3b430048 | aurel32 | GEN_VXFORM(vmrghb, 6, 0); |
6208 | 3b430048 | aurel32 | GEN_VXFORM(vmrghh, 6, 1); |
6209 | 3b430048 | aurel32 | GEN_VXFORM(vmrghw, 6, 2); |
6210 | 3b430048 | aurel32 | GEN_VXFORM(vmrglb, 6, 4); |
6211 | 3b430048 | aurel32 | GEN_VXFORM(vmrglh, 6, 5); |
6212 | 3b430048 | aurel32 | GEN_VXFORM(vmrglw, 6, 6); |
6213 | 2c277908 | aurel32 | GEN_VXFORM(vmuloub, 4, 0); |
6214 | 2c277908 | aurel32 | GEN_VXFORM(vmulouh, 4, 1); |
6215 | 2c277908 | aurel32 | GEN_VXFORM(vmulosb, 4, 4); |
6216 | 2c277908 | aurel32 | GEN_VXFORM(vmulosh, 4, 5); |
6217 | 2c277908 | aurel32 | GEN_VXFORM(vmuleub, 4, 8); |
6218 | 2c277908 | aurel32 | GEN_VXFORM(vmuleuh, 4, 9); |
6219 | 2c277908 | aurel32 | GEN_VXFORM(vmulesb, 4, 12); |
6220 | 2c277908 | aurel32 | GEN_VXFORM(vmulesh, 4, 13); |
6221 | d79f0809 | aurel32 | GEN_VXFORM(vslb, 2, 4); |
6222 | d79f0809 | aurel32 | GEN_VXFORM(vslh, 2, 5); |
6223 | d79f0809 | aurel32 | GEN_VXFORM(vslw, 2, 6); |
6224 | 07ef34c3 | aurel32 | GEN_VXFORM(vsrb, 2, 8); |
6225 | 07ef34c3 | aurel32 | GEN_VXFORM(vsrh, 2, 9); |
6226 | 07ef34c3 | aurel32 | GEN_VXFORM(vsrw, 2, 10); |
6227 | 07ef34c3 | aurel32 | GEN_VXFORM(vsrab, 2, 12); |
6228 | 07ef34c3 | aurel32 | GEN_VXFORM(vsrah, 2, 13); |
6229 | 07ef34c3 | aurel32 | GEN_VXFORM(vsraw, 2, 14); |
6230 | 7b239bec | aurel32 | GEN_VXFORM(vslo, 6, 16); |
6231 | 7b239bec | aurel32 | GEN_VXFORM(vsro, 6, 17); |
6232 | e343da72 | aurel32 | GEN_VXFORM(vaddcuw, 0, 6); |
6233 | e343da72 | aurel32 | GEN_VXFORM(vsubcuw, 0, 22); |
6234 | 5ab09f33 | aurel32 | GEN_VXFORM(vaddubs, 0, 8); |
6235 | 5ab09f33 | aurel32 | GEN_VXFORM(vadduhs, 0, 9); |
6236 | 5ab09f33 | aurel32 | GEN_VXFORM(vadduws, 0, 10); |
6237 | 5ab09f33 | aurel32 | GEN_VXFORM(vaddsbs, 0, 12); |
6238 | 5ab09f33 | aurel32 | GEN_VXFORM(vaddshs, 0, 13); |
6239 | 5ab09f33 | aurel32 | GEN_VXFORM(vaddsws, 0, 14); |
6240 | 5ab09f33 | aurel32 | GEN_VXFORM(vsububs, 0, 24); |
6241 | 5ab09f33 | aurel32 | GEN_VXFORM(vsubuhs, 0, 25); |
6242 | 5ab09f33 | aurel32 | GEN_VXFORM(vsubuws, 0, 26); |
6243 | 5ab09f33 | aurel32 | GEN_VXFORM(vsubsbs, 0, 28); |
6244 | 5ab09f33 | aurel32 | GEN_VXFORM(vsubshs, 0, 29); |
6245 | 5ab09f33 | aurel32 | GEN_VXFORM(vsubsws, 0, 30); |
6246 | 5e1d0985 | aurel32 | GEN_VXFORM(vrlb, 2, 0); |
6247 | 5e1d0985 | aurel32 | GEN_VXFORM(vrlh, 2, 1); |
6248 | 5e1d0985 | aurel32 | GEN_VXFORM(vrlw, 2, 2); |
6249 | d9430add | aurel32 | GEN_VXFORM(vsl, 2, 7); |
6250 | d9430add | aurel32 | GEN_VXFORM(vsr, 2, 11); |
6251 | 5335a145 | aurel32 | GEN_VXFORM(vpkuhum, 7, 0); |
6252 | 5335a145 | aurel32 | GEN_VXFORM(vpkuwum, 7, 1); |
6253 | 5335a145 | aurel32 | GEN_VXFORM(vpkuhus, 7, 2); |
6254 | 5335a145 | aurel32 | GEN_VXFORM(vpkuwus, 7, 3); |
6255 | 5335a145 | aurel32 | GEN_VXFORM(vpkshus, 7, 4); |
6256 | 5335a145 | aurel32 | GEN_VXFORM(vpkswus, 7, 5); |
6257 | 5335a145 | aurel32 | GEN_VXFORM(vpkshss, 7, 6); |
6258 | 5335a145 | aurel32 | GEN_VXFORM(vpkswss, 7, 7); |
6259 | 1dd9ffb9 | aurel32 | GEN_VXFORM(vpkpx, 7, 12); |
6260 | 8142cddd | aurel32 | GEN_VXFORM(vsum4ubs, 4, 24); |
6261 | 8142cddd | aurel32 | GEN_VXFORM(vsum4sbs, 4, 28); |
6262 | 8142cddd | aurel32 | GEN_VXFORM(vsum4shs, 4, 25); |
6263 | 8142cddd | aurel32 | GEN_VXFORM(vsum2sws, 4, 26); |
6264 | 8142cddd | aurel32 | GEN_VXFORM(vsumsws, 4, 30); |
6265 | 56fdd213 | aurel32 | GEN_VXFORM(vaddfp, 5, 0); |
6266 | 56fdd213 | aurel32 | GEN_VXFORM(vsubfp, 5, 1); |
6267 | 1536ff64 | aurel32 | GEN_VXFORM(vmaxfp, 5, 16); |
6268 | 1536ff64 | aurel32 | GEN_VXFORM(vminfp, 5, 17); |
6269 | fab3cbe9 | aurel32 | |
6270 | 0cbcd906 | aurel32 | #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
|
6271 | e8eaa2c0 | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
6272 | 0cbcd906 | aurel32 | { \ |
6273 | 0cbcd906 | aurel32 | TCGv_ptr ra, rb, rd; \ |
6274 | 0cbcd906 | aurel32 | if (unlikely(!ctx->altivec_enabled)) { \
|
6275 | 0cbcd906 | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
6276 | 0cbcd906 | aurel32 | return; \
|
6277 | 0cbcd906 | aurel32 | } \ |
6278 | 0cbcd906 | aurel32 | ra = gen_avr_ptr(rA(ctx->opcode)); \ |
6279 | 0cbcd906 | aurel32 | rb = gen_avr_ptr(rB(ctx->opcode)); \ |
6280 | 0cbcd906 | aurel32 | rd = gen_avr_ptr(rD(ctx->opcode)); \ |
6281 | 0cbcd906 | aurel32 | gen_helper_##opname (rd, ra, rb); \ |
6282 | 0cbcd906 | aurel32 | tcg_temp_free_ptr(ra); \ |
6283 | 0cbcd906 | aurel32 | tcg_temp_free_ptr(rb); \ |
6284 | 0cbcd906 | aurel32 | tcg_temp_free_ptr(rd); \ |
6285 | 0cbcd906 | aurel32 | } |
6286 | 0cbcd906 | aurel32 | |
6287 | 0cbcd906 | aurel32 | #define GEN_VXRFORM(name, opc2, opc3) \
|
6288 | 0cbcd906 | aurel32 | GEN_VXRFORM1(name, name, #name, opc2, opc3) \
|
6289 | 0cbcd906 | aurel32 | GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4))) |
6290 | 0cbcd906 | aurel32 | |
6291 | 1add6e23 | aurel32 | GEN_VXRFORM(vcmpequb, 3, 0) |
6292 | 1add6e23 | aurel32 | GEN_VXRFORM(vcmpequh, 3, 1) |
6293 | 1add6e23 | aurel32 | GEN_VXRFORM(vcmpequw, 3, 2) |
6294 | 1add6e23 | aurel32 | GEN_VXRFORM(vcmpgtsb, 3, 12) |
6295 | 1add6e23 | aurel32 | GEN_VXRFORM(vcmpgtsh, 3, 13) |
6296 | 1add6e23 | aurel32 | GEN_VXRFORM(vcmpgtsw, 3, 14) |
6297 | 1add6e23 | aurel32 | GEN_VXRFORM(vcmpgtub, 3, 8) |
6298 | 1add6e23 | aurel32 | GEN_VXRFORM(vcmpgtuh, 3, 9) |
6299 | 1add6e23 | aurel32 | GEN_VXRFORM(vcmpgtuw, 3, 10) |
6300 | 819ca121 | aurel32 | GEN_VXRFORM(vcmpeqfp, 3, 3) |
6301 | 819ca121 | aurel32 | GEN_VXRFORM(vcmpgefp, 3, 7) |
6302 | 819ca121 | aurel32 | GEN_VXRFORM(vcmpgtfp, 3, 11) |
6303 | 819ca121 | aurel32 | GEN_VXRFORM(vcmpbfp, 3, 15) |
6304 | 1add6e23 | aurel32 | |
6305 | c026766b | aurel32 | #define GEN_VXFORM_SIMM(name, opc2, opc3) \
|
6306 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
6307 | c026766b | aurel32 | { \ |
6308 | c026766b | aurel32 | TCGv_ptr rd; \ |
6309 | c026766b | aurel32 | TCGv_i32 simm; \ |
6310 | c026766b | aurel32 | if (unlikely(!ctx->altivec_enabled)) { \
|
6311 | c026766b | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
6312 | c026766b | aurel32 | return; \
|
6313 | c026766b | aurel32 | } \ |
6314 | c026766b | aurel32 | simm = tcg_const_i32(SIMM5(ctx->opcode)); \ |
6315 | c026766b | aurel32 | rd = gen_avr_ptr(rD(ctx->opcode)); \ |
6316 | c026766b | aurel32 | gen_helper_##name (rd, simm); \ |
6317 | c026766b | aurel32 | tcg_temp_free_i32(simm); \ |
6318 | c026766b | aurel32 | tcg_temp_free_ptr(rd); \ |
6319 | c026766b | aurel32 | } |
6320 | c026766b | aurel32 | |
6321 | c026766b | aurel32 | GEN_VXFORM_SIMM(vspltisb, 6, 12); |
6322 | c026766b | aurel32 | GEN_VXFORM_SIMM(vspltish, 6, 13); |
6323 | c026766b | aurel32 | GEN_VXFORM_SIMM(vspltisw, 6, 14); |
6324 | c026766b | aurel32 | |
6325 | de5f2484 | aurel32 | #define GEN_VXFORM_NOA(name, opc2, opc3) \
|
6326 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
6327 | de5f2484 | aurel32 | { \ |
6328 | de5f2484 | aurel32 | TCGv_ptr rb, rd; \ |
6329 | de5f2484 | aurel32 | if (unlikely(!ctx->altivec_enabled)) { \
|
6330 | de5f2484 | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
6331 | de5f2484 | aurel32 | return; \
|
6332 | de5f2484 | aurel32 | } \ |
6333 | de5f2484 | aurel32 | rb = gen_avr_ptr(rB(ctx->opcode)); \ |
6334 | de5f2484 | aurel32 | rd = gen_avr_ptr(rD(ctx->opcode)); \ |
6335 | de5f2484 | aurel32 | gen_helper_##name (rd, rb); \ |
6336 | de5f2484 | aurel32 | tcg_temp_free_ptr(rb); \ |
6337 | de5f2484 | aurel32 | tcg_temp_free_ptr(rd); \ |
6338 | de5f2484 | aurel32 | } |
6339 | de5f2484 | aurel32 | |
6340 | 6cf1c6e5 | aurel32 | GEN_VXFORM_NOA(vupkhsb, 7, 8); |
6341 | 6cf1c6e5 | aurel32 | GEN_VXFORM_NOA(vupkhsh, 7, 9); |
6342 | 6cf1c6e5 | aurel32 | GEN_VXFORM_NOA(vupklsb, 7, 10); |
6343 | 6cf1c6e5 | aurel32 | GEN_VXFORM_NOA(vupklsh, 7, 11); |
6344 | 79f85c3a | aurel32 | GEN_VXFORM_NOA(vupkhpx, 7, 13); |
6345 | 79f85c3a | aurel32 | GEN_VXFORM_NOA(vupklpx, 7, 15); |
6346 | bdfbac35 | aurel32 | GEN_VXFORM_NOA(vrefp, 5, 4); |
6347 | 071fc3b1 | aurel32 | GEN_VXFORM_NOA(vrsqrtefp, 5, 5); |
6348 | b580763f | aurel32 | GEN_VXFORM_NOA(vlogefp, 5, 7); |
6349 | f6b19645 | aurel32 | GEN_VXFORM_NOA(vrfim, 5, 8); |
6350 | f6b19645 | aurel32 | GEN_VXFORM_NOA(vrfin, 5, 9); |
6351 | f6b19645 | aurel32 | GEN_VXFORM_NOA(vrfip, 5, 10); |
6352 | f6b19645 | aurel32 | GEN_VXFORM_NOA(vrfiz, 5, 11); |
6353 | 79f85c3a | aurel32 | |
6354 | 21d21583 | aurel32 | #define GEN_VXFORM_SIMM(name, opc2, opc3) \
|
6355 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
6356 | 21d21583 | aurel32 | { \ |
6357 | 21d21583 | aurel32 | TCGv_ptr rd; \ |
6358 | 21d21583 | aurel32 | TCGv_i32 simm; \ |
6359 | 21d21583 | aurel32 | if (unlikely(!ctx->altivec_enabled)) { \
|
6360 | 21d21583 | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
6361 | 21d21583 | aurel32 | return; \
|
6362 | 21d21583 | aurel32 | } \ |
6363 | 21d21583 | aurel32 | simm = tcg_const_i32(SIMM5(ctx->opcode)); \ |
6364 | 21d21583 | aurel32 | rd = gen_avr_ptr(rD(ctx->opcode)); \ |
6365 | 21d21583 | aurel32 | gen_helper_##name (rd, simm); \ |
6366 | 21d21583 | aurel32 | tcg_temp_free_i32(simm); \ |
6367 | 21d21583 | aurel32 | tcg_temp_free_ptr(rd); \ |
6368 | 21d21583 | aurel32 | } |
6369 | 21d21583 | aurel32 | |
6370 | 27a4edb3 | aurel32 | #define GEN_VXFORM_UIMM(name, opc2, opc3) \
|
6371 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
6372 | 27a4edb3 | aurel32 | { \ |
6373 | 27a4edb3 | aurel32 | TCGv_ptr rb, rd; \ |
6374 | 27a4edb3 | aurel32 | TCGv_i32 uimm; \ |
6375 | 27a4edb3 | aurel32 | if (unlikely(!ctx->altivec_enabled)) { \
|
6376 | 27a4edb3 | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
6377 | 27a4edb3 | aurel32 | return; \
|
6378 | 27a4edb3 | aurel32 | } \ |
6379 | 27a4edb3 | aurel32 | uimm = tcg_const_i32(UIMM5(ctx->opcode)); \ |
6380 | 27a4edb3 | aurel32 | rb = gen_avr_ptr(rB(ctx->opcode)); \ |
6381 | 27a4edb3 | aurel32 | rd = gen_avr_ptr(rD(ctx->opcode)); \ |
6382 | 27a4edb3 | aurel32 | gen_helper_##name (rd, rb, uimm); \ |
6383 | 27a4edb3 | aurel32 | tcg_temp_free_i32(uimm); \ |
6384 | 27a4edb3 | aurel32 | tcg_temp_free_ptr(rb); \ |
6385 | 27a4edb3 | aurel32 | tcg_temp_free_ptr(rd); \ |
6386 | 27a4edb3 | aurel32 | } |
6387 | 27a4edb3 | aurel32 | |
6388 | e4e6bee7 | aurel32 | GEN_VXFORM_UIMM(vspltb, 6, 8); |
6389 | e4e6bee7 | aurel32 | GEN_VXFORM_UIMM(vsplth, 6, 9); |
6390 | e4e6bee7 | aurel32 | GEN_VXFORM_UIMM(vspltw, 6, 10); |
6391 | e140632e | aurel32 | GEN_VXFORM_UIMM(vcfux, 5, 12); |
6392 | e140632e | aurel32 | GEN_VXFORM_UIMM(vcfsx, 5, 13); |
6393 | 875b31db | aurel32 | GEN_VXFORM_UIMM(vctuxs, 5, 14); |
6394 | 875b31db | aurel32 | GEN_VXFORM_UIMM(vctsxs, 5, 15); |
6395 | e4e6bee7 | aurel32 | |
6396 | 99e300ef | Blue Swirl | static void gen_vsldoi(DisasContext *ctx) |
6397 | cd633b10 | aurel32 | { |
6398 | cd633b10 | aurel32 | TCGv_ptr ra, rb, rd; |
6399 | fce5ecb7 | aurel32 | TCGv_i32 sh; |
6400 | cd633b10 | aurel32 | if (unlikely(!ctx->altivec_enabled)) {
|
6401 | cd633b10 | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); |
6402 | cd633b10 | aurel32 | return;
|
6403 | cd633b10 | aurel32 | } |
6404 | cd633b10 | aurel32 | ra = gen_avr_ptr(rA(ctx->opcode)); |
6405 | cd633b10 | aurel32 | rb = gen_avr_ptr(rB(ctx->opcode)); |
6406 | cd633b10 | aurel32 | rd = gen_avr_ptr(rD(ctx->opcode)); |
6407 | cd633b10 | aurel32 | sh = tcg_const_i32(VSH(ctx->opcode)); |
6408 | cd633b10 | aurel32 | gen_helper_vsldoi (rd, ra, rb, sh); |
6409 | cd633b10 | aurel32 | tcg_temp_free_ptr(ra); |
6410 | cd633b10 | aurel32 | tcg_temp_free_ptr(rb); |
6411 | cd633b10 | aurel32 | tcg_temp_free_ptr(rd); |
6412 | fce5ecb7 | aurel32 | tcg_temp_free_i32(sh); |
6413 | cd633b10 | aurel32 | } |
6414 | cd633b10 | aurel32 | |
6415 | 707cec33 | aurel32 | #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
|
6416 | 99e300ef | Blue Swirl | static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ |
6417 | 707cec33 | aurel32 | { \ |
6418 | 707cec33 | aurel32 | TCGv_ptr ra, rb, rc, rd; \ |
6419 | 707cec33 | aurel32 | if (unlikely(!ctx->altivec_enabled)) { \
|
6420 | 707cec33 | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
6421 | 707cec33 | aurel32 | return; \
|
6422 | 707cec33 | aurel32 | } \ |
6423 | 707cec33 | aurel32 | ra = gen_avr_ptr(rA(ctx->opcode)); \ |
6424 | 707cec33 | aurel32 | rb = gen_avr_ptr(rB(ctx->opcode)); \ |
6425 | 707cec33 | aurel32 | rc = gen_avr_ptr(rC(ctx->opcode)); \ |
6426 | 707cec33 | aurel32 | rd = gen_avr_ptr(rD(ctx->opcode)); \ |
6427 | 707cec33 | aurel32 | if (Rc(ctx->opcode)) { \
|
6428 | 707cec33 | aurel32 | gen_helper_##name1 (rd, ra, rb, rc); \ |
6429 | 707cec33 | aurel32 | } else { \
|
6430 | 707cec33 | aurel32 | gen_helper_##name0 (rd, ra, rb, rc); \ |
6431 | 707cec33 | aurel32 | } \ |
6432 | 707cec33 | aurel32 | tcg_temp_free_ptr(ra); \ |
6433 | 707cec33 | aurel32 | tcg_temp_free_ptr(rb); \ |
6434 | 707cec33 | aurel32 | tcg_temp_free_ptr(rc); \ |
6435 | 707cec33 | aurel32 | tcg_temp_free_ptr(rd); \ |
6436 | 707cec33 | aurel32 | } |
6437 | 707cec33 | aurel32 | |
6438 | b161ae27 | aurel32 | GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
|
6439 | b161ae27 | aurel32 | |
6440 | 99e300ef | Blue Swirl | static void gen_vmladduhm(DisasContext *ctx) |
6441 | bcd2ee23 | aurel32 | { |
6442 | bcd2ee23 | aurel32 | TCGv_ptr ra, rb, rc, rd; |
6443 | bcd2ee23 | aurel32 | if (unlikely(!ctx->altivec_enabled)) {
|
6444 | bcd2ee23 | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); |
6445 | bcd2ee23 | aurel32 | return;
|
6446 | bcd2ee23 | aurel32 | } |
6447 | bcd2ee23 | aurel32 | ra = gen_avr_ptr(rA(ctx->opcode)); |
6448 | bcd2ee23 | aurel32 | rb = gen_avr_ptr(rB(ctx->opcode)); |
6449 | bcd2ee23 | aurel32 | rc = gen_avr_ptr(rC(ctx->opcode)); |
6450 | bcd2ee23 | aurel32 | rd = gen_avr_ptr(rD(ctx->opcode)); |
6451 | bcd2ee23 | aurel32 | gen_helper_vmladduhm(rd, ra, rb, rc); |
6452 | bcd2ee23 | aurel32 | tcg_temp_free_ptr(ra); |
6453 | bcd2ee23 | aurel32 | tcg_temp_free_ptr(rb); |
6454 | bcd2ee23 | aurel32 | tcg_temp_free_ptr(rc); |
6455 | bcd2ee23 | aurel32 | tcg_temp_free_ptr(rd); |
6456 | bcd2ee23 | aurel32 | } |
6457 | bcd2ee23 | aurel32 | |
6458 | b04ae981 | aurel32 | GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
|
6459 | 4d9903b6 | aurel32 | GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
|
6460 | eae07261 | aurel32 | GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
|
6461 | d1258698 | aurel32 | GEN_VAFORM_PAIRED(vsel, vperm, 21)
|
6462 | 35cf7c7e | aurel32 | GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
|
6463 | b04ae981 | aurel32 | |
6464 | 0487d6a8 | j_mayer | /*** SPE extension ***/
|
6465 | 0487d6a8 | j_mayer | /* Register moves */
|
6466 | 3cd7d1dd | j_mayer | |
6467 | a7812ae4 | pbrook | static always_inline void gen_load_gpr64(TCGv_i64 t, int reg) { |
6468 | f78fb44e | aurel32 | #if defined(TARGET_PPC64)
|
6469 | f78fb44e | aurel32 | tcg_gen_mov_i64(t, cpu_gpr[reg]); |
6470 | f78fb44e | aurel32 | #else
|
6471 | 36aa55dc | pbrook | tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]); |
6472 | 3cd7d1dd | j_mayer | #endif
|
6473 | f78fb44e | aurel32 | } |
6474 | 3cd7d1dd | j_mayer | |
6475 | a7812ae4 | pbrook | static always_inline void gen_store_gpr64(int reg, TCGv_i64 t) { |
6476 | f78fb44e | aurel32 | #if defined(TARGET_PPC64)
|
6477 | f78fb44e | aurel32 | tcg_gen_mov_i64(cpu_gpr[reg], t); |
6478 | f78fb44e | aurel32 | #else
|
6479 | a7812ae4 | pbrook | TCGv_i64 tmp = tcg_temp_new_i64(); |
6480 | f78fb44e | aurel32 | tcg_gen_trunc_i64_i32(cpu_gpr[reg], t); |
6481 | f78fb44e | aurel32 | tcg_gen_shri_i64(tmp, t, 32);
|
6482 | f78fb44e | aurel32 | tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp); |
6483 | a7812ae4 | pbrook | tcg_temp_free_i64(tmp); |
6484 | 3cd7d1dd | j_mayer | #endif
|
6485 | f78fb44e | aurel32 | } |
6486 | 3cd7d1dd | j_mayer | |
6487 | 0487d6a8 | j_mayer | #define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
|
6488 | 99e300ef | Blue Swirl | static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ |
6489 | 0487d6a8 | j_mayer | { \ |
6490 | 0487d6a8 | j_mayer | if (Rc(ctx->opcode)) \
|
6491 | 0487d6a8 | j_mayer | gen_##name1(ctx); \ |
6492 | 0487d6a8 | j_mayer | else \
|
6493 | 0487d6a8 | j_mayer | gen_##name0(ctx); \ |
6494 | 0487d6a8 | j_mayer | } |
6495 | 0487d6a8 | j_mayer | |
6496 | 0487d6a8 | j_mayer | /* Handler for undefined SPE opcodes */
|
6497 | b068d6a7 | j_mayer | static always_inline void gen_speundef (DisasContext *ctx) |
6498 | 0487d6a8 | j_mayer | { |
6499 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
6500 | 0487d6a8 | j_mayer | } |
6501 | 0487d6a8 | j_mayer | |
6502 | 57951c27 | aurel32 | /* SPE logic */
|
6503 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
6504 | 57951c27 | aurel32 | #define GEN_SPEOP_LOGIC2(name, tcg_op) \
|
6505 | b068d6a7 | j_mayer | static always_inline void gen_##name (DisasContext *ctx) \ |
6506 | 0487d6a8 | j_mayer | { \ |
6507 | 0487d6a8 | j_mayer | if (unlikely(!ctx->spe_enabled)) { \
|
6508 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
6509 | 0487d6a8 | j_mayer | return; \
|
6510 | 0487d6a8 | j_mayer | } \ |
6511 | 57951c27 | aurel32 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ |
6512 | 57951c27 | aurel32 | cpu_gpr[rB(ctx->opcode)]); \ |
6513 | 57951c27 | aurel32 | } |
6514 | 57951c27 | aurel32 | #else
|
6515 | 57951c27 | aurel32 | #define GEN_SPEOP_LOGIC2(name, tcg_op) \
|
6516 | 57951c27 | aurel32 | static always_inline void gen_##name (DisasContext *ctx) \ |
6517 | 57951c27 | aurel32 | { \ |
6518 | 57951c27 | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
6519 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
6520 | 57951c27 | aurel32 | return; \
|
6521 | 57951c27 | aurel32 | } \ |
6522 | 57951c27 | aurel32 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ |
6523 | 57951c27 | aurel32 | cpu_gpr[rB(ctx->opcode)]); \ |
6524 | 57951c27 | aurel32 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \ |
6525 | 57951c27 | aurel32 | cpu_gprh[rB(ctx->opcode)]); \ |
6526 | 0487d6a8 | j_mayer | } |
6527 | 57951c27 | aurel32 | #endif
|
6528 | 57951c27 | aurel32 | |
6529 | 57951c27 | aurel32 | GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl); |
6530 | 57951c27 | aurel32 | GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl); |
6531 | 57951c27 | aurel32 | GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl); |
6532 | 57951c27 | aurel32 | GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl); |
6533 | 57951c27 | aurel32 | GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl); |
6534 | 57951c27 | aurel32 | GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl); |
6535 | 57951c27 | aurel32 | GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl); |
6536 | 57951c27 | aurel32 | GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl); |
6537 | 0487d6a8 | j_mayer | |
6538 | 57951c27 | aurel32 | /* SPE logic immediate */
|
6539 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
6540 | 57951c27 | aurel32 | #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
|
6541 | 3d3a6a0a | aurel32 | static always_inline void gen_##name (DisasContext *ctx) \ |
6542 | 3d3a6a0a | aurel32 | { \ |
6543 | 3d3a6a0a | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
6544 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
6545 | 3d3a6a0a | aurel32 | return; \
|
6546 | 3d3a6a0a | aurel32 | } \ |
6547 | a7812ae4 | pbrook | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
6548 | a7812ae4 | pbrook | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ |
6549 | a7812ae4 | pbrook | TCGv_i64 t2 = tcg_temp_local_new_i64(); \ |
6550 | 57951c27 | aurel32 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
6551 | 57951c27 | aurel32 | tcg_opi(t0, t0, rB(ctx->opcode)); \ |
6552 | 57951c27 | aurel32 | tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
|
6553 | 57951c27 | aurel32 | tcg_gen_trunc_i64_i32(t1, t2); \ |
6554 | a7812ae4 | pbrook | tcg_temp_free_i64(t2); \ |
6555 | 57951c27 | aurel32 | tcg_opi(t1, t1, rB(ctx->opcode)); \ |
6556 | 57951c27 | aurel32 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \ |
6557 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); \ |
6558 | a7812ae4 | pbrook | tcg_temp_free_i32(t1); \ |
6559 | 3d3a6a0a | aurel32 | } |
6560 | 57951c27 | aurel32 | #else
|
6561 | 57951c27 | aurel32 | #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
|
6562 | b068d6a7 | j_mayer | static always_inline void gen_##name (DisasContext *ctx) \ |
6563 | 0487d6a8 | j_mayer | { \ |
6564 | 0487d6a8 | j_mayer | if (unlikely(!ctx->spe_enabled)) { \
|
6565 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
6566 | 0487d6a8 | j_mayer | return; \
|
6567 | 0487d6a8 | j_mayer | } \ |
6568 | 57951c27 | aurel32 | tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ |
6569 | 57951c27 | aurel32 | rB(ctx->opcode)); \ |
6570 | 57951c27 | aurel32 | tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \ |
6571 | 57951c27 | aurel32 | rB(ctx->opcode)); \ |
6572 | 0487d6a8 | j_mayer | } |
6573 | 57951c27 | aurel32 | #endif
|
6574 | 57951c27 | aurel32 | GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32); |
6575 | 57951c27 | aurel32 | GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32); |
6576 | 57951c27 | aurel32 | GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32); |
6577 | 57951c27 | aurel32 | GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32); |
6578 | 0487d6a8 | j_mayer | |
6579 | 57951c27 | aurel32 | /* SPE arithmetic */
|
6580 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
6581 | 57951c27 | aurel32 | #define GEN_SPEOP_ARITH1(name, tcg_op) \
|
6582 | b068d6a7 | j_mayer | static always_inline void gen_##name (DisasContext *ctx) \ |
6583 | 0487d6a8 | j_mayer | { \ |
6584 | 0487d6a8 | j_mayer | if (unlikely(!ctx->spe_enabled)) { \
|
6585 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
6586 | 0487d6a8 | j_mayer | return; \
|
6587 | 0487d6a8 | j_mayer | } \ |
6588 | a7812ae4 | pbrook | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
6589 | a7812ae4 | pbrook | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ |
6590 | a7812ae4 | pbrook | TCGv_i64 t2 = tcg_temp_local_new_i64(); \ |
6591 | 57951c27 | aurel32 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
6592 | 57951c27 | aurel32 | tcg_op(t0, t0); \ |
6593 | 57951c27 | aurel32 | tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
|
6594 | 57951c27 | aurel32 | tcg_gen_trunc_i64_i32(t1, t2); \ |
6595 | a7812ae4 | pbrook | tcg_temp_free_i64(t2); \ |
6596 | 57951c27 | aurel32 | tcg_op(t1, t1); \ |
6597 | 57951c27 | aurel32 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \ |
6598 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); \ |
6599 | a7812ae4 | pbrook | tcg_temp_free_i32(t1); \ |
6600 | 0487d6a8 | j_mayer | } |
6601 | 57951c27 | aurel32 | #else
|
6602 | a7812ae4 | pbrook | #define GEN_SPEOP_ARITH1(name, tcg_op) \
|
6603 | 57951c27 | aurel32 | static always_inline void gen_##name (DisasContext *ctx) \ |
6604 | 57951c27 | aurel32 | { \ |
6605 | 57951c27 | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
6606 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
6607 | 57951c27 | aurel32 | return; \
|
6608 | 57951c27 | aurel32 | } \ |
6609 | 57951c27 | aurel32 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \ |
6610 | 57951c27 | aurel32 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \ |
6611 | 57951c27 | aurel32 | } |
6612 | 57951c27 | aurel32 | #endif
|
6613 | 0487d6a8 | j_mayer | |
6614 | a7812ae4 | pbrook | static always_inline void gen_op_evabs (TCGv_i32 ret, TCGv_i32 arg1) |
6615 | 57951c27 | aurel32 | { |
6616 | 57951c27 | aurel32 | int l1 = gen_new_label();
|
6617 | 57951c27 | aurel32 | int l2 = gen_new_label();
|
6618 | 0487d6a8 | j_mayer | |
6619 | 57951c27 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
|
6620 | 57951c27 | aurel32 | tcg_gen_neg_i32(ret, arg1); |
6621 | 57951c27 | aurel32 | tcg_gen_br(l2); |
6622 | 57951c27 | aurel32 | gen_set_label(l1); |
6623 | a7812ae4 | pbrook | tcg_gen_mov_i32(ret, arg1); |
6624 | 57951c27 | aurel32 | gen_set_label(l2); |
6625 | 57951c27 | aurel32 | } |
6626 | 57951c27 | aurel32 | GEN_SPEOP_ARITH1(evabs, gen_op_evabs); |
6627 | 57951c27 | aurel32 | GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32); |
6628 | 57951c27 | aurel32 | GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32); |
6629 | 57951c27 | aurel32 | GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32); |
6630 | a7812ae4 | pbrook | static always_inline void gen_op_evrndw (TCGv_i32 ret, TCGv_i32 arg1) |
6631 | 0487d6a8 | j_mayer | { |
6632 | 57951c27 | aurel32 | tcg_gen_addi_i32(ret, arg1, 0x8000);
|
6633 | 57951c27 | aurel32 | tcg_gen_ext16u_i32(ret, ret); |
6634 | 57951c27 | aurel32 | } |
6635 | 57951c27 | aurel32 | GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw); |
6636 | a7812ae4 | pbrook | GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32); |
6637 | a7812ae4 | pbrook | GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32); |
6638 | 0487d6a8 | j_mayer | |
6639 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
6640 | 57951c27 | aurel32 | #define GEN_SPEOP_ARITH2(name, tcg_op) \
|
6641 | 57951c27 | aurel32 | static always_inline void gen_##name (DisasContext *ctx) \ |
6642 | 0487d6a8 | j_mayer | { \ |
6643 | 0487d6a8 | j_mayer | if (unlikely(!ctx->spe_enabled)) { \
|
6644 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
6645 | 0487d6a8 | j_mayer | return; \
|
6646 | 0487d6a8 | j_mayer | } \ |
6647 | a7812ae4 | pbrook | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
6648 | a7812ae4 | pbrook | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ |
6649 | a7812ae4 | pbrook | TCGv_i32 t2 = tcg_temp_local_new_i32(); \ |
6650 | 501e23c4 | aurel32 | TCGv_i64 t3 = tcg_temp_local_new_i64(); \ |
6651 | 57951c27 | aurel32 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
6652 | 57951c27 | aurel32 | tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \ |
6653 | 57951c27 | aurel32 | tcg_op(t0, t0, t2); \ |
6654 | 57951c27 | aurel32 | tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
|
6655 | 57951c27 | aurel32 | tcg_gen_trunc_i64_i32(t1, t3); \ |
6656 | 57951c27 | aurel32 | tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
|
6657 | 57951c27 | aurel32 | tcg_gen_trunc_i64_i32(t2, t3); \ |
6658 | a7812ae4 | pbrook | tcg_temp_free_i64(t3); \ |
6659 | 57951c27 | aurel32 | tcg_op(t1, t1, t2); \ |
6660 | a7812ae4 | pbrook | tcg_temp_free_i32(t2); \ |
6661 | 57951c27 | aurel32 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \ |
6662 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); \ |
6663 | a7812ae4 | pbrook | tcg_temp_free_i32(t1); \ |
6664 | 0487d6a8 | j_mayer | } |
6665 | 57951c27 | aurel32 | #else
|
6666 | 57951c27 | aurel32 | #define GEN_SPEOP_ARITH2(name, tcg_op) \
|
6667 | 57951c27 | aurel32 | static always_inline void gen_##name (DisasContext *ctx) \ |
6668 | 0487d6a8 | j_mayer | { \ |
6669 | 0487d6a8 | j_mayer | if (unlikely(!ctx->spe_enabled)) { \
|
6670 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
6671 | 0487d6a8 | j_mayer | return; \
|
6672 | 0487d6a8 | j_mayer | } \ |
6673 | 57951c27 | aurel32 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ |
6674 | 57951c27 | aurel32 | cpu_gpr[rB(ctx->opcode)]); \ |
6675 | 57951c27 | aurel32 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \ |
6676 | 57951c27 | aurel32 | cpu_gprh[rB(ctx->opcode)]); \ |
6677 | 0487d6a8 | j_mayer | } |
6678 | 57951c27 | aurel32 | #endif
|
6679 | 0487d6a8 | j_mayer | |
6680 | a7812ae4 | pbrook | static always_inline void gen_op_evsrwu (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
6681 | 57951c27 | aurel32 | { |
6682 | a7812ae4 | pbrook | TCGv_i32 t0; |
6683 | 57951c27 | aurel32 | int l1, l2;
|
6684 | 0487d6a8 | j_mayer | |
6685 | 57951c27 | aurel32 | l1 = gen_new_label(); |
6686 | 57951c27 | aurel32 | l2 = gen_new_label(); |
6687 | a7812ae4 | pbrook | t0 = tcg_temp_local_new_i32(); |
6688 | 57951c27 | aurel32 | /* No error here: 6 bits are used */
|
6689 | 57951c27 | aurel32 | tcg_gen_andi_i32(t0, arg2, 0x3F);
|
6690 | 57951c27 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
|
6691 | 57951c27 | aurel32 | tcg_gen_shr_i32(ret, arg1, t0); |
6692 | 57951c27 | aurel32 | tcg_gen_br(l2); |
6693 | 57951c27 | aurel32 | gen_set_label(l1); |
6694 | 57951c27 | aurel32 | tcg_gen_movi_i32(ret, 0);
|
6695 | 57951c27 | aurel32 | tcg_gen_br(l2); |
6696 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); |
6697 | 57951c27 | aurel32 | } |
6698 | 57951c27 | aurel32 | GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu); |
6699 | a7812ae4 | pbrook | static always_inline void gen_op_evsrws (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
6700 | 57951c27 | aurel32 | { |
6701 | a7812ae4 | pbrook | TCGv_i32 t0; |
6702 | 57951c27 | aurel32 | int l1, l2;
|
6703 | 57951c27 | aurel32 | |
6704 | 57951c27 | aurel32 | l1 = gen_new_label(); |
6705 | 57951c27 | aurel32 | l2 = gen_new_label(); |
6706 | a7812ae4 | pbrook | t0 = tcg_temp_local_new_i32(); |
6707 | 57951c27 | aurel32 | /* No error here: 6 bits are used */
|
6708 | 57951c27 | aurel32 | tcg_gen_andi_i32(t0, arg2, 0x3F);
|
6709 | 57951c27 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
|
6710 | 57951c27 | aurel32 | tcg_gen_sar_i32(ret, arg1, t0); |
6711 | 57951c27 | aurel32 | tcg_gen_br(l2); |
6712 | 57951c27 | aurel32 | gen_set_label(l1); |
6713 | 57951c27 | aurel32 | tcg_gen_movi_i32(ret, 0);
|
6714 | 57951c27 | aurel32 | tcg_gen_br(l2); |
6715 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); |
6716 | 57951c27 | aurel32 | } |
6717 | 57951c27 | aurel32 | GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws); |
6718 | a7812ae4 | pbrook | static always_inline void gen_op_evslw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
6719 | 57951c27 | aurel32 | { |
6720 | a7812ae4 | pbrook | TCGv_i32 t0; |
6721 | 57951c27 | aurel32 | int l1, l2;
|
6722 | 57951c27 | aurel32 | |
6723 | 57951c27 | aurel32 | l1 = gen_new_label(); |
6724 | 57951c27 | aurel32 | l2 = gen_new_label(); |
6725 | a7812ae4 | pbrook | t0 = tcg_temp_local_new_i32(); |
6726 | 57951c27 | aurel32 | /* No error here: 6 bits are used */
|
6727 | 57951c27 | aurel32 | tcg_gen_andi_i32(t0, arg2, 0x3F);
|
6728 | 57951c27 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
|
6729 | 57951c27 | aurel32 | tcg_gen_shl_i32(ret, arg1, t0); |
6730 | 57951c27 | aurel32 | tcg_gen_br(l2); |
6731 | 57951c27 | aurel32 | gen_set_label(l1); |
6732 | 57951c27 | aurel32 | tcg_gen_movi_i32(ret, 0);
|
6733 | 57951c27 | aurel32 | tcg_gen_br(l2); |
6734 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); |
6735 | 57951c27 | aurel32 | } |
6736 | 57951c27 | aurel32 | GEN_SPEOP_ARITH2(evslw, gen_op_evslw); |
6737 | a7812ae4 | pbrook | static always_inline void gen_op_evrlw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
6738 | 57951c27 | aurel32 | { |
6739 | a7812ae4 | pbrook | TCGv_i32 t0 = tcg_temp_new_i32(); |
6740 | 57951c27 | aurel32 | tcg_gen_andi_i32(t0, arg2, 0x1F);
|
6741 | 57951c27 | aurel32 | tcg_gen_rotl_i32(ret, arg1, t0); |
6742 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); |
6743 | 57951c27 | aurel32 | } |
6744 | 57951c27 | aurel32 | GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw); |
6745 | 57951c27 | aurel32 | static always_inline void gen_evmergehi (DisasContext *ctx) |
6746 | 57951c27 | aurel32 | { |
6747 | 57951c27 | aurel32 | if (unlikely(!ctx->spe_enabled)) {
|
6748 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); |
6749 | 57951c27 | aurel32 | return;
|
6750 | 57951c27 | aurel32 | } |
6751 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
6752 | a7812ae4 | pbrook | TCGv t0 = tcg_temp_new(); |
6753 | a7812ae4 | pbrook | TCGv t1 = tcg_temp_new(); |
6754 | 57951c27 | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
|
6755 | 57951c27 | aurel32 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
|
6756 | 57951c27 | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); |
6757 | 57951c27 | aurel32 | tcg_temp_free(t0); |
6758 | 57951c27 | aurel32 | tcg_temp_free(t1); |
6759 | 57951c27 | aurel32 | #else
|
6760 | 57951c27 | aurel32 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); |
6761 | 57951c27 | aurel32 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); |
6762 | 57951c27 | aurel32 | #endif
|
6763 | 57951c27 | aurel32 | } |
6764 | 57951c27 | aurel32 | GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32); |
6765 | a7812ae4 | pbrook | static always_inline void gen_op_evsubf (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
6766 | 0487d6a8 | j_mayer | { |
6767 | 57951c27 | aurel32 | tcg_gen_sub_i32(ret, arg2, arg1); |
6768 | 57951c27 | aurel32 | } |
6769 | 57951c27 | aurel32 | GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf); |
6770 | 0487d6a8 | j_mayer | |
6771 | 57951c27 | aurel32 | /* SPE arithmetic immediate */
|
6772 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
6773 | 57951c27 | aurel32 | #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
|
6774 | 57951c27 | aurel32 | static always_inline void gen_##name (DisasContext *ctx) \ |
6775 | 57951c27 | aurel32 | { \ |
6776 | 57951c27 | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
6777 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
6778 | 57951c27 | aurel32 | return; \
|
6779 | 57951c27 | aurel32 | } \ |
6780 | a7812ae4 | pbrook | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
6781 | a7812ae4 | pbrook | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ |
6782 | a7812ae4 | pbrook | TCGv_i64 t2 = tcg_temp_local_new_i64(); \ |
6783 | 57951c27 | aurel32 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \ |
6784 | 57951c27 | aurel32 | tcg_op(t0, t0, rA(ctx->opcode)); \ |
6785 | 57951c27 | aurel32 | tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
|
6786 | 57951c27 | aurel32 | tcg_gen_trunc_i64_i32(t1, t2); \ |
6787 | e06fcd75 | aurel32 | tcg_temp_free_i64(t2); \ |
6788 | 57951c27 | aurel32 | tcg_op(t1, t1, rA(ctx->opcode)); \ |
6789 | 57951c27 | aurel32 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \ |
6790 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); \ |
6791 | a7812ae4 | pbrook | tcg_temp_free_i32(t1); \ |
6792 | 57951c27 | aurel32 | } |
6793 | 57951c27 | aurel32 | #else
|
6794 | 57951c27 | aurel32 | #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
|
6795 | 57951c27 | aurel32 | static always_inline void gen_##name (DisasContext *ctx) \ |
6796 | 57951c27 | aurel32 | { \ |
6797 | 57951c27 | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
6798 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
6799 | 57951c27 | aurel32 | return; \
|
6800 | 57951c27 | aurel32 | } \ |
6801 | 57951c27 | aurel32 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ |
6802 | 57951c27 | aurel32 | rA(ctx->opcode)); \ |
6803 | 57951c27 | aurel32 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \ |
6804 | 57951c27 | aurel32 | rA(ctx->opcode)); \ |
6805 | 57951c27 | aurel32 | } |
6806 | 57951c27 | aurel32 | #endif
|
6807 | 57951c27 | aurel32 | GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32); |
6808 | 57951c27 | aurel32 | GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32); |
6809 | 57951c27 | aurel32 | |
6810 | 57951c27 | aurel32 | /* SPE comparison */
|
6811 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
6812 | 57951c27 | aurel32 | #define GEN_SPEOP_COMP(name, tcg_cond) \
|
6813 | 57951c27 | aurel32 | static always_inline void gen_##name (DisasContext *ctx) \ |
6814 | 57951c27 | aurel32 | { \ |
6815 | 57951c27 | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
6816 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
6817 | 57951c27 | aurel32 | return; \
|
6818 | 57951c27 | aurel32 | } \ |
6819 | 57951c27 | aurel32 | int l1 = gen_new_label(); \
|
6820 | 57951c27 | aurel32 | int l2 = gen_new_label(); \
|
6821 | 57951c27 | aurel32 | int l3 = gen_new_label(); \
|
6822 | 57951c27 | aurel32 | int l4 = gen_new_label(); \
|
6823 | a7812ae4 | pbrook | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
6824 | a7812ae4 | pbrook | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ |
6825 | a7812ae4 | pbrook | TCGv_i64 t2 = tcg_temp_local_new_i64(); \ |
6826 | 57951c27 | aurel32 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
6827 | 57951c27 | aurel32 | tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ |
6828 | 57951c27 | aurel32 | tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \ |
6829 | a7812ae4 | pbrook | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
|
6830 | 57951c27 | aurel32 | tcg_gen_br(l2); \ |
6831 | 57951c27 | aurel32 | gen_set_label(l1); \ |
6832 | 57951c27 | aurel32 | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \ |
6833 | 57951c27 | aurel32 | CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \ |
6834 | 57951c27 | aurel32 | gen_set_label(l2); \ |
6835 | 57951c27 | aurel32 | tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
|
6836 | 57951c27 | aurel32 | tcg_gen_trunc_i64_i32(t0, t2); \ |
6837 | 57951c27 | aurel32 | tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
|
6838 | 57951c27 | aurel32 | tcg_gen_trunc_i64_i32(t1, t2); \ |
6839 | a7812ae4 | pbrook | tcg_temp_free_i64(t2); \ |
6840 | 57951c27 | aurel32 | tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \ |
6841 | 57951c27 | aurel32 | tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ |
6842 | 57951c27 | aurel32 | ~(CRF_CH | CRF_CH_AND_CL)); \ |
6843 | 57951c27 | aurel32 | tcg_gen_br(l4); \ |
6844 | 57951c27 | aurel32 | gen_set_label(l3); \ |
6845 | 57951c27 | aurel32 | tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ |
6846 | 57951c27 | aurel32 | CRF_CH | CRF_CH_OR_CL); \ |
6847 | 57951c27 | aurel32 | gen_set_label(l4); \ |
6848 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); \ |
6849 | a7812ae4 | pbrook | tcg_temp_free_i32(t1); \ |
6850 | 57951c27 | aurel32 | } |
6851 | 57951c27 | aurel32 | #else
|
6852 | 57951c27 | aurel32 | #define GEN_SPEOP_COMP(name, tcg_cond) \
|
6853 | 57951c27 | aurel32 | static always_inline void gen_##name (DisasContext *ctx) \ |
6854 | 57951c27 | aurel32 | { \ |
6855 | 57951c27 | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
6856 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
6857 | 57951c27 | aurel32 | return; \
|
6858 | 57951c27 | aurel32 | } \ |
6859 | 57951c27 | aurel32 | int l1 = gen_new_label(); \
|
6860 | 57951c27 | aurel32 | int l2 = gen_new_label(); \
|
6861 | 57951c27 | aurel32 | int l3 = gen_new_label(); \
|
6862 | 57951c27 | aurel32 | int l4 = gen_new_label(); \
|
6863 | 57951c27 | aurel32 | \ |
6864 | 57951c27 | aurel32 | tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \ |
6865 | 57951c27 | aurel32 | cpu_gpr[rB(ctx->opcode)], l1); \ |
6866 | 57951c27 | aurel32 | tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
|
6867 | 57951c27 | aurel32 | tcg_gen_br(l2); \ |
6868 | 57951c27 | aurel32 | gen_set_label(l1); \ |
6869 | 57951c27 | aurel32 | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \ |
6870 | 57951c27 | aurel32 | CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \ |
6871 | 57951c27 | aurel32 | gen_set_label(l2); \ |
6872 | 57951c27 | aurel32 | tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \ |
6873 | 57951c27 | aurel32 | cpu_gprh[rB(ctx->opcode)], l3); \ |
6874 | 57951c27 | aurel32 | tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ |
6875 | 57951c27 | aurel32 | ~(CRF_CH | CRF_CH_AND_CL)); \ |
6876 | 57951c27 | aurel32 | tcg_gen_br(l4); \ |
6877 | 57951c27 | aurel32 | gen_set_label(l3); \ |
6878 | 57951c27 | aurel32 | tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ |
6879 | 57951c27 | aurel32 | CRF_CH | CRF_CH_OR_CL); \ |
6880 | 57951c27 | aurel32 | gen_set_label(l4); \ |
6881 | 57951c27 | aurel32 | } |
6882 | 57951c27 | aurel32 | #endif
|
6883 | 57951c27 | aurel32 | GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU); |
6884 | 57951c27 | aurel32 | GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT); |
6885 | 57951c27 | aurel32 | GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU); |
6886 | 57951c27 | aurel32 | GEN_SPEOP_COMP(evcmplts, TCG_COND_LT); |
6887 | 57951c27 | aurel32 | GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ); |
6888 | 57951c27 | aurel32 | |
6889 | 57951c27 | aurel32 | /* SPE misc */
|
6890 | 57951c27 | aurel32 | static always_inline void gen_brinc (DisasContext *ctx) |
6891 | 57951c27 | aurel32 | { |
6892 | 57951c27 | aurel32 | /* Note: brinc is usable even if SPE is disabled */
|
6893 | a7812ae4 | pbrook | gen_helper_brinc(cpu_gpr[rD(ctx->opcode)], |
6894 | a7812ae4 | pbrook | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
6895 | 0487d6a8 | j_mayer | } |
6896 | 57951c27 | aurel32 | static always_inline void gen_evmergelo (DisasContext *ctx) |
6897 | 57951c27 | aurel32 | { |
6898 | 57951c27 | aurel32 | if (unlikely(!ctx->spe_enabled)) {
|
6899 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); |
6900 | 57951c27 | aurel32 | return;
|
6901 | 57951c27 | aurel32 | } |
6902 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
6903 | a7812ae4 | pbrook | TCGv t0 = tcg_temp_new(); |
6904 | a7812ae4 | pbrook | TCGv t1 = tcg_temp_new(); |
6905 | 57951c27 | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
|
6906 | 57951c27 | aurel32 | tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
|
6907 | 57951c27 | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); |
6908 | 57951c27 | aurel32 | tcg_temp_free(t0); |
6909 | 57951c27 | aurel32 | tcg_temp_free(t1); |
6910 | 57951c27 | aurel32 | #else
|
6911 | 57951c27 | aurel32 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
6912 | 57951c27 | aurel32 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
6913 | 57951c27 | aurel32 | #endif
|
6914 | 57951c27 | aurel32 | } |
6915 | 57951c27 | aurel32 | static always_inline void gen_evmergehilo (DisasContext *ctx) |
6916 | 57951c27 | aurel32 | { |
6917 | 57951c27 | aurel32 | if (unlikely(!ctx->spe_enabled)) {
|
6918 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); |
6919 | 57951c27 | aurel32 | return;
|
6920 | 57951c27 | aurel32 | } |
6921 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
6922 | a7812ae4 | pbrook | TCGv t0 = tcg_temp_new(); |
6923 | a7812ae4 | pbrook | TCGv t1 = tcg_temp_new(); |
6924 | 57951c27 | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
|
6925 | 57951c27 | aurel32 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
|
6926 | 57951c27 | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); |
6927 | 57951c27 | aurel32 | tcg_temp_free(t0); |
6928 | 57951c27 | aurel32 | tcg_temp_free(t1); |
6929 | 57951c27 | aurel32 | #else
|
6930 | 57951c27 | aurel32 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
6931 | 57951c27 | aurel32 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); |
6932 | 57951c27 | aurel32 | #endif
|
6933 | 57951c27 | aurel32 | } |
6934 | 57951c27 | aurel32 | static always_inline void gen_evmergelohi (DisasContext *ctx) |
6935 | 57951c27 | aurel32 | { |
6936 | 57951c27 | aurel32 | if (unlikely(!ctx->spe_enabled)) {
|
6937 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); |
6938 | 57951c27 | aurel32 | return;
|
6939 | 57951c27 | aurel32 | } |
6940 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
6941 | a7812ae4 | pbrook | TCGv t0 = tcg_temp_new(); |
6942 | a7812ae4 | pbrook | TCGv t1 = tcg_temp_new(); |
6943 | 57951c27 | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
|
6944 | 57951c27 | aurel32 | tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
|
6945 | 57951c27 | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); |
6946 | 57951c27 | aurel32 | tcg_temp_free(t0); |
6947 | 57951c27 | aurel32 | tcg_temp_free(t1); |
6948 | 57951c27 | aurel32 | #else
|
6949 | 57951c27 | aurel32 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); |
6950 | 57951c27 | aurel32 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
6951 | 57951c27 | aurel32 | #endif
|
6952 | 57951c27 | aurel32 | } |
6953 | 57951c27 | aurel32 | static always_inline void gen_evsplati (DisasContext *ctx) |
6954 | 57951c27 | aurel32 | { |
6955 | 38d14952 | aurel32 | uint64_t imm = ((int32_t)(rA(ctx->opcode) << 11)) >> 27; |
6956 | 0487d6a8 | j_mayer | |
6957 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
6958 | 38d14952 | aurel32 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
|
6959 | 57951c27 | aurel32 | #else
|
6960 | 57951c27 | aurel32 | tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm); |
6961 | 57951c27 | aurel32 | tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm); |
6962 | 57951c27 | aurel32 | #endif
|
6963 | 57951c27 | aurel32 | } |
6964 | b068d6a7 | j_mayer | static always_inline void gen_evsplatfi (DisasContext *ctx) |
6965 | 0487d6a8 | j_mayer | { |
6966 | 38d14952 | aurel32 | uint64_t imm = rA(ctx->opcode) << 11;
|
6967 | 0487d6a8 | j_mayer | |
6968 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
6969 | 38d14952 | aurel32 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
|
6970 | 57951c27 | aurel32 | #else
|
6971 | 57951c27 | aurel32 | tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm); |
6972 | 57951c27 | aurel32 | tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm); |
6973 | 57951c27 | aurel32 | #endif
|
6974 | 0487d6a8 | j_mayer | } |
6975 | 0487d6a8 | j_mayer | |
6976 | 57951c27 | aurel32 | static always_inline void gen_evsel (DisasContext *ctx) |
6977 | 57951c27 | aurel32 | { |
6978 | 57951c27 | aurel32 | int l1 = gen_new_label();
|
6979 | 57951c27 | aurel32 | int l2 = gen_new_label();
|
6980 | 57951c27 | aurel32 | int l3 = gen_new_label();
|
6981 | 57951c27 | aurel32 | int l4 = gen_new_label();
|
6982 | a7812ae4 | pbrook | TCGv_i32 t0 = tcg_temp_local_new_i32(); |
6983 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
6984 | a7812ae4 | pbrook | TCGv t1 = tcg_temp_local_new(); |
6985 | a7812ae4 | pbrook | TCGv t2 = tcg_temp_local_new(); |
6986 | 57951c27 | aurel32 | #endif
|
6987 | 57951c27 | aurel32 | tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3); |
6988 | 57951c27 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
|
6989 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
6990 | 57951c27 | aurel32 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
|
6991 | 57951c27 | aurel32 | #else
|
6992 | 57951c27 | aurel32 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); |
6993 | 57951c27 | aurel32 | #endif
|
6994 | 57951c27 | aurel32 | tcg_gen_br(l2); |
6995 | 57951c27 | aurel32 | gen_set_label(l1); |
6996 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
6997 | 57951c27 | aurel32 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
|
6998 | 57951c27 | aurel32 | #else
|
6999 | 57951c27 | aurel32 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); |
7000 | 57951c27 | aurel32 | #endif
|
7001 | 57951c27 | aurel32 | gen_set_label(l2); |
7002 | 57951c27 | aurel32 | tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2); |
7003 | 57951c27 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
|
7004 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
7005 | 57951c27 | aurel32 | tcg_gen_andi_tl(t2, cpu_gpr[rA(ctx->opcode)], 0x00000000FFFFFFFFULL);
|
7006 | 57951c27 | aurel32 | #else
|
7007 | 57951c27 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
7008 | 57951c27 | aurel32 | #endif
|
7009 | 57951c27 | aurel32 | tcg_gen_br(l4); |
7010 | 57951c27 | aurel32 | gen_set_label(l3); |
7011 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
7012 | 57951c27 | aurel32 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFULL);
|
7013 | 57951c27 | aurel32 | #else
|
7014 | 57951c27 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
7015 | 57951c27 | aurel32 | #endif
|
7016 | 57951c27 | aurel32 | gen_set_label(l4); |
7017 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); |
7018 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
7019 | 57951c27 | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2); |
7020 | 57951c27 | aurel32 | tcg_temp_free(t1); |
7021 | 57951c27 | aurel32 | tcg_temp_free(t2); |
7022 | 57951c27 | aurel32 | #endif
|
7023 | 57951c27 | aurel32 | } |
7024 | e8eaa2c0 | Blue Swirl | |
7025 | e8eaa2c0 | Blue Swirl | static void gen_evsel0(DisasContext *ctx) |
7026 | 57951c27 | aurel32 | { |
7027 | 57951c27 | aurel32 | gen_evsel(ctx); |
7028 | 57951c27 | aurel32 | } |
7029 | e8eaa2c0 | Blue Swirl | |
7030 | e8eaa2c0 | Blue Swirl | static void gen_evsel1(DisasContext *ctx) |
7031 | 57951c27 | aurel32 | { |
7032 | 57951c27 | aurel32 | gen_evsel(ctx); |
7033 | 57951c27 | aurel32 | } |
7034 | e8eaa2c0 | Blue Swirl | |
7035 | e8eaa2c0 | Blue Swirl | static void gen_evsel2(DisasContext *ctx) |
7036 | 57951c27 | aurel32 | { |
7037 | 57951c27 | aurel32 | gen_evsel(ctx); |
7038 | 57951c27 | aurel32 | } |
7039 | e8eaa2c0 | Blue Swirl | |
7040 | e8eaa2c0 | Blue Swirl | static void gen_evsel3(DisasContext *ctx) |
7041 | 57951c27 | aurel32 | { |
7042 | 57951c27 | aurel32 | gen_evsel(ctx); |
7043 | 57951c27 | aurel32 | } |
7044 | 0487d6a8 | j_mayer | |
7045 | 0487d6a8 | j_mayer | GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); //// |
7046 | 0487d6a8 | j_mayer | GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE); |
7047 | 0487d6a8 | j_mayer | GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); //// |
7048 | 0487d6a8 | j_mayer | GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE); |
7049 | 0487d6a8 | j_mayer | GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); //// |
7050 | 0487d6a8 | j_mayer | GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); //// |
7051 | 0487d6a8 | j_mayer | GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); //// |
7052 | 0487d6a8 | j_mayer | GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); // |
7053 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); //// |
7054 | 0487d6a8 | j_mayer | GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); //// |
7055 | 0487d6a8 | j_mayer | GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); //// |
7056 | 0487d6a8 | j_mayer | GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); //// |
7057 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); //// |
7058 | 0487d6a8 | j_mayer | GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); //// |
7059 | 0487d6a8 | j_mayer | GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); //// |
7060 | 0487d6a8 | j_mayer | GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE); |
7061 | 0487d6a8 | j_mayer | GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); //// |
7062 | 0487d6a8 | j_mayer | GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE); |
7063 | 0487d6a8 | j_mayer | GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); // |
7064 | 0487d6a8 | j_mayer | GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE); |
7065 | 0487d6a8 | j_mayer | GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); //// |
7066 | 0487d6a8 | j_mayer | GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); //// |
7067 | 0487d6a8 | j_mayer | GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); //// |
7068 | 0487d6a8 | j_mayer | GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); //// |
7069 | 0487d6a8 | j_mayer | GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); //// |
7070 | 0487d6a8 | j_mayer | |
7071 | 6a6ae23f | aurel32 | /* SPE load and stores */
|
7072 | 76db3ba4 | aurel32 | static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, TCGv EA, int sh) |
7073 | 6a6ae23f | aurel32 | { |
7074 | 6a6ae23f | aurel32 | target_ulong uimm = rB(ctx->opcode); |
7075 | 6a6ae23f | aurel32 | |
7076 | 76db3ba4 | aurel32 | if (rA(ctx->opcode) == 0) { |
7077 | 6a6ae23f | aurel32 | tcg_gen_movi_tl(EA, uimm << sh); |
7078 | 76db3ba4 | aurel32 | } else {
|
7079 | 6a6ae23f | aurel32 | tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh); |
7080 | 76db3ba4 | aurel32 | #if defined(TARGET_PPC64)
|
7081 | 76db3ba4 | aurel32 | if (!ctx->sf_mode) {
|
7082 | 76db3ba4 | aurel32 | tcg_gen_ext32u_tl(EA, EA); |
7083 | 76db3ba4 | aurel32 | } |
7084 | 76db3ba4 | aurel32 | #endif
|
7085 | 76db3ba4 | aurel32 | } |
7086 | 0487d6a8 | j_mayer | } |
7087 | 6a6ae23f | aurel32 | |
7088 | 6a6ae23f | aurel32 | static always_inline void gen_op_evldd(DisasContext *ctx, TCGv addr) |
7089 | 6a6ae23f | aurel32 | { |
7090 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
7091 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr); |
7092 | 6a6ae23f | aurel32 | #else
|
7093 | 6a6ae23f | aurel32 | TCGv_i64 t0 = tcg_temp_new_i64(); |
7094 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, t0, addr); |
7095 | 6a6ae23f | aurel32 | tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0); |
7096 | 6a6ae23f | aurel32 | tcg_gen_shri_i64(t0, t0, 32);
|
7097 | 6a6ae23f | aurel32 | tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0); |
7098 | 6a6ae23f | aurel32 | tcg_temp_free_i64(t0); |
7099 | 6a6ae23f | aurel32 | #endif
|
7100 | 0487d6a8 | j_mayer | } |
7101 | 6a6ae23f | aurel32 | |
7102 | 6a6ae23f | aurel32 | static always_inline void gen_op_evldw(DisasContext *ctx, TCGv addr) |
7103 | 6a6ae23f | aurel32 | { |
7104 | 0487d6a8 | j_mayer | #if defined(TARGET_PPC64)
|
7105 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
7106 | 76db3ba4 | aurel32 | gen_qemu_ld32u(ctx, t0, addr); |
7107 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
|
7108 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 4);
|
7109 | 76db3ba4 | aurel32 | gen_qemu_ld32u(ctx, t0, addr); |
7110 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7111 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
7112 | 6a6ae23f | aurel32 | #else
|
7113 | 76db3ba4 | aurel32 | gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr); |
7114 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 4);
|
7115 | 76db3ba4 | aurel32 | gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr); |
7116 | 6a6ae23f | aurel32 | #endif
|
7117 | 0487d6a8 | j_mayer | } |
7118 | 6a6ae23f | aurel32 | |
7119 | 6a6ae23f | aurel32 | static always_inline void gen_op_evldh(DisasContext *ctx, TCGv addr) |
7120 | 6a6ae23f | aurel32 | { |
7121 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
7122 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
7123 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
7124 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
|
7125 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
7126 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
7127 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(t0, t0, 32);
|
7128 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7129 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
7130 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
7131 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(t0, t0, 16);
|
7132 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7133 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
7134 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
7135 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7136 | 0487d6a8 | j_mayer | #else
|
7137 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
7138 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
|
7139 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
7140 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
7141 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); |
7142 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
7143 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
7144 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
|
7145 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
7146 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
7147 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7148 | 0487d6a8 | j_mayer | #endif
|
7149 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
7150 | 0487d6a8 | j_mayer | } |
7151 | 0487d6a8 | j_mayer | |
7152 | 6a6ae23f | aurel32 | static always_inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr) |
7153 | 6a6ae23f | aurel32 | { |
7154 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
7155 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
7156 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
7157 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
|
7158 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(t0, t0, 16);
|
7159 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7160 | 6a6ae23f | aurel32 | #else
|
7161 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(t0, t0, 16);
|
7162 | 6a6ae23f | aurel32 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); |
7163 | 6a6ae23f | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); |
7164 | 6a6ae23f | aurel32 | #endif
|
7165 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
7166 | 0487d6a8 | j_mayer | } |
7167 | 0487d6a8 | j_mayer | |
7168 | 6a6ae23f | aurel32 | static always_inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr) |
7169 | 6a6ae23f | aurel32 | { |
7170 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
7171 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
7172 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
7173 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
|
7174 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7175 | 6a6ae23f | aurel32 | #else
|
7176 | 6a6ae23f | aurel32 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); |
7177 | 6a6ae23f | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); |
7178 | 6a6ae23f | aurel32 | #endif
|
7179 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
7180 | 0487d6a8 | j_mayer | } |
7181 | 0487d6a8 | j_mayer | |
7182 | 6a6ae23f | aurel32 | static always_inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr) |
7183 | 6a6ae23f | aurel32 | { |
7184 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
7185 | 76db3ba4 | aurel32 | gen_qemu_ld16s(ctx, t0, addr); |
7186 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
7187 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
|
7188 | 6a6ae23f | aurel32 | tcg_gen_ext32u_tl(t0, t0); |
7189 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7190 | 6a6ae23f | aurel32 | #else
|
7191 | 6a6ae23f | aurel32 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); |
7192 | 6a6ae23f | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); |
7193 | 6a6ae23f | aurel32 | #endif
|
7194 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
7195 | 6a6ae23f | aurel32 | } |
7196 | 6a6ae23f | aurel32 | |
7197 | 6a6ae23f | aurel32 | static always_inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr) |
7198 | 6a6ae23f | aurel32 | { |
7199 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
7200 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
7201 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
7202 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
|
7203 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
7204 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
7205 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(t0, t0, 16);
|
7206 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7207 | 6a6ae23f | aurel32 | #else
|
7208 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
7209 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
|
7210 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
7211 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
7212 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
|
7213 | 6a6ae23f | aurel32 | #endif
|
7214 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
7215 | 6a6ae23f | aurel32 | } |
7216 | 6a6ae23f | aurel32 | |
7217 | 6a6ae23f | aurel32 | static always_inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr) |
7218 | 6a6ae23f | aurel32 | { |
7219 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
7220 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
7221 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr); |
7222 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
7223 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
7224 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(t0, t0, 32);
|
7225 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7226 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
7227 | 6a6ae23f | aurel32 | #else
|
7228 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr); |
7229 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
7230 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr); |
7231 | 6a6ae23f | aurel32 | #endif
|
7232 | 6a6ae23f | aurel32 | } |
7233 | 6a6ae23f | aurel32 | |
7234 | 6a6ae23f | aurel32 | static always_inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr) |
7235 | 6a6ae23f | aurel32 | { |
7236 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
7237 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
7238 | 76db3ba4 | aurel32 | gen_qemu_ld16s(ctx, t0, addr); |
7239 | 6a6ae23f | aurel32 | tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0); |
7240 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
7241 | 76db3ba4 | aurel32 | gen_qemu_ld16s(ctx, t0, addr); |
7242 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(t0, t0, 32);
|
7243 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7244 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
7245 | 6a6ae23f | aurel32 | #else
|
7246 | 76db3ba4 | aurel32 | gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr); |
7247 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
7248 | 76db3ba4 | aurel32 | gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr); |
7249 | 6a6ae23f | aurel32 | #endif
|
7250 | 6a6ae23f | aurel32 | } |
7251 | 6a6ae23f | aurel32 | |
7252 | 6a6ae23f | aurel32 | static always_inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr) |
7253 | 6a6ae23f | aurel32 | { |
7254 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
7255 | 76db3ba4 | aurel32 | gen_qemu_ld32u(ctx, t0, addr); |
7256 | 0487d6a8 | j_mayer | #if defined(TARGET_PPC64)
|
7257 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
|
7258 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7259 | 6a6ae23f | aurel32 | #else
|
7260 | 6a6ae23f | aurel32 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); |
7261 | 6a6ae23f | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); |
7262 | 6a6ae23f | aurel32 | #endif
|
7263 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
7264 | 6a6ae23f | aurel32 | } |
7265 | 6a6ae23f | aurel32 | |
7266 | 6a6ae23f | aurel32 | static always_inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr) |
7267 | 6a6ae23f | aurel32 | { |
7268 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
7269 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
7270 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
7271 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
|
7272 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(t0, t0, 32);
|
7273 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7274 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
7275 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
7276 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7277 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(t0, t0, 16);
|
7278 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7279 | 6a6ae23f | aurel32 | #else
|
7280 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
7281 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
|
7282 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); |
7283 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
7284 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
7285 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
|
7286 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); |
7287 | 0487d6a8 | j_mayer | #endif
|
7288 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
7289 | 6a6ae23f | aurel32 | } |
7290 | 6a6ae23f | aurel32 | |
7291 | 6a6ae23f | aurel32 | static always_inline void gen_op_evstdd(DisasContext *ctx, TCGv addr) |
7292 | 6a6ae23f | aurel32 | { |
7293 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
7294 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr); |
7295 | 0487d6a8 | j_mayer | #else
|
7296 | 6a6ae23f | aurel32 | TCGv_i64 t0 = tcg_temp_new_i64(); |
7297 | 6a6ae23f | aurel32 | tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]); |
7298 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, t0, addr); |
7299 | 6a6ae23f | aurel32 | tcg_temp_free_i64(t0); |
7300 | 6a6ae23f | aurel32 | #endif
|
7301 | 6a6ae23f | aurel32 | } |
7302 | 6a6ae23f | aurel32 | |
7303 | 6a6ae23f | aurel32 | static always_inline void gen_op_evstdw(DisasContext *ctx, TCGv addr) |
7304 | 6a6ae23f | aurel32 | { |
7305 | 0487d6a8 | j_mayer | #if defined(TARGET_PPC64)
|
7306 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
7307 | 6a6ae23f | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
|
7308 | 76db3ba4 | aurel32 | gen_qemu_st32(ctx, t0, addr); |
7309 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
7310 | 6a6ae23f | aurel32 | #else
|
7311 | 76db3ba4 | aurel32 | gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
7312 | 6a6ae23f | aurel32 | #endif
|
7313 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 4);
|
7314 | 76db3ba4 | aurel32 | gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr); |
7315 | 6a6ae23f | aurel32 | } |
7316 | 6a6ae23f | aurel32 | |
7317 | 6a6ae23f | aurel32 | static always_inline void gen_op_evstdh(DisasContext *ctx, TCGv addr) |
7318 | 6a6ae23f | aurel32 | { |
7319 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
7320 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
7321 | 6a6ae23f | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
|
7322 | 6a6ae23f | aurel32 | #else
|
7323 | 6a6ae23f | aurel32 | tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
|
7324 | 6a6ae23f | aurel32 | #endif
|
7325 | 76db3ba4 | aurel32 | gen_qemu_st16(ctx, t0, addr); |
7326 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
7327 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
7328 | 6a6ae23f | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
|
7329 | 76db3ba4 | aurel32 | gen_qemu_st16(ctx, t0, addr); |
7330 | 6a6ae23f | aurel32 | #else
|
7331 | 76db3ba4 | aurel32 | gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
7332 | 6a6ae23f | aurel32 | #endif
|
7333 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
7334 | 6a6ae23f | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
|
7335 | 76db3ba4 | aurel32 | gen_qemu_st16(ctx, t0, addr); |
7336 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
7337 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
7338 | 76db3ba4 | aurel32 | gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr); |
7339 | 6a6ae23f | aurel32 | } |
7340 | 6a6ae23f | aurel32 | |
7341 | 6a6ae23f | aurel32 | static always_inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr) |
7342 | 6a6ae23f | aurel32 | { |
7343 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
7344 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
7345 | 6a6ae23f | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
|
7346 | 6a6ae23f | aurel32 | #else
|
7347 | 6a6ae23f | aurel32 | tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
|
7348 | 6a6ae23f | aurel32 | #endif
|
7349 | 76db3ba4 | aurel32 | gen_qemu_st16(ctx, t0, addr); |
7350 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
7351 | 6a6ae23f | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
|
7352 | 76db3ba4 | aurel32 | gen_qemu_st16(ctx, t0, addr); |
7353 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
7354 | 6a6ae23f | aurel32 | } |
7355 | 6a6ae23f | aurel32 | |
7356 | 6a6ae23f | aurel32 | static always_inline void gen_op_evstwho(DisasContext *ctx, TCGv addr) |
7357 | 6a6ae23f | aurel32 | { |
7358 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
7359 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
7360 | 6a6ae23f | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
|
7361 | 76db3ba4 | aurel32 | gen_qemu_st16(ctx, t0, addr); |
7362 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
7363 | 6a6ae23f | aurel32 | #else
|
7364 | 76db3ba4 | aurel32 | gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
7365 | 6a6ae23f | aurel32 | #endif
|
7366 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
7367 | 76db3ba4 | aurel32 | gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr); |
7368 | 6a6ae23f | aurel32 | } |
7369 | 6a6ae23f | aurel32 | |
7370 | 6a6ae23f | aurel32 | static always_inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr) |
7371 | 6a6ae23f | aurel32 | { |
7372 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
7373 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
7374 | 6a6ae23f | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
|
7375 | 76db3ba4 | aurel32 | gen_qemu_st32(ctx, t0, addr); |
7376 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
7377 | 6a6ae23f | aurel32 | #else
|
7378 | 76db3ba4 | aurel32 | gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
7379 | 6a6ae23f | aurel32 | #endif
|
7380 | 6a6ae23f | aurel32 | } |
7381 | 6a6ae23f | aurel32 | |
7382 | 6a6ae23f | aurel32 | static always_inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr) |
7383 | 6a6ae23f | aurel32 | { |
7384 | 76db3ba4 | aurel32 | gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr); |
7385 | 6a6ae23f | aurel32 | } |
7386 | 6a6ae23f | aurel32 | |
7387 | 6a6ae23f | aurel32 | #define GEN_SPEOP_LDST(name, opc2, sh) \
|
7388 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
7389 | 6a6ae23f | aurel32 | { \ |
7390 | 6a6ae23f | aurel32 | TCGv t0; \ |
7391 | 6a6ae23f | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
7392 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
7393 | 6a6ae23f | aurel32 | return; \
|
7394 | 6a6ae23f | aurel32 | } \ |
7395 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); \ |
7396 | 6a6ae23f | aurel32 | t0 = tcg_temp_new(); \ |
7397 | 6a6ae23f | aurel32 | if (Rc(ctx->opcode)) { \
|
7398 | 76db3ba4 | aurel32 | gen_addr_spe_imm_index(ctx, t0, sh); \ |
7399 | 6a6ae23f | aurel32 | } else { \
|
7400 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); \ |
7401 | 6a6ae23f | aurel32 | } \ |
7402 | 6a6ae23f | aurel32 | gen_op_##name(ctx, t0); \ |
7403 | 6a6ae23f | aurel32 | tcg_temp_free(t0); \ |
7404 | 6a6ae23f | aurel32 | } |
7405 | 6a6ae23f | aurel32 | |
7406 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evldd, 0x00, 3); |
7407 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evldw, 0x01, 3); |
7408 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evldh, 0x02, 3); |
7409 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evlhhesplat, 0x04, 1); |
7410 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evlhhousplat, 0x06, 1); |
7411 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evlhhossplat, 0x07, 1); |
7412 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evlwhe, 0x08, 2); |
7413 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evlwhou, 0x0A, 2); |
7414 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evlwhos, 0x0B, 2); |
7415 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2); |
7416 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2); |
7417 | 6a6ae23f | aurel32 | |
7418 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evstdd, 0x10, 3); |
7419 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evstdw, 0x11, 3); |
7420 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evstdh, 0x12, 3); |
7421 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evstwhe, 0x18, 2); |
7422 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evstwho, 0x1A, 2); |
7423 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evstwwe, 0x1C, 2); |
7424 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evstwwo, 0x1E, 2); |
7425 | 0487d6a8 | j_mayer | |
7426 | 0487d6a8 | j_mayer | /* Multiply and add - TODO */
|
7427 | 0487d6a8 | j_mayer | #if 0
|
7428 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE);
|
7429 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE);
|
7430 | 0487d6a8 | j_mayer | GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE);
|
7431 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE);
|
7432 | 0487d6a8 | j_mayer | GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE);
|
7433 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE);
|
7434 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE);
|
7435 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE);
|
7436 | 0487d6a8 | j_mayer | GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE);
|
7437 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE);
|
7438 | 0487d6a8 | j_mayer | GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE);
|
7439 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE);
|
7440 | 0487d6a8 | j_mayer | |
7441 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE);
|
7442 | 0487d6a8 | j_mayer | GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE);
|
7443 | 0487d6a8 | j_mayer | GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE);
|
7444 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE);
|
7445 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE);
|
7446 | 0487d6a8 | j_mayer | GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE);
|
7447 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE);
|
7448 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE);
|
7449 | 0487d6a8 | j_mayer | GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE);
|
7450 | 0487d6a8 | j_mayer | GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE);
|
7451 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE);
|
7452 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE);
|
7453 | 0487d6a8 | j_mayer | GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE);
|
7454 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE);
|
7455 | 0487d6a8 | j_mayer | |
7456 | 0487d6a8 | j_mayer | GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE);
|
7457 | 0487d6a8 | j_mayer | GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE);
|
7458 | 0487d6a8 | j_mayer | GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE);
|
7459 | 0487d6a8 | j_mayer | GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE);
|
7460 | 0487d6a8 | j_mayer | GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE);
|
7461 | 0487d6a8 | j_mayer | GEN_SPE(evmra, speundef, 0x07, 0x13, 0x0000F800, PPC_SPE);
|
7462 | 0487d6a8 | j_mayer | |
7463 | 0487d6a8 | j_mayer | GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE);
|
7464 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE);
|
7465 | 0487d6a8 | j_mayer | GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE);
|
7466 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE);
|
7467 | 0487d6a8 | j_mayer | GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE);
|
7468 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE);
|
7469 | 0487d6a8 | j_mayer | GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE);
|
7470 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE);
|
7471 | 0487d6a8 | j_mayer | GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE);
|
7472 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE);
|
7473 | 0487d6a8 | j_mayer | GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE);
|
7474 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE);
|
7475 | 0487d6a8 | j_mayer | |
7476 | 0487d6a8 | j_mayer | GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE);
|
7477 | 0487d6a8 | j_mayer | GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE);
|
7478 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE);
|
7479 | 0487d6a8 | j_mayer | GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE);
|
7480 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE);
|
7481 | 0487d6a8 | j_mayer | |
7482 | 0487d6a8 | j_mayer | GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE);
|
7483 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE);
|
7484 | 0487d6a8 | j_mayer | GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE);
|
7485 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE);
|
7486 | 0487d6a8 | j_mayer | GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE);
|
7487 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE);
|
7488 | 0487d6a8 | j_mayer | GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE);
|
7489 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE);
|
7490 | 0487d6a8 | j_mayer | GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE);
|
7491 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE);
|
7492 | 0487d6a8 | j_mayer | GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE);
|
7493 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE);
|
7494 | 0487d6a8 | j_mayer | |
7495 | 0487d6a8 | j_mayer | GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE);
|
7496 | 0487d6a8 | j_mayer | GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE);
|
7497 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE);
|
7498 | 0487d6a8 | j_mayer | GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE);
|
7499 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
|
7500 | 0487d6a8 | j_mayer | #endif
|
7501 | 0487d6a8 | j_mayer | |
7502 | 0487d6a8 | j_mayer | /*** SPE floating-point extension ***/
|
7503 | 1c97856d | aurel32 | #if defined(TARGET_PPC64)
|
7504 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_CONV_32_32(name) \
|
7505 | b068d6a7 | j_mayer | static always_inline void gen_##name (DisasContext *ctx) \ |
7506 | 0487d6a8 | j_mayer | { \ |
7507 | 1c97856d | aurel32 | TCGv_i32 t0; \ |
7508 | 1c97856d | aurel32 | TCGv t1; \ |
7509 | 1c97856d | aurel32 | t0 = tcg_temp_new_i32(); \ |
7510 | 1c97856d | aurel32 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \ |
7511 | 1c97856d | aurel32 | gen_helper_##name(t0, t0); \ |
7512 | 1c97856d | aurel32 | t1 = tcg_temp_new(); \ |
7513 | 1c97856d | aurel32 | tcg_gen_extu_i32_tl(t1, t0); \ |
7514 | 1c97856d | aurel32 | tcg_temp_free_i32(t0); \ |
7515 | 1c97856d | aurel32 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \ |
7516 | 1c97856d | aurel32 | 0xFFFFFFFF00000000ULL); \
|
7517 | 1c97856d | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \ |
7518 | 1c97856d | aurel32 | tcg_temp_free(t1); \ |
7519 | 0487d6a8 | j_mayer | } |
7520 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_CONV_32_64(name) \
|
7521 | 1c97856d | aurel32 | static always_inline void gen_##name (DisasContext *ctx) \ |
7522 | 1c97856d | aurel32 | { \ |
7523 | 1c97856d | aurel32 | TCGv_i32 t0; \ |
7524 | 1c97856d | aurel32 | TCGv t1; \ |
7525 | 1c97856d | aurel32 | t0 = tcg_temp_new_i32(); \ |
7526 | 1c97856d | aurel32 | gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \ |
7527 | 1c97856d | aurel32 | t1 = tcg_temp_new(); \ |
7528 | 1c97856d | aurel32 | tcg_gen_extu_i32_tl(t1, t0); \ |
7529 | 1c97856d | aurel32 | tcg_temp_free_i32(t0); \ |
7530 | 1c97856d | aurel32 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \ |
7531 | 1c97856d | aurel32 | 0xFFFFFFFF00000000ULL); \
|
7532 | 1c97856d | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \ |
7533 | 1c97856d | aurel32 | tcg_temp_free(t1); \ |
7534 | 1c97856d | aurel32 | } |
7535 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_CONV_64_32(name) \
|
7536 | 1c97856d | aurel32 | static always_inline void gen_##name (DisasContext *ctx) \ |
7537 | 1c97856d | aurel32 | { \ |
7538 | 1c97856d | aurel32 | TCGv_i32 t0 = tcg_temp_new_i32(); \ |
7539 | 1c97856d | aurel32 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \ |
7540 | 1c97856d | aurel32 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \ |
7541 | 1c97856d | aurel32 | tcg_temp_free_i32(t0); \ |
7542 | 1c97856d | aurel32 | } |
7543 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_CONV_64_64(name) \
|
7544 | 1c97856d | aurel32 | static always_inline void gen_##name (DisasContext *ctx) \ |
7545 | 1c97856d | aurel32 | { \ |
7546 | 1c97856d | aurel32 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ |
7547 | 1c97856d | aurel32 | } |
7548 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_ARITH2_32_32(name) \
|
7549 | 57951c27 | aurel32 | static always_inline void gen_##name (DisasContext *ctx) \ |
7550 | 57951c27 | aurel32 | { \ |
7551 | 1c97856d | aurel32 | TCGv_i32 t0, t1; \ |
7552 | 1c97856d | aurel32 | TCGv_i64 t2; \ |
7553 | 57951c27 | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
7554 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
7555 | 57951c27 | aurel32 | return; \
|
7556 | 57951c27 | aurel32 | } \ |
7557 | 1c97856d | aurel32 | t0 = tcg_temp_new_i32(); \ |
7558 | 1c97856d | aurel32 | t1 = tcg_temp_new_i32(); \ |
7559 | 1c97856d | aurel32 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
7560 | 1c97856d | aurel32 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ |
7561 | 1c97856d | aurel32 | gen_helper_##name(t0, t0, t1); \ |
7562 | 1c97856d | aurel32 | tcg_temp_free_i32(t1); \ |
7563 | 1c97856d | aurel32 | t2 = tcg_temp_new(); \ |
7564 | 1c97856d | aurel32 | tcg_gen_extu_i32_tl(t2, t0); \ |
7565 | 1c97856d | aurel32 | tcg_temp_free_i32(t0); \ |
7566 | 1c97856d | aurel32 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \ |
7567 | 1c97856d | aurel32 | 0xFFFFFFFF00000000ULL); \
|
7568 | 1c97856d | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \ |
7569 | 1c97856d | aurel32 | tcg_temp_free(t2); \ |
7570 | 57951c27 | aurel32 | } |
7571 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_ARITH2_64_64(name) \
|
7572 | 57951c27 | aurel32 | static always_inline void gen_##name (DisasContext *ctx) \ |
7573 | 57951c27 | aurel32 | { \ |
7574 | 57951c27 | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
7575 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
7576 | 57951c27 | aurel32 | return; \
|
7577 | 57951c27 | aurel32 | } \ |
7578 | 1c97856d | aurel32 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ |
7579 | 1c97856d | aurel32 | cpu_gpr[rB(ctx->opcode)]); \ |
7580 | 57951c27 | aurel32 | } |
7581 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_COMP_32(name) \
|
7582 | 57951c27 | aurel32 | static always_inline void gen_##name (DisasContext *ctx) \ |
7583 | 57951c27 | aurel32 | { \ |
7584 | 1c97856d | aurel32 | TCGv_i32 t0, t1; \ |
7585 | 57951c27 | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
7586 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
7587 | 57951c27 | aurel32 | return; \
|
7588 | 57951c27 | aurel32 | } \ |
7589 | 1c97856d | aurel32 | t0 = tcg_temp_new_i32(); \ |
7590 | 1c97856d | aurel32 | t1 = tcg_temp_new_i32(); \ |
7591 | 1c97856d | aurel32 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
7592 | 1c97856d | aurel32 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ |
7593 | 1c97856d | aurel32 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \ |
7594 | 1c97856d | aurel32 | tcg_temp_free_i32(t0); \ |
7595 | 1c97856d | aurel32 | tcg_temp_free_i32(t1); \ |
7596 | 1c97856d | aurel32 | } |
7597 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_COMP_64(name) \
|
7598 | 1c97856d | aurel32 | static always_inline void gen_##name (DisasContext *ctx) \ |
7599 | 1c97856d | aurel32 | { \ |
7600 | 1c97856d | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
7601 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
7602 | 1c97856d | aurel32 | return; \
|
7603 | 1c97856d | aurel32 | } \ |
7604 | 1c97856d | aurel32 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \ |
7605 | 1c97856d | aurel32 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ |
7606 | 1c97856d | aurel32 | } |
7607 | 1c97856d | aurel32 | #else
|
7608 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_CONV_32_32(name) \
|
7609 | 1c97856d | aurel32 | static always_inline void gen_##name (DisasContext *ctx) \ |
7610 | 1c97856d | aurel32 | { \ |
7611 | 1c97856d | aurel32 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ |
7612 | 57951c27 | aurel32 | } |
7613 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_CONV_32_64(name) \
|
7614 | 1c97856d | aurel32 | static always_inline void gen_##name (DisasContext *ctx) \ |
7615 | 1c97856d | aurel32 | { \ |
7616 | 1c97856d | aurel32 | TCGv_i64 t0 = tcg_temp_new_i64(); \ |
7617 | 1c97856d | aurel32 | gen_load_gpr64(t0, rB(ctx->opcode)); \ |
7618 | 1c97856d | aurel32 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \ |
7619 | 1c97856d | aurel32 | tcg_temp_free_i64(t0); \ |
7620 | 1c97856d | aurel32 | } |
7621 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_CONV_64_32(name) \
|
7622 | 1c97856d | aurel32 | static always_inline void gen_##name (DisasContext *ctx) \ |
7623 | 1c97856d | aurel32 | { \ |
7624 | 1c97856d | aurel32 | TCGv_i64 t0 = tcg_temp_new_i64(); \ |
7625 | 1c97856d | aurel32 | gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \ |
7626 | 1c97856d | aurel32 | gen_store_gpr64(rD(ctx->opcode), t0); \ |
7627 | 1c97856d | aurel32 | tcg_temp_free_i64(t0); \ |
7628 | 1c97856d | aurel32 | } |
7629 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_CONV_64_64(name) \
|
7630 | 1c97856d | aurel32 | static always_inline void gen_##name (DisasContext *ctx) \ |
7631 | 1c97856d | aurel32 | { \ |
7632 | 1c97856d | aurel32 | TCGv_i64 t0 = tcg_temp_new_i64(); \ |
7633 | 1c97856d | aurel32 | gen_load_gpr64(t0, rB(ctx->opcode)); \ |
7634 | 1c97856d | aurel32 | gen_helper_##name(t0, t0); \ |
7635 | 1c97856d | aurel32 | gen_store_gpr64(rD(ctx->opcode), t0); \ |
7636 | 1c97856d | aurel32 | tcg_temp_free_i64(t0); \ |
7637 | 1c97856d | aurel32 | } |
7638 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_ARITH2_32_32(name) \
|
7639 | 1c97856d | aurel32 | static always_inline void gen_##name (DisasContext *ctx) \ |
7640 | 1c97856d | aurel32 | { \ |
7641 | 1c97856d | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
7642 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
7643 | 1c97856d | aurel32 | return; \
|
7644 | 1c97856d | aurel32 | } \ |
7645 | 1c97856d | aurel32 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], \ |
7646 | 1c97856d | aurel32 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ |
7647 | 1c97856d | aurel32 | } |
7648 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_ARITH2_64_64(name) \
|
7649 | 1c97856d | aurel32 | static always_inline void gen_##name (DisasContext *ctx) \ |
7650 | 1c97856d | aurel32 | { \ |
7651 | 1c97856d | aurel32 | TCGv_i64 t0, t1; \ |
7652 | 1c97856d | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
7653 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
7654 | 1c97856d | aurel32 | return; \
|
7655 | 1c97856d | aurel32 | } \ |
7656 | 1c97856d | aurel32 | t0 = tcg_temp_new_i64(); \ |
7657 | 1c97856d | aurel32 | t1 = tcg_temp_new_i64(); \ |
7658 | 1c97856d | aurel32 | gen_load_gpr64(t0, rA(ctx->opcode)); \ |
7659 | 1c97856d | aurel32 | gen_load_gpr64(t1, rB(ctx->opcode)); \ |
7660 | 1c97856d | aurel32 | gen_helper_##name(t0, t0, t1); \ |
7661 | 1c97856d | aurel32 | gen_store_gpr64(rD(ctx->opcode), t0); \ |
7662 | 1c97856d | aurel32 | tcg_temp_free_i64(t0); \ |
7663 | 1c97856d | aurel32 | tcg_temp_free_i64(t1); \ |
7664 | 1c97856d | aurel32 | } |
7665 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_COMP_32(name) \
|
7666 | 1c97856d | aurel32 | static always_inline void gen_##name (DisasContext *ctx) \ |
7667 | 1c97856d | aurel32 | { \ |
7668 | 1c97856d | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
7669 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
7670 | 1c97856d | aurel32 | return; \
|
7671 | 1c97856d | aurel32 | } \ |
7672 | 1c97856d | aurel32 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \ |
7673 | 1c97856d | aurel32 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ |
7674 | 1c97856d | aurel32 | } |
7675 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_COMP_64(name) \
|
7676 | 1c97856d | aurel32 | static always_inline void gen_##name (DisasContext *ctx) \ |
7677 | 1c97856d | aurel32 | { \ |
7678 | 1c97856d | aurel32 | TCGv_i64 t0, t1; \ |
7679 | 1c97856d | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
7680 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
7681 | 1c97856d | aurel32 | return; \
|
7682 | 1c97856d | aurel32 | } \ |
7683 | 1c97856d | aurel32 | t0 = tcg_temp_new_i64(); \ |
7684 | 1c97856d | aurel32 | t1 = tcg_temp_new_i64(); \ |
7685 | 1c97856d | aurel32 | gen_load_gpr64(t0, rA(ctx->opcode)); \ |
7686 | 1c97856d | aurel32 | gen_load_gpr64(t1, rB(ctx->opcode)); \ |
7687 | 1c97856d | aurel32 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \ |
7688 | 1c97856d | aurel32 | tcg_temp_free_i64(t0); \ |
7689 | 1c97856d | aurel32 | tcg_temp_free_i64(t1); \ |
7690 | 1c97856d | aurel32 | } |
7691 | 1c97856d | aurel32 | #endif
|
7692 | 57951c27 | aurel32 | |
7693 | 0487d6a8 | j_mayer | /* Single precision floating-point vectors operations */
|
7694 | 0487d6a8 | j_mayer | /* Arithmetic */
|
7695 | 1c97856d | aurel32 | GEN_SPEFPUOP_ARITH2_64_64(evfsadd); |
7696 | 1c97856d | aurel32 | GEN_SPEFPUOP_ARITH2_64_64(evfssub); |
7697 | 1c97856d | aurel32 | GEN_SPEFPUOP_ARITH2_64_64(evfsmul); |
7698 | 1c97856d | aurel32 | GEN_SPEFPUOP_ARITH2_64_64(evfsdiv); |
7699 | 1c97856d | aurel32 | static always_inline void gen_evfsabs (DisasContext *ctx) |
7700 | 1c97856d | aurel32 | { |
7701 | 1c97856d | aurel32 | if (unlikely(!ctx->spe_enabled)) {
|
7702 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); |
7703 | 1c97856d | aurel32 | return;
|
7704 | 1c97856d | aurel32 | } |
7705 | 1c97856d | aurel32 | #if defined(TARGET_PPC64)
|
7706 | 1c97856d | aurel32 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
|
7707 | 1c97856d | aurel32 | #else
|
7708 | 1c97856d | aurel32 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
|
7709 | 1c97856d | aurel32 | tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
|
7710 | 1c97856d | aurel32 | #endif
|
7711 | 1c97856d | aurel32 | } |
7712 | 1c97856d | aurel32 | static always_inline void gen_evfsnabs (DisasContext *ctx) |
7713 | 1c97856d | aurel32 | { |
7714 | 1c97856d | aurel32 | if (unlikely(!ctx->spe_enabled)) {
|
7715 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); |
7716 | 1c97856d | aurel32 | return;
|
7717 | 1c97856d | aurel32 | } |
7718 | 1c97856d | aurel32 | #if defined(TARGET_PPC64)
|
7719 | 1c97856d | aurel32 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
|
7720 | 1c97856d | aurel32 | #else
|
7721 | 1c97856d | aurel32 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
|
7722 | 1c97856d | aurel32 | tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
|
7723 | 1c97856d | aurel32 | #endif
|
7724 | 1c97856d | aurel32 | } |
7725 | 1c97856d | aurel32 | static always_inline void gen_evfsneg (DisasContext *ctx) |
7726 | 1c97856d | aurel32 | { |
7727 | 1c97856d | aurel32 | if (unlikely(!ctx->spe_enabled)) {
|
7728 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); |
7729 | 1c97856d | aurel32 | return;
|
7730 | 1c97856d | aurel32 | } |
7731 | 1c97856d | aurel32 | #if defined(TARGET_PPC64)
|
7732 | 1c97856d | aurel32 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
|
7733 | 1c97856d | aurel32 | #else
|
7734 | 1c97856d | aurel32 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
|
7735 | 1c97856d | aurel32 | tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
|
7736 | 1c97856d | aurel32 | #endif
|
7737 | 1c97856d | aurel32 | } |
7738 | 1c97856d | aurel32 | |
7739 | 0487d6a8 | j_mayer | /* Conversion */
|
7740 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_64(evfscfui); |
7741 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_64(evfscfsi); |
7742 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_64(evfscfuf); |
7743 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_64(evfscfsf); |
7744 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_64(evfsctui); |
7745 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_64(evfsctsi); |
7746 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_64(evfsctuf); |
7747 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_64(evfsctsf); |
7748 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_64(evfsctuiz); |
7749 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_64(evfsctsiz); |
7750 | 1c97856d | aurel32 | |
7751 | 0487d6a8 | j_mayer | /* Comparison */
|
7752 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_64(evfscmpgt); |
7753 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_64(evfscmplt); |
7754 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_64(evfscmpeq); |
7755 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_64(evfststgt); |
7756 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_64(evfststlt); |
7757 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_64(evfststeq); |
7758 | 0487d6a8 | j_mayer | |
7759 | 0487d6a8 | j_mayer | /* Opcodes definitions */
|
7760 | 40569b7e | aurel32 | GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPE_SINGLE); // |
7761 | 40569b7e | aurel32 | GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPE_SINGLE); // |
7762 | 40569b7e | aurel32 | GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPE_SINGLE); // |
7763 | 40569b7e | aurel32 | GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPE_SINGLE); // |
7764 | 40569b7e | aurel32 | GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPE_SINGLE); // |
7765 | 40569b7e | aurel32 | GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPE_SINGLE); // |
7766 | 40569b7e | aurel32 | GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPE_SINGLE); // |
7767 | 40569b7e | aurel32 | GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPE_SINGLE); // |
7768 | 40569b7e | aurel32 | GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPE_SINGLE); // |
7769 | 40569b7e | aurel32 | GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPE_SINGLE); // |
7770 | 40569b7e | aurel32 | GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPE_SINGLE); // |
7771 | 40569b7e | aurel32 | GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPE_SINGLE); // |
7772 | 40569b7e | aurel32 | GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPE_SINGLE); // |
7773 | 40569b7e | aurel32 | GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPE_SINGLE); // |
7774 | 0487d6a8 | j_mayer | |
7775 | 0487d6a8 | j_mayer | /* Single precision floating-point operations */
|
7776 | 0487d6a8 | j_mayer | /* Arithmetic */
|
7777 | 1c97856d | aurel32 | GEN_SPEFPUOP_ARITH2_32_32(efsadd); |
7778 | 1c97856d | aurel32 | GEN_SPEFPUOP_ARITH2_32_32(efssub); |
7779 | 1c97856d | aurel32 | GEN_SPEFPUOP_ARITH2_32_32(efsmul); |
7780 | 1c97856d | aurel32 | GEN_SPEFPUOP_ARITH2_32_32(efsdiv); |
7781 | 1c97856d | aurel32 | static always_inline void gen_efsabs (DisasContext *ctx) |
7782 | 1c97856d | aurel32 | { |
7783 | 1c97856d | aurel32 | if (unlikely(!ctx->spe_enabled)) {
|
7784 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); |
7785 | 1c97856d | aurel32 | return;
|
7786 | 1c97856d | aurel32 | } |
7787 | 1c97856d | aurel32 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
|
7788 | 1c97856d | aurel32 | } |
7789 | 1c97856d | aurel32 | static always_inline void gen_efsnabs (DisasContext *ctx) |
7790 | 1c97856d | aurel32 | { |
7791 | 1c97856d | aurel32 | if (unlikely(!ctx->spe_enabled)) {
|
7792 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); |
7793 | 1c97856d | aurel32 | return;
|
7794 | 1c97856d | aurel32 | } |
7795 | 1c97856d | aurel32 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
|
7796 | 1c97856d | aurel32 | } |
7797 | 1c97856d | aurel32 | static always_inline void gen_efsneg (DisasContext *ctx) |
7798 | 1c97856d | aurel32 | { |
7799 | 1c97856d | aurel32 | if (unlikely(!ctx->spe_enabled)) {
|
7800 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); |
7801 | 1c97856d | aurel32 | return;
|
7802 | 1c97856d | aurel32 | } |
7803 | 1c97856d | aurel32 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
|
7804 | 1c97856d | aurel32 | } |
7805 | 1c97856d | aurel32 | |
7806 | 0487d6a8 | j_mayer | /* Conversion */
|
7807 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_32(efscfui); |
7808 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_32(efscfsi); |
7809 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_32(efscfuf); |
7810 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_32(efscfsf); |
7811 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_32(efsctui); |
7812 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_32(efsctsi); |
7813 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_32(efsctuf); |
7814 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_32(efsctsf); |
7815 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_32(efsctuiz); |
7816 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_32(efsctsiz); |
7817 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_64(efscfd); |
7818 | 1c97856d | aurel32 | |
7819 | 0487d6a8 | j_mayer | /* Comparison */
|
7820 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_32(efscmpgt); |
7821 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_32(efscmplt); |
7822 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_32(efscmpeq); |
7823 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_32(efststgt); |
7824 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_32(efststlt); |
7825 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_32(efststeq); |
7826 | 0487d6a8 | j_mayer | |
7827 | 0487d6a8 | j_mayer | /* Opcodes definitions */
|
7828 | 40569b7e | aurel32 | GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPE_SINGLE); // |
7829 | 40569b7e | aurel32 | GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPE_SINGLE); // |
7830 | 40569b7e | aurel32 | GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPE_SINGLE); // |
7831 | 40569b7e | aurel32 | GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPE_SINGLE); // |
7832 | 40569b7e | aurel32 | GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPE_SINGLE); // |
7833 | 40569b7e | aurel32 | GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPE_SINGLE); // |
7834 | 40569b7e | aurel32 | GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPE_SINGLE); // |
7835 | 40569b7e | aurel32 | GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPE_SINGLE); // |
7836 | 40569b7e | aurel32 | GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPE_SINGLE); // |
7837 | 40569b7e | aurel32 | GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPE_SINGLE); // |
7838 | 40569b7e | aurel32 | GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPE_SINGLE); // |
7839 | 40569b7e | aurel32 | GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPE_SINGLE); // |
7840 | 40569b7e | aurel32 | GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPE_SINGLE); // |
7841 | 40569b7e | aurel32 | GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPE_SINGLE); // |
7842 | 0487d6a8 | j_mayer | |
7843 | 0487d6a8 | j_mayer | /* Double precision floating-point operations */
|
7844 | 0487d6a8 | j_mayer | /* Arithmetic */
|
7845 | 1c97856d | aurel32 | GEN_SPEFPUOP_ARITH2_64_64(efdadd); |
7846 | 1c97856d | aurel32 | GEN_SPEFPUOP_ARITH2_64_64(efdsub); |
7847 | 1c97856d | aurel32 | GEN_SPEFPUOP_ARITH2_64_64(efdmul); |
7848 | 1c97856d | aurel32 | GEN_SPEFPUOP_ARITH2_64_64(efddiv); |
7849 | 1c97856d | aurel32 | static always_inline void gen_efdabs (DisasContext *ctx) |
7850 | 1c97856d | aurel32 | { |
7851 | 1c97856d | aurel32 | if (unlikely(!ctx->spe_enabled)) {
|
7852 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); |
7853 | 1c97856d | aurel32 | return;
|
7854 | 1c97856d | aurel32 | } |
7855 | 1c97856d | aurel32 | #if defined(TARGET_PPC64)
|
7856 | 1c97856d | aurel32 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
|
7857 | 1c97856d | aurel32 | #else
|
7858 | 1c97856d | aurel32 | tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
|
7859 | 1c97856d | aurel32 | #endif
|
7860 | 1c97856d | aurel32 | } |
7861 | 1c97856d | aurel32 | static always_inline void gen_efdnabs (DisasContext *ctx) |
7862 | 1c97856d | aurel32 | { |
7863 | 1c97856d | aurel32 | if (unlikely(!ctx->spe_enabled)) {
|
7864 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); |
7865 | 1c97856d | aurel32 | return;
|
7866 | 1c97856d | aurel32 | } |
7867 | 1c97856d | aurel32 | #if defined(TARGET_PPC64)
|
7868 | 1c97856d | aurel32 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
|
7869 | 1c97856d | aurel32 | #else
|
7870 | 1c97856d | aurel32 | tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
|
7871 | 1c97856d | aurel32 | #endif
|
7872 | 1c97856d | aurel32 | } |
7873 | 1c97856d | aurel32 | static always_inline void gen_efdneg (DisasContext *ctx) |
7874 | 1c97856d | aurel32 | { |
7875 | 1c97856d | aurel32 | if (unlikely(!ctx->spe_enabled)) {
|
7876 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); |
7877 | 1c97856d | aurel32 | return;
|
7878 | 1c97856d | aurel32 | } |
7879 | 1c97856d | aurel32 | #if defined(TARGET_PPC64)
|
7880 | 1c97856d | aurel32 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
|
7881 | 1c97856d | aurel32 | #else
|
7882 | 1c97856d | aurel32 | tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
|
7883 | 1c97856d | aurel32 | #endif
|
7884 | 1c97856d | aurel32 | } |
7885 | 1c97856d | aurel32 | |
7886 | 0487d6a8 | j_mayer | /* Conversion */
|
7887 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_32(efdcfui); |
7888 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_32(efdcfsi); |
7889 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_32(efdcfuf); |
7890 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_32(efdcfsf); |
7891 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_64(efdctui); |
7892 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_64(efdctsi); |
7893 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_64(efdctuf); |
7894 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_64(efdctsf); |
7895 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_64(efdctuiz); |
7896 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_64(efdctsiz); |
7897 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_32(efdcfs); |
7898 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_64(efdcfuid); |
7899 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_64(efdcfsid); |
7900 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_64(efdctuidz); |
7901 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_64(efdctsidz); |
7902 | 0487d6a8 | j_mayer | |
7903 | 0487d6a8 | j_mayer | /* Comparison */
|
7904 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_64(efdcmpgt); |
7905 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_64(efdcmplt); |
7906 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_64(efdcmpeq); |
7907 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_64(efdtstgt); |
7908 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_64(efdtstlt); |
7909 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_64(efdtsteq); |
7910 | 0487d6a8 | j_mayer | |
7911 | 0487d6a8 | j_mayer | /* Opcodes definitions */
|
7912 | 40569b7e | aurel32 | GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPE_DOUBLE); // |
7913 | 40569b7e | aurel32 | GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPE_DOUBLE); // |
7914 | 40569b7e | aurel32 | GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPE_DOUBLE); // |
7915 | 40569b7e | aurel32 | GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPE_DOUBLE); // |
7916 | 40569b7e | aurel32 | GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPE_DOUBLE); // |
7917 | 40569b7e | aurel32 | GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPE_DOUBLE); // |
7918 | 40569b7e | aurel32 | GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPE_DOUBLE); // |
7919 | 40569b7e | aurel32 | GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPE_DOUBLE); // |
7920 | 40569b7e | aurel32 | GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPE_DOUBLE); // |
7921 | 40569b7e | aurel32 | GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPE_DOUBLE); // |
7922 | 40569b7e | aurel32 | GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPE_DOUBLE); // |
7923 | 40569b7e | aurel32 | GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPE_DOUBLE); // |
7924 | 40569b7e | aurel32 | GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPE_DOUBLE); // |
7925 | 40569b7e | aurel32 | GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPE_DOUBLE); // |
7926 | 40569b7e | aurel32 | GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPE_DOUBLE); // |
7927 | 40569b7e | aurel32 | GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPE_DOUBLE); // |
7928 | 0487d6a8 | j_mayer | |
7929 | 5c55ff99 | Blue Swirl | static opcode_t opcodes[] = {
|
7930 | 5c55ff99 | Blue Swirl | GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), |
7931 | 5c55ff99 | Blue Swirl | GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), |
7932 | 5c55ff99 | Blue Swirl | GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), |
7933 | 5c55ff99 | Blue Swirl | GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER), |
7934 | 5c55ff99 | Blue Swirl | GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), |
7935 | 5c55ff99 | Blue Swirl | GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), |
7936 | 5c55ff99 | Blue Swirl | GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
7937 | 5c55ff99 | Blue Swirl | GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
7938 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
7939 | 5c55ff99 | Blue Swirl | GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
7940 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), |
7941 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), |
7942 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), |
7943 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), |
7944 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
7945 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
7946 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), |
7947 | 5c55ff99 | Blue Swirl | #endif
|
7948 | 5c55ff99 | Blue Swirl | GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), |
7949 | 5c55ff99 | Blue Swirl | GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), |
7950 | 5c55ff99 | Blue Swirl | GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
7951 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
7952 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
7953 | 5c55ff99 | Blue Swirl | GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), |
7954 | 5c55ff99 | Blue Swirl | GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), |
7955 | 5c55ff99 | Blue Swirl | GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), |
7956 | 5c55ff99 | Blue Swirl | GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
7957 | 5c55ff99 | Blue Swirl | GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
7958 | 5c55ff99 | Blue Swirl | GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
7959 | 5c55ff99 | Blue Swirl | GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
7960 | 5c55ff99 | Blue Swirl | GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB), |
7961 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
7962 | 5c55ff99 | Blue Swirl | GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), |
7963 | 5c55ff99 | Blue Swirl | #endif
|
7964 | 5c55ff99 | Blue Swirl | GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
7965 | 5c55ff99 | Blue Swirl | GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
7966 | 5c55ff99 | Blue Swirl | GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
7967 | 5c55ff99 | Blue Swirl | GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), |
7968 | 5c55ff99 | Blue Swirl | GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), |
7969 | 5c55ff99 | Blue Swirl | GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), |
7970 | 5c55ff99 | Blue Swirl | GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), |
7971 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
7972 | 5c55ff99 | Blue Swirl | GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), |
7973 | 5c55ff99 | Blue Swirl | GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), |
7974 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), |
7975 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), |
7976 | 5c55ff99 | Blue Swirl | GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), |
7977 | 5c55ff99 | Blue Swirl | #endif
|
7978 | 5c55ff99 | Blue Swirl | GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES), |
7979 | 5c55ff99 | Blue Swirl | GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT), |
7980 | 5c55ff99 | Blue Swirl | GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT), |
7981 | 5c55ff99 | Blue Swirl | GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT), |
7982 | 5c55ff99 | Blue Swirl | GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT), |
7983 | 5c55ff99 | Blue Swirl | GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT), |
7984 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT), |
7985 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT), |
7986 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT), |
7987 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT), |
7988 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00010000, PPC_FLOAT), |
7989 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT), |
7990 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
7991 | 5c55ff99 | Blue Swirl | GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B), |
7992 | 5c55ff99 | Blue Swirl | GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX), |
7993 | 5c55ff99 | Blue Swirl | GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B), |
7994 | 5c55ff99 | Blue Swirl | #endif
|
7995 | 5c55ff99 | Blue Swirl | GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
7996 | 5c55ff99 | Blue Swirl | GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
7997 | 5c55ff99 | Blue Swirl | GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), |
7998 | 5c55ff99 | Blue Swirl | GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), |
7999 | 5c55ff99 | Blue Swirl | GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), |
8000 | 5c55ff99 | Blue Swirl | GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), |
8001 | 5c55ff99 | Blue Swirl | GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO), |
8002 | 5c55ff99 | Blue Swirl | GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), |
8003 | 5c55ff99 | Blue Swirl | GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES), |
8004 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), |
8005 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
8006 | 5c55ff99 | Blue Swirl | GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B), |
8007 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), |
8008 | 5c55ff99 | Blue Swirl | #endif
|
8009 | 5c55ff99 | Blue Swirl | GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), |
8010 | 5c55ff99 | Blue Swirl | GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT), |
8011 | 5c55ff99 | Blue Swirl | GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), |
8012 | 5c55ff99 | Blue Swirl | GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), |
8013 | 5c55ff99 | Blue Swirl | GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), |
8014 | 5c55ff99 | Blue Swirl | GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), |
8015 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), |
8016 | 5c55ff99 | Blue Swirl | GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), |
8017 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
8018 | 5c55ff99 | Blue Swirl | GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), |
8019 | 5c55ff99 | Blue Swirl | GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), |
8020 | 5c55ff99 | Blue Swirl | #endif
|
8021 | 5c55ff99 | Blue Swirl | GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW), |
8022 | 5c55ff99 | Blue Swirl | GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), |
8023 | 5c55ff99 | Blue Swirl | GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), |
8024 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
8025 | 5c55ff99 | Blue Swirl | GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), |
8026 | 5c55ff99 | Blue Swirl | GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), |
8027 | 5c55ff99 | Blue Swirl | #endif
|
8028 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), |
8029 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), |
8030 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), |
8031 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), |
8032 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), |
8033 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), |
8034 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
8035 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), |
8036 | 5c55ff99 | Blue Swirl | #endif
|
8037 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC), |
8038 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC), |
8039 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), |
8040 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), |
8041 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), |
8042 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE), |
8043 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE), |
8044 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ), |
8045 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT), |
8046 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), |
8047 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC), |
8048 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), |
8049 | 5c55ff99 | Blue Swirl | GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), |
8050 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), |
8051 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), |
8052 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), |
8053 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), |
8054 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), |
8055 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
8056 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), |
8057 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, |
8058 | 5c55ff99 | Blue Swirl | PPC_SEGMENT_64B), |
8059 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), |
8060 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, |
8061 | 5c55ff99 | Blue Swirl | PPC_SEGMENT_64B), |
8062 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x00000000, PPC_SEGMENT_64B), |
8063 | 5c55ff99 | Blue Swirl | #endif
|
8064 | 5c55ff99 | Blue Swirl | GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), |
8065 | 5c55ff99 | Blue Swirl | GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE), |
8066 | 5c55ff99 | Blue Swirl | GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE), |
8067 | 5c55ff99 | Blue Swirl | GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), |
8068 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
8069 | 5c55ff99 | Blue Swirl | GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI), |
8070 | 5c55ff99 | Blue Swirl | GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI), |
8071 | 5c55ff99 | Blue Swirl | #endif
|
8072 | 5c55ff99 | Blue Swirl | GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), |
8073 | 5c55ff99 | Blue Swirl | GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), |
8074 | 5c55ff99 | Blue Swirl | GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR), |
8075 | 5c55ff99 | Blue Swirl | GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR), |
8076 | 5c55ff99 | Blue Swirl | GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR), |
8077 | 5c55ff99 | Blue Swirl | GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR), |
8078 | 5c55ff99 | Blue Swirl | GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR), |
8079 | 5c55ff99 | Blue Swirl | GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR), |
8080 | 5c55ff99 | Blue Swirl | GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR), |
8081 | 5c55ff99 | Blue Swirl | GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR), |
8082 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR), |
8083 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), |
8084 | 5c55ff99 | Blue Swirl | GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR), |
8085 | 5c55ff99 | Blue Swirl | GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR), |
8086 | 5c55ff99 | Blue Swirl | GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR), |
8087 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR), |
8088 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR), |
8089 | 5c55ff99 | Blue Swirl | GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR), |
8090 | 5c55ff99 | Blue Swirl | GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR), |
8091 | 5c55ff99 | Blue Swirl | GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), |
8092 | 5c55ff99 | Blue Swirl | GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR), |
8093 | 5c55ff99 | Blue Swirl | GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR), |
8094 | 5c55ff99 | Blue Swirl | GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR), |
8095 | 5c55ff99 | Blue Swirl | GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR), |
8096 | 5c55ff99 | Blue Swirl | GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR), |
8097 | 5c55ff99 | Blue Swirl | GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR), |
8098 | 5c55ff99 | Blue Swirl | GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR), |
8099 | 5c55ff99 | Blue Swirl | GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR), |
8100 | 5c55ff99 | Blue Swirl | GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR), |
8101 | 5c55ff99 | Blue Swirl | GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR), |
8102 | 5c55ff99 | Blue Swirl | GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR), |
8103 | 5c55ff99 | Blue Swirl | GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR), |
8104 | 5c55ff99 | Blue Swirl | GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR), |
8105 | 5c55ff99 | Blue Swirl | GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR), |
8106 | 5c55ff99 | Blue Swirl | GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR), |
8107 | 5c55ff99 | Blue Swirl | GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR), |
8108 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC), |
8109 | 5c55ff99 | Blue Swirl | GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), |
8110 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), |
8111 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), |
8112 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), |
8113 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB), |
8114 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB), |
8115 | 5c55ff99 | Blue Swirl | GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), |
8116 | 5c55ff99 | Blue Swirl | GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER), |
8117 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER), |
8118 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER), |
8119 | 5c55ff99 | Blue Swirl | GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER), |
8120 | 5c55ff99 | Blue Swirl | GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER), |
8121 | 5c55ff99 | Blue Swirl | GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2), |
8122 | 5c55ff99 | Blue Swirl | GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2), |
8123 | 5c55ff99 | Blue Swirl | GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2), |
8124 | 5c55ff99 | Blue Swirl | GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2), |
8125 | 5c55ff99 | Blue Swirl | GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2), |
8126 | 5c55ff99 | Blue Swirl | GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2), |
8127 | 5c55ff99 | Blue Swirl | GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2), |
8128 | 5c55ff99 | Blue Swirl | GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2), |
8129 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), |
8130 | 5c55ff99 | Blue Swirl | GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), |
8131 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), |
8132 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), |
8133 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), |
8134 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), |
8135 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX), |
8136 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX), |
8137 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), |
8138 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), |
8139 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), |
8140 | 5c55ff99 | Blue Swirl | GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), |
8141 | 5c55ff99 | Blue Swirl | GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), |
8142 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), |
8143 | 5c55ff99 | Blue Swirl | GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE), |
8144 | 5c55ff99 | Blue Swirl | GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), |
8145 | 5c55ff99 | Blue Swirl | GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), |
8146 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), |
8147 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), |
8148 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), |
8149 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), |
8150 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), |
8151 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), |
8152 | 5c55ff99 | Blue Swirl | GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), |
8153 | 5c55ff99 | Blue Swirl | GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE), |
8154 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), |
8155 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, PPC_BOOKE), |
8156 | 5c55ff99 | Blue Swirl | GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE), |
8157 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE), |
8158 | 5c55ff99 | Blue Swirl | GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), |
8159 | 5c55ff99 | Blue Swirl | GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), |
8160 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), |
8161 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), |
8162 | 5c55ff99 | Blue Swirl | GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC), |
8163 | 5c55ff99 | Blue Swirl | GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), |
8164 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE), |
8165 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE), |
8166 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE), |
8167 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE), |
8168 | 5c55ff99 | Blue Swirl | |
8169 | 5c55ff99 | Blue Swirl | #undef GEN_INT_ARITH_ADD
|
8170 | 5c55ff99 | Blue Swirl | #undef GEN_INT_ARITH_ADD_CONST
|
8171 | 5c55ff99 | Blue Swirl | #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
|
8172 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), |
8173 | 5c55ff99 | Blue Swirl | #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
|
8174 | 5c55ff99 | Blue Swirl | add_ca, compute_ca, compute_ov) \ |
8175 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), |
8176 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) |
8177 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) |
8178 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) |
8179 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) |
8180 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) |
8181 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) |
8182 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) |
8183 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) |
8184 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) |
8185 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) |
8186 | 5c55ff99 | Blue Swirl | |
8187 | 5c55ff99 | Blue Swirl | #undef GEN_INT_ARITH_DIVW
|
8188 | 5c55ff99 | Blue Swirl | #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
|
8189 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) |
8190 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), |
8191 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), |
8192 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), |
8193 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), |
8194 | 5c55ff99 | Blue Swirl | |
8195 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
8196 | 5c55ff99 | Blue Swirl | #undef GEN_INT_ARITH_DIVD
|
8197 | 5c55ff99 | Blue Swirl | #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
|
8198 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) |
8199 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), |
8200 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), |
8201 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), |
8202 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), |
8203 | 5c55ff99 | Blue Swirl | |
8204 | 5c55ff99 | Blue Swirl | #undef GEN_INT_ARITH_MUL_HELPER
|
8205 | 5c55ff99 | Blue Swirl | #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
|
8206 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) |
8207 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
|
8208 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
|
8209 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
|
8210 | 5c55ff99 | Blue Swirl | #endif
|
8211 | 5c55ff99 | Blue Swirl | |
8212 | 5c55ff99 | Blue Swirl | #undef GEN_INT_ARITH_SUBF
|
8213 | 5c55ff99 | Blue Swirl | #undef GEN_INT_ARITH_SUBF_CONST
|
8214 | 5c55ff99 | Blue Swirl | #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
|
8215 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), |
8216 | 5c55ff99 | Blue Swirl | #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
|
8217 | 5c55ff99 | Blue Swirl | add_ca, compute_ca, compute_ov) \ |
8218 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), |
8219 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) |
8220 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) |
8221 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) |
8222 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) |
8223 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) |
8224 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) |
8225 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) |
8226 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) |
8227 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) |
8228 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) |
8229 | 5c55ff99 | Blue Swirl | |
8230 | 5c55ff99 | Blue Swirl | #undef GEN_LOGICAL1
|
8231 | 5c55ff99 | Blue Swirl | #undef GEN_LOGICAL2
|
8232 | 5c55ff99 | Blue Swirl | #define GEN_LOGICAL2(name, tcg_op, opc, type) \
|
8233 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) |
8234 | 5c55ff99 | Blue Swirl | #define GEN_LOGICAL1(name, tcg_op, opc, type) \
|
8235 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) |
8236 | 5c55ff99 | Blue Swirl | GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
|
8237 | 5c55ff99 | Blue Swirl | GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
|
8238 | 5c55ff99 | Blue Swirl | GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
|
8239 | 5c55ff99 | Blue Swirl | GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
|
8240 | 5c55ff99 | Blue Swirl | GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
|
8241 | 5c55ff99 | Blue Swirl | GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
|
8242 | 5c55ff99 | Blue Swirl | GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
|
8243 | 5c55ff99 | Blue Swirl | GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
|
8244 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
8245 | 5c55ff99 | Blue Swirl | GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
|
8246 | 5c55ff99 | Blue Swirl | #endif
|
8247 | 5c55ff99 | Blue Swirl | |
8248 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
8249 | 5c55ff99 | Blue Swirl | #undef GEN_PPC64_R2
|
8250 | 5c55ff99 | Blue Swirl | #undef GEN_PPC64_R4
|
8251 | 5c55ff99 | Blue Swirl | #define GEN_PPC64_R2(name, opc1, opc2) \
|
8252 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ |
8253 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ |
8254 | 5c55ff99 | Blue Swirl | PPC_64B) |
8255 | 5c55ff99 | Blue Swirl | #define GEN_PPC64_R4(name, opc1, opc2) \
|
8256 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ |
8257 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ |
8258 | 5c55ff99 | Blue Swirl | PPC_64B), \ |
8259 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ |
8260 | 5c55ff99 | Blue Swirl | PPC_64B), \ |
8261 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ |
8262 | 5c55ff99 | Blue Swirl | PPC_64B) |
8263 | 5c55ff99 | Blue Swirl | GEN_PPC64_R4(rldicl, 0x1E, 0x00), |
8264 | 5c55ff99 | Blue Swirl | GEN_PPC64_R4(rldicr, 0x1E, 0x02), |
8265 | 5c55ff99 | Blue Swirl | GEN_PPC64_R4(rldic, 0x1E, 0x04), |
8266 | 5c55ff99 | Blue Swirl | GEN_PPC64_R2(rldcl, 0x1E, 0x08), |
8267 | 5c55ff99 | Blue Swirl | GEN_PPC64_R2(rldcr, 0x1E, 0x09), |
8268 | 5c55ff99 | Blue Swirl | GEN_PPC64_R4(rldimi, 0x1E, 0x06), |
8269 | 5c55ff99 | Blue Swirl | #endif
|
8270 | 5c55ff99 | Blue Swirl | |
8271 | 5c55ff99 | Blue Swirl | #undef _GEN_FLOAT_ACB
|
8272 | 5c55ff99 | Blue Swirl | #undef GEN_FLOAT_ACB
|
8273 | 5c55ff99 | Blue Swirl | #undef _GEN_FLOAT_AB
|
8274 | 5c55ff99 | Blue Swirl | #undef GEN_FLOAT_AB
|
8275 | 5c55ff99 | Blue Swirl | #undef _GEN_FLOAT_AC
|
8276 | 5c55ff99 | Blue Swirl | #undef GEN_FLOAT_AC
|
8277 | 5c55ff99 | Blue Swirl | #undef GEN_FLOAT_B
|
8278 | 5c55ff99 | Blue Swirl | #undef GEN_FLOAT_BS
|
8279 | 5c55ff99 | Blue Swirl | #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
|
8280 | 5c55ff99 | Blue Swirl | GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) |
8281 | 5c55ff99 | Blue Swirl | #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
|
8282 | 5c55ff99 | Blue Swirl | _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \ |
8283 | 5c55ff99 | Blue Swirl | _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type) |
8284 | 5c55ff99 | Blue Swirl | #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
|
8285 | 5c55ff99 | Blue Swirl | GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) |
8286 | 5c55ff99 | Blue Swirl | #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
|
8287 | 5c55ff99 | Blue Swirl | _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \ |
8288 | 5c55ff99 | Blue Swirl | _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type) |
8289 | 5c55ff99 | Blue Swirl | #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
|
8290 | 5c55ff99 | Blue Swirl | GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) |
8291 | 5c55ff99 | Blue Swirl | #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
|
8292 | 5c55ff99 | Blue Swirl | _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \ |
8293 | 5c55ff99 | Blue Swirl | _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type) |
8294 | 5c55ff99 | Blue Swirl | #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
|
8295 | 5c55ff99 | Blue Swirl | GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) |
8296 | 5c55ff99 | Blue Swirl | #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
|
8297 | 5c55ff99 | Blue Swirl | GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) |
8298 | 5c55ff99 | Blue Swirl | |
8299 | 5c55ff99 | Blue Swirl | GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT), |
8300 | 5c55ff99 | Blue Swirl | GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT), |
8301 | 5c55ff99 | Blue Swirl | GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT), |
8302 | 5c55ff99 | Blue Swirl | GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT), |
8303 | 5c55ff99 | Blue Swirl | GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES), |
8304 | 5c55ff99 | Blue Swirl | GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE), |
8305 | 5c55ff99 | Blue Swirl | _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL), |
8306 | 5c55ff99 | Blue Swirl | GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT), |
8307 | 5c55ff99 | Blue Swirl | GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT), |
8308 | 5c55ff99 | Blue Swirl | GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT), |
8309 | 5c55ff99 | Blue Swirl | GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT), |
8310 | 5c55ff99 | Blue Swirl | GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT), |
8311 | 5c55ff99 | Blue Swirl | GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT), |
8312 | 5c55ff99 | Blue Swirl | GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT), |
8313 | 5c55ff99 | Blue Swirl | GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT), |
8314 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
8315 | 5c55ff99 | Blue Swirl | GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B), |
8316 | 5c55ff99 | Blue Swirl | GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B), |
8317 | 5c55ff99 | Blue Swirl | GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B), |
8318 | 5c55ff99 | Blue Swirl | #endif
|
8319 | 5c55ff99 | Blue Swirl | GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT), |
8320 | 5c55ff99 | Blue Swirl | GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT), |
8321 | 5c55ff99 | Blue Swirl | GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT), |
8322 | 5c55ff99 | Blue Swirl | GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT), |
8323 | 5c55ff99 | Blue Swirl | GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT), |
8324 | 5c55ff99 | Blue Swirl | GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT), |
8325 | 5c55ff99 | Blue Swirl | GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT), |
8326 | 5c55ff99 | Blue Swirl | |
8327 | 5c55ff99 | Blue Swirl | #undef GEN_LD
|
8328 | 5c55ff99 | Blue Swirl | #undef GEN_LDU
|
8329 | 5c55ff99 | Blue Swirl | #undef GEN_LDUX
|
8330 | 5c55ff99 | Blue Swirl | #undef GEN_LDX
|
8331 | 5c55ff99 | Blue Swirl | #undef GEN_LDS
|
8332 | 5c55ff99 | Blue Swirl | #define GEN_LD(name, ldop, opc, type) \
|
8333 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), |
8334 | 5c55ff99 | Blue Swirl | #define GEN_LDU(name, ldop, opc, type) \
|
8335 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), |
8336 | 5c55ff99 | Blue Swirl | #define GEN_LDUX(name, ldop, opc2, opc3, type) \
|
8337 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), |
8338 | 5c55ff99 | Blue Swirl | #define GEN_LDX(name, ldop, opc2, opc3, type) \
|
8339 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type), |
8340 | 5c55ff99 | Blue Swirl | #define GEN_LDS(name, ldop, op, type) \
|
8341 | 5c55ff99 | Blue Swirl | GEN_LD(name, ldop, op | 0x20, type) \
|
8342 | 5c55ff99 | Blue Swirl | GEN_LDU(name, ldop, op | 0x21, type) \
|
8343 | 5c55ff99 | Blue Swirl | GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \ |
8344 | 5c55ff99 | Blue Swirl | GEN_LDX(name, ldop, 0x17, op | 0x00, type) |
8345 | 5c55ff99 | Blue Swirl | |
8346 | 5c55ff99 | Blue Swirl | GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
|
8347 | 5c55ff99 | Blue Swirl | GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
|
8348 | 5c55ff99 | Blue Swirl | GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
|
8349 | 5c55ff99 | Blue Swirl | GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
|
8350 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
8351 | 5c55ff99 | Blue Swirl | GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B) |
8352 | 5c55ff99 | Blue Swirl | GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B) |
8353 | 5c55ff99 | Blue Swirl | GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B) |
8354 | 5c55ff99 | Blue Swirl | GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B) |
8355 | 5c55ff99 | Blue Swirl | #endif
|
8356 | 5c55ff99 | Blue Swirl | GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) |
8357 | 5c55ff99 | Blue Swirl | GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) |
8358 | 5c55ff99 | Blue Swirl | |
8359 | 5c55ff99 | Blue Swirl | #undef GEN_ST
|
8360 | 5c55ff99 | Blue Swirl | #undef GEN_STU
|
8361 | 5c55ff99 | Blue Swirl | #undef GEN_STUX
|
8362 | 5c55ff99 | Blue Swirl | #undef GEN_STX
|
8363 | 5c55ff99 | Blue Swirl | #undef GEN_STS
|
8364 | 5c55ff99 | Blue Swirl | #define GEN_ST(name, stop, opc, type) \
|
8365 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), |
8366 | 5c55ff99 | Blue Swirl | #define GEN_STU(name, stop, opc, type) \
|
8367 | 5c55ff99 | Blue Swirl | GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type), |
8368 | 5c55ff99 | Blue Swirl | #define GEN_STUX(name, stop, opc2, opc3, type) \
|
8369 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), |
8370 | 5c55ff99 | Blue Swirl | #define GEN_STX(name, stop, opc2, opc3, type) \
|
8371 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type), |
8372 | 5c55ff99 | Blue Swirl | #define GEN_STS(name, stop, op, type) \
|
8373 | 5c55ff99 | Blue Swirl | GEN_ST(name, stop, op | 0x20, type) \
|
8374 | 5c55ff99 | Blue Swirl | GEN_STU(name, stop, op | 0x21, type) \
|
8375 | 5c55ff99 | Blue Swirl | GEN_STUX(name, stop, 0x17, op | 0x01, type) \ |
8376 | 5c55ff99 | Blue Swirl | GEN_STX(name, stop, 0x17, op | 0x00, type) |
8377 | 5c55ff99 | Blue Swirl | |
8378 | 5c55ff99 | Blue Swirl | GEN_STS(stb, st8, 0x06, PPC_INTEGER)
|
8379 | 5c55ff99 | Blue Swirl | GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
|
8380 | 5c55ff99 | Blue Swirl | GEN_STS(stw, st32, 0x04, PPC_INTEGER)
|
8381 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
8382 | 5c55ff99 | Blue Swirl | GEN_STUX(std, st64, 0x15, 0x05, PPC_64B) |
8383 | 5c55ff99 | Blue Swirl | GEN_STX(std, st64, 0x15, 0x04, PPC_64B) |
8384 | 5c55ff99 | Blue Swirl | #endif
|
8385 | 5c55ff99 | Blue Swirl | GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) |
8386 | 5c55ff99 | Blue Swirl | GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) |
8387 | 5c55ff99 | Blue Swirl | |
8388 | 5c55ff99 | Blue Swirl | #undef GEN_LDF
|
8389 | 5c55ff99 | Blue Swirl | #undef GEN_LDUF
|
8390 | 5c55ff99 | Blue Swirl | #undef GEN_LDUXF
|
8391 | 5c55ff99 | Blue Swirl | #undef GEN_LDXF
|
8392 | 5c55ff99 | Blue Swirl | #undef GEN_LDFS
|
8393 | 5c55ff99 | Blue Swirl | #define GEN_LDF(name, ldop, opc, type) \
|
8394 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), |
8395 | 5c55ff99 | Blue Swirl | #define GEN_LDUF(name, ldop, opc, type) \
|
8396 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), |
8397 | 5c55ff99 | Blue Swirl | #define GEN_LDUXF(name, ldop, opc, type) \
|
8398 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type), |
8399 | 5c55ff99 | Blue Swirl | #define GEN_LDXF(name, ldop, opc2, opc3, type) \
|
8400 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type), |
8401 | 5c55ff99 | Blue Swirl | #define GEN_LDFS(name, ldop, op, type) \
|
8402 | 5c55ff99 | Blue Swirl | GEN_LDF(name, ldop, op | 0x20, type) \
|
8403 | 5c55ff99 | Blue Swirl | GEN_LDUF(name, ldop, op | 0x21, type) \
|
8404 | 5c55ff99 | Blue Swirl | GEN_LDUXF(name, ldop, op | 0x01, type) \
|
8405 | 5c55ff99 | Blue Swirl | GEN_LDXF(name, ldop, 0x17, op | 0x00, type) |
8406 | 5c55ff99 | Blue Swirl | |
8407 | 5c55ff99 | Blue Swirl | GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
|
8408 | 5c55ff99 | Blue Swirl | GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
|
8409 | 5c55ff99 | Blue Swirl | |
8410 | 5c55ff99 | Blue Swirl | #undef GEN_STF
|
8411 | 5c55ff99 | Blue Swirl | #undef GEN_STUF
|
8412 | 5c55ff99 | Blue Swirl | #undef GEN_STUXF
|
8413 | 5c55ff99 | Blue Swirl | #undef GEN_STXF
|
8414 | 5c55ff99 | Blue Swirl | #undef GEN_STFS
|
8415 | 5c55ff99 | Blue Swirl | #define GEN_STF(name, stop, opc, type) \
|
8416 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), |
8417 | 5c55ff99 | Blue Swirl | #define GEN_STUF(name, stop, opc, type) \
|
8418 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), |
8419 | 5c55ff99 | Blue Swirl | #define GEN_STUXF(name, stop, opc, type) \
|
8420 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type), |
8421 | 5c55ff99 | Blue Swirl | #define GEN_STXF(name, stop, opc2, opc3, type) \
|
8422 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type), |
8423 | 5c55ff99 | Blue Swirl | #define GEN_STFS(name, stop, op, type) \
|
8424 | 5c55ff99 | Blue Swirl | GEN_STF(name, stop, op | 0x20, type) \
|
8425 | 5c55ff99 | Blue Swirl | GEN_STUF(name, stop, op | 0x21, type) \
|
8426 | 5c55ff99 | Blue Swirl | GEN_STUXF(name, stop, op | 0x01, type) \
|
8427 | 5c55ff99 | Blue Swirl | GEN_STXF(name, stop, 0x17, op | 0x00, type) |
8428 | 5c55ff99 | Blue Swirl | |
8429 | 5c55ff99 | Blue Swirl | GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
|
8430 | 5c55ff99 | Blue Swirl | GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
|
8431 | 5c55ff99 | Blue Swirl | GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX) |
8432 | 5c55ff99 | Blue Swirl | |
8433 | 5c55ff99 | Blue Swirl | #undef GEN_CRLOGIC
|
8434 | 5c55ff99 | Blue Swirl | #define GEN_CRLOGIC(name, tcg_op, opc) \
|
8435 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) |
8436 | 5c55ff99 | Blue Swirl | GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
|
8437 | 5c55ff99 | Blue Swirl | GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
|
8438 | 5c55ff99 | Blue Swirl | GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
|
8439 | 5c55ff99 | Blue Swirl | GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
|
8440 | 5c55ff99 | Blue Swirl | GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
|
8441 | 5c55ff99 | Blue Swirl | GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
|
8442 | 5c55ff99 | Blue Swirl | GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
|
8443 | 5c55ff99 | Blue Swirl | GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
|
8444 | 5c55ff99 | Blue Swirl | |
8445 | 5c55ff99 | Blue Swirl | #undef GEN_MAC_HANDLER
|
8446 | 5c55ff99 | Blue Swirl | #define GEN_MAC_HANDLER(name, opc2, opc3) \
|
8447 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) |
8448 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(macchw, 0x0C, 0x05), |
8449 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), |
8450 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(macchws, 0x0C, 0x07), |
8451 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), |
8452 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), |
8453 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), |
8454 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), |
8455 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), |
8456 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(machhw, 0x0C, 0x01), |
8457 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), |
8458 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(machhws, 0x0C, 0x03), |
8459 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), |
8460 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), |
8461 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), |
8462 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), |
8463 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), |
8464 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), |
8465 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), |
8466 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), |
8467 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), |
8468 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), |
8469 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), |
8470 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), |
8471 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), |
8472 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), |
8473 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), |
8474 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), |
8475 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), |
8476 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), |
8477 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), |
8478 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), |
8479 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), |
8480 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), |
8481 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), |
8482 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), |
8483 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), |
8484 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(mulchw, 0x08, 0x05), |
8485 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), |
8486 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), |
8487 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), |
8488 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), |
8489 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), |
8490 | 5c55ff99 | Blue Swirl | |
8491 | 5c55ff99 | Blue Swirl | #undef GEN_VR_LDX
|
8492 | 5c55ff99 | Blue Swirl | #undef GEN_VR_STX
|
8493 | 5c55ff99 | Blue Swirl | #undef GEN_VR_LVE
|
8494 | 5c55ff99 | Blue Swirl | #undef GEN_VR_STVE
|
8495 | 5c55ff99 | Blue Swirl | #define GEN_VR_LDX(name, opc2, opc3) \
|
8496 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) |
8497 | 5c55ff99 | Blue Swirl | #define GEN_VR_STX(name, opc2, opc3) \
|
8498 | 5c55ff99 | Blue Swirl | GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) |
8499 | 5c55ff99 | Blue Swirl | #define GEN_VR_LVE(name, opc2, opc3) \
|
8500 | 5c55ff99 | Blue Swirl | GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) |
8501 | 5c55ff99 | Blue Swirl | #define GEN_VR_STVE(name, opc2, opc3) \
|
8502 | 5c55ff99 | Blue Swirl | GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) |
8503 | 5c55ff99 | Blue Swirl | GEN_VR_LDX(lvx, 0x07, 0x03), |
8504 | 5c55ff99 | Blue Swirl | GEN_VR_LDX(lvxl, 0x07, 0x0B), |
8505 | 5c55ff99 | Blue Swirl | GEN_VR_LVE(bx, 0x07, 0x00), |
8506 | 5c55ff99 | Blue Swirl | GEN_VR_LVE(hx, 0x07, 0x01), |
8507 | 5c55ff99 | Blue Swirl | GEN_VR_LVE(wx, 0x07, 0x02), |
8508 | 5c55ff99 | Blue Swirl | GEN_VR_STX(svx, 0x07, 0x07), |
8509 | 5c55ff99 | Blue Swirl | GEN_VR_STX(svxl, 0x07, 0x0F), |
8510 | 5c55ff99 | Blue Swirl | GEN_VR_STVE(bx, 0x07, 0x04), |
8511 | 5c55ff99 | Blue Swirl | GEN_VR_STVE(hx, 0x07, 0x05), |
8512 | 5c55ff99 | Blue Swirl | GEN_VR_STVE(wx, 0x07, 0x06), |
8513 | 5c55ff99 | Blue Swirl | |
8514 | 5c55ff99 | Blue Swirl | #undef GEN_VX_LOGICAL
|
8515 | 5c55ff99 | Blue Swirl | #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
|
8516 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) |
8517 | 5c55ff99 | Blue Swirl | GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16), |
8518 | 5c55ff99 | Blue Swirl | GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17), |
8519 | 5c55ff99 | Blue Swirl | GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18), |
8520 | 5c55ff99 | Blue Swirl | GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19), |
8521 | 5c55ff99 | Blue Swirl | GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20), |
8522 | 5c55ff99 | Blue Swirl | |
8523 | 5c55ff99 | Blue Swirl | #undef GEN_VXFORM
|
8524 | 5c55ff99 | Blue Swirl | #define GEN_VXFORM(name, opc2, opc3) \
|
8525 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) |
8526 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vaddubm, 0, 0), |
8527 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vadduhm, 0, 1), |
8528 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vadduwm, 0, 2), |
8529 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsububm, 0, 16), |
8530 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsubuhm, 0, 17), |
8531 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsubuwm, 0, 18), |
8532 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmaxub, 1, 0), |
8533 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmaxuh, 1, 1), |
8534 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmaxuw, 1, 2), |
8535 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmaxsb, 1, 4), |
8536 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmaxsh, 1, 5), |
8537 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmaxsw, 1, 6), |
8538 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vminub, 1, 8), |
8539 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vminuh, 1, 9), |
8540 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vminuw, 1, 10), |
8541 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vminsb, 1, 12), |
8542 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vminsh, 1, 13), |
8543 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vminsw, 1, 14), |
8544 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vavgub, 1, 16), |
8545 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vavguh, 1, 17), |
8546 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vavguw, 1, 18), |
8547 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vavgsb, 1, 20), |
8548 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vavgsh, 1, 21), |
8549 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vavgsw, 1, 22), |
8550 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmrghb, 6, 0), |
8551 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmrghh, 6, 1), |
8552 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmrghw, 6, 2), |
8553 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmrglb, 6, 4), |
8554 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmrglh, 6, 5), |
8555 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmrglw, 6, 6), |
8556 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmuloub, 4, 0), |
8557 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmulouh, 4, 1), |
8558 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmulosb, 4, 4), |
8559 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmulosh, 4, 5), |
8560 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmuleub, 4, 8), |
8561 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmuleuh, 4, 9), |
8562 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmulesb, 4, 12), |
8563 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmulesh, 4, 13), |
8564 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vslb, 2, 4), |
8565 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vslh, 2, 5), |
8566 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vslw, 2, 6), |
8567 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsrb, 2, 8), |
8568 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsrh, 2, 9), |
8569 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsrw, 2, 10), |
8570 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsrab, 2, 12), |
8571 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsrah, 2, 13), |
8572 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsraw, 2, 14), |
8573 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vslo, 6, 16), |
8574 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsro, 6, 17), |
8575 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vaddcuw, 0, 6), |
8576 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsubcuw, 0, 22), |
8577 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vaddubs, 0, 8), |
8578 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vadduhs, 0, 9), |
8579 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vadduws, 0, 10), |
8580 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vaddsbs, 0, 12), |
8581 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vaddshs, 0, 13), |
8582 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vaddsws, 0, 14), |
8583 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsububs, 0, 24), |
8584 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsubuhs, 0, 25), |
8585 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsubuws, 0, 26), |
8586 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsubsbs, 0, 28), |
8587 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsubshs, 0, 29), |
8588 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsubsws, 0, 30), |
8589 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vrlb, 2, 0), |
8590 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vrlh, 2, 1), |
8591 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vrlw, 2, 2), |
8592 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsl, 2, 7), |
8593 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsr, 2, 11), |
8594 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vpkuhum, 7, 0), |
8595 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vpkuwum, 7, 1), |
8596 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vpkuhus, 7, 2), |
8597 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vpkuwus, 7, 3), |
8598 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vpkshus, 7, 4), |
8599 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vpkswus, 7, 5), |
8600 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vpkshss, 7, 6), |
8601 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vpkswss, 7, 7), |
8602 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vpkpx, 7, 12), |
8603 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsum4ubs, 4, 24), |
8604 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsum4sbs, 4, 28), |
8605 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsum4shs, 4, 25), |
8606 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsum2sws, 4, 26), |
8607 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsumsws, 4, 30), |
8608 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vaddfp, 5, 0), |
8609 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsubfp, 5, 1), |
8610 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmaxfp, 5, 16), |
8611 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vminfp, 5, 17), |
8612 | 5c55ff99 | Blue Swirl | |
8613 | 5c55ff99 | Blue Swirl | #undef GEN_VXRFORM1
|
8614 | 5c55ff99 | Blue Swirl | #undef GEN_VXRFORM
|
8615 | 5c55ff99 | Blue Swirl | #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
|
8616 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC), |
8617 | 5c55ff99 | Blue Swirl | #define GEN_VXRFORM(name, opc2, opc3) \
|
8618 | 5c55ff99 | Blue Swirl | GEN_VXRFORM1(name, name, #name, opc2, opc3) \
|
8619 | 5c55ff99 | Blue Swirl | GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4))) |
8620 | 5c55ff99 | Blue Swirl | GEN_VXRFORM(vcmpequb, 3, 0) |
8621 | 5c55ff99 | Blue Swirl | GEN_VXRFORM(vcmpequh, 3, 1) |
8622 | 5c55ff99 | Blue Swirl | GEN_VXRFORM(vcmpequw, 3, 2) |
8623 | 5c55ff99 | Blue Swirl | GEN_VXRFORM(vcmpgtsb, 3, 12) |
8624 | 5c55ff99 | Blue Swirl | GEN_VXRFORM(vcmpgtsh, 3, 13) |
8625 | 5c55ff99 | Blue Swirl | GEN_VXRFORM(vcmpgtsw, 3, 14) |
8626 | 5c55ff99 | Blue Swirl | GEN_VXRFORM(vcmpgtub, 3, 8) |
8627 | 5c55ff99 | Blue Swirl | GEN_VXRFORM(vcmpgtuh, 3, 9) |
8628 | 5c55ff99 | Blue Swirl | GEN_VXRFORM(vcmpgtuw, 3, 10) |
8629 | 5c55ff99 | Blue Swirl | GEN_VXRFORM(vcmpeqfp, 3, 3) |
8630 | 5c55ff99 | Blue Swirl | GEN_VXRFORM(vcmpgefp, 3, 7) |
8631 | 5c55ff99 | Blue Swirl | GEN_VXRFORM(vcmpgtfp, 3, 11) |
8632 | 5c55ff99 | Blue Swirl | GEN_VXRFORM(vcmpbfp, 3, 15) |
8633 | 5c55ff99 | Blue Swirl | |
8634 | 5c55ff99 | Blue Swirl | #undef GEN_VXFORM_SIMM
|
8635 | 5c55ff99 | Blue Swirl | #define GEN_VXFORM_SIMM(name, opc2, opc3) \
|
8636 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) |
8637 | 5c55ff99 | Blue Swirl | GEN_VXFORM_SIMM(vspltisb, 6, 12), |
8638 | 5c55ff99 | Blue Swirl | GEN_VXFORM_SIMM(vspltish, 6, 13), |
8639 | 5c55ff99 | Blue Swirl | GEN_VXFORM_SIMM(vspltisw, 6, 14), |
8640 | 5c55ff99 | Blue Swirl | |
8641 | 5c55ff99 | Blue Swirl | #undef GEN_VXFORM_NOA
|
8642 | 5c55ff99 | Blue Swirl | #define GEN_VXFORM_NOA(name, opc2, opc3) \
|
8643 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC) |
8644 | 5c55ff99 | Blue Swirl | GEN_VXFORM_NOA(vupkhsb, 7, 8), |
8645 | 5c55ff99 | Blue Swirl | GEN_VXFORM_NOA(vupkhsh, 7, 9), |
8646 | 5c55ff99 | Blue Swirl | GEN_VXFORM_NOA(vupklsb, 7, 10), |
8647 | 5c55ff99 | Blue Swirl | GEN_VXFORM_NOA(vupklsh, 7, 11), |
8648 | 5c55ff99 | Blue Swirl | GEN_VXFORM_NOA(vupkhpx, 7, 13), |
8649 | 5c55ff99 | Blue Swirl | GEN_VXFORM_NOA(vupklpx, 7, 15), |
8650 | 5c55ff99 | Blue Swirl | GEN_VXFORM_NOA(vrefp, 5, 4), |
8651 | 5c55ff99 | Blue Swirl | GEN_VXFORM_NOA(vrsqrtefp, 5, 5), |
8652 | 5c55ff99 | Blue Swirl | GEN_VXFORM_NOA(vlogefp, 5, 7), |
8653 | 5c55ff99 | Blue Swirl | GEN_VXFORM_NOA(vrfim, 5, 8), |
8654 | 5c55ff99 | Blue Swirl | GEN_VXFORM_NOA(vrfin, 5, 9), |
8655 | 5c55ff99 | Blue Swirl | GEN_VXFORM_NOA(vrfip, 5, 10), |
8656 | 5c55ff99 | Blue Swirl | GEN_VXFORM_NOA(vrfiz, 5, 11), |
8657 | 5c55ff99 | Blue Swirl | |
8658 | 5c55ff99 | Blue Swirl | #undef GEN_VXFORM_UIMM
|
8659 | 5c55ff99 | Blue Swirl | #define GEN_VXFORM_UIMM(name, opc2, opc3) \
|
8660 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) |
8661 | 5c55ff99 | Blue Swirl | GEN_VXFORM_UIMM(vspltb, 6, 8), |
8662 | 5c55ff99 | Blue Swirl | GEN_VXFORM_UIMM(vsplth, 6, 9), |
8663 | 5c55ff99 | Blue Swirl | GEN_VXFORM_UIMM(vspltw, 6, 10), |
8664 | 5c55ff99 | Blue Swirl | GEN_VXFORM_UIMM(vcfux, 5, 12), |
8665 | 5c55ff99 | Blue Swirl | GEN_VXFORM_UIMM(vcfsx, 5, 13), |
8666 | 5c55ff99 | Blue Swirl | GEN_VXFORM_UIMM(vctuxs, 5, 14), |
8667 | 5c55ff99 | Blue Swirl | GEN_VXFORM_UIMM(vctsxs, 5, 15), |
8668 | 5c55ff99 | Blue Swirl | |
8669 | 5c55ff99 | Blue Swirl | #undef GEN_VAFORM_PAIRED
|
8670 | 5c55ff99 | Blue Swirl | #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
|
8671 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC) |
8672 | 5c55ff99 | Blue Swirl | GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
|
8673 | 5c55ff99 | Blue Swirl | GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
|
8674 | 5c55ff99 | Blue Swirl | GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
|
8675 | 5c55ff99 | Blue Swirl | GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
|
8676 | 5c55ff99 | Blue Swirl | GEN_VAFORM_PAIRED(vsel, vperm, 21),
|
8677 | 5c55ff99 | Blue Swirl | GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
|
8678 | 5c55ff99 | Blue Swirl | |
8679 | 5c55ff99 | Blue Swirl | #undef GEN_SPE
|
8680 | 5c55ff99 | Blue Swirl | #define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
|
8681 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) |
8682 | 5c55ff99 | Blue Swirl | GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE), |
8683 | 5c55ff99 | Blue Swirl | GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE), |
8684 | 5c55ff99 | Blue Swirl | GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE), |
8685 | 5c55ff99 | Blue Swirl | GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE), |
8686 | 5c55ff99 | Blue Swirl | GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE), |
8687 | 5c55ff99 | Blue Swirl | GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE), |
8688 | 5c55ff99 | Blue Swirl | GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE), |
8689 | 5c55ff99 | Blue Swirl | GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE), |
8690 | 5c55ff99 | Blue Swirl | GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE), |
8691 | 5c55ff99 | Blue Swirl | GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE), |
8692 | 5c55ff99 | Blue Swirl | GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE), |
8693 | 5c55ff99 | Blue Swirl | GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE), |
8694 | 5c55ff99 | Blue Swirl | GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE), |
8695 | 5c55ff99 | Blue Swirl | GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE), |
8696 | 5c55ff99 | Blue Swirl | GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE), |
8697 | 5c55ff99 | Blue Swirl | GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE), |
8698 | 5c55ff99 | Blue Swirl | GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE), |
8699 | 5c55ff99 | Blue Swirl | GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE), |
8700 | 5c55ff99 | Blue Swirl | GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE), |
8701 | 5c55ff99 | Blue Swirl | GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE), |
8702 | 5c55ff99 | Blue Swirl | GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE), |
8703 | 5c55ff99 | Blue Swirl | GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE), |
8704 | 5c55ff99 | Blue Swirl | GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE), |
8705 | 5c55ff99 | Blue Swirl | GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE), |
8706 | 5c55ff99 | Blue Swirl | GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE), |
8707 | 5c55ff99 | Blue Swirl | |
8708 | 5c55ff99 | Blue Swirl | GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPE_SINGLE), |
8709 | 5c55ff99 | Blue Swirl | GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPE_SINGLE), |
8710 | 5c55ff99 | Blue Swirl | GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPE_SINGLE), |
8711 | 5c55ff99 | Blue Swirl | GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPE_SINGLE), |
8712 | 5c55ff99 | Blue Swirl | GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPE_SINGLE), |
8713 | 5c55ff99 | Blue Swirl | GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPE_SINGLE), |
8714 | 5c55ff99 | Blue Swirl | GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPE_SINGLE), |
8715 | 5c55ff99 | Blue Swirl | GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPE_SINGLE), |
8716 | 5c55ff99 | Blue Swirl | GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPE_SINGLE), |
8717 | 5c55ff99 | Blue Swirl | GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPE_SINGLE), |
8718 | 5c55ff99 | Blue Swirl | GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPE_SINGLE), |
8719 | 5c55ff99 | Blue Swirl | GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPE_SINGLE), |
8720 | 5c55ff99 | Blue Swirl | GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPE_SINGLE), |
8721 | 5c55ff99 | Blue Swirl | GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPE_SINGLE), |
8722 | 5c55ff99 | Blue Swirl | |
8723 | 5c55ff99 | Blue Swirl | GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPE_SINGLE), |
8724 | 5c55ff99 | Blue Swirl | GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPE_SINGLE), |
8725 | 5c55ff99 | Blue Swirl | GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPE_SINGLE), |
8726 | 5c55ff99 | Blue Swirl | GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPE_SINGLE), |
8727 | 5c55ff99 | Blue Swirl | GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPE_SINGLE), |
8728 | 5c55ff99 | Blue Swirl | GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPE_SINGLE), |
8729 | 5c55ff99 | Blue Swirl | GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPE_SINGLE), |
8730 | 5c55ff99 | Blue Swirl | GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPE_SINGLE), |
8731 | 5c55ff99 | Blue Swirl | GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPE_SINGLE), |
8732 | 5c55ff99 | Blue Swirl | GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPE_SINGLE), |
8733 | 5c55ff99 | Blue Swirl | GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPE_SINGLE), |
8734 | 5c55ff99 | Blue Swirl | GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPE_SINGLE), |
8735 | 5c55ff99 | Blue Swirl | GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPE_SINGLE), |
8736 | 5c55ff99 | Blue Swirl | GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPE_SINGLE), |
8737 | 5c55ff99 | Blue Swirl | |
8738 | 5c55ff99 | Blue Swirl | GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPE_DOUBLE), |
8739 | 5c55ff99 | Blue Swirl | GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPE_DOUBLE), |
8740 | 5c55ff99 | Blue Swirl | GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPE_DOUBLE), |
8741 | 5c55ff99 | Blue Swirl | GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPE_DOUBLE), |
8742 | 5c55ff99 | Blue Swirl | GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPE_DOUBLE), |
8743 | 5c55ff99 | Blue Swirl | GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPE_DOUBLE), |
8744 | 5c55ff99 | Blue Swirl | GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPE_DOUBLE), |
8745 | 5c55ff99 | Blue Swirl | GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPE_DOUBLE), |
8746 | 5c55ff99 | Blue Swirl | GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPE_DOUBLE), |
8747 | 5c55ff99 | Blue Swirl | GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPE_DOUBLE), |
8748 | 5c55ff99 | Blue Swirl | GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPE_DOUBLE), |
8749 | 5c55ff99 | Blue Swirl | GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPE_DOUBLE), |
8750 | 5c55ff99 | Blue Swirl | GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPE_DOUBLE), |
8751 | 5c55ff99 | Blue Swirl | GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPE_DOUBLE), |
8752 | 5c55ff99 | Blue Swirl | GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPE_DOUBLE), |
8753 | 5c55ff99 | Blue Swirl | GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPE_DOUBLE), |
8754 | 5c55ff99 | Blue Swirl | |
8755 | 5c55ff99 | Blue Swirl | #undef GEN_SPEOP_LDST
|
8756 | 5c55ff99 | Blue Swirl | #define GEN_SPEOP_LDST(name, opc2, sh) \
|
8757 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE) |
8758 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evldd, 0x00, 3), |
8759 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evldw, 0x01, 3), |
8760 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evldh, 0x02, 3), |
8761 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evlhhesplat, 0x04, 1), |
8762 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evlhhousplat, 0x06, 1), |
8763 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evlhhossplat, 0x07, 1), |
8764 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evlwhe, 0x08, 2), |
8765 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evlwhou, 0x0A, 2), |
8766 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evlwhos, 0x0B, 2), |
8767 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2), |
8768 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2), |
8769 | 5c55ff99 | Blue Swirl | |
8770 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evstdd, 0x10, 3), |
8771 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evstdw, 0x11, 3), |
8772 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evstdh, 0x12, 3), |
8773 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evstwhe, 0x18, 2), |
8774 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evstwho, 0x1A, 2), |
8775 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evstwwe, 0x1C, 2), |
8776 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evstwwo, 0x1E, 2), |
8777 | 5c55ff99 | Blue Swirl | }; |
8778 | 5c55ff99 | Blue Swirl | |
8779 | 3fc6c082 | bellard | #include "translate_init.c" |
8780 | 0411a972 | j_mayer | #include "helper_regs.h" |
8781 | 79aceca5 | bellard | |
8782 | 9a64fbe4 | bellard | /*****************************************************************************/
|
8783 | 3fc6c082 | bellard | /* Misc PowerPC helpers */
|
8784 | 36081602 | j_mayer | void cpu_dump_state (CPUState *env, FILE *f,
|
8785 | 36081602 | j_mayer | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
8786 | 36081602 | j_mayer | int flags)
|
8787 | 79aceca5 | bellard | { |
8788 | 3fc6c082 | bellard | #define RGPL 4 |
8789 | 3fc6c082 | bellard | #define RFPL 4 |
8790 | 3fc6c082 | bellard | |
8791 | 79aceca5 | bellard | int i;
|
8792 | 79aceca5 | bellard | |
8793 | 077fc206 | j_mayer | cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " XER %08x\n", |
8794 | 3d7b417e | aurel32 | env->nip, env->lr, env->ctr, env->xer); |
8795 | 6b542af7 | j_mayer | cpu_fprintf(f, "MSR " ADDRX " HID0 " ADDRX " HF " ADDRX " idx %d\n", |
8796 | 6b542af7 | j_mayer | env->msr, env->spr[SPR_HID0], env->hflags, env->mmu_idx); |
8797 | d9bce9d9 | j_mayer | #if !defined(NO_TIMER_DUMP)
|
8798 | 077fc206 | j_mayer | cpu_fprintf(f, "TB %08x %08x "
|
8799 | 76a66253 | j_mayer | #if !defined(CONFIG_USER_ONLY)
|
8800 | 76a66253 | j_mayer | "DECR %08x"
|
8801 | 76a66253 | j_mayer | #endif
|
8802 | 76a66253 | j_mayer | "\n",
|
8803 | 077fc206 | j_mayer | cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) |
8804 | 76a66253 | j_mayer | #if !defined(CONFIG_USER_ONLY)
|
8805 | 76a66253 | j_mayer | , cpu_ppc_load_decr(env) |
8806 | 76a66253 | j_mayer | #endif
|
8807 | 76a66253 | j_mayer | ); |
8808 | 077fc206 | j_mayer | #endif
|
8809 | 76a66253 | j_mayer | for (i = 0; i < 32; i++) { |
8810 | 3fc6c082 | bellard | if ((i & (RGPL - 1)) == 0) |
8811 | 3fc6c082 | bellard | cpu_fprintf(f, "GPR%02d", i);
|
8812 | 6b542af7 | j_mayer | cpu_fprintf(f, " " REGX, ppc_dump_gpr(env, i));
|
8813 | 3fc6c082 | bellard | if ((i & (RGPL - 1)) == (RGPL - 1)) |
8814 | 7fe48483 | bellard | cpu_fprintf(f, "\n");
|
8815 | 76a66253 | j_mayer | } |
8816 | 3fc6c082 | bellard | cpu_fprintf(f, "CR ");
|
8817 | 76a66253 | j_mayer | for (i = 0; i < 8; i++) |
8818 | 7fe48483 | bellard | cpu_fprintf(f, "%01x", env->crf[i]);
|
8819 | 7fe48483 | bellard | cpu_fprintf(f, " [");
|
8820 | 76a66253 | j_mayer | for (i = 0; i < 8; i++) { |
8821 | 76a66253 | j_mayer | char a = '-'; |
8822 | 76a66253 | j_mayer | if (env->crf[i] & 0x08) |
8823 | 76a66253 | j_mayer | a = 'L';
|
8824 | 76a66253 | j_mayer | else if (env->crf[i] & 0x04) |
8825 | 76a66253 | j_mayer | a = 'G';
|
8826 | 76a66253 | j_mayer | else if (env->crf[i] & 0x02) |
8827 | 76a66253 | j_mayer | a = 'E';
|
8828 | 7fe48483 | bellard | cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); |
8829 | 76a66253 | j_mayer | } |
8830 | 6b542af7 | j_mayer | cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve); |
8831 | 3fc6c082 | bellard | for (i = 0; i < 32; i++) { |
8832 | 3fc6c082 | bellard | if ((i & (RFPL - 1)) == 0) |
8833 | 3fc6c082 | bellard | cpu_fprintf(f, "FPR%02d", i);
|
8834 | 26a76461 | bellard | cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
|
8835 | 3fc6c082 | bellard | if ((i & (RFPL - 1)) == (RFPL - 1)) |
8836 | 7fe48483 | bellard | cpu_fprintf(f, "\n");
|
8837 | 79aceca5 | bellard | } |
8838 | 7889270a | aurel32 | cpu_fprintf(f, "FPSCR %08x\n", env->fpscr);
|
8839 | f2e63a42 | j_mayer | #if !defined(CONFIG_USER_ONLY)
|
8840 | 6b542af7 | j_mayer | cpu_fprintf(f, "SRR0 " ADDRX " SRR1 " ADDRX " SDR1 " ADDRX "\n", |
8841 | 3fc6c082 | bellard | env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1); |
8842 | f2e63a42 | j_mayer | #endif
|
8843 | 79aceca5 | bellard | |
8844 | 3fc6c082 | bellard | #undef RGPL
|
8845 | 3fc6c082 | bellard | #undef RFPL
|
8846 | 79aceca5 | bellard | } |
8847 | 79aceca5 | bellard | |
8848 | 76a66253 | j_mayer | void cpu_dump_statistics (CPUState *env, FILE*f,
|
8849 | 76a66253 | j_mayer | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
8850 | 76a66253 | j_mayer | int flags)
|
8851 | 76a66253 | j_mayer | { |
8852 | 76a66253 | j_mayer | #if defined(DO_PPC_STATISTICS)
|
8853 | 76a66253 | j_mayer | opc_handler_t **t1, **t2, **t3, *handler; |
8854 | 76a66253 | j_mayer | int op1, op2, op3;
|
8855 | 76a66253 | j_mayer | |
8856 | 76a66253 | j_mayer | t1 = env->opcodes; |
8857 | 76a66253 | j_mayer | for (op1 = 0; op1 < 64; op1++) { |
8858 | 76a66253 | j_mayer | handler = t1[op1]; |
8859 | 76a66253 | j_mayer | if (is_indirect_opcode(handler)) {
|
8860 | 76a66253 | j_mayer | t2 = ind_table(handler); |
8861 | 76a66253 | j_mayer | for (op2 = 0; op2 < 32; op2++) { |
8862 | 76a66253 | j_mayer | handler = t2[op2]; |
8863 | 76a66253 | j_mayer | if (is_indirect_opcode(handler)) {
|
8864 | 76a66253 | j_mayer | t3 = ind_table(handler); |
8865 | 76a66253 | j_mayer | for (op3 = 0; op3 < 32; op3++) { |
8866 | 76a66253 | j_mayer | handler = t3[op3]; |
8867 | 76a66253 | j_mayer | if (handler->count == 0) |
8868 | 76a66253 | j_mayer | continue;
|
8869 | 76a66253 | j_mayer | cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
|
8870 | 76a66253 | j_mayer | "%016llx %lld\n",
|
8871 | 76a66253 | j_mayer | op1, op2, op3, op1, (op3 << 5) | op2,
|
8872 | 76a66253 | j_mayer | handler->oname, |
8873 | 76a66253 | j_mayer | handler->count, handler->count); |
8874 | 76a66253 | j_mayer | } |
8875 | 76a66253 | j_mayer | } else {
|
8876 | 76a66253 | j_mayer | if (handler->count == 0) |
8877 | 76a66253 | j_mayer | continue;
|
8878 | 76a66253 | j_mayer | cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
|
8879 | 76a66253 | j_mayer | "%016llx %lld\n",
|
8880 | 76a66253 | j_mayer | op1, op2, op1, op2, handler->oname, |
8881 | 76a66253 | j_mayer | handler->count, handler->count); |
8882 | 76a66253 | j_mayer | } |
8883 | 76a66253 | j_mayer | } |
8884 | 76a66253 | j_mayer | } else {
|
8885 | 76a66253 | j_mayer | if (handler->count == 0) |
8886 | 76a66253 | j_mayer | continue;
|
8887 | 76a66253 | j_mayer | cpu_fprintf(f, "%02x (%02x ) %16s: %016llx %lld\n",
|
8888 | 76a66253 | j_mayer | op1, op1, handler->oname, |
8889 | 76a66253 | j_mayer | handler->count, handler->count); |
8890 | 76a66253 | j_mayer | } |
8891 | 76a66253 | j_mayer | } |
8892 | 76a66253 | j_mayer | #endif
|
8893 | 76a66253 | j_mayer | } |
8894 | 76a66253 | j_mayer | |
8895 | 9a64fbe4 | bellard | /*****************************************************************************/
|
8896 | 2cfc5f17 | ths | static always_inline void gen_intermediate_code_internal (CPUState *env, |
8897 | 2cfc5f17 | ths | TranslationBlock *tb, |
8898 | 2cfc5f17 | ths | int search_pc)
|
8899 | 79aceca5 | bellard | { |
8900 | 9fddaa0c | bellard | DisasContext ctx, *ctxp = &ctx; |
8901 | 79aceca5 | bellard | opc_handler_t **table, *handler; |
8902 | 0fa85d43 | bellard | target_ulong pc_start; |
8903 | 79aceca5 | bellard | uint16_t *gen_opc_end; |
8904 | a1d1bb31 | aliguori | CPUBreakpoint *bp; |
8905 | 79aceca5 | bellard | int j, lj = -1; |
8906 | 2e70f6ef | pbrook | int num_insns;
|
8907 | 2e70f6ef | pbrook | int max_insns;
|
8908 | 79aceca5 | bellard | |
8909 | 79aceca5 | bellard | pc_start = tb->pc; |
8910 | 79aceca5 | bellard | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
8911 | 046d6672 | bellard | ctx.nip = pc_start; |
8912 | 79aceca5 | bellard | ctx.tb = tb; |
8913 | e1833e1f | j_mayer | ctx.exception = POWERPC_EXCP_NONE; |
8914 | 3fc6c082 | bellard | ctx.spr_cb = env->spr_cb; |
8915 | 76db3ba4 | aurel32 | ctx.mem_idx = env->mmu_idx; |
8916 | 76db3ba4 | aurel32 | ctx.access_type = -1;
|
8917 | 76db3ba4 | aurel32 | ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0; |
8918 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
8919 | d9bce9d9 | j_mayer | ctx.sf_mode = msr_sf; |
8920 | 9a64fbe4 | bellard | #endif
|
8921 | 3cc62370 | bellard | ctx.fpu_enabled = msr_fp; |
8922 | a9d9eb8f | j_mayer | if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
|
8923 | d26bfc9a | j_mayer | ctx.spe_enabled = msr_spe; |
8924 | d26bfc9a | j_mayer | else
|
8925 | d26bfc9a | j_mayer | ctx.spe_enabled = 0;
|
8926 | a9d9eb8f | j_mayer | if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
|
8927 | a9d9eb8f | j_mayer | ctx.altivec_enabled = msr_vr; |
8928 | a9d9eb8f | j_mayer | else
|
8929 | a9d9eb8f | j_mayer | ctx.altivec_enabled = 0;
|
8930 | d26bfc9a | j_mayer | if ((env->flags & POWERPC_FLAG_SE) && msr_se)
|
8931 | 8cbcb4fa | aurel32 | ctx.singlestep_enabled = CPU_SINGLE_STEP; |
8932 | d26bfc9a | j_mayer | else
|
8933 | 8cbcb4fa | aurel32 | ctx.singlestep_enabled = 0;
|
8934 | d26bfc9a | j_mayer | if ((env->flags & POWERPC_FLAG_BE) && msr_be)
|
8935 | 8cbcb4fa | aurel32 | ctx.singlestep_enabled |= CPU_BRANCH_STEP; |
8936 | 8cbcb4fa | aurel32 | if (unlikely(env->singlestep_enabled))
|
8937 | 8cbcb4fa | aurel32 | ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP; |
8938 | 3fc6c082 | bellard | #if defined (DO_SINGLE_STEP) && 0 |
8939 | 9a64fbe4 | bellard | /* Single step trace mode */
|
8940 | 9a64fbe4 | bellard | msr_se = 1;
|
8941 | 9a64fbe4 | bellard | #endif
|
8942 | 2e70f6ef | pbrook | num_insns = 0;
|
8943 | 2e70f6ef | pbrook | max_insns = tb->cflags & CF_COUNT_MASK; |
8944 | 2e70f6ef | pbrook | if (max_insns == 0) |
8945 | 2e70f6ef | pbrook | max_insns = CF_COUNT_MASK; |
8946 | 2e70f6ef | pbrook | |
8947 | 2e70f6ef | pbrook | gen_icount_start(); |
8948 | 9a64fbe4 | bellard | /* Set env in case of segfault during code fetch */
|
8949 | e1833e1f | j_mayer | while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
|
8950 | c0ce998e | aliguori | if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
|
8951 | c0ce998e | aliguori | TAILQ_FOREACH(bp, &env->breakpoints, entry) { |
8952 | a1d1bb31 | aliguori | if (bp->pc == ctx.nip) {
|
8953 | e06fcd75 | aurel32 | gen_debug_exception(ctxp); |
8954 | ea4e754f | bellard | break;
|
8955 | ea4e754f | bellard | } |
8956 | ea4e754f | bellard | } |
8957 | ea4e754f | bellard | } |
8958 | 76a66253 | j_mayer | if (unlikely(search_pc)) {
|
8959 | 79aceca5 | bellard | j = gen_opc_ptr - gen_opc_buf; |
8960 | 79aceca5 | bellard | if (lj < j) {
|
8961 | 79aceca5 | bellard | lj++; |
8962 | 79aceca5 | bellard | while (lj < j)
|
8963 | 79aceca5 | bellard | gen_opc_instr_start[lj++] = 0;
|
8964 | 79aceca5 | bellard | } |
8965 | af4b6c54 | aurel32 | gen_opc_pc[lj] = ctx.nip; |
8966 | af4b6c54 | aurel32 | gen_opc_instr_start[lj] = 1;
|
8967 | af4b6c54 | aurel32 | gen_opc_icount[lj] = num_insns; |
8968 | 79aceca5 | bellard | } |
8969 | d12d51d5 | aliguori | LOG_DISAS("----------------\n");
|
8970 | d12d51d5 | aliguori | LOG_DISAS("nip=" ADDRX " super=%d ir=%d\n", |
8971 | d12d51d5 | aliguori | ctx.nip, ctx.mem_idx, (int)msr_ir);
|
8972 | 2e70f6ef | pbrook | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
8973 | 2e70f6ef | pbrook | gen_io_start(); |
8974 | 76db3ba4 | aurel32 | if (unlikely(ctx.le_mode)) {
|
8975 | 056401ea | j_mayer | ctx.opcode = bswap32(ldl_code(ctx.nip)); |
8976 | 056401ea | j_mayer | } else {
|
8977 | 056401ea | j_mayer | ctx.opcode = ldl_code(ctx.nip); |
8978 | 111bfab3 | bellard | } |
8979 | d12d51d5 | aliguori | LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
|
8980 | 9a64fbe4 | bellard | ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode), |
8981 | 056401ea | j_mayer | opc3(ctx.opcode), little_endian ? "little" : "big"); |
8982 | 046d6672 | bellard | ctx.nip += 4;
|
8983 | 3fc6c082 | bellard | table = env->opcodes; |
8984 | 2e70f6ef | pbrook | num_insns++; |
8985 | 79aceca5 | bellard | handler = table[opc1(ctx.opcode)]; |
8986 | 79aceca5 | bellard | if (is_indirect_opcode(handler)) {
|
8987 | 79aceca5 | bellard | table = ind_table(handler); |
8988 | 79aceca5 | bellard | handler = table[opc2(ctx.opcode)]; |
8989 | 79aceca5 | bellard | if (is_indirect_opcode(handler)) {
|
8990 | 79aceca5 | bellard | table = ind_table(handler); |
8991 | 79aceca5 | bellard | handler = table[opc3(ctx.opcode)]; |
8992 | 79aceca5 | bellard | } |
8993 | 79aceca5 | bellard | } |
8994 | 79aceca5 | bellard | /* Is opcode *REALLY* valid ? */
|
8995 | 76a66253 | j_mayer | if (unlikely(handler->handler == &gen_invalid)) {
|
8996 | 93fcfe39 | aliguori | if (qemu_log_enabled()) {
|
8997 | 93fcfe39 | aliguori | qemu_log("invalid/unsupported opcode: "
|
8998 | 93fcfe39 | aliguori | "%02x - %02x - %02x (%08x) " ADDRX " %d\n", |
8999 | 93fcfe39 | aliguori | opc1(ctx.opcode), opc2(ctx.opcode), |
9000 | 93fcfe39 | aliguori | opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir); |
9001 | 4b3686fa | bellard | } else {
|
9002 | 4b3686fa | bellard | printf("invalid/unsupported opcode: "
|
9003 | 6b542af7 | j_mayer | "%02x - %02x - %02x (%08x) " ADDRX " %d\n", |
9004 | 4b3686fa | bellard | opc1(ctx.opcode), opc2(ctx.opcode), |
9005 | 0411a972 | j_mayer | opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir); |
9006 | 4b3686fa | bellard | } |
9007 | 76a66253 | j_mayer | } else {
|
9008 | 76a66253 | j_mayer | if (unlikely((ctx.opcode & handler->inval) != 0)) { |
9009 | 93fcfe39 | aliguori | if (qemu_log_enabled()) {
|
9010 | 93fcfe39 | aliguori | qemu_log("invalid bits: %08x for opcode: "
|
9011 | 93fcfe39 | aliguori | "%02x - %02x - %02x (%08x) " ADDRX "\n", |
9012 | 93fcfe39 | aliguori | ctx.opcode & handler->inval, opc1(ctx.opcode), |
9013 | 93fcfe39 | aliguori | opc2(ctx.opcode), opc3(ctx.opcode), |
9014 | 93fcfe39 | aliguori | ctx.opcode, ctx.nip - 4);
|
9015 | 9a64fbe4 | bellard | } else {
|
9016 | 9a64fbe4 | bellard | printf("invalid bits: %08x for opcode: "
|
9017 | 6b542af7 | j_mayer | "%02x - %02x - %02x (%08x) " ADDRX "\n", |
9018 | 76a66253 | j_mayer | ctx.opcode & handler->inval, opc1(ctx.opcode), |
9019 | 76a66253 | j_mayer | opc2(ctx.opcode), opc3(ctx.opcode), |
9020 | 046d6672 | bellard | ctx.opcode, ctx.nip - 4);
|
9021 | 76a66253 | j_mayer | } |
9022 | e06fcd75 | aurel32 | gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL); |
9023 | 4b3686fa | bellard | break;
|
9024 | 79aceca5 | bellard | } |
9025 | 79aceca5 | bellard | } |
9026 | 4b3686fa | bellard | (*(handler->handler))(&ctx); |
9027 | 76a66253 | j_mayer | #if defined(DO_PPC_STATISTICS)
|
9028 | 76a66253 | j_mayer | handler->count++; |
9029 | 76a66253 | j_mayer | #endif
|
9030 | 9a64fbe4 | bellard | /* Check trace mode exceptions */
|
9031 | 8cbcb4fa | aurel32 | if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
|
9032 | 8cbcb4fa | aurel32 | (ctx.nip <= 0x100 || ctx.nip > 0xF00) && |
9033 | 8cbcb4fa | aurel32 | ctx.exception != POWERPC_SYSCALL && |
9034 | 8cbcb4fa | aurel32 | ctx.exception != POWERPC_EXCP_TRAP && |
9035 | 8cbcb4fa | aurel32 | ctx.exception != POWERPC_EXCP_BRANCH)) { |
9036 | e06fcd75 | aurel32 | gen_exception(ctxp, POWERPC_EXCP_TRACE); |
9037 | d26bfc9a | j_mayer | } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) || |
9038 | 2e70f6ef | pbrook | (env->singlestep_enabled) || |
9039 | 1b530a6d | aurel32 | singlestep || |
9040 | 2e70f6ef | pbrook | num_insns >= max_insns)) { |
9041 | d26bfc9a | j_mayer | /* if we reach a page boundary or are single stepping, stop
|
9042 | d26bfc9a | j_mayer | * generation
|
9043 | d26bfc9a | j_mayer | */
|
9044 | 8dd4983c | bellard | break;
|
9045 | 76a66253 | j_mayer | } |
9046 | 3fc6c082 | bellard | } |
9047 | 2e70f6ef | pbrook | if (tb->cflags & CF_LAST_IO)
|
9048 | 2e70f6ef | pbrook | gen_io_end(); |
9049 | e1833e1f | j_mayer | if (ctx.exception == POWERPC_EXCP_NONE) {
|
9050 | c1942362 | bellard | gen_goto_tb(&ctx, 0, ctx.nip);
|
9051 | e1833e1f | j_mayer | } else if (ctx.exception != POWERPC_EXCP_BRANCH) { |
9052 | 8cbcb4fa | aurel32 | if (unlikely(env->singlestep_enabled)) {
|
9053 | e06fcd75 | aurel32 | gen_debug_exception(ctxp); |
9054 | 8cbcb4fa | aurel32 | } |
9055 | 76a66253 | j_mayer | /* Generate the return instruction */
|
9056 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
9057 | 9a64fbe4 | bellard | } |
9058 | 2e70f6ef | pbrook | gen_icount_end(tb, num_insns); |
9059 | 79aceca5 | bellard | *gen_opc_ptr = INDEX_op_end; |
9060 | 76a66253 | j_mayer | if (unlikely(search_pc)) {
|
9061 | 9a64fbe4 | bellard | j = gen_opc_ptr - gen_opc_buf; |
9062 | 9a64fbe4 | bellard | lj++; |
9063 | 9a64fbe4 | bellard | while (lj <= j)
|
9064 | 9a64fbe4 | bellard | gen_opc_instr_start[lj++] = 0;
|
9065 | 9a64fbe4 | bellard | } else {
|
9066 | 046d6672 | bellard | tb->size = ctx.nip - pc_start; |
9067 | 2e70f6ef | pbrook | tb->icount = num_insns; |
9068 | 9a64fbe4 | bellard | } |
9069 | d9bce9d9 | j_mayer | #if defined(DEBUG_DISAS)
|
9070 | 93fcfe39 | aliguori | qemu_log_mask(CPU_LOG_TB_CPU, "---------------- excp: %04x\n", ctx.exception);
|
9071 | 93fcfe39 | aliguori | log_cpu_state_mask(CPU_LOG_TB_CPU, env, 0);
|
9072 | 8fec2b8c | aliguori | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
|
9073 | 76a66253 | j_mayer | int flags;
|
9074 | 237c0af0 | j_mayer | flags = env->bfd_mach; |
9075 | 76db3ba4 | aurel32 | flags |= ctx.le_mode << 16;
|
9076 | 93fcfe39 | aliguori | qemu_log("IN: %s\n", lookup_symbol(pc_start));
|
9077 | 93fcfe39 | aliguori | log_target_disas(pc_start, ctx.nip - pc_start, flags); |
9078 | 93fcfe39 | aliguori | qemu_log("\n");
|
9079 | 9fddaa0c | bellard | } |
9080 | 79aceca5 | bellard | #endif
|
9081 | 79aceca5 | bellard | } |
9082 | 79aceca5 | bellard | |
9083 | 2cfc5f17 | ths | void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb) |
9084 | 79aceca5 | bellard | { |
9085 | 2cfc5f17 | ths | gen_intermediate_code_internal(env, tb, 0);
|
9086 | 79aceca5 | bellard | } |
9087 | 79aceca5 | bellard | |
9088 | 2cfc5f17 | ths | void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb) |
9089 | 79aceca5 | bellard | { |
9090 | 2cfc5f17 | ths | gen_intermediate_code_internal(env, tb, 1);
|
9091 | 79aceca5 | bellard | } |
9092 | d2856f1a | aurel32 | |
9093 | d2856f1a | aurel32 | void gen_pc_load(CPUState *env, TranslationBlock *tb,
|
9094 | d2856f1a | aurel32 | unsigned long searched_pc, int pc_pos, void *puc) |
9095 | d2856f1a | aurel32 | { |
9096 | d2856f1a | aurel32 | env->nip = gen_opc_pc[pc_pos]; |
9097 | d2856f1a | aurel32 | } |