target-arm: Log bad system register accesses with LOG_UNIMP
Log guest attempts to access unimplemented system registers viathe LOG_UNIMP reporting mechanism (for both the 32 bit and 64 bitinstruction sets). This is particularly useful for debuggingproblems where the guest is trying to use a system register that...
target-arm: Define names for SCTLR bits
The SCTLR is full of bits for enabling or disabling various things, and sothere are many places in the code which check if certain bits are set.Define some named constants for the SCTLR bits so these checks are easier...
target-arm: Restrict check_ap() use of S and R bits to v6 and earlier
The SCTLR bits S and R (8 and 9) only exist in ARMv6 and earlier.In ARMv7 these bits RAZ, and in ARMv8 they are reassigned. Guardthe use of them in check_ap() so that we don't get incorrect results...
target-arm: Remove unused ARMCPUState sr substruct
Remove the 'struct sr' from ARMCPUState -- it isn't actually used and isa hangover from the original separate system register implementation usedby the SuSE linux-user-mode-only AArch64 target.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
target-arm: A64: Implement floating point pairwise insns
Add support for the floating-point pairwise operationsFADDP, FMAXP, FMAXNMP, FMINP and FMINNMP. To do this we use thecode which was previously handling only integer pairwise operations,and push the integer-specific decode and handling of unallocated...
softfloat: Support halving the result of muladd operation
The ARMv8 instruction set includes a fused floating pointreciprocal square root step instruction which demands an"(x * y + z) / 2" fused operation. Support this by addinga flag to the softfloat muladd operations which requests...
target-arm: A64: Implement remaining 3-same instructions
Implement the remaining instructions in the SIMD 3-reg-sameand scalar-3-reg-same groups: FMULX, FRECPS, FRSQRTS, FACGE,FACGT, FMLA and FMLS.
target-arm/kvm-consts.h: Define QEMU constants for known KVM CPUs
Extend the set of CPUs for which we provide a QEMU_KVM_ARM_TARGET_*constant to include all the ones currently supported by the kernelheaders we are using.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: A64: Implement scalar three different instructions
Implement the scalar three different instruction group:it only has three instructions in it.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Richard Henderson <rth@twiddle.net>
target-arm: A64: Implement SIMD FP compare and set insns
This adds all forms of the SIMD floating point and set instructions:
FCM(GT|GE|EQ|LE|LT)
Most of the heavy lifting is done by either the existing neon helpers orsome new helpers for the 64bit double cases. Most of the code paths are...
View all revisions | View revisions
Also available in: Atom