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1 | 06a1cea5 | Peter Crosthwaite | /*
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2 | 06a1cea5 | Peter Crosthwaite | * ARM PrimeCell PL330 DMA Controller
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3 | 06a1cea5 | Peter Crosthwaite | *
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4 | 06a1cea5 | Peter Crosthwaite | * Copyright (c) 2009 Samsung Electronics.
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5 | 06a1cea5 | Peter Crosthwaite | * Contributed by Kirill Batuzov <batuzovk@ispras.ru>
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6 | 06a1cea5 | Peter Crosthwaite | * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com)
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7 | 06a1cea5 | Peter Crosthwaite | * Copyright (c) 2012 PetaLogix Pty Ltd.
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8 | 06a1cea5 | Peter Crosthwaite | *
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9 | 06a1cea5 | Peter Crosthwaite | * This program is free software; you can redistribute it and/or
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10 | 06a1cea5 | Peter Crosthwaite | * modify it under the terms of the GNU General Public License
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11 | 06a1cea5 | Peter Crosthwaite | * as published by the Free Software Foundation; version 2 or later.
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12 | 06a1cea5 | Peter Crosthwaite | *
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13 | 06a1cea5 | Peter Crosthwaite | * You should have received a copy of the GNU General Public License along
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14 | 06a1cea5 | Peter Crosthwaite | * with this program; if not, see <http://www.gnu.org/licenses/>.
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15 | 06a1cea5 | Peter Crosthwaite | */
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16 | 06a1cea5 | Peter Crosthwaite | |
17 | 0d09e41a | Paolo Bonzini | #include "hw/sysbus.h" |
18 | 06a1cea5 | Peter Crosthwaite | #include "qemu/timer.h" |
19 | 06a1cea5 | Peter Crosthwaite | #include "sysemu/dma.h" |
20 | 06a1cea5 | Peter Crosthwaite | |
21 | 06a1cea5 | Peter Crosthwaite | #ifndef PL330_ERR_DEBUG
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22 | 06a1cea5 | Peter Crosthwaite | #define PL330_ERR_DEBUG 0 |
23 | 06a1cea5 | Peter Crosthwaite | #endif
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24 | 06a1cea5 | Peter Crosthwaite | |
25 | 06a1cea5 | Peter Crosthwaite | #define DB_PRINT_L(lvl, fmt, args...) do {\ |
26 | 06a1cea5 | Peter Crosthwaite | if (PL330_ERR_DEBUG >= lvl) {\
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27 | 06a1cea5 | Peter Crosthwaite | fprintf(stderr, "PL330: %s:" fmt, __func__, ## args);\ |
28 | 06a1cea5 | Peter Crosthwaite | } \ |
29 | 06a1cea5 | Peter Crosthwaite | } while (0); |
30 | 06a1cea5 | Peter Crosthwaite | |
31 | 06a1cea5 | Peter Crosthwaite | #define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) |
32 | 06a1cea5 | Peter Crosthwaite | |
33 | 06a1cea5 | Peter Crosthwaite | #define PL330_PERIPH_NUM 32 |
34 | 06a1cea5 | Peter Crosthwaite | #define PL330_MAX_BURST_LEN 128 |
35 | 06a1cea5 | Peter Crosthwaite | #define PL330_INSN_MAXSIZE 6 |
36 | 06a1cea5 | Peter Crosthwaite | |
37 | 06a1cea5 | Peter Crosthwaite | #define PL330_FIFO_OK 0 |
38 | 06a1cea5 | Peter Crosthwaite | #define PL330_FIFO_STALL 1 |
39 | 06a1cea5 | Peter Crosthwaite | #define PL330_FIFO_ERR (-1) |
40 | 06a1cea5 | Peter Crosthwaite | |
41 | 06a1cea5 | Peter Crosthwaite | #define PL330_FAULT_UNDEF_INSTR (1 << 0) |
42 | 06a1cea5 | Peter Crosthwaite | #define PL330_FAULT_OPERAND_INVALID (1 << 1) |
43 | 06a1cea5 | Peter Crosthwaite | #define PL330_FAULT_DMAGO_ERR (1 << 4) |
44 | 06a1cea5 | Peter Crosthwaite | #define PL330_FAULT_EVENT_ERR (1 << 5) |
45 | 06a1cea5 | Peter Crosthwaite | #define PL330_FAULT_CH_PERIPH_ERR (1 << 6) |
46 | 06a1cea5 | Peter Crosthwaite | #define PL330_FAULT_CH_RDWR_ERR (1 << 7) |
47 | 06a1cea5 | Peter Crosthwaite | #define PL330_FAULT_ST_DATA_UNAVAILABLE (1 << 12) |
48 | 06a1cea5 | Peter Crosthwaite | #define PL330_FAULT_FIFOEMPTY_ERR (1 << 13) |
49 | 06a1cea5 | Peter Crosthwaite | #define PL330_FAULT_INSTR_FETCH_ERR (1 << 16) |
50 | 06a1cea5 | Peter Crosthwaite | #define PL330_FAULT_DATA_WRITE_ERR (1 << 17) |
51 | 06a1cea5 | Peter Crosthwaite | #define PL330_FAULT_DATA_READ_ERR (1 << 18) |
52 | 06a1cea5 | Peter Crosthwaite | #define PL330_FAULT_DBG_INSTR (1 << 30) |
53 | 06a1cea5 | Peter Crosthwaite | #define PL330_FAULT_LOCKUP_ERR (1 << 31) |
54 | 06a1cea5 | Peter Crosthwaite | |
55 | 06a1cea5 | Peter Crosthwaite | #define PL330_UNTAGGED 0xff |
56 | 06a1cea5 | Peter Crosthwaite | |
57 | 06a1cea5 | Peter Crosthwaite | #define PL330_SINGLE 0x0 |
58 | 06a1cea5 | Peter Crosthwaite | #define PL330_BURST 0x1 |
59 | 06a1cea5 | Peter Crosthwaite | |
60 | 06a1cea5 | Peter Crosthwaite | #define PL330_WATCHDOG_LIMIT 1024 |
61 | 06a1cea5 | Peter Crosthwaite | |
62 | 06a1cea5 | Peter Crosthwaite | /* IOMEM mapped registers */
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63 | 06a1cea5 | Peter Crosthwaite | #define PL330_REG_DSR 0x000 |
64 | 06a1cea5 | Peter Crosthwaite | #define PL330_REG_DPC 0x004 |
65 | 06a1cea5 | Peter Crosthwaite | #define PL330_REG_INTEN 0x020 |
66 | 06a1cea5 | Peter Crosthwaite | #define PL330_REG_INT_EVENT_RIS 0x024 |
67 | 06a1cea5 | Peter Crosthwaite | #define PL330_REG_INTMIS 0x028 |
68 | 06a1cea5 | Peter Crosthwaite | #define PL330_REG_INTCLR 0x02C |
69 | 06a1cea5 | Peter Crosthwaite | #define PL330_REG_FSRD 0x030 |
70 | 06a1cea5 | Peter Crosthwaite | #define PL330_REG_FSRC 0x034 |
71 | 06a1cea5 | Peter Crosthwaite | #define PL330_REG_FTRD 0x038 |
72 | 06a1cea5 | Peter Crosthwaite | #define PL330_REG_FTR_BASE 0x040 |
73 | 06a1cea5 | Peter Crosthwaite | #define PL330_REG_CSR_BASE 0x100 |
74 | 06a1cea5 | Peter Crosthwaite | #define PL330_REG_CPC_BASE 0x104 |
75 | 06a1cea5 | Peter Crosthwaite | #define PL330_REG_CHANCTRL 0x400 |
76 | 06a1cea5 | Peter Crosthwaite | #define PL330_REG_DBGSTATUS 0xD00 |
77 | 06a1cea5 | Peter Crosthwaite | #define PL330_REG_DBGCMD 0xD04 |
78 | 06a1cea5 | Peter Crosthwaite | #define PL330_REG_DBGINST0 0xD08 |
79 | 06a1cea5 | Peter Crosthwaite | #define PL330_REG_DBGINST1 0xD0C |
80 | 06a1cea5 | Peter Crosthwaite | #define PL330_REG_CR0_BASE 0xE00 |
81 | 06a1cea5 | Peter Crosthwaite | #define PL330_REG_PERIPH_ID 0xFE0 |
82 | 06a1cea5 | Peter Crosthwaite | |
83 | 06a1cea5 | Peter Crosthwaite | #define PL330_IOMEM_SIZE 0x1000 |
84 | 06a1cea5 | Peter Crosthwaite | |
85 | 06a1cea5 | Peter Crosthwaite | #define CFG_BOOT_ADDR 2 |
86 | 06a1cea5 | Peter Crosthwaite | #define CFG_INS 3 |
87 | 06a1cea5 | Peter Crosthwaite | #define CFG_PNS 4 |
88 | 06a1cea5 | Peter Crosthwaite | #define CFG_CRD 5 |
89 | 06a1cea5 | Peter Crosthwaite | |
90 | 06a1cea5 | Peter Crosthwaite | static const uint32_t pl330_id[] = { |
91 | 06a1cea5 | Peter Crosthwaite | 0x30, 0x13, 0x24, 0x00, 0x0D, 0xF0, 0x05, 0xB1 |
92 | 06a1cea5 | Peter Crosthwaite | }; |
93 | 06a1cea5 | Peter Crosthwaite | |
94 | 06a1cea5 | Peter Crosthwaite | /* DMA channel states as they are described in PL330 Technical Reference Manual
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95 | 06a1cea5 | Peter Crosthwaite | * Most of them will not be used in emulation.
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96 | 06a1cea5 | Peter Crosthwaite | */
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97 | 06a1cea5 | Peter Crosthwaite | typedef enum { |
98 | 06a1cea5 | Peter Crosthwaite | pl330_chan_stopped = 0,
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99 | 06a1cea5 | Peter Crosthwaite | pl330_chan_executing = 1,
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100 | 06a1cea5 | Peter Crosthwaite | pl330_chan_cache_miss = 2,
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101 | 06a1cea5 | Peter Crosthwaite | pl330_chan_updating_pc = 3,
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102 | 06a1cea5 | Peter Crosthwaite | pl330_chan_waiting_event = 4,
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103 | 06a1cea5 | Peter Crosthwaite | pl330_chan_at_barrier = 5,
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104 | 06a1cea5 | Peter Crosthwaite | pl330_chan_queue_busy = 6,
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105 | 06a1cea5 | Peter Crosthwaite | pl330_chan_waiting_periph = 7,
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106 | 06a1cea5 | Peter Crosthwaite | pl330_chan_killing = 8,
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107 | 06a1cea5 | Peter Crosthwaite | pl330_chan_completing = 9,
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108 | 06a1cea5 | Peter Crosthwaite | pl330_chan_fault_completing = 14,
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109 | 06a1cea5 | Peter Crosthwaite | pl330_chan_fault = 15,
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110 | 06a1cea5 | Peter Crosthwaite | } PL330ChanState; |
111 | 06a1cea5 | Peter Crosthwaite | |
112 | 06a1cea5 | Peter Crosthwaite | typedef struct PL330State PL330State; |
113 | 06a1cea5 | Peter Crosthwaite | |
114 | 06a1cea5 | Peter Crosthwaite | typedef struct PL330Chan { |
115 | 06a1cea5 | Peter Crosthwaite | uint32_t src; |
116 | 06a1cea5 | Peter Crosthwaite | uint32_t dst; |
117 | 06a1cea5 | Peter Crosthwaite | uint32_t pc; |
118 | 06a1cea5 | Peter Crosthwaite | uint32_t control; |
119 | 06a1cea5 | Peter Crosthwaite | uint32_t status; |
120 | 06a1cea5 | Peter Crosthwaite | uint32_t lc[2];
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121 | 06a1cea5 | Peter Crosthwaite | uint32_t fault_type; |
122 | 06a1cea5 | Peter Crosthwaite | uint32_t watchdog_timer; |
123 | 06a1cea5 | Peter Crosthwaite | |
124 | 06a1cea5 | Peter Crosthwaite | bool ns;
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125 | 06a1cea5 | Peter Crosthwaite | uint8_t request_flag; |
126 | 06a1cea5 | Peter Crosthwaite | uint8_t wakeup; |
127 | 06a1cea5 | Peter Crosthwaite | uint8_t wfp_sbp; |
128 | 06a1cea5 | Peter Crosthwaite | |
129 | 06a1cea5 | Peter Crosthwaite | uint8_t state; |
130 | 06a1cea5 | Peter Crosthwaite | uint8_t stall; |
131 | 06a1cea5 | Peter Crosthwaite | |
132 | 06a1cea5 | Peter Crosthwaite | bool is_manager;
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133 | 06a1cea5 | Peter Crosthwaite | PL330State *parent; |
134 | 06a1cea5 | Peter Crosthwaite | uint8_t tag; |
135 | 06a1cea5 | Peter Crosthwaite | } PL330Chan; |
136 | 06a1cea5 | Peter Crosthwaite | |
137 | 06a1cea5 | Peter Crosthwaite | static const VMStateDescription vmstate_pl330_chan = { |
138 | 06a1cea5 | Peter Crosthwaite | .name = "pl330_chan",
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139 | 06a1cea5 | Peter Crosthwaite | .version_id = 1,
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140 | 06a1cea5 | Peter Crosthwaite | .minimum_version_id = 1,
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141 | 06a1cea5 | Peter Crosthwaite | .minimum_version_id_old = 1,
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142 | 06a1cea5 | Peter Crosthwaite | .fields = (VMStateField[]) { |
143 | 06a1cea5 | Peter Crosthwaite | VMSTATE_UINT32(src, PL330Chan), |
144 | 06a1cea5 | Peter Crosthwaite | VMSTATE_UINT32(dst, PL330Chan), |
145 | 06a1cea5 | Peter Crosthwaite | VMSTATE_UINT32(pc, PL330Chan), |
146 | 06a1cea5 | Peter Crosthwaite | VMSTATE_UINT32(control, PL330Chan), |
147 | 06a1cea5 | Peter Crosthwaite | VMSTATE_UINT32(status, PL330Chan), |
148 | 06a1cea5 | Peter Crosthwaite | VMSTATE_UINT32_ARRAY(lc, PL330Chan, 2),
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149 | 06a1cea5 | Peter Crosthwaite | VMSTATE_UINT32(fault_type, PL330Chan), |
150 | 06a1cea5 | Peter Crosthwaite | VMSTATE_UINT32(watchdog_timer, PL330Chan), |
151 | 06a1cea5 | Peter Crosthwaite | VMSTATE_BOOL(ns, PL330Chan), |
152 | 06a1cea5 | Peter Crosthwaite | VMSTATE_UINT8(request_flag, PL330Chan), |
153 | 06a1cea5 | Peter Crosthwaite | VMSTATE_UINT8(wakeup, PL330Chan), |
154 | 06a1cea5 | Peter Crosthwaite | VMSTATE_UINT8(wfp_sbp, PL330Chan), |
155 | 06a1cea5 | Peter Crosthwaite | VMSTATE_UINT8(state, PL330Chan), |
156 | 06a1cea5 | Peter Crosthwaite | VMSTATE_UINT8(stall, PL330Chan), |
157 | 06a1cea5 | Peter Crosthwaite | VMSTATE_END_OF_LIST() |
158 | 06a1cea5 | Peter Crosthwaite | } |
159 | 06a1cea5 | Peter Crosthwaite | }; |
160 | 06a1cea5 | Peter Crosthwaite | |
161 | 06a1cea5 | Peter Crosthwaite | typedef struct PL330Fifo { |
162 | 06a1cea5 | Peter Crosthwaite | uint8_t *buf; |
163 | 06a1cea5 | Peter Crosthwaite | uint8_t *tag; |
164 | 06a1cea5 | Peter Crosthwaite | uint32_t head; |
165 | 06a1cea5 | Peter Crosthwaite | uint32_t num; |
166 | 06a1cea5 | Peter Crosthwaite | uint32_t buf_size; |
167 | 06a1cea5 | Peter Crosthwaite | } PL330Fifo; |
168 | 06a1cea5 | Peter Crosthwaite | |
169 | 06a1cea5 | Peter Crosthwaite | static const VMStateDescription vmstate_pl330_fifo = { |
170 | 06a1cea5 | Peter Crosthwaite | .name = "pl330_chan",
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171 | 06a1cea5 | Peter Crosthwaite | .version_id = 1,
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172 | 06a1cea5 | Peter Crosthwaite | .minimum_version_id = 1,
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173 | 06a1cea5 | Peter Crosthwaite | .minimum_version_id_old = 1,
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174 | 06a1cea5 | Peter Crosthwaite | .fields = (VMStateField[]) { |
175 | 06a1cea5 | Peter Crosthwaite | VMSTATE_VBUFFER_UINT32(buf, PL330Fifo, 1, NULL, 0, buf_size), |
176 | 06a1cea5 | Peter Crosthwaite | VMSTATE_VBUFFER_UINT32(tag, PL330Fifo, 1, NULL, 0, buf_size), |
177 | 06a1cea5 | Peter Crosthwaite | VMSTATE_UINT32(head, PL330Fifo), |
178 | 06a1cea5 | Peter Crosthwaite | VMSTATE_UINT32(num, PL330Fifo), |
179 | 06a1cea5 | Peter Crosthwaite | VMSTATE_UINT32(buf_size, PL330Fifo), |
180 | 06a1cea5 | Peter Crosthwaite | VMSTATE_END_OF_LIST() |
181 | 06a1cea5 | Peter Crosthwaite | } |
182 | 06a1cea5 | Peter Crosthwaite | }; |
183 | 06a1cea5 | Peter Crosthwaite | |
184 | 06a1cea5 | Peter Crosthwaite | typedef struct PL330QueueEntry { |
185 | 06a1cea5 | Peter Crosthwaite | uint32_t addr; |
186 | 06a1cea5 | Peter Crosthwaite | uint32_t len; |
187 | 06a1cea5 | Peter Crosthwaite | uint8_t n; |
188 | 06a1cea5 | Peter Crosthwaite | bool inc;
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189 | 06a1cea5 | Peter Crosthwaite | bool z;
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190 | 06a1cea5 | Peter Crosthwaite | uint8_t tag; |
191 | 06a1cea5 | Peter Crosthwaite | uint8_t seqn; |
192 | 06a1cea5 | Peter Crosthwaite | } PL330QueueEntry; |
193 | 06a1cea5 | Peter Crosthwaite | |
194 | 06a1cea5 | Peter Crosthwaite | static const VMStateDescription vmstate_pl330_queue_entry = { |
195 | 06a1cea5 | Peter Crosthwaite | .name = "pl330_queue_entry",
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196 | 06a1cea5 | Peter Crosthwaite | .version_id = 1,
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197 | 06a1cea5 | Peter Crosthwaite | .minimum_version_id = 1,
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198 | 06a1cea5 | Peter Crosthwaite | .minimum_version_id_old = 1,
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199 | 06a1cea5 | Peter Crosthwaite | .fields = (VMStateField[]) { |
200 | 06a1cea5 | Peter Crosthwaite | VMSTATE_UINT32(addr, PL330QueueEntry), |
201 | 06a1cea5 | Peter Crosthwaite | VMSTATE_UINT32(len, PL330QueueEntry), |
202 | 06a1cea5 | Peter Crosthwaite | VMSTATE_UINT8(n, PL330QueueEntry), |
203 | 06a1cea5 | Peter Crosthwaite | VMSTATE_BOOL(inc, PL330QueueEntry), |
204 | 06a1cea5 | Peter Crosthwaite | VMSTATE_BOOL(z, PL330QueueEntry), |
205 | 06a1cea5 | Peter Crosthwaite | VMSTATE_UINT8(tag, PL330QueueEntry), |
206 | 06a1cea5 | Peter Crosthwaite | VMSTATE_UINT8(seqn, PL330QueueEntry), |
207 | 06a1cea5 | Peter Crosthwaite | VMSTATE_END_OF_LIST() |
208 | 06a1cea5 | Peter Crosthwaite | } |
209 | 06a1cea5 | Peter Crosthwaite | }; |
210 | 06a1cea5 | Peter Crosthwaite | |
211 | 06a1cea5 | Peter Crosthwaite | typedef struct PL330Queue { |
212 | 06a1cea5 | Peter Crosthwaite | PL330State *parent; |
213 | 06a1cea5 | Peter Crosthwaite | PL330QueueEntry *queue; |
214 | 06a1cea5 | Peter Crosthwaite | uint32_t queue_size; |
215 | 06a1cea5 | Peter Crosthwaite | } PL330Queue; |
216 | 06a1cea5 | Peter Crosthwaite | |
217 | 06a1cea5 | Peter Crosthwaite | static const VMStateDescription vmstate_pl330_queue = { |
218 | 06a1cea5 | Peter Crosthwaite | .name = "pl330_queue",
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219 | 06a1cea5 | Peter Crosthwaite | .version_id = 1,
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220 | 06a1cea5 | Peter Crosthwaite | .minimum_version_id = 1,
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221 | 06a1cea5 | Peter Crosthwaite | .minimum_version_id_old = 1,
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222 | 06a1cea5 | Peter Crosthwaite | .fields = (VMStateField[]) { |
223 | 06a1cea5 | Peter Crosthwaite | VMSTATE_STRUCT_VARRAY_UINT32(queue, PL330Queue, queue_size, 1,
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224 | 06a1cea5 | Peter Crosthwaite | vmstate_pl330_queue_entry, PL330QueueEntry), |
225 | 06a1cea5 | Peter Crosthwaite | VMSTATE_END_OF_LIST() |
226 | 06a1cea5 | Peter Crosthwaite | } |
227 | 06a1cea5 | Peter Crosthwaite | }; |
228 | 06a1cea5 | Peter Crosthwaite | |
229 | 06a1cea5 | Peter Crosthwaite | struct PL330State {
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230 | 06a1cea5 | Peter Crosthwaite | SysBusDevice busdev; |
231 | 06a1cea5 | Peter Crosthwaite | MemoryRegion iomem; |
232 | 06a1cea5 | Peter Crosthwaite | qemu_irq irq_abort; |
233 | 06a1cea5 | Peter Crosthwaite | qemu_irq *irq; |
234 | 06a1cea5 | Peter Crosthwaite | |
235 | 06a1cea5 | Peter Crosthwaite | /* Config registers. cfg[5] = CfgDn. */
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236 | 06a1cea5 | Peter Crosthwaite | uint32_t cfg[6];
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237 | 06a1cea5 | Peter Crosthwaite | #define EVENT_SEC_STATE 3 |
238 | 06a1cea5 | Peter Crosthwaite | #define PERIPH_SEC_STATE 4 |
239 | 06a1cea5 | Peter Crosthwaite | /* cfg 0 bits and pieces */
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240 | 06a1cea5 | Peter Crosthwaite | uint32_t num_chnls; |
241 | 06a1cea5 | Peter Crosthwaite | uint8_t num_periph_req; |
242 | 06a1cea5 | Peter Crosthwaite | uint8_t num_events; |
243 | 06a1cea5 | Peter Crosthwaite | uint8_t mgr_ns_at_rst; |
244 | 06a1cea5 | Peter Crosthwaite | /* cfg 1 bits and pieces */
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245 | 06a1cea5 | Peter Crosthwaite | uint8_t i_cache_len; |
246 | 06a1cea5 | Peter Crosthwaite | uint8_t num_i_cache_lines; |
247 | 06a1cea5 | Peter Crosthwaite | /* CRD bits and pieces */
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248 | 06a1cea5 | Peter Crosthwaite | uint8_t data_width; |
249 | 06a1cea5 | Peter Crosthwaite | uint8_t wr_cap; |
250 | 06a1cea5 | Peter Crosthwaite | uint8_t wr_q_dep; |
251 | 06a1cea5 | Peter Crosthwaite | uint8_t rd_cap; |
252 | 06a1cea5 | Peter Crosthwaite | uint8_t rd_q_dep; |
253 | 06a1cea5 | Peter Crosthwaite | uint16_t data_buffer_dep; |
254 | 06a1cea5 | Peter Crosthwaite | |
255 | 06a1cea5 | Peter Crosthwaite | PL330Chan manager; |
256 | 06a1cea5 | Peter Crosthwaite | PL330Chan *chan; |
257 | 06a1cea5 | Peter Crosthwaite | PL330Fifo fifo; |
258 | 06a1cea5 | Peter Crosthwaite | PL330Queue read_queue; |
259 | 06a1cea5 | Peter Crosthwaite | PL330Queue write_queue; |
260 | 06a1cea5 | Peter Crosthwaite | uint8_t *lo_seqn; |
261 | 06a1cea5 | Peter Crosthwaite | uint8_t *hi_seqn; |
262 | 06a1cea5 | Peter Crosthwaite | QEMUTimer *timer; /* is used for restore dma. */
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263 | 06a1cea5 | Peter Crosthwaite | |
264 | 06a1cea5 | Peter Crosthwaite | uint32_t inten; |
265 | 06a1cea5 | Peter Crosthwaite | uint32_t int_status; |
266 | 06a1cea5 | Peter Crosthwaite | uint32_t ev_status; |
267 | 06a1cea5 | Peter Crosthwaite | uint32_t dbg[2];
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268 | 06a1cea5 | Peter Crosthwaite | uint8_t debug_status; |
269 | 06a1cea5 | Peter Crosthwaite | uint8_t num_faulting; |
270 | 06a1cea5 | Peter Crosthwaite | uint8_t periph_busy[PL330_PERIPH_NUM]; |
271 | 06a1cea5 | Peter Crosthwaite | |
272 | 06a1cea5 | Peter Crosthwaite | }; |
273 | 06a1cea5 | Peter Crosthwaite | |
274 | 06a1cea5 | Peter Crosthwaite | #define TYPE_PL330 "pl330" |
275 | 06a1cea5 | Peter Crosthwaite | #define PL330(obj) OBJECT_CHECK(PL330State, (obj), TYPE_PL330)
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276 | 06a1cea5 | Peter Crosthwaite | |
277 | 06a1cea5 | Peter Crosthwaite | static const VMStateDescription vmstate_pl330 = { |
278 | 06a1cea5 | Peter Crosthwaite | .name = "pl330",
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279 | 06a1cea5 | Peter Crosthwaite | .version_id = 1,
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280 | 06a1cea5 | Peter Crosthwaite | .minimum_version_id = 1,
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281 | 06a1cea5 | Peter Crosthwaite | .minimum_version_id_old = 1,
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282 | 06a1cea5 | Peter Crosthwaite | .fields = (VMStateField[]) { |
283 | 06a1cea5 | Peter Crosthwaite | VMSTATE_STRUCT(manager, PL330State, 0, vmstate_pl330_chan, PL330Chan),
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284 | 06a1cea5 | Peter Crosthwaite | VMSTATE_STRUCT_VARRAY_UINT32(chan, PL330State, num_chnls, 0,
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285 | 06a1cea5 | Peter Crosthwaite | vmstate_pl330_chan, PL330Chan), |
286 | 06a1cea5 | Peter Crosthwaite | VMSTATE_VBUFFER_UINT32(lo_seqn, PL330State, 1, NULL, 0, num_chnls), |
287 | 06a1cea5 | Peter Crosthwaite | VMSTATE_VBUFFER_UINT32(hi_seqn, PL330State, 1, NULL, 0, num_chnls), |
288 | 06a1cea5 | Peter Crosthwaite | VMSTATE_STRUCT(fifo, PL330State, 0, vmstate_pl330_fifo, PL330Fifo),
|
289 | 06a1cea5 | Peter Crosthwaite | VMSTATE_STRUCT(read_queue, PL330State, 0, vmstate_pl330_queue,
|
290 | 06a1cea5 | Peter Crosthwaite | PL330Queue), |
291 | 06a1cea5 | Peter Crosthwaite | VMSTATE_STRUCT(write_queue, PL330State, 0, vmstate_pl330_queue,
|
292 | 06a1cea5 | Peter Crosthwaite | PL330Queue), |
293 | 06a1cea5 | Peter Crosthwaite | VMSTATE_TIMER(timer, PL330State), |
294 | 06a1cea5 | Peter Crosthwaite | VMSTATE_UINT32(inten, PL330State), |
295 | 06a1cea5 | Peter Crosthwaite | VMSTATE_UINT32(int_status, PL330State), |
296 | 06a1cea5 | Peter Crosthwaite | VMSTATE_UINT32(ev_status, PL330State), |
297 | 06a1cea5 | Peter Crosthwaite | VMSTATE_UINT32_ARRAY(dbg, PL330State, 2),
|
298 | 06a1cea5 | Peter Crosthwaite | VMSTATE_UINT8(debug_status, PL330State), |
299 | 06a1cea5 | Peter Crosthwaite | VMSTATE_UINT8(num_faulting, PL330State), |
300 | 06a1cea5 | Peter Crosthwaite | VMSTATE_UINT8_ARRAY(periph_busy, PL330State, PL330_PERIPH_NUM), |
301 | 06a1cea5 | Peter Crosthwaite | VMSTATE_END_OF_LIST() |
302 | 06a1cea5 | Peter Crosthwaite | } |
303 | 06a1cea5 | Peter Crosthwaite | }; |
304 | 06a1cea5 | Peter Crosthwaite | |
305 | 06a1cea5 | Peter Crosthwaite | typedef struct PL330InsnDesc { |
306 | 06a1cea5 | Peter Crosthwaite | /* OPCODE of the instruction */
|
307 | 06a1cea5 | Peter Crosthwaite | uint8_t opcode; |
308 | 06a1cea5 | Peter Crosthwaite | /* Mask so we can select several sibling instructions, such as
|
309 | 06a1cea5 | Peter Crosthwaite | DMALD, DMALDS and DMALDB */
|
310 | 06a1cea5 | Peter Crosthwaite | uint8_t opmask; |
311 | 06a1cea5 | Peter Crosthwaite | /* Size of instruction in bytes */
|
312 | 06a1cea5 | Peter Crosthwaite | uint8_t size; |
313 | 06a1cea5 | Peter Crosthwaite | /* Interpreter */
|
314 | 06a1cea5 | Peter Crosthwaite | void (*exec)(PL330Chan *, uint8_t opcode, uint8_t *args, int len); |
315 | 06a1cea5 | Peter Crosthwaite | } PL330InsnDesc; |
316 | 06a1cea5 | Peter Crosthwaite | |
317 | 06a1cea5 | Peter Crosthwaite | |
318 | 06a1cea5 | Peter Crosthwaite | /* MFIFO Implementation
|
319 | 06a1cea5 | Peter Crosthwaite | *
|
320 | 06a1cea5 | Peter Crosthwaite | * MFIFO is implemented as a cyclic buffer of BUF_SIZE size. Tagged bytes are
|
321 | 06a1cea5 | Peter Crosthwaite | * stored in this buffer. Data is stored in BUF field, tags - in the
|
322 | 06a1cea5 | Peter Crosthwaite | * corresponding array elements of TAG field.
|
323 | 06a1cea5 | Peter Crosthwaite | */
|
324 | 06a1cea5 | Peter Crosthwaite | |
325 | 06a1cea5 | Peter Crosthwaite | /* Initialize queue. */
|
326 | 06a1cea5 | Peter Crosthwaite | |
327 | 06a1cea5 | Peter Crosthwaite | static void pl330_fifo_init(PL330Fifo *s, uint32_t size) |
328 | 06a1cea5 | Peter Crosthwaite | { |
329 | 06a1cea5 | Peter Crosthwaite | s->buf = g_malloc0(size); |
330 | 06a1cea5 | Peter Crosthwaite | s->tag = g_malloc0(size); |
331 | 06a1cea5 | Peter Crosthwaite | s->buf_size = size; |
332 | 06a1cea5 | Peter Crosthwaite | } |
333 | 06a1cea5 | Peter Crosthwaite | |
334 | 06a1cea5 | Peter Crosthwaite | /* Cyclic increment */
|
335 | 06a1cea5 | Peter Crosthwaite | |
336 | 06a1cea5 | Peter Crosthwaite | static inline int pl330_fifo_inc(PL330Fifo *s, int x) |
337 | 06a1cea5 | Peter Crosthwaite | { |
338 | 06a1cea5 | Peter Crosthwaite | return (x + 1) % s->buf_size; |
339 | 06a1cea5 | Peter Crosthwaite | } |
340 | 06a1cea5 | Peter Crosthwaite | |
341 | 06a1cea5 | Peter Crosthwaite | /* Number of empty bytes in MFIFO */
|
342 | 06a1cea5 | Peter Crosthwaite | |
343 | 06a1cea5 | Peter Crosthwaite | static inline int pl330_fifo_num_free(PL330Fifo *s) |
344 | 06a1cea5 | Peter Crosthwaite | { |
345 | 06a1cea5 | Peter Crosthwaite | return s->buf_size - s->num;
|
346 | 06a1cea5 | Peter Crosthwaite | } |
347 | 06a1cea5 | Peter Crosthwaite | |
348 | 06a1cea5 | Peter Crosthwaite | /* Push LEN bytes of data stored in BUF to MFIFO and tag it with TAG.
|
349 | 06a1cea5 | Peter Crosthwaite | * Zero returned on success, PL330_FIFO_STALL if there is no enough free
|
350 | 06a1cea5 | Peter Crosthwaite | * space in MFIFO to store requested amount of data. If push was unsuccessful
|
351 | 06a1cea5 | Peter Crosthwaite | * no data is stored to MFIFO.
|
352 | 06a1cea5 | Peter Crosthwaite | */
|
353 | 06a1cea5 | Peter Crosthwaite | |
354 | 06a1cea5 | Peter Crosthwaite | static int pl330_fifo_push(PL330Fifo *s, uint8_t *buf, int len, uint8_t tag) |
355 | 06a1cea5 | Peter Crosthwaite | { |
356 | 06a1cea5 | Peter Crosthwaite | int i;
|
357 | 06a1cea5 | Peter Crosthwaite | |
358 | 06a1cea5 | Peter Crosthwaite | if (s->buf_size - s->num < len) {
|
359 | 06a1cea5 | Peter Crosthwaite | return PL330_FIFO_STALL;
|
360 | 06a1cea5 | Peter Crosthwaite | } |
361 | 06a1cea5 | Peter Crosthwaite | for (i = 0; i < len; i++) { |
362 | 06a1cea5 | Peter Crosthwaite | int push_idx = (s->head + s->num + i) % s->buf_size;
|
363 | 06a1cea5 | Peter Crosthwaite | s->buf[push_idx] = buf[i]; |
364 | 06a1cea5 | Peter Crosthwaite | s->tag[push_idx] = tag; |
365 | 06a1cea5 | Peter Crosthwaite | } |
366 | 06a1cea5 | Peter Crosthwaite | s->num += len; |
367 | 06a1cea5 | Peter Crosthwaite | return PL330_FIFO_OK;
|
368 | 06a1cea5 | Peter Crosthwaite | } |
369 | 06a1cea5 | Peter Crosthwaite | |
370 | 06a1cea5 | Peter Crosthwaite | /* Get LEN bytes of data from MFIFO and store it to BUF. Tag value of each
|
371 | 06a1cea5 | Peter Crosthwaite | * byte is verified. Zero returned on success, PL330_FIFO_ERR on tag mismatch
|
372 | 06a1cea5 | Peter Crosthwaite | * and PL330_FIFO_STALL if there is no enough data in MFIFO. If get was
|
373 | 06a1cea5 | Peter Crosthwaite | * unsuccessful no data is removed from MFIFO.
|
374 | 06a1cea5 | Peter Crosthwaite | */
|
375 | 06a1cea5 | Peter Crosthwaite | |
376 | 06a1cea5 | Peter Crosthwaite | static int pl330_fifo_get(PL330Fifo *s, uint8_t *buf, int len, uint8_t tag) |
377 | 06a1cea5 | Peter Crosthwaite | { |
378 | 06a1cea5 | Peter Crosthwaite | int i;
|
379 | 06a1cea5 | Peter Crosthwaite | |
380 | 06a1cea5 | Peter Crosthwaite | if (s->num < len) {
|
381 | 06a1cea5 | Peter Crosthwaite | return PL330_FIFO_STALL;
|
382 | 06a1cea5 | Peter Crosthwaite | } |
383 | 06a1cea5 | Peter Crosthwaite | for (i = 0; i < len; i++) { |
384 | 06a1cea5 | Peter Crosthwaite | if (s->tag[s->head] == tag) {
|
385 | 06a1cea5 | Peter Crosthwaite | int get_idx = (s->head + i) % s->buf_size;
|
386 | 06a1cea5 | Peter Crosthwaite | buf[i] = s->buf[get_idx]; |
387 | 06a1cea5 | Peter Crosthwaite | } else { /* Tag mismatch - Rollback transaction */ |
388 | 06a1cea5 | Peter Crosthwaite | return PL330_FIFO_ERR;
|
389 | 06a1cea5 | Peter Crosthwaite | } |
390 | 06a1cea5 | Peter Crosthwaite | } |
391 | 06a1cea5 | Peter Crosthwaite | s->head = (s->head + len) % s->buf_size; |
392 | 06a1cea5 | Peter Crosthwaite | s->num -= len; |
393 | 06a1cea5 | Peter Crosthwaite | return PL330_FIFO_OK;
|
394 | 06a1cea5 | Peter Crosthwaite | } |
395 | 06a1cea5 | Peter Crosthwaite | |
396 | 06a1cea5 | Peter Crosthwaite | /* Reset MFIFO. This completely erases all data in it. */
|
397 | 06a1cea5 | Peter Crosthwaite | |
398 | 06a1cea5 | Peter Crosthwaite | static inline void pl330_fifo_reset(PL330Fifo *s) |
399 | 06a1cea5 | Peter Crosthwaite | { |
400 | 06a1cea5 | Peter Crosthwaite | s->head = 0;
|
401 | 06a1cea5 | Peter Crosthwaite | s->num = 0;
|
402 | 06a1cea5 | Peter Crosthwaite | } |
403 | 06a1cea5 | Peter Crosthwaite | |
404 | 06a1cea5 | Peter Crosthwaite | /* Return tag of the first byte stored in MFIFO. If MFIFO is empty
|
405 | 06a1cea5 | Peter Crosthwaite | * PL330_UNTAGGED is returned.
|
406 | 06a1cea5 | Peter Crosthwaite | */
|
407 | 06a1cea5 | Peter Crosthwaite | |
408 | 06a1cea5 | Peter Crosthwaite | static inline uint8_t pl330_fifo_tag(PL330Fifo *s) |
409 | 06a1cea5 | Peter Crosthwaite | { |
410 | 06a1cea5 | Peter Crosthwaite | return (!s->num) ? PL330_UNTAGGED : s->tag[s->head];
|
411 | 06a1cea5 | Peter Crosthwaite | } |
412 | 06a1cea5 | Peter Crosthwaite | |
413 | 06a1cea5 | Peter Crosthwaite | /* Returns non-zero if tag TAG is present in fifo or zero otherwise */
|
414 | 06a1cea5 | Peter Crosthwaite | |
415 | 06a1cea5 | Peter Crosthwaite | static int pl330_fifo_has_tag(PL330Fifo *s, uint8_t tag) |
416 | 06a1cea5 | Peter Crosthwaite | { |
417 | 06a1cea5 | Peter Crosthwaite | int i, n;
|
418 | 06a1cea5 | Peter Crosthwaite | |
419 | 06a1cea5 | Peter Crosthwaite | i = s->head; |
420 | 06a1cea5 | Peter Crosthwaite | for (n = 0; n < s->num; n++) { |
421 | 06a1cea5 | Peter Crosthwaite | if (s->tag[i] == tag) {
|
422 | 06a1cea5 | Peter Crosthwaite | return 1; |
423 | 06a1cea5 | Peter Crosthwaite | } |
424 | 06a1cea5 | Peter Crosthwaite | i = pl330_fifo_inc(s, i); |
425 | 06a1cea5 | Peter Crosthwaite | } |
426 | 06a1cea5 | Peter Crosthwaite | return 0; |
427 | 06a1cea5 | Peter Crosthwaite | } |
428 | 06a1cea5 | Peter Crosthwaite | |
429 | 06a1cea5 | Peter Crosthwaite | /* Remove all entry tagged with TAG from MFIFO */
|
430 | 06a1cea5 | Peter Crosthwaite | |
431 | 06a1cea5 | Peter Crosthwaite | static void pl330_fifo_tagged_remove(PL330Fifo *s, uint8_t tag) |
432 | 06a1cea5 | Peter Crosthwaite | { |
433 | 06a1cea5 | Peter Crosthwaite | int i, t, n;
|
434 | 06a1cea5 | Peter Crosthwaite | |
435 | 06a1cea5 | Peter Crosthwaite | t = i = s->head; |
436 | 06a1cea5 | Peter Crosthwaite | for (n = 0; n < s->num; n++) { |
437 | 06a1cea5 | Peter Crosthwaite | if (s->tag[i] != tag) {
|
438 | 06a1cea5 | Peter Crosthwaite | s->buf[t] = s->buf[i]; |
439 | 06a1cea5 | Peter Crosthwaite | s->tag[t] = s->tag[i]; |
440 | 06a1cea5 | Peter Crosthwaite | t = pl330_fifo_inc(s, t); |
441 | 06a1cea5 | Peter Crosthwaite | } else {
|
442 | 06a1cea5 | Peter Crosthwaite | s->num = s->num - 1;
|
443 | 06a1cea5 | Peter Crosthwaite | } |
444 | 06a1cea5 | Peter Crosthwaite | i = pl330_fifo_inc(s, i); |
445 | 06a1cea5 | Peter Crosthwaite | } |
446 | 06a1cea5 | Peter Crosthwaite | } |
447 | 06a1cea5 | Peter Crosthwaite | |
448 | 06a1cea5 | Peter Crosthwaite | /* Read-Write Queue implementation
|
449 | 06a1cea5 | Peter Crosthwaite | *
|
450 | 06a1cea5 | Peter Crosthwaite | * A Read-Write Queue stores up to QUEUE_SIZE instructions (loads or stores).
|
451 | 06a1cea5 | Peter Crosthwaite | * Each instruction is described by source (for loads) or destination (for
|
452 | 06a1cea5 | Peter Crosthwaite | * stores) address ADDR, width of data to be loaded/stored LEN, number of
|
453 | 06a1cea5 | Peter Crosthwaite | * stores/loads to be performed N, INC bit, Z bit and TAG to identify channel
|
454 | 06a1cea5 | Peter Crosthwaite | * this instruction belongs to. Queue does not store any information about
|
455 | 06a1cea5 | Peter Crosthwaite | * nature of the instruction: is it load or store. PL330 has different queues
|
456 | 06a1cea5 | Peter Crosthwaite | * for loads and stores so this is already known at the top level where it
|
457 | 06a1cea5 | Peter Crosthwaite | * matters.
|
458 | 06a1cea5 | Peter Crosthwaite | *
|
459 | 06a1cea5 | Peter Crosthwaite | * Queue works as FIFO for instructions with equivalent tags, but can issue
|
460 | 06a1cea5 | Peter Crosthwaite | * instructions with different tags in arbitrary order. SEQN field attached to
|
461 | 06a1cea5 | Peter Crosthwaite | * each instruction helps to achieve this. For each TAG queue contains
|
462 | 06a1cea5 | Peter Crosthwaite | * instructions with consecutive SEQN values ranging from LO_SEQN[TAG] to
|
463 | 06a1cea5 | Peter Crosthwaite | * HI_SEQN[TAG]-1 inclusive. SEQN is 8-bit unsigned integer, so SEQN=255 is
|
464 | 06a1cea5 | Peter Crosthwaite | * followed by SEQN=0.
|
465 | 06a1cea5 | Peter Crosthwaite | *
|
466 | 06a1cea5 | Peter Crosthwaite | * Z bit indicates that zeroes should be stored. No MFIFO fetches are performed
|
467 | 06a1cea5 | Peter Crosthwaite | * in this case.
|
468 | 06a1cea5 | Peter Crosthwaite | */
|
469 | 06a1cea5 | Peter Crosthwaite | |
470 | 06a1cea5 | Peter Crosthwaite | static void pl330_queue_reset(PL330Queue *s) |
471 | 06a1cea5 | Peter Crosthwaite | { |
472 | 06a1cea5 | Peter Crosthwaite | int i;
|
473 | 06a1cea5 | Peter Crosthwaite | |
474 | 06a1cea5 | Peter Crosthwaite | for (i = 0; i < s->queue_size; i++) { |
475 | 06a1cea5 | Peter Crosthwaite | s->queue[i].tag = PL330_UNTAGGED; |
476 | 06a1cea5 | Peter Crosthwaite | } |
477 | 06a1cea5 | Peter Crosthwaite | } |
478 | 06a1cea5 | Peter Crosthwaite | |
479 | 06a1cea5 | Peter Crosthwaite | /* Initialize queue */
|
480 | 06a1cea5 | Peter Crosthwaite | static void pl330_queue_init(PL330Queue *s, int size, PL330State *parent) |
481 | 06a1cea5 | Peter Crosthwaite | { |
482 | 06a1cea5 | Peter Crosthwaite | s->parent = parent; |
483 | 06a1cea5 | Peter Crosthwaite | s->queue = g_new0(PL330QueueEntry, size); |
484 | 06a1cea5 | Peter Crosthwaite | s->queue_size = size; |
485 | 06a1cea5 | Peter Crosthwaite | } |
486 | 06a1cea5 | Peter Crosthwaite | |
487 | 06a1cea5 | Peter Crosthwaite | /* Returns pointer to an empty slot or NULL if queue is full */
|
488 | 06a1cea5 | Peter Crosthwaite | static PL330QueueEntry *pl330_queue_find_empty(PL330Queue *s)
|
489 | 06a1cea5 | Peter Crosthwaite | { |
490 | 06a1cea5 | Peter Crosthwaite | int i;
|
491 | 06a1cea5 | Peter Crosthwaite | |
492 | 06a1cea5 | Peter Crosthwaite | for (i = 0; i < s->queue_size; i++) { |
493 | 06a1cea5 | Peter Crosthwaite | if (s->queue[i].tag == PL330_UNTAGGED) {
|
494 | 06a1cea5 | Peter Crosthwaite | return &s->queue[i];
|
495 | 06a1cea5 | Peter Crosthwaite | } |
496 | 06a1cea5 | Peter Crosthwaite | } |
497 | 06a1cea5 | Peter Crosthwaite | return NULL; |
498 | 06a1cea5 | Peter Crosthwaite | } |
499 | 06a1cea5 | Peter Crosthwaite | |
500 | 06a1cea5 | Peter Crosthwaite | /* Put instruction in queue.
|
501 | 06a1cea5 | Peter Crosthwaite | * Return value:
|
502 | 06a1cea5 | Peter Crosthwaite | * - zero - OK
|
503 | 06a1cea5 | Peter Crosthwaite | * - non-zero - queue is full
|
504 | 06a1cea5 | Peter Crosthwaite | */
|
505 | 06a1cea5 | Peter Crosthwaite | |
506 | 06a1cea5 | Peter Crosthwaite | static int pl330_queue_put_insn(PL330Queue *s, uint32_t addr, |
507 | 06a1cea5 | Peter Crosthwaite | int len, int n, bool inc, bool z, uint8_t tag) |
508 | 06a1cea5 | Peter Crosthwaite | { |
509 | 06a1cea5 | Peter Crosthwaite | PL330QueueEntry *entry = pl330_queue_find_empty(s); |
510 | 06a1cea5 | Peter Crosthwaite | |
511 | 06a1cea5 | Peter Crosthwaite | if (!entry) {
|
512 | 06a1cea5 | Peter Crosthwaite | return 1; |
513 | 06a1cea5 | Peter Crosthwaite | } |
514 | 06a1cea5 | Peter Crosthwaite | entry->tag = tag; |
515 | 06a1cea5 | Peter Crosthwaite | entry->addr = addr; |
516 | 06a1cea5 | Peter Crosthwaite | entry->len = len; |
517 | 06a1cea5 | Peter Crosthwaite | entry->n = n; |
518 | 06a1cea5 | Peter Crosthwaite | entry->z = z; |
519 | 06a1cea5 | Peter Crosthwaite | entry->inc = inc; |
520 | 06a1cea5 | Peter Crosthwaite | entry->seqn = s->parent->hi_seqn[tag]; |
521 | 06a1cea5 | Peter Crosthwaite | s->parent->hi_seqn[tag]++; |
522 | 06a1cea5 | Peter Crosthwaite | return 0; |
523 | 06a1cea5 | Peter Crosthwaite | } |
524 | 06a1cea5 | Peter Crosthwaite | |
525 | 06a1cea5 | Peter Crosthwaite | /* Returns a pointer to queue slot containing instruction which satisfies
|
526 | 06a1cea5 | Peter Crosthwaite | * following conditions:
|
527 | 06a1cea5 | Peter Crosthwaite | * - it has valid tag value (not PL330_UNTAGGED)
|
528 | 06a1cea5 | Peter Crosthwaite | * - if enforce_seq is set it has to be issuable without violating queue
|
529 | 06a1cea5 | Peter Crosthwaite | * logic (see above)
|
530 | 06a1cea5 | Peter Crosthwaite | * - if TAG argument is not PL330_UNTAGGED this instruction has tag value
|
531 | 06a1cea5 | Peter Crosthwaite | * equivalent to the argument TAG value.
|
532 | 06a1cea5 | Peter Crosthwaite | * If such instruction cannot be found NULL is returned.
|
533 | 06a1cea5 | Peter Crosthwaite | */
|
534 | 06a1cea5 | Peter Crosthwaite | |
535 | 06a1cea5 | Peter Crosthwaite | static PL330QueueEntry *pl330_queue_find_insn(PL330Queue *s, uint8_t tag,
|
536 | 06a1cea5 | Peter Crosthwaite | bool enforce_seq)
|
537 | 06a1cea5 | Peter Crosthwaite | { |
538 | 06a1cea5 | Peter Crosthwaite | int i;
|
539 | 06a1cea5 | Peter Crosthwaite | |
540 | 06a1cea5 | Peter Crosthwaite | for (i = 0; i < s->queue_size; i++) { |
541 | 06a1cea5 | Peter Crosthwaite | if (s->queue[i].tag != PL330_UNTAGGED) {
|
542 | 06a1cea5 | Peter Crosthwaite | if ((!enforce_seq ||
|
543 | 06a1cea5 | Peter Crosthwaite | s->queue[i].seqn == s->parent->lo_seqn[s->queue[i].tag]) && |
544 | 06a1cea5 | Peter Crosthwaite | (s->queue[i].tag == tag || tag == PL330_UNTAGGED || |
545 | 06a1cea5 | Peter Crosthwaite | s->queue[i].z)) { |
546 | 06a1cea5 | Peter Crosthwaite | return &s->queue[i];
|
547 | 06a1cea5 | Peter Crosthwaite | } |
548 | 06a1cea5 | Peter Crosthwaite | } |
549 | 06a1cea5 | Peter Crosthwaite | } |
550 | 06a1cea5 | Peter Crosthwaite | return NULL; |
551 | 06a1cea5 | Peter Crosthwaite | } |
552 | 06a1cea5 | Peter Crosthwaite | |
553 | 06a1cea5 | Peter Crosthwaite | /* Removes instruction from queue. */
|
554 | 06a1cea5 | Peter Crosthwaite | |
555 | 06a1cea5 | Peter Crosthwaite | static inline void pl330_queue_remove_insn(PL330Queue *s, PL330QueueEntry *e) |
556 | 06a1cea5 | Peter Crosthwaite | { |
557 | 06a1cea5 | Peter Crosthwaite | s->parent->lo_seqn[e->tag]++; |
558 | 06a1cea5 | Peter Crosthwaite | e->tag = PL330_UNTAGGED; |
559 | 06a1cea5 | Peter Crosthwaite | } |
560 | 06a1cea5 | Peter Crosthwaite | |
561 | 06a1cea5 | Peter Crosthwaite | /* Removes all instructions tagged with TAG from queue. */
|
562 | 06a1cea5 | Peter Crosthwaite | |
563 | 06a1cea5 | Peter Crosthwaite | static inline void pl330_queue_remove_tagged(PL330Queue *s, uint8_t tag) |
564 | 06a1cea5 | Peter Crosthwaite | { |
565 | 06a1cea5 | Peter Crosthwaite | int i;
|
566 | 06a1cea5 | Peter Crosthwaite | |
567 | 06a1cea5 | Peter Crosthwaite | for (i = 0; i < s->queue_size; i++) { |
568 | 06a1cea5 | Peter Crosthwaite | if (s->queue[i].tag == tag) {
|
569 | 06a1cea5 | Peter Crosthwaite | s->queue[i].tag = PL330_UNTAGGED; |
570 | 06a1cea5 | Peter Crosthwaite | } |
571 | 06a1cea5 | Peter Crosthwaite | } |
572 | 06a1cea5 | Peter Crosthwaite | } |
573 | 06a1cea5 | Peter Crosthwaite | |
574 | 06a1cea5 | Peter Crosthwaite | /* DMA instruction execution engine */
|
575 | 06a1cea5 | Peter Crosthwaite | |
576 | 06a1cea5 | Peter Crosthwaite | /* Moves DMA channel to the FAULT state and updates it's status. */
|
577 | 06a1cea5 | Peter Crosthwaite | |
578 | 06a1cea5 | Peter Crosthwaite | static inline void pl330_fault(PL330Chan *ch, uint32_t flags) |
579 | 06a1cea5 | Peter Crosthwaite | { |
580 | 06a1cea5 | Peter Crosthwaite | DB_PRINT("ch: %p, flags: %x\n", ch, flags);
|
581 | 06a1cea5 | Peter Crosthwaite | ch->fault_type |= flags; |
582 | 06a1cea5 | Peter Crosthwaite | if (ch->state == pl330_chan_fault) {
|
583 | 06a1cea5 | Peter Crosthwaite | return;
|
584 | 06a1cea5 | Peter Crosthwaite | } |
585 | 06a1cea5 | Peter Crosthwaite | ch->state = pl330_chan_fault; |
586 | 06a1cea5 | Peter Crosthwaite | ch->parent->num_faulting++; |
587 | 06a1cea5 | Peter Crosthwaite | if (ch->parent->num_faulting == 1) { |
588 | 06a1cea5 | Peter Crosthwaite | DB_PRINT("abort interrupt raised\n");
|
589 | 06a1cea5 | Peter Crosthwaite | qemu_irq_raise(ch->parent->irq_abort); |
590 | 06a1cea5 | Peter Crosthwaite | } |
591 | 06a1cea5 | Peter Crosthwaite | } |
592 | 06a1cea5 | Peter Crosthwaite | |
593 | 06a1cea5 | Peter Crosthwaite | /*
|
594 | 06a1cea5 | Peter Crosthwaite | * For information about instructions see PL330 Technical Reference Manual.
|
595 | 06a1cea5 | Peter Crosthwaite | *
|
596 | 06a1cea5 | Peter Crosthwaite | * Arguments:
|
597 | 06a1cea5 | Peter Crosthwaite | * CH - channel executing the instruction
|
598 | 06a1cea5 | Peter Crosthwaite | * OPCODE - opcode
|
599 | 06a1cea5 | Peter Crosthwaite | * ARGS - array of 8-bit arguments
|
600 | 06a1cea5 | Peter Crosthwaite | * LEN - number of elements in ARGS array
|
601 | 06a1cea5 | Peter Crosthwaite | */
|
602 | 06a1cea5 | Peter Crosthwaite | |
603 | 06a1cea5 | Peter Crosthwaite | static void pl330_dmaaddh(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) |
604 | 06a1cea5 | Peter Crosthwaite | { |
605 | 06a1cea5 | Peter Crosthwaite | uint16_t im = (((uint16_t)args[1]) << 8) | ((uint16_t)args[0]); |
606 | 06a1cea5 | Peter Crosthwaite | uint8_t ra = (opcode >> 1) & 1; |
607 | 06a1cea5 | Peter Crosthwaite | |
608 | 06a1cea5 | Peter Crosthwaite | if (ch->is_manager) {
|
609 | 06a1cea5 | Peter Crosthwaite | pl330_fault(ch, PL330_FAULT_UNDEF_INSTR); |
610 | 06a1cea5 | Peter Crosthwaite | return;
|
611 | 06a1cea5 | Peter Crosthwaite | } |
612 | 06a1cea5 | Peter Crosthwaite | if (ra) {
|
613 | 06a1cea5 | Peter Crosthwaite | ch->dst += im; |
614 | 06a1cea5 | Peter Crosthwaite | } else {
|
615 | 06a1cea5 | Peter Crosthwaite | ch->src += im; |
616 | 06a1cea5 | Peter Crosthwaite | } |
617 | 06a1cea5 | Peter Crosthwaite | } |
618 | 06a1cea5 | Peter Crosthwaite | |
619 | 06a1cea5 | Peter Crosthwaite | static void pl330_dmaend(PL330Chan *ch, uint8_t opcode, |
620 | 06a1cea5 | Peter Crosthwaite | uint8_t *args, int len)
|
621 | 06a1cea5 | Peter Crosthwaite | { |
622 | 06a1cea5 | Peter Crosthwaite | PL330State *s = ch->parent; |
623 | 06a1cea5 | Peter Crosthwaite | |
624 | 06a1cea5 | Peter Crosthwaite | if (ch->state == pl330_chan_executing && !ch->is_manager) {
|
625 | 06a1cea5 | Peter Crosthwaite | /* Wait for all transfers to complete */
|
626 | 06a1cea5 | Peter Crosthwaite | if (pl330_fifo_has_tag(&s->fifo, ch->tag) ||
|
627 | 06a1cea5 | Peter Crosthwaite | pl330_queue_find_insn(&s->read_queue, ch->tag, false) != NULL || |
628 | 06a1cea5 | Peter Crosthwaite | pl330_queue_find_insn(&s->write_queue, ch->tag, false) != NULL) { |
629 | 06a1cea5 | Peter Crosthwaite | |
630 | 06a1cea5 | Peter Crosthwaite | ch->stall = 1;
|
631 | 06a1cea5 | Peter Crosthwaite | return;
|
632 | 06a1cea5 | Peter Crosthwaite | } |
633 | 06a1cea5 | Peter Crosthwaite | } |
634 | 06a1cea5 | Peter Crosthwaite | DB_PRINT("DMA ending!\n");
|
635 | 06a1cea5 | Peter Crosthwaite | pl330_fifo_tagged_remove(&s->fifo, ch->tag); |
636 | 06a1cea5 | Peter Crosthwaite | pl330_queue_remove_tagged(&s->read_queue, ch->tag); |
637 | 06a1cea5 | Peter Crosthwaite | pl330_queue_remove_tagged(&s->write_queue, ch->tag); |
638 | 06a1cea5 | Peter Crosthwaite | ch->state = pl330_chan_stopped; |
639 | 06a1cea5 | Peter Crosthwaite | } |
640 | 06a1cea5 | Peter Crosthwaite | |
641 | 06a1cea5 | Peter Crosthwaite | static void pl330_dmaflushp(PL330Chan *ch, uint8_t opcode, |
642 | 06a1cea5 | Peter Crosthwaite | uint8_t *args, int len)
|
643 | 06a1cea5 | Peter Crosthwaite | { |
644 | 06a1cea5 | Peter Crosthwaite | uint8_t periph_id; |
645 | 06a1cea5 | Peter Crosthwaite | |
646 | 06a1cea5 | Peter Crosthwaite | if (args[0] & 7) { |
647 | 06a1cea5 | Peter Crosthwaite | pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); |
648 | 06a1cea5 | Peter Crosthwaite | return;
|
649 | 06a1cea5 | Peter Crosthwaite | } |
650 | 06a1cea5 | Peter Crosthwaite | periph_id = (args[0] >> 3) & 0x1f; |
651 | 06a1cea5 | Peter Crosthwaite | if (periph_id >= ch->parent->num_periph_req) {
|
652 | 06a1cea5 | Peter Crosthwaite | pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); |
653 | 06a1cea5 | Peter Crosthwaite | return;
|
654 | 06a1cea5 | Peter Crosthwaite | } |
655 | 06a1cea5 | Peter Crosthwaite | if (ch->ns && !(ch->parent->cfg[CFG_PNS] & (1 << periph_id))) { |
656 | 06a1cea5 | Peter Crosthwaite | pl330_fault(ch, PL330_FAULT_CH_PERIPH_ERR); |
657 | 06a1cea5 | Peter Crosthwaite | return;
|
658 | 06a1cea5 | Peter Crosthwaite | } |
659 | 06a1cea5 | Peter Crosthwaite | /* Do nothing */
|
660 | 06a1cea5 | Peter Crosthwaite | } |
661 | 06a1cea5 | Peter Crosthwaite | |
662 | 06a1cea5 | Peter Crosthwaite | static void pl330_dmago(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) |
663 | 06a1cea5 | Peter Crosthwaite | { |
664 | 06a1cea5 | Peter Crosthwaite | uint8_t chan_id; |
665 | 06a1cea5 | Peter Crosthwaite | uint8_t ns; |
666 | 06a1cea5 | Peter Crosthwaite | uint32_t pc; |
667 | 06a1cea5 | Peter Crosthwaite | PL330Chan *s; |
668 | 06a1cea5 | Peter Crosthwaite | |
669 | 06a1cea5 | Peter Crosthwaite | DB_PRINT("\n");
|
670 | 06a1cea5 | Peter Crosthwaite | |
671 | 06a1cea5 | Peter Crosthwaite | if (!ch->is_manager) {
|
672 | 06a1cea5 | Peter Crosthwaite | pl330_fault(ch, PL330_FAULT_UNDEF_INSTR); |
673 | 06a1cea5 | Peter Crosthwaite | return;
|
674 | 06a1cea5 | Peter Crosthwaite | } |
675 | 06a1cea5 | Peter Crosthwaite | ns = !!(opcode & 2);
|
676 | 06a1cea5 | Peter Crosthwaite | chan_id = args[0] & 7; |
677 | 06a1cea5 | Peter Crosthwaite | if ((args[0] >> 3)) { |
678 | 06a1cea5 | Peter Crosthwaite | pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); |
679 | 06a1cea5 | Peter Crosthwaite | return;
|
680 | 06a1cea5 | Peter Crosthwaite | } |
681 | 06a1cea5 | Peter Crosthwaite | if (chan_id >= ch->parent->num_chnls) {
|
682 | 06a1cea5 | Peter Crosthwaite | pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); |
683 | 06a1cea5 | Peter Crosthwaite | return;
|
684 | 06a1cea5 | Peter Crosthwaite | } |
685 | 06a1cea5 | Peter Crosthwaite | pc = (((uint32_t)args[4]) << 24) | (((uint32_t)args[3]) << 16) | |
686 | 06a1cea5 | Peter Crosthwaite | (((uint32_t)args[2]) << 8) | (((uint32_t)args[1])); |
687 | 06a1cea5 | Peter Crosthwaite | if (ch->parent->chan[chan_id].state != pl330_chan_stopped) {
|
688 | 06a1cea5 | Peter Crosthwaite | pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); |
689 | 06a1cea5 | Peter Crosthwaite | return;
|
690 | 06a1cea5 | Peter Crosthwaite | } |
691 | 06a1cea5 | Peter Crosthwaite | if (ch->ns && !ns) {
|
692 | 06a1cea5 | Peter Crosthwaite | pl330_fault(ch, PL330_FAULT_DMAGO_ERR); |
693 | 06a1cea5 | Peter Crosthwaite | return;
|
694 | 06a1cea5 | Peter Crosthwaite | } |
695 | 06a1cea5 | Peter Crosthwaite | s = &ch->parent->chan[chan_id]; |
696 | 06a1cea5 | Peter Crosthwaite | s->ns = ns; |
697 | 06a1cea5 | Peter Crosthwaite | s->pc = pc; |
698 | 06a1cea5 | Peter Crosthwaite | s->state = pl330_chan_executing; |
699 | 06a1cea5 | Peter Crosthwaite | } |
700 | 06a1cea5 | Peter Crosthwaite | |
701 | 06a1cea5 | Peter Crosthwaite | static void pl330_dmald(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) |
702 | 06a1cea5 | Peter Crosthwaite | { |
703 | 06a1cea5 | Peter Crosthwaite | uint8_t bs = opcode & 3;
|
704 | 06a1cea5 | Peter Crosthwaite | uint32_t size, num; |
705 | 06a1cea5 | Peter Crosthwaite | bool inc;
|
706 | 06a1cea5 | Peter Crosthwaite | |
707 | 06a1cea5 | Peter Crosthwaite | if (bs == 2) { |
708 | 06a1cea5 | Peter Crosthwaite | pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); |
709 | 06a1cea5 | Peter Crosthwaite | return;
|
710 | 06a1cea5 | Peter Crosthwaite | } |
711 | 06a1cea5 | Peter Crosthwaite | if ((bs == 1 && ch->request_flag == PL330_BURST) || |
712 | 06a1cea5 | Peter Crosthwaite | (bs == 3 && ch->request_flag == PL330_SINGLE)) {
|
713 | 06a1cea5 | Peter Crosthwaite | /* Perform NOP */
|
714 | 06a1cea5 | Peter Crosthwaite | return;
|
715 | 06a1cea5 | Peter Crosthwaite | } |
716 | 06a1cea5 | Peter Crosthwaite | if (bs == 1 && ch->request_flag == PL330_SINGLE) { |
717 | 06a1cea5 | Peter Crosthwaite | num = 1;
|
718 | 06a1cea5 | Peter Crosthwaite | } else {
|
719 | 06a1cea5 | Peter Crosthwaite | num = ((ch->control >> 4) & 0xf) + 1; |
720 | 06a1cea5 | Peter Crosthwaite | } |
721 | 06a1cea5 | Peter Crosthwaite | size = (uint32_t)1 << ((ch->control >> 1) & 0x7); |
722 | 06a1cea5 | Peter Crosthwaite | inc = !!(ch->control & 1);
|
723 | 06a1cea5 | Peter Crosthwaite | ch->stall = pl330_queue_put_insn(&ch->parent->read_queue, ch->src, |
724 | 06a1cea5 | Peter Crosthwaite | size, num, inc, 0, ch->tag);
|
725 | 06a1cea5 | Peter Crosthwaite | if (!ch->stall) {
|
726 | 06a1cea5 | Peter Crosthwaite | DB_PRINT("channel:%d address:%08x size:%d num:%d %c\n",
|
727 | 06a1cea5 | Peter Crosthwaite | ch->tag, ch->src, size, num, inc ? 'Y' : 'N'); |
728 | 06a1cea5 | Peter Crosthwaite | ch->src += inc ? size * num - (ch->src & (size - 1)) : 0; |
729 | 06a1cea5 | Peter Crosthwaite | } |
730 | 06a1cea5 | Peter Crosthwaite | } |
731 | 06a1cea5 | Peter Crosthwaite | |
732 | 06a1cea5 | Peter Crosthwaite | static void pl330_dmaldp(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) |
733 | 06a1cea5 | Peter Crosthwaite | { |
734 | 06a1cea5 | Peter Crosthwaite | uint8_t periph_id; |
735 | 06a1cea5 | Peter Crosthwaite | |
736 | 06a1cea5 | Peter Crosthwaite | if (args[0] & 7) { |
737 | 06a1cea5 | Peter Crosthwaite | pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); |
738 | 06a1cea5 | Peter Crosthwaite | return;
|
739 | 06a1cea5 | Peter Crosthwaite | } |
740 | 06a1cea5 | Peter Crosthwaite | periph_id = (args[0] >> 3) & 0x1f; |
741 | 06a1cea5 | Peter Crosthwaite | if (periph_id >= ch->parent->num_periph_req) {
|
742 | 06a1cea5 | Peter Crosthwaite | pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); |
743 | 06a1cea5 | Peter Crosthwaite | return;
|
744 | 06a1cea5 | Peter Crosthwaite | } |
745 | 06a1cea5 | Peter Crosthwaite | if (ch->ns && !(ch->parent->cfg[CFG_PNS] & (1 << periph_id))) { |
746 | 06a1cea5 | Peter Crosthwaite | pl330_fault(ch, PL330_FAULT_CH_PERIPH_ERR); |
747 | 06a1cea5 | Peter Crosthwaite | return;
|
748 | 06a1cea5 | Peter Crosthwaite | } |
749 | 06a1cea5 | Peter Crosthwaite | pl330_dmald(ch, opcode, args, len); |
750 | 06a1cea5 | Peter Crosthwaite | } |
751 | 06a1cea5 | Peter Crosthwaite | |
752 | 06a1cea5 | Peter Crosthwaite | static void pl330_dmalp(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) |
753 | 06a1cea5 | Peter Crosthwaite | { |
754 | 06a1cea5 | Peter Crosthwaite | uint8_t lc = (opcode & 2) >> 1; |
755 | 06a1cea5 | Peter Crosthwaite | |
756 | 06a1cea5 | Peter Crosthwaite | ch->lc[lc] = args[0];
|
757 | 06a1cea5 | Peter Crosthwaite | } |
758 | 06a1cea5 | Peter Crosthwaite | |
759 | 06a1cea5 | Peter Crosthwaite | static void pl330_dmakill(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) |
760 | 06a1cea5 | Peter Crosthwaite | { |
761 | 06a1cea5 | Peter Crosthwaite | if (ch->state == pl330_chan_fault ||
|
762 | 06a1cea5 | Peter Crosthwaite | ch->state == pl330_chan_fault_completing) { |
763 | 06a1cea5 | Peter Crosthwaite | /* This is the only way for a channel to leave the faulting state */
|
764 | 06a1cea5 | Peter Crosthwaite | ch->fault_type = 0;
|
765 | 06a1cea5 | Peter Crosthwaite | ch->parent->num_faulting--; |
766 | 06a1cea5 | Peter Crosthwaite | if (ch->parent->num_faulting == 0) { |
767 | 06a1cea5 | Peter Crosthwaite | DB_PRINT("abort interrupt lowered\n");
|
768 | 06a1cea5 | Peter Crosthwaite | qemu_irq_lower(ch->parent->irq_abort); |
769 | 06a1cea5 | Peter Crosthwaite | } |
770 | 06a1cea5 | Peter Crosthwaite | } |
771 | 06a1cea5 | Peter Crosthwaite | ch->state = pl330_chan_killing; |
772 | 06a1cea5 | Peter Crosthwaite | pl330_fifo_tagged_remove(&ch->parent->fifo, ch->tag); |
773 | 06a1cea5 | Peter Crosthwaite | pl330_queue_remove_tagged(&ch->parent->read_queue, ch->tag); |
774 | 06a1cea5 | Peter Crosthwaite | pl330_queue_remove_tagged(&ch->parent->write_queue, ch->tag); |
775 | 06a1cea5 | Peter Crosthwaite | ch->state = pl330_chan_stopped; |
776 | 06a1cea5 | Peter Crosthwaite | } |
777 | 06a1cea5 | Peter Crosthwaite | |
778 | 06a1cea5 | Peter Crosthwaite | static void pl330_dmalpend(PL330Chan *ch, uint8_t opcode, |
779 | 06a1cea5 | Peter Crosthwaite | uint8_t *args, int len)
|
780 | 06a1cea5 | Peter Crosthwaite | { |
781 | 06a1cea5 | Peter Crosthwaite | uint8_t nf = (opcode & 0x10) >> 4; |
782 | 06a1cea5 | Peter Crosthwaite | uint8_t bs = opcode & 3;
|
783 | 06a1cea5 | Peter Crosthwaite | uint8_t lc = (opcode & 4) >> 2; |
784 | 06a1cea5 | Peter Crosthwaite | |
785 | 06a1cea5 | Peter Crosthwaite | if (bs == 2) { |
786 | 06a1cea5 | Peter Crosthwaite | pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); |
787 | 06a1cea5 | Peter Crosthwaite | return;
|
788 | 06a1cea5 | Peter Crosthwaite | } |
789 | 06a1cea5 | Peter Crosthwaite | if ((bs == 1 && ch->request_flag == PL330_BURST) || |
790 | 06a1cea5 | Peter Crosthwaite | (bs == 3 && ch->request_flag == PL330_SINGLE)) {
|
791 | 06a1cea5 | Peter Crosthwaite | /* Perform NOP */
|
792 | 06a1cea5 | Peter Crosthwaite | return;
|
793 | 06a1cea5 | Peter Crosthwaite | } |
794 | 06a1cea5 | Peter Crosthwaite | if (!nf || ch->lc[lc]) {
|
795 | 06a1cea5 | Peter Crosthwaite | if (nf) {
|
796 | 06a1cea5 | Peter Crosthwaite | ch->lc[lc]--; |
797 | 06a1cea5 | Peter Crosthwaite | } |
798 | 06a1cea5 | Peter Crosthwaite | DB_PRINT("loop reiteration\n");
|
799 | 06a1cea5 | Peter Crosthwaite | ch->pc -= args[0];
|
800 | 06a1cea5 | Peter Crosthwaite | ch->pc -= len + 1;
|
801 | 06a1cea5 | Peter Crosthwaite | /* "ch->pc -= args[0] + len + 1" is incorrect when args[0] == 256 */
|
802 | 06a1cea5 | Peter Crosthwaite | } else {
|
803 | 06a1cea5 | Peter Crosthwaite | DB_PRINT("loop fallthrough\n");
|
804 | 06a1cea5 | Peter Crosthwaite | } |
805 | 06a1cea5 | Peter Crosthwaite | } |
806 | 06a1cea5 | Peter Crosthwaite | |
807 | 06a1cea5 | Peter Crosthwaite | |
808 | 06a1cea5 | Peter Crosthwaite | static void pl330_dmamov(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) |
809 | 06a1cea5 | Peter Crosthwaite | { |
810 | 06a1cea5 | Peter Crosthwaite | uint8_t rd = args[0] & 7; |
811 | 06a1cea5 | Peter Crosthwaite | uint32_t im; |
812 | 06a1cea5 | Peter Crosthwaite | |
813 | 06a1cea5 | Peter Crosthwaite | if ((args[0] >> 3)) { |
814 | 06a1cea5 | Peter Crosthwaite | pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); |
815 | 06a1cea5 | Peter Crosthwaite | return;
|
816 | 06a1cea5 | Peter Crosthwaite | } |
817 | 06a1cea5 | Peter Crosthwaite | im = (((uint32_t)args[4]) << 24) | (((uint32_t)args[3]) << 16) | |
818 | 06a1cea5 | Peter Crosthwaite | (((uint32_t)args[2]) << 8) | (((uint32_t)args[1])); |
819 | 06a1cea5 | Peter Crosthwaite | switch (rd) {
|
820 | 06a1cea5 | Peter Crosthwaite | case 0: |
821 | 06a1cea5 | Peter Crosthwaite | ch->src = im; |
822 | 06a1cea5 | Peter Crosthwaite | break;
|
823 | 06a1cea5 | Peter Crosthwaite | case 1: |
824 | 06a1cea5 | Peter Crosthwaite | ch->control = im; |
825 | 06a1cea5 | Peter Crosthwaite | break;
|
826 | 06a1cea5 | Peter Crosthwaite | case 2: |
827 | 06a1cea5 | Peter Crosthwaite | ch->dst = im; |
828 | 06a1cea5 | Peter Crosthwaite | break;
|
829 | 06a1cea5 | Peter Crosthwaite | default:
|
830 | 06a1cea5 | Peter Crosthwaite | pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); |
831 | 06a1cea5 | Peter Crosthwaite | return;
|
832 | 06a1cea5 | Peter Crosthwaite | } |
833 | 06a1cea5 | Peter Crosthwaite | } |
834 | 06a1cea5 | Peter Crosthwaite | |
835 | 06a1cea5 | Peter Crosthwaite | static void pl330_dmanop(PL330Chan *ch, uint8_t opcode, |
836 | 06a1cea5 | Peter Crosthwaite | uint8_t *args, int len)
|
837 | 06a1cea5 | Peter Crosthwaite | { |
838 | 06a1cea5 | Peter Crosthwaite | /* NOP is NOP. */
|
839 | 06a1cea5 | Peter Crosthwaite | } |
840 | 06a1cea5 | Peter Crosthwaite | |
841 | 06a1cea5 | Peter Crosthwaite | static void pl330_dmarmb(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) |
842 | 06a1cea5 | Peter Crosthwaite | { |
843 | 06a1cea5 | Peter Crosthwaite | if (pl330_queue_find_insn(&ch->parent->read_queue, ch->tag, false)) { |
844 | 06a1cea5 | Peter Crosthwaite | ch->state = pl330_chan_at_barrier; |
845 | 06a1cea5 | Peter Crosthwaite | ch->stall = 1;
|
846 | 06a1cea5 | Peter Crosthwaite | return;
|
847 | 06a1cea5 | Peter Crosthwaite | } else {
|
848 | 06a1cea5 | Peter Crosthwaite | ch->state = pl330_chan_executing; |
849 | 06a1cea5 | Peter Crosthwaite | } |
850 | 06a1cea5 | Peter Crosthwaite | } |
851 | 06a1cea5 | Peter Crosthwaite | |
852 | 06a1cea5 | Peter Crosthwaite | static void pl330_dmasev(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) |
853 | 06a1cea5 | Peter Crosthwaite | { |
854 | 06a1cea5 | Peter Crosthwaite | uint8_t ev_id; |
855 | 06a1cea5 | Peter Crosthwaite | |
856 | 06a1cea5 | Peter Crosthwaite | if (args[0] & 7) { |
857 | 06a1cea5 | Peter Crosthwaite | pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); |
858 | 06a1cea5 | Peter Crosthwaite | return;
|
859 | 06a1cea5 | Peter Crosthwaite | } |
860 | 06a1cea5 | Peter Crosthwaite | ev_id = (args[0] >> 3) & 0x1f; |
861 | 06a1cea5 | Peter Crosthwaite | if (ev_id >= ch->parent->num_events) {
|
862 | 06a1cea5 | Peter Crosthwaite | pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); |
863 | 06a1cea5 | Peter Crosthwaite | return;
|
864 | 06a1cea5 | Peter Crosthwaite | } |
865 | 06a1cea5 | Peter Crosthwaite | if (ch->ns && !(ch->parent->cfg[CFG_INS] & (1 << ev_id))) { |
866 | 06a1cea5 | Peter Crosthwaite | pl330_fault(ch, PL330_FAULT_EVENT_ERR); |
867 | 06a1cea5 | Peter Crosthwaite | return;
|
868 | 06a1cea5 | Peter Crosthwaite | } |
869 | 06a1cea5 | Peter Crosthwaite | if (ch->parent->inten & (1 << ev_id)) { |
870 | 06a1cea5 | Peter Crosthwaite | ch->parent->int_status |= (1 << ev_id);
|
871 | 06a1cea5 | Peter Crosthwaite | DB_PRINT("event interrupt raised %d\n", ev_id);
|
872 | 06a1cea5 | Peter Crosthwaite | qemu_irq_raise(ch->parent->irq[ev_id]); |
873 | 06a1cea5 | Peter Crosthwaite | } |
874 | fd7f8a99 | Peter Crosthwaite | ch->parent->ev_status |= (1 << ev_id);
|
875 | 06a1cea5 | Peter Crosthwaite | } |
876 | 06a1cea5 | Peter Crosthwaite | |
877 | 06a1cea5 | Peter Crosthwaite | static void pl330_dmast(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len) |
878 | 06a1cea5 | Peter Crosthwaite | { |
879 | 06a1cea5 | Peter Crosthwaite | uint8_t bs = opcode & 3;
|
880 | 06a1cea5 | Peter Crosthwaite | uint32_t size, num; |
881 | 06a1cea5 | Peter Crosthwaite | bool inc;
|
882 | 06a1cea5 | Peter Crosthwaite | |
883 | 06a1cea5 | Peter Crosthwaite | if (bs == 2) { |
884 | 06a1cea5 | Peter Crosthwaite | pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); |
885 | 06a1cea5 | Peter Crosthwaite | return;
|
886 | 06a1cea5 | Peter Crosthwaite | } |
887 | 06a1cea5 | Peter Crosthwaite | if ((bs == 1 && ch->request_flag == PL330_BURST) || |
888 | 06a1cea5 | Peter Crosthwaite | (bs == 3 && ch->request_flag == PL330_SINGLE)) {
|
889 | 06a1cea5 | Peter Crosthwaite | /* Perform NOP */
|
890 | 06a1cea5 | Peter Crosthwaite | return;
|
891 | 06a1cea5 | Peter Crosthwaite | } |
892 | 06a1cea5 | Peter Crosthwaite | num = ((ch->control >> 18) & 0xf) + 1; |
893 | 06a1cea5 | Peter Crosthwaite | size = (uint32_t)1 << ((ch->control >> 15) & 0x7); |
894 | 06a1cea5 | Peter Crosthwaite | inc = !!((ch->control >> 14) & 1); |
895 | 06a1cea5 | Peter Crosthwaite | ch->stall = pl330_queue_put_insn(&ch->parent->write_queue, ch->dst, |
896 | 06a1cea5 | Peter Crosthwaite | size, num, inc, 0, ch->tag);
|
897 | 06a1cea5 | Peter Crosthwaite | if (!ch->stall) {
|
898 | 06a1cea5 | Peter Crosthwaite | DB_PRINT("channel:%d address:%08x size:%d num:%d %c\n",
|
899 | 06a1cea5 | Peter Crosthwaite | ch->tag, ch->dst, size, num, inc ? 'Y' : 'N'); |
900 | 06a1cea5 | Peter Crosthwaite | ch->dst += inc ? size * num - (ch->dst & (size - 1)) : 0; |
901 | 06a1cea5 | Peter Crosthwaite | } |
902 | 06a1cea5 | Peter Crosthwaite | } |
903 | 06a1cea5 | Peter Crosthwaite | |
904 | 06a1cea5 | Peter Crosthwaite | static void pl330_dmastp(PL330Chan *ch, uint8_t opcode, |
905 | 06a1cea5 | Peter Crosthwaite | uint8_t *args, int len)
|
906 | 06a1cea5 | Peter Crosthwaite | { |
907 | 06a1cea5 | Peter Crosthwaite | uint8_t periph_id; |
908 | 06a1cea5 | Peter Crosthwaite | |
909 | 06a1cea5 | Peter Crosthwaite | if (args[0] & 7) { |
910 | 06a1cea5 | Peter Crosthwaite | pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); |
911 | 06a1cea5 | Peter Crosthwaite | return;
|
912 | 06a1cea5 | Peter Crosthwaite | } |
913 | 06a1cea5 | Peter Crosthwaite | periph_id = (args[0] >> 3) & 0x1f; |
914 | 06a1cea5 | Peter Crosthwaite | if (periph_id >= ch->parent->num_periph_req) {
|
915 | 06a1cea5 | Peter Crosthwaite | pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); |
916 | 06a1cea5 | Peter Crosthwaite | return;
|
917 | 06a1cea5 | Peter Crosthwaite | } |
918 | 06a1cea5 | Peter Crosthwaite | if (ch->ns && !(ch->parent->cfg[CFG_PNS] & (1 << periph_id))) { |
919 | 06a1cea5 | Peter Crosthwaite | pl330_fault(ch, PL330_FAULT_CH_PERIPH_ERR); |
920 | 06a1cea5 | Peter Crosthwaite | return;
|
921 | 06a1cea5 | Peter Crosthwaite | } |
922 | 06a1cea5 | Peter Crosthwaite | pl330_dmast(ch, opcode, args, len); |
923 | 06a1cea5 | Peter Crosthwaite | } |
924 | 06a1cea5 | Peter Crosthwaite | |
925 | 06a1cea5 | Peter Crosthwaite | static void pl330_dmastz(PL330Chan *ch, uint8_t opcode, |
926 | 06a1cea5 | Peter Crosthwaite | uint8_t *args, int len)
|
927 | 06a1cea5 | Peter Crosthwaite | { |
928 | 06a1cea5 | Peter Crosthwaite | uint32_t size, num; |
929 | 06a1cea5 | Peter Crosthwaite | bool inc;
|
930 | 06a1cea5 | Peter Crosthwaite | |
931 | 06a1cea5 | Peter Crosthwaite | num = ((ch->control >> 18) & 0xf) + 1; |
932 | 06a1cea5 | Peter Crosthwaite | size = (uint32_t)1 << ((ch->control >> 15) & 0x7); |
933 | 06a1cea5 | Peter Crosthwaite | inc = !!((ch->control >> 14) & 1); |
934 | 06a1cea5 | Peter Crosthwaite | ch->stall = pl330_queue_put_insn(&ch->parent->write_queue, ch->dst, |
935 | 06a1cea5 | Peter Crosthwaite | size, num, inc, 1, ch->tag);
|
936 | 06a1cea5 | Peter Crosthwaite | if (inc) {
|
937 | 06a1cea5 | Peter Crosthwaite | ch->dst += size * num; |
938 | 06a1cea5 | Peter Crosthwaite | } |
939 | 06a1cea5 | Peter Crosthwaite | } |
940 | 06a1cea5 | Peter Crosthwaite | |
941 | 06a1cea5 | Peter Crosthwaite | static void pl330_dmawfe(PL330Chan *ch, uint8_t opcode, |
942 | 06a1cea5 | Peter Crosthwaite | uint8_t *args, int len)
|
943 | 06a1cea5 | Peter Crosthwaite | { |
944 | 06a1cea5 | Peter Crosthwaite | uint8_t ev_id; |
945 | 06a1cea5 | Peter Crosthwaite | int i;
|
946 | 06a1cea5 | Peter Crosthwaite | |
947 | 06a1cea5 | Peter Crosthwaite | if (args[0] & 5) { |
948 | 06a1cea5 | Peter Crosthwaite | pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); |
949 | 06a1cea5 | Peter Crosthwaite | return;
|
950 | 06a1cea5 | Peter Crosthwaite | } |
951 | 06a1cea5 | Peter Crosthwaite | ev_id = (args[0] >> 3) & 0x1f; |
952 | 06a1cea5 | Peter Crosthwaite | if (ev_id >= ch->parent->num_events) {
|
953 | 06a1cea5 | Peter Crosthwaite | pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); |
954 | 06a1cea5 | Peter Crosthwaite | return;
|
955 | 06a1cea5 | Peter Crosthwaite | } |
956 | 06a1cea5 | Peter Crosthwaite | if (ch->ns && !(ch->parent->cfg[CFG_INS] & (1 << ev_id))) { |
957 | 06a1cea5 | Peter Crosthwaite | pl330_fault(ch, PL330_FAULT_EVENT_ERR); |
958 | 06a1cea5 | Peter Crosthwaite | return;
|
959 | 06a1cea5 | Peter Crosthwaite | } |
960 | 06a1cea5 | Peter Crosthwaite | ch->wakeup = ev_id; |
961 | 06a1cea5 | Peter Crosthwaite | ch->state = pl330_chan_waiting_event; |
962 | 06a1cea5 | Peter Crosthwaite | if (~ch->parent->inten & ch->parent->ev_status & 1 << ev_id) { |
963 | 06a1cea5 | Peter Crosthwaite | ch->state = pl330_chan_executing; |
964 | 06a1cea5 | Peter Crosthwaite | /* If anyone else is currently waiting on the same event, let them
|
965 | 06a1cea5 | Peter Crosthwaite | * clear the ev_status so they pick up event as well
|
966 | 06a1cea5 | Peter Crosthwaite | */
|
967 | 06a1cea5 | Peter Crosthwaite | for (i = 0; i < ch->parent->num_chnls; ++i) { |
968 | 06a1cea5 | Peter Crosthwaite | PL330Chan *peer = &ch->parent->chan[i]; |
969 | 06a1cea5 | Peter Crosthwaite | if (peer->state == pl330_chan_waiting_event &&
|
970 | 06a1cea5 | Peter Crosthwaite | peer->wakeup == ev_id) { |
971 | 06a1cea5 | Peter Crosthwaite | return;
|
972 | 06a1cea5 | Peter Crosthwaite | } |
973 | 06a1cea5 | Peter Crosthwaite | } |
974 | 06a1cea5 | Peter Crosthwaite | ch->parent->ev_status &= ~(1 << ev_id);
|
975 | 06a1cea5 | Peter Crosthwaite | } else {
|
976 | 06a1cea5 | Peter Crosthwaite | ch->stall = 1;
|
977 | 06a1cea5 | Peter Crosthwaite | } |
978 | 06a1cea5 | Peter Crosthwaite | } |
979 | 06a1cea5 | Peter Crosthwaite | |
980 | 06a1cea5 | Peter Crosthwaite | static void pl330_dmawfp(PL330Chan *ch, uint8_t opcode, |
981 | 06a1cea5 | Peter Crosthwaite | uint8_t *args, int len)
|
982 | 06a1cea5 | Peter Crosthwaite | { |
983 | 06a1cea5 | Peter Crosthwaite | uint8_t bs = opcode & 3;
|
984 | 06a1cea5 | Peter Crosthwaite | uint8_t periph_id; |
985 | 06a1cea5 | Peter Crosthwaite | |
986 | 06a1cea5 | Peter Crosthwaite | if (args[0] & 7) { |
987 | 06a1cea5 | Peter Crosthwaite | pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); |
988 | 06a1cea5 | Peter Crosthwaite | return;
|
989 | 06a1cea5 | Peter Crosthwaite | } |
990 | 06a1cea5 | Peter Crosthwaite | periph_id = (args[0] >> 3) & 0x1f; |
991 | 06a1cea5 | Peter Crosthwaite | if (periph_id >= ch->parent->num_periph_req) {
|
992 | 06a1cea5 | Peter Crosthwaite | pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); |
993 | 06a1cea5 | Peter Crosthwaite | return;
|
994 | 06a1cea5 | Peter Crosthwaite | } |
995 | 06a1cea5 | Peter Crosthwaite | if (ch->ns && !(ch->parent->cfg[CFG_PNS] & (1 << periph_id))) { |
996 | 06a1cea5 | Peter Crosthwaite | pl330_fault(ch, PL330_FAULT_CH_PERIPH_ERR); |
997 | 06a1cea5 | Peter Crosthwaite | return;
|
998 | 06a1cea5 | Peter Crosthwaite | } |
999 | 06a1cea5 | Peter Crosthwaite | switch (bs) {
|
1000 | 06a1cea5 | Peter Crosthwaite | case 0: /* S */ |
1001 | 06a1cea5 | Peter Crosthwaite | ch->request_flag = PL330_SINGLE; |
1002 | 06a1cea5 | Peter Crosthwaite | ch->wfp_sbp = 0;
|
1003 | 06a1cea5 | Peter Crosthwaite | break;
|
1004 | 06a1cea5 | Peter Crosthwaite | case 1: /* P */ |
1005 | 06a1cea5 | Peter Crosthwaite | ch->request_flag = PL330_BURST; |
1006 | 06a1cea5 | Peter Crosthwaite | ch->wfp_sbp = 2;
|
1007 | 06a1cea5 | Peter Crosthwaite | break;
|
1008 | 06a1cea5 | Peter Crosthwaite | case 2: /* B */ |
1009 | 06a1cea5 | Peter Crosthwaite | ch->request_flag = PL330_BURST; |
1010 | 06a1cea5 | Peter Crosthwaite | ch->wfp_sbp = 1;
|
1011 | 06a1cea5 | Peter Crosthwaite | break;
|
1012 | 06a1cea5 | Peter Crosthwaite | default:
|
1013 | 06a1cea5 | Peter Crosthwaite | pl330_fault(ch, PL330_FAULT_OPERAND_INVALID); |
1014 | 06a1cea5 | Peter Crosthwaite | return;
|
1015 | 06a1cea5 | Peter Crosthwaite | } |
1016 | 06a1cea5 | Peter Crosthwaite | |
1017 | 06a1cea5 | Peter Crosthwaite | if (ch->parent->periph_busy[periph_id]) {
|
1018 | 06a1cea5 | Peter Crosthwaite | ch->state = pl330_chan_waiting_periph; |
1019 | 06a1cea5 | Peter Crosthwaite | ch->stall = 1;
|
1020 | 06a1cea5 | Peter Crosthwaite | } else if (ch->state == pl330_chan_waiting_periph) { |
1021 | 06a1cea5 | Peter Crosthwaite | ch->state = pl330_chan_executing; |
1022 | 06a1cea5 | Peter Crosthwaite | } |
1023 | 06a1cea5 | Peter Crosthwaite | } |
1024 | 06a1cea5 | Peter Crosthwaite | |
1025 | 06a1cea5 | Peter Crosthwaite | static void pl330_dmawmb(PL330Chan *ch, uint8_t opcode, |
1026 | 06a1cea5 | Peter Crosthwaite | uint8_t *args, int len)
|
1027 | 06a1cea5 | Peter Crosthwaite | { |
1028 | 06a1cea5 | Peter Crosthwaite | if (pl330_queue_find_insn(&ch->parent->write_queue, ch->tag, false)) { |
1029 | 06a1cea5 | Peter Crosthwaite | ch->state = pl330_chan_at_barrier; |
1030 | 06a1cea5 | Peter Crosthwaite | ch->stall = 1;
|
1031 | 06a1cea5 | Peter Crosthwaite | return;
|
1032 | 06a1cea5 | Peter Crosthwaite | } else {
|
1033 | 06a1cea5 | Peter Crosthwaite | ch->state = pl330_chan_executing; |
1034 | 06a1cea5 | Peter Crosthwaite | } |
1035 | 06a1cea5 | Peter Crosthwaite | } |
1036 | 06a1cea5 | Peter Crosthwaite | |
1037 | 06a1cea5 | Peter Crosthwaite | /* NULL terminated array of the instruction descriptions. */
|
1038 | 06a1cea5 | Peter Crosthwaite | static const PL330InsnDesc insn_desc[] = { |
1039 | 06a1cea5 | Peter Crosthwaite | { .opcode = 0x54, .opmask = 0xFD, .size = 3, .exec = pl330_dmaaddh, }, |
1040 | 06a1cea5 | Peter Crosthwaite | { .opcode = 0x00, .opmask = 0xFF, .size = 1, .exec = pl330_dmaend, }, |
1041 | 06a1cea5 | Peter Crosthwaite | { .opcode = 0x35, .opmask = 0xFF, .size = 2, .exec = pl330_dmaflushp, }, |
1042 | 06a1cea5 | Peter Crosthwaite | { .opcode = 0xA0, .opmask = 0xFD, .size = 6, .exec = pl330_dmago, }, |
1043 | 06a1cea5 | Peter Crosthwaite | { .opcode = 0x04, .opmask = 0xFC, .size = 1, .exec = pl330_dmald, }, |
1044 | 06a1cea5 | Peter Crosthwaite | { .opcode = 0x25, .opmask = 0xFD, .size = 2, .exec = pl330_dmaldp, }, |
1045 | 06a1cea5 | Peter Crosthwaite | { .opcode = 0x20, .opmask = 0xFD, .size = 2, .exec = pl330_dmalp, }, |
1046 | 06a1cea5 | Peter Crosthwaite | /* dmastp must be before dmalpend in this list, because their maps
|
1047 | 06a1cea5 | Peter Crosthwaite | * are overlapping
|
1048 | 06a1cea5 | Peter Crosthwaite | */
|
1049 | 06a1cea5 | Peter Crosthwaite | { .opcode = 0x29, .opmask = 0xFD, .size = 2, .exec = pl330_dmastp, }, |
1050 | 06a1cea5 | Peter Crosthwaite | { .opcode = 0x28, .opmask = 0xE8, .size = 2, .exec = pl330_dmalpend, }, |
1051 | 06a1cea5 | Peter Crosthwaite | { .opcode = 0x01, .opmask = 0xFF, .size = 1, .exec = pl330_dmakill, }, |
1052 | 06a1cea5 | Peter Crosthwaite | { .opcode = 0xBC, .opmask = 0xFF, .size = 6, .exec = pl330_dmamov, }, |
1053 | 06a1cea5 | Peter Crosthwaite | { .opcode = 0x18, .opmask = 0xFF, .size = 1, .exec = pl330_dmanop, }, |
1054 | 06a1cea5 | Peter Crosthwaite | { .opcode = 0x12, .opmask = 0xFF, .size = 1, .exec = pl330_dmarmb, }, |
1055 | 06a1cea5 | Peter Crosthwaite | { .opcode = 0x34, .opmask = 0xFF, .size = 2, .exec = pl330_dmasev, }, |
1056 | 06a1cea5 | Peter Crosthwaite | { .opcode = 0x08, .opmask = 0xFC, .size = 1, .exec = pl330_dmast, }, |
1057 | 06a1cea5 | Peter Crosthwaite | { .opcode = 0x0C, .opmask = 0xFF, .size = 1, .exec = pl330_dmastz, }, |
1058 | 06a1cea5 | Peter Crosthwaite | { .opcode = 0x36, .opmask = 0xFF, .size = 2, .exec = pl330_dmawfe, }, |
1059 | 06a1cea5 | Peter Crosthwaite | { .opcode = 0x30, .opmask = 0xFC, .size = 2, .exec = pl330_dmawfp, }, |
1060 | 06a1cea5 | Peter Crosthwaite | { .opcode = 0x13, .opmask = 0xFF, .size = 1, .exec = pl330_dmawmb, }, |
1061 | 06a1cea5 | Peter Crosthwaite | { .opcode = 0x00, .opmask = 0x00, .size = 0, .exec = NULL, } |
1062 | 06a1cea5 | Peter Crosthwaite | }; |
1063 | 06a1cea5 | Peter Crosthwaite | |
1064 | 06a1cea5 | Peter Crosthwaite | /* Instructions which can be issued via debug registers. */
|
1065 | 06a1cea5 | Peter Crosthwaite | static const PL330InsnDesc debug_insn_desc[] = { |
1066 | 06a1cea5 | Peter Crosthwaite | { .opcode = 0xA0, .opmask = 0xFD, .size = 6, .exec = pl330_dmago, }, |
1067 | 06a1cea5 | Peter Crosthwaite | { .opcode = 0x01, .opmask = 0xFF, .size = 1, .exec = pl330_dmakill, }, |
1068 | 06a1cea5 | Peter Crosthwaite | { .opcode = 0x34, .opmask = 0xFF, .size = 2, .exec = pl330_dmasev, }, |
1069 | 06a1cea5 | Peter Crosthwaite | { .opcode = 0x00, .opmask = 0x00, .size = 0, .exec = NULL, } |
1070 | 06a1cea5 | Peter Crosthwaite | }; |
1071 | 06a1cea5 | Peter Crosthwaite | |
1072 | 06a1cea5 | Peter Crosthwaite | static inline const PL330InsnDesc *pl330_fetch_insn(PL330Chan *ch) |
1073 | 06a1cea5 | Peter Crosthwaite | { |
1074 | 06a1cea5 | Peter Crosthwaite | uint8_t opcode; |
1075 | 06a1cea5 | Peter Crosthwaite | int i;
|
1076 | 06a1cea5 | Peter Crosthwaite | |
1077 | 06a1cea5 | Peter Crosthwaite | dma_memory_read(&dma_context_memory, ch->pc, &opcode, 1);
|
1078 | 06a1cea5 | Peter Crosthwaite | for (i = 0; insn_desc[i].size; i++) { |
1079 | 06a1cea5 | Peter Crosthwaite | if ((opcode & insn_desc[i].opmask) == insn_desc[i].opcode) {
|
1080 | 06a1cea5 | Peter Crosthwaite | return &insn_desc[i];
|
1081 | 06a1cea5 | Peter Crosthwaite | } |
1082 | 06a1cea5 | Peter Crosthwaite | } |
1083 | 06a1cea5 | Peter Crosthwaite | return NULL; |
1084 | 06a1cea5 | Peter Crosthwaite | } |
1085 | 06a1cea5 | Peter Crosthwaite | |
1086 | 06a1cea5 | Peter Crosthwaite | static inline void pl330_exec_insn(PL330Chan *ch, const PL330InsnDesc *insn) |
1087 | 06a1cea5 | Peter Crosthwaite | { |
1088 | 06a1cea5 | Peter Crosthwaite | uint8_t buf[PL330_INSN_MAXSIZE]; |
1089 | 06a1cea5 | Peter Crosthwaite | |
1090 | 06a1cea5 | Peter Crosthwaite | assert(insn->size <= PL330_INSN_MAXSIZE); |
1091 | 06a1cea5 | Peter Crosthwaite | dma_memory_read(&dma_context_memory, ch->pc, buf, insn->size); |
1092 | 06a1cea5 | Peter Crosthwaite | insn->exec(ch, buf[0], &buf[1], insn->size - 1); |
1093 | 06a1cea5 | Peter Crosthwaite | } |
1094 | 06a1cea5 | Peter Crosthwaite | |
1095 | 06a1cea5 | Peter Crosthwaite | static inline void pl330_update_pc(PL330Chan *ch, |
1096 | 06a1cea5 | Peter Crosthwaite | const PL330InsnDesc *insn)
|
1097 | 06a1cea5 | Peter Crosthwaite | { |
1098 | 06a1cea5 | Peter Crosthwaite | ch->pc += insn->size; |
1099 | 06a1cea5 | Peter Crosthwaite | } |
1100 | 06a1cea5 | Peter Crosthwaite | |
1101 | 06a1cea5 | Peter Crosthwaite | /* Try to execute current instruction in channel CH. Number of executed
|
1102 | 06a1cea5 | Peter Crosthwaite | instructions is returned (0 or 1). */
|
1103 | 06a1cea5 | Peter Crosthwaite | static int pl330_chan_exec(PL330Chan *ch) |
1104 | 06a1cea5 | Peter Crosthwaite | { |
1105 | 06a1cea5 | Peter Crosthwaite | const PL330InsnDesc *insn;
|
1106 | 06a1cea5 | Peter Crosthwaite | |
1107 | 06a1cea5 | Peter Crosthwaite | if (ch->state != pl330_chan_executing &&
|
1108 | 06a1cea5 | Peter Crosthwaite | ch->state != pl330_chan_waiting_periph && |
1109 | 06a1cea5 | Peter Crosthwaite | ch->state != pl330_chan_at_barrier && |
1110 | 06a1cea5 | Peter Crosthwaite | ch->state != pl330_chan_waiting_event) { |
1111 | 06a1cea5 | Peter Crosthwaite | DB_PRINT("%d\n", ch->state);
|
1112 | 06a1cea5 | Peter Crosthwaite | return 0; |
1113 | 06a1cea5 | Peter Crosthwaite | } |
1114 | 06a1cea5 | Peter Crosthwaite | ch->stall = 0;
|
1115 | 06a1cea5 | Peter Crosthwaite | insn = pl330_fetch_insn(ch); |
1116 | 06a1cea5 | Peter Crosthwaite | if (!insn) {
|
1117 | 06a1cea5 | Peter Crosthwaite | DB_PRINT("pl330 undefined instruction\n");
|
1118 | 06a1cea5 | Peter Crosthwaite | pl330_fault(ch, PL330_FAULT_UNDEF_INSTR); |
1119 | 06a1cea5 | Peter Crosthwaite | return 0; |
1120 | 06a1cea5 | Peter Crosthwaite | } |
1121 | 06a1cea5 | Peter Crosthwaite | pl330_exec_insn(ch, insn); |
1122 | 06a1cea5 | Peter Crosthwaite | if (!ch->stall) {
|
1123 | 06a1cea5 | Peter Crosthwaite | pl330_update_pc(ch, insn); |
1124 | 06a1cea5 | Peter Crosthwaite | ch->watchdog_timer = 0;
|
1125 | 06a1cea5 | Peter Crosthwaite | return 1; |
1126 | 06a1cea5 | Peter Crosthwaite | /* WDT only active in exec state */
|
1127 | 06a1cea5 | Peter Crosthwaite | } else if (ch->state == pl330_chan_executing) { |
1128 | 06a1cea5 | Peter Crosthwaite | ch->watchdog_timer++; |
1129 | 06a1cea5 | Peter Crosthwaite | if (ch->watchdog_timer >= PL330_WATCHDOG_LIMIT) {
|
1130 | 06a1cea5 | Peter Crosthwaite | pl330_fault(ch, PL330_FAULT_LOCKUP_ERR); |
1131 | 06a1cea5 | Peter Crosthwaite | } |
1132 | 06a1cea5 | Peter Crosthwaite | } |
1133 | 06a1cea5 | Peter Crosthwaite | return 0; |
1134 | 06a1cea5 | Peter Crosthwaite | } |
1135 | 06a1cea5 | Peter Crosthwaite | |
1136 | 06a1cea5 | Peter Crosthwaite | /* Try to execute 1 instruction in each channel, one instruction from read
|
1137 | 06a1cea5 | Peter Crosthwaite | queue and one instruction from write queue. Number of successfully executed
|
1138 | 06a1cea5 | Peter Crosthwaite | instructions is returned. */
|
1139 | 06a1cea5 | Peter Crosthwaite | static int pl330_exec_cycle(PL330Chan *channel) |
1140 | 06a1cea5 | Peter Crosthwaite | { |
1141 | 06a1cea5 | Peter Crosthwaite | PL330State *s = channel->parent; |
1142 | 06a1cea5 | Peter Crosthwaite | PL330QueueEntry *q; |
1143 | 06a1cea5 | Peter Crosthwaite | int i;
|
1144 | 06a1cea5 | Peter Crosthwaite | int num_exec = 0; |
1145 | 06a1cea5 | Peter Crosthwaite | int fifo_res = 0; |
1146 | 06a1cea5 | Peter Crosthwaite | uint8_t buf[PL330_MAX_BURST_LEN]; |
1147 | 06a1cea5 | Peter Crosthwaite | |
1148 | 06a1cea5 | Peter Crosthwaite | /* Execute one instruction in each channel */
|
1149 | 06a1cea5 | Peter Crosthwaite | num_exec += pl330_chan_exec(channel); |
1150 | 06a1cea5 | Peter Crosthwaite | |
1151 | 06a1cea5 | Peter Crosthwaite | /* Execute one instruction from read queue */
|
1152 | 06a1cea5 | Peter Crosthwaite | q = pl330_queue_find_insn(&s->read_queue, PL330_UNTAGGED, true);
|
1153 | 06a1cea5 | Peter Crosthwaite | if (q != NULL && q->len <= pl330_fifo_num_free(&s->fifo)) { |
1154 | 06a1cea5 | Peter Crosthwaite | int len = q->len - (q->addr & (q->len - 1)); |
1155 | 06a1cea5 | Peter Crosthwaite | |
1156 | 06a1cea5 | Peter Crosthwaite | dma_memory_read(&dma_context_memory, q->addr, buf, len); |
1157 | 06a1cea5 | Peter Crosthwaite | if (PL330_ERR_DEBUG > 1) { |
1158 | 06a1cea5 | Peter Crosthwaite | DB_PRINT("PL330 read from memory @%08x (size = %08x):\n",
|
1159 | 06a1cea5 | Peter Crosthwaite | q->addr, len); |
1160 | 3568ac2a | Ed Maste | qemu_hexdump((char *)buf, stderr, "", len); |
1161 | 06a1cea5 | Peter Crosthwaite | } |
1162 | 06a1cea5 | Peter Crosthwaite | fifo_res = pl330_fifo_push(&s->fifo, buf, len, q->tag); |
1163 | 06a1cea5 | Peter Crosthwaite | if (fifo_res == PL330_FIFO_OK) {
|
1164 | 06a1cea5 | Peter Crosthwaite | if (q->inc) {
|
1165 | 06a1cea5 | Peter Crosthwaite | q->addr += len; |
1166 | 06a1cea5 | Peter Crosthwaite | } |
1167 | 06a1cea5 | Peter Crosthwaite | q->n--; |
1168 | 06a1cea5 | Peter Crosthwaite | if (!q->n) {
|
1169 | 06a1cea5 | Peter Crosthwaite | pl330_queue_remove_insn(&s->read_queue, q); |
1170 | 06a1cea5 | Peter Crosthwaite | } |
1171 | 06a1cea5 | Peter Crosthwaite | num_exec++; |
1172 | 06a1cea5 | Peter Crosthwaite | } |
1173 | 06a1cea5 | Peter Crosthwaite | } |
1174 | 06a1cea5 | Peter Crosthwaite | |
1175 | 06a1cea5 | Peter Crosthwaite | /* Execute one instruction from write queue. */
|
1176 | 06a1cea5 | Peter Crosthwaite | q = pl330_queue_find_insn(&s->write_queue, pl330_fifo_tag(&s->fifo), true);
|
1177 | 06a1cea5 | Peter Crosthwaite | if (q != NULL) { |
1178 | 06a1cea5 | Peter Crosthwaite | int len = q->len - (q->addr & (q->len - 1)); |
1179 | 06a1cea5 | Peter Crosthwaite | |
1180 | 06a1cea5 | Peter Crosthwaite | if (q->z) {
|
1181 | 06a1cea5 | Peter Crosthwaite | for (i = 0; i < len; i++) { |
1182 | 06a1cea5 | Peter Crosthwaite | buf[i] = 0;
|
1183 | 06a1cea5 | Peter Crosthwaite | } |
1184 | 06a1cea5 | Peter Crosthwaite | } else {
|
1185 | 06a1cea5 | Peter Crosthwaite | fifo_res = pl330_fifo_get(&s->fifo, buf, len, q->tag); |
1186 | 06a1cea5 | Peter Crosthwaite | } |
1187 | 06a1cea5 | Peter Crosthwaite | if (fifo_res == PL330_FIFO_OK || q->z) {
|
1188 | 06a1cea5 | Peter Crosthwaite | dma_memory_write(&dma_context_memory, q->addr, buf, len); |
1189 | 06a1cea5 | Peter Crosthwaite | if (PL330_ERR_DEBUG > 1) { |
1190 | 06a1cea5 | Peter Crosthwaite | DB_PRINT("PL330 read from memory @%08x (size = %08x):\n",
|
1191 | 06a1cea5 | Peter Crosthwaite | q->addr, len); |
1192 | 3568ac2a | Ed Maste | qemu_hexdump((char *)buf, stderr, "", len); |
1193 | 06a1cea5 | Peter Crosthwaite | } |
1194 | 06a1cea5 | Peter Crosthwaite | if (q->inc) {
|
1195 | 06a1cea5 | Peter Crosthwaite | q->addr += len; |
1196 | 06a1cea5 | Peter Crosthwaite | } |
1197 | 06a1cea5 | Peter Crosthwaite | num_exec++; |
1198 | 06a1cea5 | Peter Crosthwaite | } else if (fifo_res == PL330_FIFO_STALL) { |
1199 | 06a1cea5 | Peter Crosthwaite | pl330_fault(&channel->parent->chan[q->tag], |
1200 | 06a1cea5 | Peter Crosthwaite | PL330_FAULT_FIFOEMPTY_ERR); |
1201 | 06a1cea5 | Peter Crosthwaite | } |
1202 | 06a1cea5 | Peter Crosthwaite | q->n--; |
1203 | 06a1cea5 | Peter Crosthwaite | if (!q->n) {
|
1204 | 06a1cea5 | Peter Crosthwaite | pl330_queue_remove_insn(&s->write_queue, q); |
1205 | 06a1cea5 | Peter Crosthwaite | } |
1206 | 06a1cea5 | Peter Crosthwaite | } |
1207 | 06a1cea5 | Peter Crosthwaite | |
1208 | 06a1cea5 | Peter Crosthwaite | return num_exec;
|
1209 | 06a1cea5 | Peter Crosthwaite | } |
1210 | 06a1cea5 | Peter Crosthwaite | |
1211 | 06a1cea5 | Peter Crosthwaite | static int pl330_exec_channel(PL330Chan *channel) |
1212 | 06a1cea5 | Peter Crosthwaite | { |
1213 | 06a1cea5 | Peter Crosthwaite | int insr_exec = 0; |
1214 | 06a1cea5 | Peter Crosthwaite | |
1215 | 06a1cea5 | Peter Crosthwaite | /* TODO: Is it all right to execute everything or should we do per-cycle
|
1216 | 06a1cea5 | Peter Crosthwaite | simulation? */
|
1217 | 06a1cea5 | Peter Crosthwaite | while (pl330_exec_cycle(channel)) {
|
1218 | 06a1cea5 | Peter Crosthwaite | insr_exec++; |
1219 | 06a1cea5 | Peter Crosthwaite | } |
1220 | 06a1cea5 | Peter Crosthwaite | |
1221 | 06a1cea5 | Peter Crosthwaite | /* Detect deadlock */
|
1222 | 06a1cea5 | Peter Crosthwaite | if (channel->state == pl330_chan_executing) {
|
1223 | 06a1cea5 | Peter Crosthwaite | pl330_fault(channel, PL330_FAULT_LOCKUP_ERR); |
1224 | 06a1cea5 | Peter Crosthwaite | } |
1225 | 06a1cea5 | Peter Crosthwaite | /* Situation when one of the queues has deadlocked but all channels
|
1226 | 06a1cea5 | Peter Crosthwaite | * have finished their programs should be impossible.
|
1227 | 06a1cea5 | Peter Crosthwaite | */
|
1228 | 06a1cea5 | Peter Crosthwaite | |
1229 | 06a1cea5 | Peter Crosthwaite | return insr_exec;
|
1230 | 06a1cea5 | Peter Crosthwaite | } |
1231 | 06a1cea5 | Peter Crosthwaite | |
1232 | 06a1cea5 | Peter Crosthwaite | static inline void pl330_exec(PL330State *s) |
1233 | 06a1cea5 | Peter Crosthwaite | { |
1234 | 06a1cea5 | Peter Crosthwaite | DB_PRINT("\n");
|
1235 | 06a1cea5 | Peter Crosthwaite | int i, insr_exec;
|
1236 | 06a1cea5 | Peter Crosthwaite | do {
|
1237 | 06a1cea5 | Peter Crosthwaite | insr_exec = pl330_exec_channel(&s->manager); |
1238 | 06a1cea5 | Peter Crosthwaite | |
1239 | 06a1cea5 | Peter Crosthwaite | for (i = 0; i < s->num_chnls; i++) { |
1240 | 06a1cea5 | Peter Crosthwaite | insr_exec += pl330_exec_channel(&s->chan[i]); |
1241 | 06a1cea5 | Peter Crosthwaite | } |
1242 | 06a1cea5 | Peter Crosthwaite | } while (insr_exec);
|
1243 | 06a1cea5 | Peter Crosthwaite | } |
1244 | 06a1cea5 | Peter Crosthwaite | |
1245 | 06a1cea5 | Peter Crosthwaite | static void pl330_exec_cycle_timer(void *opaque) |
1246 | 06a1cea5 | Peter Crosthwaite | { |
1247 | 06a1cea5 | Peter Crosthwaite | PL330State *s = (PL330State *)opaque; |
1248 | 06a1cea5 | Peter Crosthwaite | pl330_exec(s); |
1249 | 06a1cea5 | Peter Crosthwaite | } |
1250 | 06a1cea5 | Peter Crosthwaite | |
1251 | 06a1cea5 | Peter Crosthwaite | /* Stop or restore dma operations */
|
1252 | 06a1cea5 | Peter Crosthwaite | |
1253 | 06a1cea5 | Peter Crosthwaite | static void pl330_dma_stop_irq(void *opaque, int irq, int level) |
1254 | 06a1cea5 | Peter Crosthwaite | { |
1255 | 06a1cea5 | Peter Crosthwaite | PL330State *s = (PL330State *)opaque; |
1256 | 06a1cea5 | Peter Crosthwaite | |
1257 | 06a1cea5 | Peter Crosthwaite | if (s->periph_busy[irq] != level) {
|
1258 | 06a1cea5 | Peter Crosthwaite | s->periph_busy[irq] = level; |
1259 | 06a1cea5 | Peter Crosthwaite | qemu_mod_timer(s->timer, qemu_get_clock_ns(vm_clock)); |
1260 | 06a1cea5 | Peter Crosthwaite | } |
1261 | 06a1cea5 | Peter Crosthwaite | } |
1262 | 06a1cea5 | Peter Crosthwaite | |
1263 | 06a1cea5 | Peter Crosthwaite | static void pl330_debug_exec(PL330State *s) |
1264 | 06a1cea5 | Peter Crosthwaite | { |
1265 | 06a1cea5 | Peter Crosthwaite | uint8_t args[5];
|
1266 | 06a1cea5 | Peter Crosthwaite | uint8_t opcode; |
1267 | 06a1cea5 | Peter Crosthwaite | uint8_t chan_id; |
1268 | 06a1cea5 | Peter Crosthwaite | int i;
|
1269 | 06a1cea5 | Peter Crosthwaite | PL330Chan *ch; |
1270 | 06a1cea5 | Peter Crosthwaite | const PL330InsnDesc *insn;
|
1271 | 06a1cea5 | Peter Crosthwaite | |
1272 | 06a1cea5 | Peter Crosthwaite | s->debug_status = 1;
|
1273 | 06a1cea5 | Peter Crosthwaite | chan_id = (s->dbg[0] >> 8) & 0x07; |
1274 | 06a1cea5 | Peter Crosthwaite | opcode = (s->dbg[0] >> 16) & 0xff; |
1275 | 06a1cea5 | Peter Crosthwaite | args[0] = (s->dbg[0] >> 24) & 0xff; |
1276 | 06a1cea5 | Peter Crosthwaite | args[1] = (s->dbg[1] >> 0) & 0xff; |
1277 | 06a1cea5 | Peter Crosthwaite | args[2] = (s->dbg[1] >> 8) & 0xff; |
1278 | 06a1cea5 | Peter Crosthwaite | args[3] = (s->dbg[1] >> 16) & 0xff; |
1279 | 06a1cea5 | Peter Crosthwaite | args[4] = (s->dbg[1] >> 24) & 0xff; |
1280 | 06a1cea5 | Peter Crosthwaite | DB_PRINT("chan id: %d\n", chan_id);
|
1281 | 06a1cea5 | Peter Crosthwaite | if (s->dbg[0] & 1) { |
1282 | 06a1cea5 | Peter Crosthwaite | ch = &s->chan[chan_id]; |
1283 | 06a1cea5 | Peter Crosthwaite | } else {
|
1284 | 06a1cea5 | Peter Crosthwaite | ch = &s->manager; |
1285 | 06a1cea5 | Peter Crosthwaite | } |
1286 | 06a1cea5 | Peter Crosthwaite | insn = NULL;
|
1287 | 06a1cea5 | Peter Crosthwaite | for (i = 0; debug_insn_desc[i].size; i++) { |
1288 | 06a1cea5 | Peter Crosthwaite | if ((opcode & debug_insn_desc[i].opmask) == debug_insn_desc[i].opcode) {
|
1289 | 06a1cea5 | Peter Crosthwaite | insn = &debug_insn_desc[i]; |
1290 | 06a1cea5 | Peter Crosthwaite | } |
1291 | 06a1cea5 | Peter Crosthwaite | } |
1292 | 06a1cea5 | Peter Crosthwaite | if (!insn) {
|
1293 | 06a1cea5 | Peter Crosthwaite | pl330_fault(ch, PL330_FAULT_UNDEF_INSTR | PL330_FAULT_DBG_INSTR); |
1294 | 06a1cea5 | Peter Crosthwaite | return ;
|
1295 | 06a1cea5 | Peter Crosthwaite | } |
1296 | 06a1cea5 | Peter Crosthwaite | ch->stall = 0;
|
1297 | 06a1cea5 | Peter Crosthwaite | insn->exec(ch, opcode, args, insn->size - 1);
|
1298 | 06a1cea5 | Peter Crosthwaite | if (ch->fault_type) {
|
1299 | 06a1cea5 | Peter Crosthwaite | ch->fault_type |= PL330_FAULT_DBG_INSTR; |
1300 | 06a1cea5 | Peter Crosthwaite | } |
1301 | 06a1cea5 | Peter Crosthwaite | if (ch->stall) {
|
1302 | 06a1cea5 | Peter Crosthwaite | qemu_log_mask(LOG_UNIMP, "pl330: stall of debug instruction not "
|
1303 | 06a1cea5 | Peter Crosthwaite | "implemented\n");
|
1304 | 06a1cea5 | Peter Crosthwaite | } |
1305 | 06a1cea5 | Peter Crosthwaite | s->debug_status = 0;
|
1306 | 06a1cea5 | Peter Crosthwaite | } |
1307 | 06a1cea5 | Peter Crosthwaite | |
1308 | 06a1cea5 | Peter Crosthwaite | /* IOMEM mapped registers */
|
1309 | 06a1cea5 | Peter Crosthwaite | |
1310 | 06a1cea5 | Peter Crosthwaite | static void pl330_iomem_write(void *opaque, hwaddr offset, |
1311 | 06a1cea5 | Peter Crosthwaite | uint64_t value, unsigned size)
|
1312 | 06a1cea5 | Peter Crosthwaite | { |
1313 | 06a1cea5 | Peter Crosthwaite | PL330State *s = (PL330State *) opaque; |
1314 | 06a1cea5 | Peter Crosthwaite | uint32_t i; |
1315 | 06a1cea5 | Peter Crosthwaite | |
1316 | 06a1cea5 | Peter Crosthwaite | DB_PRINT("addr: %08x data: %08x\n", (unsigned)offset, (unsigned)value); |
1317 | 06a1cea5 | Peter Crosthwaite | |
1318 | 06a1cea5 | Peter Crosthwaite | switch (offset) {
|
1319 | 06a1cea5 | Peter Crosthwaite | case PL330_REG_INTEN:
|
1320 | 06a1cea5 | Peter Crosthwaite | s->inten = value; |
1321 | 06a1cea5 | Peter Crosthwaite | break;
|
1322 | 06a1cea5 | Peter Crosthwaite | case PL330_REG_INTCLR:
|
1323 | 06a1cea5 | Peter Crosthwaite | for (i = 0; i < s->num_events; i++) { |
1324 | 06a1cea5 | Peter Crosthwaite | if (s->int_status & s->inten & value & (1 << i)) { |
1325 | 06a1cea5 | Peter Crosthwaite | DB_PRINT("event interrupt lowered %d\n", i);
|
1326 | 06a1cea5 | Peter Crosthwaite | qemu_irq_lower(s->irq[i]); |
1327 | 06a1cea5 | Peter Crosthwaite | } |
1328 | 06a1cea5 | Peter Crosthwaite | } |
1329 | 06a1cea5 | Peter Crosthwaite | s->ev_status &= ~(value & s->inten); |
1330 | 06a1cea5 | Peter Crosthwaite | s->int_status &= ~(value & s->inten); |
1331 | 06a1cea5 | Peter Crosthwaite | break;
|
1332 | 06a1cea5 | Peter Crosthwaite | case PL330_REG_DBGCMD:
|
1333 | 06a1cea5 | Peter Crosthwaite | if ((value & 3) == 0) { |
1334 | 06a1cea5 | Peter Crosthwaite | pl330_debug_exec(s); |
1335 | 06a1cea5 | Peter Crosthwaite | pl330_exec(s); |
1336 | 06a1cea5 | Peter Crosthwaite | } else {
|
1337 | 06a1cea5 | Peter Crosthwaite | qemu_log_mask(LOG_GUEST_ERROR, "pl330: write of illegal value %u "
|
1338 | 06a1cea5 | Peter Crosthwaite | "for offset " TARGET_FMT_plx "\n", (unsigned)value, |
1339 | 06a1cea5 | Peter Crosthwaite | offset); |
1340 | 06a1cea5 | Peter Crosthwaite | } |
1341 | 06a1cea5 | Peter Crosthwaite | break;
|
1342 | 06a1cea5 | Peter Crosthwaite | case PL330_REG_DBGINST0:
|
1343 | 06a1cea5 | Peter Crosthwaite | DB_PRINT("s->dbg[0] = %08x\n", (unsigned)value); |
1344 | 06a1cea5 | Peter Crosthwaite | s->dbg[0] = value;
|
1345 | 06a1cea5 | Peter Crosthwaite | break;
|
1346 | 06a1cea5 | Peter Crosthwaite | case PL330_REG_DBGINST1:
|
1347 | 06a1cea5 | Peter Crosthwaite | DB_PRINT("s->dbg[1] = %08x\n", (unsigned)value); |
1348 | 06a1cea5 | Peter Crosthwaite | s->dbg[1] = value;
|
1349 | 06a1cea5 | Peter Crosthwaite | break;
|
1350 | 06a1cea5 | Peter Crosthwaite | default:
|
1351 | 06a1cea5 | Peter Crosthwaite | qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad write offset " TARGET_FMT_plx
|
1352 | 06a1cea5 | Peter Crosthwaite | "\n", offset);
|
1353 | 06a1cea5 | Peter Crosthwaite | break;
|
1354 | 06a1cea5 | Peter Crosthwaite | } |
1355 | 06a1cea5 | Peter Crosthwaite | } |
1356 | 06a1cea5 | Peter Crosthwaite | |
1357 | 06a1cea5 | Peter Crosthwaite | static inline uint32_t pl330_iomem_read_imp(void *opaque, |
1358 | 06a1cea5 | Peter Crosthwaite | hwaddr offset) |
1359 | 06a1cea5 | Peter Crosthwaite | { |
1360 | 06a1cea5 | Peter Crosthwaite | PL330State *s = (PL330State *)opaque; |
1361 | 06a1cea5 | Peter Crosthwaite | int chan_id;
|
1362 | 06a1cea5 | Peter Crosthwaite | int i;
|
1363 | 06a1cea5 | Peter Crosthwaite | uint32_t res; |
1364 | 06a1cea5 | Peter Crosthwaite | |
1365 | 06a1cea5 | Peter Crosthwaite | if (offset >= PL330_REG_PERIPH_ID && offset < PL330_REG_PERIPH_ID + 32) { |
1366 | 06a1cea5 | Peter Crosthwaite | return pl330_id[(offset - PL330_REG_PERIPH_ID) >> 2]; |
1367 | 06a1cea5 | Peter Crosthwaite | } |
1368 | 06a1cea5 | Peter Crosthwaite | if (offset >= PL330_REG_CR0_BASE && offset < PL330_REG_CR0_BASE + 24) { |
1369 | 06a1cea5 | Peter Crosthwaite | return s->cfg[(offset - PL330_REG_CR0_BASE) >> 2]; |
1370 | 06a1cea5 | Peter Crosthwaite | } |
1371 | 06a1cea5 | Peter Crosthwaite | if (offset >= PL330_REG_CHANCTRL && offset < PL330_REG_DBGSTATUS) {
|
1372 | 06a1cea5 | Peter Crosthwaite | offset -= PL330_REG_CHANCTRL; |
1373 | 06a1cea5 | Peter Crosthwaite | chan_id = offset >> 5;
|
1374 | 06a1cea5 | Peter Crosthwaite | if (chan_id >= s->num_chnls) {
|
1375 | 06a1cea5 | Peter Crosthwaite | qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset "
|
1376 | 06a1cea5 | Peter Crosthwaite | TARGET_FMT_plx "\n", offset);
|
1377 | 06a1cea5 | Peter Crosthwaite | return 0; |
1378 | 06a1cea5 | Peter Crosthwaite | } |
1379 | 06a1cea5 | Peter Crosthwaite | switch (offset & 0x1f) { |
1380 | 06a1cea5 | Peter Crosthwaite | case 0x00: |
1381 | 06a1cea5 | Peter Crosthwaite | return s->chan[chan_id].src;
|
1382 | 06a1cea5 | Peter Crosthwaite | case 0x04: |
1383 | 06a1cea5 | Peter Crosthwaite | return s->chan[chan_id].dst;
|
1384 | 06a1cea5 | Peter Crosthwaite | case 0x08: |
1385 | 06a1cea5 | Peter Crosthwaite | return s->chan[chan_id].control;
|
1386 | 06a1cea5 | Peter Crosthwaite | case 0x0C: |
1387 | 06a1cea5 | Peter Crosthwaite | return s->chan[chan_id].lc[0]; |
1388 | 06a1cea5 | Peter Crosthwaite | case 0x10: |
1389 | 06a1cea5 | Peter Crosthwaite | return s->chan[chan_id].lc[1]; |
1390 | 06a1cea5 | Peter Crosthwaite | default:
|
1391 | 06a1cea5 | Peter Crosthwaite | qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset "
|
1392 | 06a1cea5 | Peter Crosthwaite | TARGET_FMT_plx "\n", offset);
|
1393 | 06a1cea5 | Peter Crosthwaite | return 0; |
1394 | 06a1cea5 | Peter Crosthwaite | } |
1395 | 06a1cea5 | Peter Crosthwaite | } |
1396 | 06a1cea5 | Peter Crosthwaite | if (offset >= PL330_REG_CSR_BASE && offset < 0x400) { |
1397 | 06a1cea5 | Peter Crosthwaite | offset -= PL330_REG_CSR_BASE; |
1398 | 06a1cea5 | Peter Crosthwaite | chan_id = offset >> 3;
|
1399 | 06a1cea5 | Peter Crosthwaite | if (chan_id >= s->num_chnls) {
|
1400 | 06a1cea5 | Peter Crosthwaite | qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset "
|
1401 | 06a1cea5 | Peter Crosthwaite | TARGET_FMT_plx "\n", offset);
|
1402 | 06a1cea5 | Peter Crosthwaite | return 0; |
1403 | 06a1cea5 | Peter Crosthwaite | } |
1404 | 06a1cea5 | Peter Crosthwaite | switch ((offset >> 2) & 1) { |
1405 | 06a1cea5 | Peter Crosthwaite | case 0x0: |
1406 | 06a1cea5 | Peter Crosthwaite | res = (s->chan[chan_id].ns << 21) |
|
1407 | 06a1cea5 | Peter Crosthwaite | (s->chan[chan_id].wakeup << 4) |
|
1408 | 06a1cea5 | Peter Crosthwaite | (s->chan[chan_id].state) | |
1409 | 06a1cea5 | Peter Crosthwaite | (s->chan[chan_id].wfp_sbp << 14);
|
1410 | 06a1cea5 | Peter Crosthwaite | return res;
|
1411 | 06a1cea5 | Peter Crosthwaite | case 0x1: |
1412 | 06a1cea5 | Peter Crosthwaite | return s->chan[chan_id].pc;
|
1413 | 06a1cea5 | Peter Crosthwaite | default:
|
1414 | 06a1cea5 | Peter Crosthwaite | qemu_log_mask(LOG_GUEST_ERROR, "pl330: read error\n");
|
1415 | 06a1cea5 | Peter Crosthwaite | return 0; |
1416 | 06a1cea5 | Peter Crosthwaite | } |
1417 | 06a1cea5 | Peter Crosthwaite | } |
1418 | 06a1cea5 | Peter Crosthwaite | if (offset >= PL330_REG_FTR_BASE && offset < 0x100) { |
1419 | 06a1cea5 | Peter Crosthwaite | offset -= PL330_REG_FTR_BASE; |
1420 | 06a1cea5 | Peter Crosthwaite | chan_id = offset >> 2;
|
1421 | 06a1cea5 | Peter Crosthwaite | if (chan_id >= s->num_chnls) {
|
1422 | 06a1cea5 | Peter Crosthwaite | qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset "
|
1423 | 06a1cea5 | Peter Crosthwaite | TARGET_FMT_plx "\n", offset);
|
1424 | 06a1cea5 | Peter Crosthwaite | return 0; |
1425 | 06a1cea5 | Peter Crosthwaite | } |
1426 | 06a1cea5 | Peter Crosthwaite | return s->chan[chan_id].fault_type;
|
1427 | 06a1cea5 | Peter Crosthwaite | } |
1428 | 06a1cea5 | Peter Crosthwaite | switch (offset) {
|
1429 | 06a1cea5 | Peter Crosthwaite | case PL330_REG_DSR:
|
1430 | 06a1cea5 | Peter Crosthwaite | return (s->manager.ns << 9) | (s->manager.wakeup << 4) | |
1431 | 06a1cea5 | Peter Crosthwaite | (s->manager.state & 0xf);
|
1432 | 06a1cea5 | Peter Crosthwaite | case PL330_REG_DPC:
|
1433 | 06a1cea5 | Peter Crosthwaite | return s->manager.pc;
|
1434 | 06a1cea5 | Peter Crosthwaite | case PL330_REG_INTEN:
|
1435 | 06a1cea5 | Peter Crosthwaite | return s->inten;
|
1436 | 06a1cea5 | Peter Crosthwaite | case PL330_REG_INT_EVENT_RIS:
|
1437 | 06a1cea5 | Peter Crosthwaite | return s->ev_status;
|
1438 | 06a1cea5 | Peter Crosthwaite | case PL330_REG_INTMIS:
|
1439 | 06a1cea5 | Peter Crosthwaite | return s->int_status;
|
1440 | 06a1cea5 | Peter Crosthwaite | case PL330_REG_INTCLR:
|
1441 | 06a1cea5 | Peter Crosthwaite | /* Documentation says that we can't read this register
|
1442 | 06a1cea5 | Peter Crosthwaite | * but linux kernel does it
|
1443 | 06a1cea5 | Peter Crosthwaite | */
|
1444 | 06a1cea5 | Peter Crosthwaite | return 0; |
1445 | 06a1cea5 | Peter Crosthwaite | case PL330_REG_FSRD:
|
1446 | 06a1cea5 | Peter Crosthwaite | return s->manager.state ? 1 : 0; |
1447 | 06a1cea5 | Peter Crosthwaite | case PL330_REG_FSRC:
|
1448 | 06a1cea5 | Peter Crosthwaite | res = 0;
|
1449 | 06a1cea5 | Peter Crosthwaite | for (i = 0; i < s->num_chnls; i++) { |
1450 | 06a1cea5 | Peter Crosthwaite | if (s->chan[i].state == pl330_chan_fault ||
|
1451 | 06a1cea5 | Peter Crosthwaite | s->chan[i].state == pl330_chan_fault_completing) { |
1452 | 06a1cea5 | Peter Crosthwaite | res |= 1 << i;
|
1453 | 06a1cea5 | Peter Crosthwaite | } |
1454 | 06a1cea5 | Peter Crosthwaite | } |
1455 | 06a1cea5 | Peter Crosthwaite | return res;
|
1456 | 06a1cea5 | Peter Crosthwaite | case PL330_REG_FTRD:
|
1457 | 06a1cea5 | Peter Crosthwaite | return s->manager.fault_type;
|
1458 | 06a1cea5 | Peter Crosthwaite | case PL330_REG_DBGSTATUS:
|
1459 | 06a1cea5 | Peter Crosthwaite | return s->debug_status;
|
1460 | 06a1cea5 | Peter Crosthwaite | default:
|
1461 | 06a1cea5 | Peter Crosthwaite | qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset "
|
1462 | 06a1cea5 | Peter Crosthwaite | TARGET_FMT_plx "\n", offset);
|
1463 | 06a1cea5 | Peter Crosthwaite | } |
1464 | 06a1cea5 | Peter Crosthwaite | return 0; |
1465 | 06a1cea5 | Peter Crosthwaite | } |
1466 | 06a1cea5 | Peter Crosthwaite | |
1467 | 06a1cea5 | Peter Crosthwaite | static uint64_t pl330_iomem_read(void *opaque, hwaddr offset, |
1468 | 06a1cea5 | Peter Crosthwaite | unsigned size)
|
1469 | 06a1cea5 | Peter Crosthwaite | { |
1470 | 06a1cea5 | Peter Crosthwaite | int ret = pl330_iomem_read_imp(opaque, offset);
|
1471 | 06a1cea5 | Peter Crosthwaite | DB_PRINT("addr: %08x data: %08x\n", (unsigned)offset, ret); |
1472 | 06a1cea5 | Peter Crosthwaite | return ret;
|
1473 | 06a1cea5 | Peter Crosthwaite | } |
1474 | 06a1cea5 | Peter Crosthwaite | |
1475 | 06a1cea5 | Peter Crosthwaite | static const MemoryRegionOps pl330_ops = { |
1476 | 06a1cea5 | Peter Crosthwaite | .read = pl330_iomem_read, |
1477 | 06a1cea5 | Peter Crosthwaite | .write = pl330_iomem_write, |
1478 | 06a1cea5 | Peter Crosthwaite | .endianness = DEVICE_NATIVE_ENDIAN, |
1479 | 06a1cea5 | Peter Crosthwaite | .impl = { |
1480 | 06a1cea5 | Peter Crosthwaite | .min_access_size = 4,
|
1481 | 06a1cea5 | Peter Crosthwaite | .max_access_size = 4,
|
1482 | 06a1cea5 | Peter Crosthwaite | } |
1483 | 06a1cea5 | Peter Crosthwaite | }; |
1484 | 06a1cea5 | Peter Crosthwaite | |
1485 | 06a1cea5 | Peter Crosthwaite | /* Controller logic and initialization */
|
1486 | 06a1cea5 | Peter Crosthwaite | |
1487 | 06a1cea5 | Peter Crosthwaite | static void pl330_chan_reset(PL330Chan *ch) |
1488 | 06a1cea5 | Peter Crosthwaite | { |
1489 | 06a1cea5 | Peter Crosthwaite | ch->src = 0;
|
1490 | 06a1cea5 | Peter Crosthwaite | ch->dst = 0;
|
1491 | 06a1cea5 | Peter Crosthwaite | ch->pc = 0;
|
1492 | 06a1cea5 | Peter Crosthwaite | ch->state = pl330_chan_stopped; |
1493 | 06a1cea5 | Peter Crosthwaite | ch->watchdog_timer = 0;
|
1494 | 06a1cea5 | Peter Crosthwaite | ch->stall = 0;
|
1495 | 06a1cea5 | Peter Crosthwaite | ch->control = 0;
|
1496 | 06a1cea5 | Peter Crosthwaite | ch->status = 0;
|
1497 | 06a1cea5 | Peter Crosthwaite | ch->fault_type = 0;
|
1498 | 06a1cea5 | Peter Crosthwaite | } |
1499 | 06a1cea5 | Peter Crosthwaite | |
1500 | 06a1cea5 | Peter Crosthwaite | static void pl330_reset(DeviceState *d) |
1501 | 06a1cea5 | Peter Crosthwaite | { |
1502 | 06a1cea5 | Peter Crosthwaite | int i;
|
1503 | 06a1cea5 | Peter Crosthwaite | PL330State *s = PL330(d); |
1504 | 06a1cea5 | Peter Crosthwaite | |
1505 | 06a1cea5 | Peter Crosthwaite | s->inten = 0;
|
1506 | 06a1cea5 | Peter Crosthwaite | s->int_status = 0;
|
1507 | 06a1cea5 | Peter Crosthwaite | s->ev_status = 0;
|
1508 | 06a1cea5 | Peter Crosthwaite | s->debug_status = 0;
|
1509 | 06a1cea5 | Peter Crosthwaite | s->num_faulting = 0;
|
1510 | 06a1cea5 | Peter Crosthwaite | s->manager.ns = s->mgr_ns_at_rst; |
1511 | 06a1cea5 | Peter Crosthwaite | pl330_fifo_reset(&s->fifo); |
1512 | 06a1cea5 | Peter Crosthwaite | pl330_queue_reset(&s->read_queue); |
1513 | 06a1cea5 | Peter Crosthwaite | pl330_queue_reset(&s->write_queue); |
1514 | 06a1cea5 | Peter Crosthwaite | |
1515 | 06a1cea5 | Peter Crosthwaite | for (i = 0; i < s->num_chnls; i++) { |
1516 | 06a1cea5 | Peter Crosthwaite | pl330_chan_reset(&s->chan[i]); |
1517 | 06a1cea5 | Peter Crosthwaite | } |
1518 | 06a1cea5 | Peter Crosthwaite | for (i = 0; i < s->num_periph_req; i++) { |
1519 | 06a1cea5 | Peter Crosthwaite | s->periph_busy[i] = 0;
|
1520 | 06a1cea5 | Peter Crosthwaite | } |
1521 | 06a1cea5 | Peter Crosthwaite | |
1522 | 06a1cea5 | Peter Crosthwaite | qemu_del_timer(s->timer); |
1523 | 06a1cea5 | Peter Crosthwaite | } |
1524 | 06a1cea5 | Peter Crosthwaite | |
1525 | 06a1cea5 | Peter Crosthwaite | static void pl330_realize(DeviceState *dev, Error **errp) |
1526 | 06a1cea5 | Peter Crosthwaite | { |
1527 | 06a1cea5 | Peter Crosthwaite | int i;
|
1528 | 06a1cea5 | Peter Crosthwaite | PL330State *s = PL330(dev); |
1529 | 06a1cea5 | Peter Crosthwaite | |
1530 | 06a1cea5 | Peter Crosthwaite | sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq_abort); |
1531 | 06a1cea5 | Peter Crosthwaite | memory_region_init_io(&s->iomem, &pl330_ops, s, "dma", PL330_IOMEM_SIZE);
|
1532 | 06a1cea5 | Peter Crosthwaite | sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); |
1533 | 06a1cea5 | Peter Crosthwaite | |
1534 | 06a1cea5 | Peter Crosthwaite | s->timer = qemu_new_timer_ns(vm_clock, pl330_exec_cycle_timer, s); |
1535 | 06a1cea5 | Peter Crosthwaite | |
1536 | 06a1cea5 | Peter Crosthwaite | s->cfg[0] = (s->mgr_ns_at_rst ? 0x4 : 0) | |
1537 | 06a1cea5 | Peter Crosthwaite | (s->num_periph_req > 0 ? 1 : 0) | |
1538 | 06a1cea5 | Peter Crosthwaite | ((s->num_chnls - 1) & 0x7) << 4 | |
1539 | 06a1cea5 | Peter Crosthwaite | ((s->num_periph_req - 1) & 0x1f) << 12 | |
1540 | 06a1cea5 | Peter Crosthwaite | ((s->num_events - 1) & 0x1f) << 17; |
1541 | 06a1cea5 | Peter Crosthwaite | |
1542 | 06a1cea5 | Peter Crosthwaite | switch (s->i_cache_len) {
|
1543 | 06a1cea5 | Peter Crosthwaite | case (4): |
1544 | 06a1cea5 | Peter Crosthwaite | s->cfg[1] |= 2; |
1545 | 06a1cea5 | Peter Crosthwaite | break;
|
1546 | 06a1cea5 | Peter Crosthwaite | case (8): |
1547 | 06a1cea5 | Peter Crosthwaite | s->cfg[1] |= 3; |
1548 | 06a1cea5 | Peter Crosthwaite | break;
|
1549 | 06a1cea5 | Peter Crosthwaite | case (16): |
1550 | 06a1cea5 | Peter Crosthwaite | s->cfg[1] |= 4; |
1551 | 06a1cea5 | Peter Crosthwaite | break;
|
1552 | 06a1cea5 | Peter Crosthwaite | case (32): |
1553 | 06a1cea5 | Peter Crosthwaite | s->cfg[1] |= 5; |
1554 | 06a1cea5 | Peter Crosthwaite | break;
|
1555 | 06a1cea5 | Peter Crosthwaite | default:
|
1556 | 06a1cea5 | Peter Crosthwaite | error_setg(errp, "Bad value for i-cache_len property: %d\n",
|
1557 | 06a1cea5 | Peter Crosthwaite | s->i_cache_len); |
1558 | 06a1cea5 | Peter Crosthwaite | return;
|
1559 | 06a1cea5 | Peter Crosthwaite | } |
1560 | 06a1cea5 | Peter Crosthwaite | s->cfg[1] |= ((s->num_i_cache_lines - 1) & 0xf) << 4; |
1561 | 06a1cea5 | Peter Crosthwaite | |
1562 | 06a1cea5 | Peter Crosthwaite | s->chan = g_new0(PL330Chan, s->num_chnls); |
1563 | 06a1cea5 | Peter Crosthwaite | s->hi_seqn = g_new0(uint8_t, s->num_chnls); |
1564 | 06a1cea5 | Peter Crosthwaite | s->lo_seqn = g_new0(uint8_t, s->num_chnls); |
1565 | 06a1cea5 | Peter Crosthwaite | for (i = 0; i < s->num_chnls; i++) { |
1566 | 06a1cea5 | Peter Crosthwaite | s->chan[i].parent = s; |
1567 | 06a1cea5 | Peter Crosthwaite | s->chan[i].tag = (uint8_t)i; |
1568 | 06a1cea5 | Peter Crosthwaite | } |
1569 | 06a1cea5 | Peter Crosthwaite | s->manager.parent = s; |
1570 | 06a1cea5 | Peter Crosthwaite | s->manager.tag = s->num_chnls; |
1571 | 06a1cea5 | Peter Crosthwaite | s->manager.is_manager = true;
|
1572 | 06a1cea5 | Peter Crosthwaite | |
1573 | 06a1cea5 | Peter Crosthwaite | s->irq = g_new0(qemu_irq, s->num_events); |
1574 | 06a1cea5 | Peter Crosthwaite | for (i = 0; i < s->num_events; i++) { |
1575 | 06a1cea5 | Peter Crosthwaite | sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]); |
1576 | 06a1cea5 | Peter Crosthwaite | } |
1577 | 06a1cea5 | Peter Crosthwaite | |
1578 | 06a1cea5 | Peter Crosthwaite | qdev_init_gpio_in(dev, pl330_dma_stop_irq, PL330_PERIPH_NUM); |
1579 | 06a1cea5 | Peter Crosthwaite | |
1580 | 06a1cea5 | Peter Crosthwaite | switch (s->data_width) {
|
1581 | 06a1cea5 | Peter Crosthwaite | case (32): |
1582 | 06a1cea5 | Peter Crosthwaite | s->cfg[CFG_CRD] |= 0x2;
|
1583 | 06a1cea5 | Peter Crosthwaite | break;
|
1584 | 06a1cea5 | Peter Crosthwaite | case (64): |
1585 | 06a1cea5 | Peter Crosthwaite | s->cfg[CFG_CRD] |= 0x3;
|
1586 | 06a1cea5 | Peter Crosthwaite | break;
|
1587 | 06a1cea5 | Peter Crosthwaite | case (128): |
1588 | 06a1cea5 | Peter Crosthwaite | s->cfg[CFG_CRD] |= 0x4;
|
1589 | 06a1cea5 | Peter Crosthwaite | break;
|
1590 | 06a1cea5 | Peter Crosthwaite | default:
|
1591 | 06a1cea5 | Peter Crosthwaite | error_setg(errp, "Bad value for data_width property: %d\n",
|
1592 | 06a1cea5 | Peter Crosthwaite | s->data_width); |
1593 | 06a1cea5 | Peter Crosthwaite | return;
|
1594 | 06a1cea5 | Peter Crosthwaite | } |
1595 | 06a1cea5 | Peter Crosthwaite | |
1596 | 06a1cea5 | Peter Crosthwaite | s->cfg[CFG_CRD] |= ((s->wr_cap - 1) & 0x7) << 4 | |
1597 | 06a1cea5 | Peter Crosthwaite | ((s->wr_q_dep - 1) & 0xf) << 8 | |
1598 | 06a1cea5 | Peter Crosthwaite | ((s->rd_cap - 1) & 0x7) << 12 | |
1599 | 06a1cea5 | Peter Crosthwaite | ((s->rd_q_dep - 1) & 0xf) << 16 | |
1600 | 06a1cea5 | Peter Crosthwaite | ((s->data_buffer_dep - 1) & 0x1ff) << 20; |
1601 | 06a1cea5 | Peter Crosthwaite | |
1602 | 06a1cea5 | Peter Crosthwaite | pl330_queue_init(&s->read_queue, s->rd_q_dep, s); |
1603 | 06a1cea5 | Peter Crosthwaite | pl330_queue_init(&s->write_queue, s->wr_q_dep, s); |
1604 | 06a1cea5 | Peter Crosthwaite | pl330_fifo_init(&s->fifo, s->data_buffer_dep); |
1605 | 06a1cea5 | Peter Crosthwaite | } |
1606 | 06a1cea5 | Peter Crosthwaite | |
1607 | 06a1cea5 | Peter Crosthwaite | static Property pl330_properties[] = {
|
1608 | 06a1cea5 | Peter Crosthwaite | /* CR0 */
|
1609 | 06a1cea5 | Peter Crosthwaite | DEFINE_PROP_UINT32("num_chnls", PL330State, num_chnls, 8), |
1610 | 06a1cea5 | Peter Crosthwaite | DEFINE_PROP_UINT8("num_periph_req", PL330State, num_periph_req, 4), |
1611 | 06a1cea5 | Peter Crosthwaite | DEFINE_PROP_UINT8("num_events", PL330State, num_events, 16), |
1612 | 06a1cea5 | Peter Crosthwaite | DEFINE_PROP_UINT8("mgr_ns_at_rst", PL330State, mgr_ns_at_rst, 0), |
1613 | 06a1cea5 | Peter Crosthwaite | /* CR1 */
|
1614 | 06a1cea5 | Peter Crosthwaite | DEFINE_PROP_UINT8("i-cache_len", PL330State, i_cache_len, 4), |
1615 | 06a1cea5 | Peter Crosthwaite | DEFINE_PROP_UINT8("num_i-cache_lines", PL330State, num_i_cache_lines, 8), |
1616 | 06a1cea5 | Peter Crosthwaite | /* CR2-4 */
|
1617 | 06a1cea5 | Peter Crosthwaite | DEFINE_PROP_UINT32("boot_addr", PL330State, cfg[CFG_BOOT_ADDR], 0), |
1618 | 06a1cea5 | Peter Crosthwaite | DEFINE_PROP_UINT32("INS", PL330State, cfg[CFG_INS], 0), |
1619 | 06a1cea5 | Peter Crosthwaite | DEFINE_PROP_UINT32("PNS", PL330State, cfg[CFG_PNS], 0), |
1620 | 06a1cea5 | Peter Crosthwaite | /* CRD */
|
1621 | 06a1cea5 | Peter Crosthwaite | DEFINE_PROP_UINT8("data_width", PL330State, data_width, 64), |
1622 | 06a1cea5 | Peter Crosthwaite | DEFINE_PROP_UINT8("wr_cap", PL330State, wr_cap, 8), |
1623 | 06a1cea5 | Peter Crosthwaite | DEFINE_PROP_UINT8("wr_q_dep", PL330State, wr_q_dep, 16), |
1624 | 06a1cea5 | Peter Crosthwaite | DEFINE_PROP_UINT8("rd_cap", PL330State, rd_cap, 8), |
1625 | 06a1cea5 | Peter Crosthwaite | DEFINE_PROP_UINT8("rd_q_dep", PL330State, rd_q_dep, 16), |
1626 | 06a1cea5 | Peter Crosthwaite | DEFINE_PROP_UINT16("data_buffer_dep", PL330State, data_buffer_dep, 256), |
1627 | 06a1cea5 | Peter Crosthwaite | |
1628 | 06a1cea5 | Peter Crosthwaite | DEFINE_PROP_END_OF_LIST(), |
1629 | 06a1cea5 | Peter Crosthwaite | }; |
1630 | 06a1cea5 | Peter Crosthwaite | |
1631 | 06a1cea5 | Peter Crosthwaite | static void pl330_class_init(ObjectClass *klass, void *data) |
1632 | 06a1cea5 | Peter Crosthwaite | { |
1633 | 06a1cea5 | Peter Crosthwaite | DeviceClass *dc = DEVICE_CLASS(klass); |
1634 | 06a1cea5 | Peter Crosthwaite | |
1635 | 06a1cea5 | Peter Crosthwaite | dc->realize = pl330_realize; |
1636 | 06a1cea5 | Peter Crosthwaite | dc->reset = pl330_reset; |
1637 | 06a1cea5 | Peter Crosthwaite | dc->props = pl330_properties; |
1638 | 06a1cea5 | Peter Crosthwaite | dc->vmsd = &vmstate_pl330; |
1639 | 06a1cea5 | Peter Crosthwaite | } |
1640 | 06a1cea5 | Peter Crosthwaite | |
1641 | 06a1cea5 | Peter Crosthwaite | static const TypeInfo pl330_type_info = { |
1642 | 06a1cea5 | Peter Crosthwaite | .name = TYPE_PL330, |
1643 | 06a1cea5 | Peter Crosthwaite | .parent = TYPE_SYS_BUS_DEVICE, |
1644 | 06a1cea5 | Peter Crosthwaite | .instance_size = sizeof(PL330State),
|
1645 | 06a1cea5 | Peter Crosthwaite | .class_init = pl330_class_init, |
1646 | 06a1cea5 | Peter Crosthwaite | }; |
1647 | 06a1cea5 | Peter Crosthwaite | |
1648 | 06a1cea5 | Peter Crosthwaite | static void pl330_register_types(void) |
1649 | 06a1cea5 | Peter Crosthwaite | { |
1650 | 06a1cea5 | Peter Crosthwaite | type_register_static(&pl330_type_info); |
1651 | 06a1cea5 | Peter Crosthwaite | } |
1652 | 06a1cea5 | Peter Crosthwaite | |
1653 | 06a1cea5 | Peter Crosthwaite | type_init(pl330_register_types) |