microblaze/petalogix_s3adsp1800_mmu: Fix UART IRQ
The UART IRQ is edge sensitive, whereas the machine was registering itas level sensitive. Fix.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
intc/xilinx_intc: Don't clear level sens. IRQs without ACK
For level sensitive interrupts, ISR bits are cleared when the input pinis lowered. This is incorrect. Only software can clear ISR bits (viaIAR or direct write to ISR with !MER).
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>...
Merge remote-tracking branch 'luiz/queue/qmp' into staging
Merge remote-tracking branch 'kwolf/for-anthony' into staging
Merge remote-tracking branch 'rth/fix-ppc64' into staging
tcg-ppc64: bswap64 rotates output 32 bits
If our input and output is in the same register, bswap64 tries toundo a rotate of the input. This just ends up rotating the output.
Cc: qemu-stable@nongnu.orgSigned-off-by: Anton Blanchard <anton@samba.org>Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Fix add2_i64
add2_i64 was adding the lower double word to the upper double wordof each input. Fix this so we add the lower double words, then theupper double words with carry propagation.
Cc: qemu-stable@nongnu.orgSigned-off-by: Anton Blanchard <anton@samba.org>...
tcg-ppc64: rotr_i32 rotates wrong amount
rotr_i32 calculates the amount to left shift and puts it into atemporary, but then doesn't use it when doing the shift.
tcg-ppc64: Fix RLDCL opcode
The rldcl instruction doesn't have an sh field, so the minor opcodeis shifted 1 bit. We were using the XO30 macro which shifted theminor opcode 2 bits.
Remove XO30 and add MD30 and MDS30 macros which match thePower ISA categories....
vmdk: Allow reading variable size descriptor files
the hard-coded 2k buffer on the stack won't allow reading big descriptorfiles which can be generated when storing big images. For example 500Gvmdk splitted to 2G chunks.
Signed-off-by: Evgeny Budilovsky <evgeny.budilovsky@ravellosystems.com>...
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