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1 | 69b91039 | bellard | /*
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2 | 69b91039 | bellard | * QEMU PCI bus manager
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3 | 69b91039 | bellard | *
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4 | 69b91039 | bellard | * Copyright (c) 2004 Fabrice Bellard
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5 | 69b91039 | bellard | *
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6 | 69b91039 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 69b91039 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 69b91039 | bellard | * in the Software without restriction, including without limitation the rights
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9 | 69b91039 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 69b91039 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 69b91039 | bellard | * furnished to do so, subject to the following conditions:
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12 | 69b91039 | bellard | *
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13 | 69b91039 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 69b91039 | bellard | * all copies or substantial portions of the Software.
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15 | 69b91039 | bellard | *
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16 | 69b91039 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 69b91039 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 69b91039 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 69b91039 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 69b91039 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 69b91039 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 69b91039 | bellard | * THE SOFTWARE.
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23 | 69b91039 | bellard | */
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24 | 69b91039 | bellard | #include "vl.h" |
25 | 69b91039 | bellard | |
26 | 69b91039 | bellard | //#define DEBUG_PCI
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27 | 69b91039 | bellard | |
28 | 0ac32c83 | bellard | #define PCI_VENDOR_ID 0x00 /* 16 bits */ |
29 | 0ac32c83 | bellard | #define PCI_DEVICE_ID 0x02 /* 16 bits */ |
30 | 0ac32c83 | bellard | #define PCI_COMMAND 0x04 /* 16 bits */ |
31 | 0ac32c83 | bellard | #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ |
32 | 0ac32c83 | bellard | #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ |
33 | 0ac32c83 | bellard | #define PCI_CLASS_DEVICE 0x0a /* Device class */ |
34 | 0ac32c83 | bellard | #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ |
35 | 0ac32c83 | bellard | #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ |
36 | 0ac32c83 | bellard | #define PCI_MIN_GNT 0x3e /* 8 bits */ |
37 | 0ac32c83 | bellard | #define PCI_MAX_LAT 0x3f /* 8 bits */ |
38 | 0ac32c83 | bellard | |
39 | 0ac32c83 | bellard | /* just used for simpler irq handling. */
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40 | 0ac32c83 | bellard | #define PCI_DEVICES_MAX 64 |
41 | 0ac32c83 | bellard | #define PCI_IRQ_WORDS ((PCI_DEVICES_MAX + 31) / 32) |
42 | 0ac32c83 | bellard | |
43 | 69b91039 | bellard | typedef struct PCIBridge { |
44 | 69b91039 | bellard | uint32_t config_reg; |
45 | 69b91039 | bellard | PCIDevice **pci_bus[256];
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46 | 69b91039 | bellard | } PCIBridge; |
47 | 69b91039 | bellard | |
48 | 69b91039 | bellard | static PCIBridge pci_bridge;
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49 | 69b91039 | bellard | target_phys_addr_t pci_mem_base; |
50 | 0ac32c83 | bellard | static int pci_irq_index; |
51 | 0ac32c83 | bellard | static uint32_t pci_irq_levels[4][PCI_IRQ_WORDS]; |
52 | 69b91039 | bellard | |
53 | 69b91039 | bellard | /* -1 for devfn means auto assign */
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54 | 69b91039 | bellard | PCIDevice *pci_register_device(const char *name, int instance_size, |
55 | 69b91039 | bellard | int bus_num, int devfn, |
56 | 69b91039 | bellard | PCIConfigReadFunc *config_read, |
57 | 69b91039 | bellard | PCIConfigWriteFunc *config_write) |
58 | 69b91039 | bellard | { |
59 | 69b91039 | bellard | PCIBridge *s = &pci_bridge; |
60 | 69b91039 | bellard | PCIDevice *pci_dev, **bus; |
61 | 69b91039 | bellard | |
62 | 0ac32c83 | bellard | if (pci_irq_index >= PCI_DEVICES_MAX)
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63 | 0ac32c83 | bellard | return NULL; |
64 | 0ac32c83 | bellard | |
65 | 69b91039 | bellard | if (!s->pci_bus[bus_num]) {
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66 | 69b91039 | bellard | s->pci_bus[bus_num] = qemu_mallocz(256 * sizeof(PCIDevice *)); |
67 | 69b91039 | bellard | if (!s->pci_bus[bus_num])
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68 | 69b91039 | bellard | return NULL; |
69 | 69b91039 | bellard | } |
70 | 69b91039 | bellard | bus = s->pci_bus[bus_num]; |
71 | 69b91039 | bellard | if (devfn < 0) { |
72 | 69b91039 | bellard | for(devfn = 0 ; devfn < 256; devfn += 8) { |
73 | 69b91039 | bellard | if (!bus[devfn])
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74 | 69b91039 | bellard | goto found;
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75 | 69b91039 | bellard | } |
76 | 69b91039 | bellard | return NULL; |
77 | 69b91039 | bellard | found: ;
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78 | 69b91039 | bellard | } |
79 | 69b91039 | bellard | pci_dev = qemu_mallocz(instance_size); |
80 | 69b91039 | bellard | if (!pci_dev)
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81 | 69b91039 | bellard | return NULL; |
82 | 69b91039 | bellard | pci_dev->bus_num = bus_num; |
83 | 69b91039 | bellard | pci_dev->devfn = devfn; |
84 | 69b91039 | bellard | pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
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85 | 0ac32c83 | bellard | |
86 | 0ac32c83 | bellard | if (!config_read)
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87 | 0ac32c83 | bellard | config_read = pci_default_read_config; |
88 | 0ac32c83 | bellard | if (!config_write)
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89 | 0ac32c83 | bellard | config_write = pci_default_write_config; |
90 | 69b91039 | bellard | pci_dev->config_read = config_read; |
91 | 69b91039 | bellard | pci_dev->config_write = config_write; |
92 | 0ac32c83 | bellard | pci_dev->irq_index = pci_irq_index++; |
93 | 69b91039 | bellard | bus[devfn] = pci_dev; |
94 | 69b91039 | bellard | return pci_dev;
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95 | 69b91039 | bellard | } |
96 | 69b91039 | bellard | |
97 | 69b91039 | bellard | void pci_register_io_region(PCIDevice *pci_dev, int region_num, |
98 | 69b91039 | bellard | uint32_t size, int type,
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99 | 69b91039 | bellard | PCIMapIORegionFunc *map_func) |
100 | 69b91039 | bellard | { |
101 | 69b91039 | bellard | PCIIORegion *r; |
102 | 69b91039 | bellard | |
103 | 69b91039 | bellard | if ((unsigned int)region_num >= 6) |
104 | 69b91039 | bellard | return;
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105 | 69b91039 | bellard | r = &pci_dev->io_regions[region_num]; |
106 | 69b91039 | bellard | r->addr = -1;
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107 | 69b91039 | bellard | r->size = size; |
108 | 69b91039 | bellard | r->type = type; |
109 | 69b91039 | bellard | r->map_func = map_func; |
110 | 69b91039 | bellard | } |
111 | 69b91039 | bellard | |
112 | 0ac32c83 | bellard | static void pci_addr_writel(void* opaque, uint32_t addr, uint32_t val) |
113 | 69b91039 | bellard | { |
114 | 69b91039 | bellard | PCIBridge *s = opaque; |
115 | 69b91039 | bellard | s->config_reg = val; |
116 | 69b91039 | bellard | } |
117 | 69b91039 | bellard | |
118 | 0ac32c83 | bellard | static uint32_t pci_addr_readl(void* opaque, uint32_t addr) |
119 | 69b91039 | bellard | { |
120 | 69b91039 | bellard | PCIBridge *s = opaque; |
121 | 69b91039 | bellard | return s->config_reg;
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122 | 69b91039 | bellard | } |
123 | 69b91039 | bellard | |
124 | 0ac32c83 | bellard | static void pci_update_mappings(PCIDevice *d) |
125 | 0ac32c83 | bellard | { |
126 | 0ac32c83 | bellard | PCIIORegion *r; |
127 | 0ac32c83 | bellard | int cmd, i;
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128 | 0ac32c83 | bellard | uint32_t last_addr, new_addr; |
129 | 0ac32c83 | bellard | |
130 | 0ac32c83 | bellard | cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND)); |
131 | 0ac32c83 | bellard | for(i = 0; i < 6; i++) { |
132 | 0ac32c83 | bellard | r = &d->io_regions[i]; |
133 | 0ac32c83 | bellard | if (r->size != 0) { |
134 | 0ac32c83 | bellard | if (r->type & PCI_ADDRESS_SPACE_IO) {
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135 | 0ac32c83 | bellard | if (cmd & PCI_COMMAND_IO) {
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136 | 0ac32c83 | bellard | new_addr = le32_to_cpu(*(uint32_t *)(d->config + |
137 | 0ac32c83 | bellard | 0x10 + i * 4)); |
138 | 0ac32c83 | bellard | new_addr = new_addr & ~(r->size - 1);
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139 | 0ac32c83 | bellard | last_addr = new_addr + r->size - 1;
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140 | 0ac32c83 | bellard | /* NOTE: we have only 64K ioports on PC */
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141 | 0ac32c83 | bellard | if (last_addr <= new_addr || new_addr == 0 || |
142 | 0ac32c83 | bellard | last_addr >= 0x10000) {
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143 | 0ac32c83 | bellard | new_addr = -1;
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144 | 0ac32c83 | bellard | } |
145 | 0ac32c83 | bellard | } else {
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146 | 0ac32c83 | bellard | new_addr = -1;
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147 | 0ac32c83 | bellard | } |
148 | 0ac32c83 | bellard | } else {
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149 | 0ac32c83 | bellard | if (cmd & PCI_COMMAND_MEMORY) {
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150 | 0ac32c83 | bellard | new_addr = le32_to_cpu(*(uint32_t *)(d->config + |
151 | 0ac32c83 | bellard | 0x10 + i * 4)); |
152 | 0ac32c83 | bellard | new_addr = new_addr & ~(r->size - 1);
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153 | 0ac32c83 | bellard | last_addr = new_addr + r->size - 1;
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154 | 0ac32c83 | bellard | /* NOTE: we do not support wrapping */
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155 | 0ac32c83 | bellard | /* XXX: as we cannot support really dynamic
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156 | 0ac32c83 | bellard | mappings, we handle specific values as invalid
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157 | 0ac32c83 | bellard | mappings. */
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158 | 0ac32c83 | bellard | if (last_addr <= new_addr || new_addr == 0 || |
159 | 0ac32c83 | bellard | last_addr == -1) {
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160 | 0ac32c83 | bellard | new_addr = -1;
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161 | 0ac32c83 | bellard | } |
162 | 0ac32c83 | bellard | } else {
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163 | 0ac32c83 | bellard | new_addr = -1;
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164 | 0ac32c83 | bellard | } |
165 | 0ac32c83 | bellard | } |
166 | 0ac32c83 | bellard | /* now do the real mapping */
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167 | 0ac32c83 | bellard | if (new_addr != r->addr) {
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168 | 0ac32c83 | bellard | if (r->addr != -1) { |
169 | 0ac32c83 | bellard | if (r->type & PCI_ADDRESS_SPACE_IO) {
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170 | 0ac32c83 | bellard | int class;
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171 | 0ac32c83 | bellard | /* NOTE: specific hack for IDE in PC case:
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172 | 0ac32c83 | bellard | only one byte must be mapped. */
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173 | 0ac32c83 | bellard | class = d->config[0x0a] | (d->config[0x0b] << 8); |
174 | 0ac32c83 | bellard | if (class == 0x0101 && r->size == 4) { |
175 | 0ac32c83 | bellard | isa_unassign_ioport(r->addr + 2, 1); |
176 | 0ac32c83 | bellard | } else {
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177 | 0ac32c83 | bellard | isa_unassign_ioport(r->addr, r->size); |
178 | 0ac32c83 | bellard | } |
179 | 0ac32c83 | bellard | } else {
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180 | 0ac32c83 | bellard | cpu_register_physical_memory(r->addr + pci_mem_base, |
181 | 0ac32c83 | bellard | r->size, |
182 | 0ac32c83 | bellard | IO_MEM_UNASSIGNED); |
183 | 0ac32c83 | bellard | } |
184 | 0ac32c83 | bellard | } |
185 | 0ac32c83 | bellard | r->addr = new_addr; |
186 | 0ac32c83 | bellard | if (r->addr != -1) { |
187 | 0ac32c83 | bellard | r->map_func(d, i, r->addr, r->size, r->type); |
188 | 0ac32c83 | bellard | } |
189 | 0ac32c83 | bellard | } |
190 | 0ac32c83 | bellard | } |
191 | 0ac32c83 | bellard | } |
192 | 0ac32c83 | bellard | } |
193 | 0ac32c83 | bellard | |
194 | 0ac32c83 | bellard | uint32_t pci_default_read_config(PCIDevice *d, |
195 | 0ac32c83 | bellard | uint32_t address, int len)
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196 | 69b91039 | bellard | { |
197 | 0ac32c83 | bellard | uint32_t val; |
198 | 0ac32c83 | bellard | switch(len) {
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199 | 0ac32c83 | bellard | case 1: |
200 | 0ac32c83 | bellard | val = d->config[address]; |
201 | 0ac32c83 | bellard | break;
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202 | 0ac32c83 | bellard | case 2: |
203 | 0ac32c83 | bellard | val = le16_to_cpu(*(uint16_t *)(d->config + address)); |
204 | 0ac32c83 | bellard | break;
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205 | 0ac32c83 | bellard | default:
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206 | 0ac32c83 | bellard | case 4: |
207 | 0ac32c83 | bellard | val = le32_to_cpu(*(uint32_t *)(d->config + address)); |
208 | 0ac32c83 | bellard | break;
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209 | 0ac32c83 | bellard | } |
210 | 0ac32c83 | bellard | return val;
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211 | 0ac32c83 | bellard | } |
212 | 0ac32c83 | bellard | |
213 | 0ac32c83 | bellard | void pci_default_write_config(PCIDevice *d,
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214 | 0ac32c83 | bellard | uint32_t address, uint32_t val, int len)
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215 | 0ac32c83 | bellard | { |
216 | 0ac32c83 | bellard | int can_write, i;
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217 | 7bf5be70 | bellard | uint32_t end, addr; |
218 | 0ac32c83 | bellard | |
219 | 0ac32c83 | bellard | if (len == 4 && (address >= 0x10 && address < 0x10 + 4 * 6)) { |
220 | 0ac32c83 | bellard | PCIIORegion *r; |
221 | 0ac32c83 | bellard | int reg;
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222 | 0ac32c83 | bellard | |
223 | 0ac32c83 | bellard | reg = (address - 0x10) >> 2; |
224 | 0ac32c83 | bellard | r = &d->io_regions[reg]; |
225 | 0ac32c83 | bellard | if (r->size == 0) |
226 | 0ac32c83 | bellard | goto default_config;
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227 | 0ac32c83 | bellard | /* compute the stored value */
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228 | 0ac32c83 | bellard | val &= ~(r->size - 1);
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229 | 0ac32c83 | bellard | val |= r->type; |
230 | 0ac32c83 | bellard | *(uint32_t *)(d->config + 0x10 + reg * 4) = cpu_to_le32(val); |
231 | 0ac32c83 | bellard | pci_update_mappings(d); |
232 | 69b91039 | bellard | return;
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233 | 0ac32c83 | bellard | } |
234 | 0ac32c83 | bellard | default_config:
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235 | 0ac32c83 | bellard | /* not efficient, but simple */
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236 | 7bf5be70 | bellard | addr = address; |
237 | 0ac32c83 | bellard | for(i = 0; i < len; i++) { |
238 | 0ac32c83 | bellard | /* default read/write accesses */
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239 | 7bf5be70 | bellard | switch(addr) {
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240 | 0ac32c83 | bellard | case 0x00: |
241 | 0ac32c83 | bellard | case 0x01: |
242 | 0ac32c83 | bellard | case 0x02: |
243 | 0ac32c83 | bellard | case 0x03: |
244 | 0ac32c83 | bellard | case 0x08: |
245 | 0ac32c83 | bellard | case 0x09: |
246 | 0ac32c83 | bellard | case 0x0a: |
247 | 0ac32c83 | bellard | case 0x0b: |
248 | 0ac32c83 | bellard | case 0x0e: |
249 | 0ac32c83 | bellard | case 0x3d: |
250 | 0ac32c83 | bellard | can_write = 0;
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251 | 0ac32c83 | bellard | break;
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252 | 0ac32c83 | bellard | default:
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253 | 0ac32c83 | bellard | can_write = 1;
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254 | 0ac32c83 | bellard | break;
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255 | 0ac32c83 | bellard | } |
256 | 0ac32c83 | bellard | if (can_write) {
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257 | 7bf5be70 | bellard | d->config[addr] = val; |
258 | 0ac32c83 | bellard | } |
259 | 7bf5be70 | bellard | addr++; |
260 | 0ac32c83 | bellard | val >>= 8;
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261 | 0ac32c83 | bellard | } |
262 | 0ac32c83 | bellard | |
263 | 0ac32c83 | bellard | end = address + len; |
264 | 0ac32c83 | bellard | if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) { |
265 | 0ac32c83 | bellard | /* if the command register is modified, we must modify the mappings */
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266 | 0ac32c83 | bellard | pci_update_mappings(d); |
267 | 69b91039 | bellard | } |
268 | 69b91039 | bellard | } |
269 | 69b91039 | bellard | |
270 | 69b91039 | bellard | static void pci_data_write(void *opaque, uint32_t addr, |
271 | 69b91039 | bellard | uint32_t val, int len)
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272 | 69b91039 | bellard | { |
273 | 69b91039 | bellard | PCIBridge *s = opaque; |
274 | 69b91039 | bellard | PCIDevice **bus, *pci_dev; |
275 | 0ac32c83 | bellard | int config_addr;
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276 | 69b91039 | bellard | |
277 | 69b91039 | bellard | #if defined(DEBUG_PCI) && 0 |
278 | 69b91039 | bellard | printf("pci_data_write: addr=%08x val=%08x len=%d\n",
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279 | 69b91039 | bellard | s->config_reg, val, len); |
280 | 69b91039 | bellard | #endif
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281 | 69b91039 | bellard | if (!(s->config_reg & (1 << 31))) { |
282 | 69b91039 | bellard | return;
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283 | 69b91039 | bellard | } |
284 | 69b91039 | bellard | if ((s->config_reg & 0x3) != 0) { |
285 | 69b91039 | bellard | return;
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286 | 69b91039 | bellard | } |
287 | 69b91039 | bellard | bus = s->pci_bus[(s->config_reg >> 16) & 0xff]; |
288 | 69b91039 | bellard | if (!bus)
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289 | 69b91039 | bellard | return;
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290 | 69b91039 | bellard | pci_dev = bus[(s->config_reg >> 8) & 0xff]; |
291 | 69b91039 | bellard | if (!pci_dev)
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292 | 69b91039 | bellard | return;
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293 | 69b91039 | bellard | config_addr = (s->config_reg & 0xfc) | (addr & 3); |
294 | 69b91039 | bellard | #if defined(DEBUG_PCI)
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295 | 69b91039 | bellard | printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
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296 | 69b91039 | bellard | pci_dev->name, config_addr, val, len); |
297 | 69b91039 | bellard | #endif
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298 | 0ac32c83 | bellard | pci_dev->config_write(pci_dev, config_addr, val, len); |
299 | 69b91039 | bellard | } |
300 | 69b91039 | bellard | |
301 | 69b91039 | bellard | static uint32_t pci_data_read(void *opaque, uint32_t addr, |
302 | 69b91039 | bellard | int len)
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303 | 69b91039 | bellard | { |
304 | 69b91039 | bellard | PCIBridge *s = opaque; |
305 | 69b91039 | bellard | PCIDevice **bus, *pci_dev; |
306 | 69b91039 | bellard | int config_addr;
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307 | 69b91039 | bellard | uint32_t val; |
308 | 69b91039 | bellard | |
309 | 69b91039 | bellard | if (!(s->config_reg & (1 << 31))) |
310 | 69b91039 | bellard | goto fail;
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311 | 69b91039 | bellard | if ((s->config_reg & 0x3) != 0) |
312 | 69b91039 | bellard | goto fail;
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313 | 69b91039 | bellard | bus = s->pci_bus[(s->config_reg >> 16) & 0xff]; |
314 | 69b91039 | bellard | if (!bus)
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315 | 69b91039 | bellard | goto fail;
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316 | 69b91039 | bellard | pci_dev = bus[(s->config_reg >> 8) & 0xff]; |
317 | 69b91039 | bellard | if (!pci_dev) {
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318 | 69b91039 | bellard | fail:
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319 | 63ce9e0a | bellard | switch(len) {
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320 | 63ce9e0a | bellard | case 1: |
321 | 63ce9e0a | bellard | val = 0xff;
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322 | 63ce9e0a | bellard | break;
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323 | 63ce9e0a | bellard | case 2: |
324 | 63ce9e0a | bellard | val = 0xffff;
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325 | 63ce9e0a | bellard | break;
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326 | 63ce9e0a | bellard | default:
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327 | 63ce9e0a | bellard | case 4: |
328 | 63ce9e0a | bellard | val = 0xffffffff;
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329 | 63ce9e0a | bellard | break;
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330 | 63ce9e0a | bellard | } |
331 | 69b91039 | bellard | goto the_end;
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332 | 69b91039 | bellard | } |
333 | 69b91039 | bellard | config_addr = (s->config_reg & 0xfc) | (addr & 3); |
334 | 69b91039 | bellard | val = pci_dev->config_read(pci_dev, config_addr, len); |
335 | 69b91039 | bellard | #if defined(DEBUG_PCI)
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336 | 69b91039 | bellard | printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
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337 | 69b91039 | bellard | pci_dev->name, config_addr, val, len); |
338 | 69b91039 | bellard | #endif
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339 | 69b91039 | bellard | the_end:
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340 | 69b91039 | bellard | #if defined(DEBUG_PCI) && 0 |
341 | 69b91039 | bellard | printf("pci_data_read: addr=%08x val=%08x len=%d\n",
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342 | 69b91039 | bellard | s->config_reg, val, len); |
343 | 69b91039 | bellard | #endif
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344 | 69b91039 | bellard | return val;
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345 | 69b91039 | bellard | } |
346 | 69b91039 | bellard | |
347 | 69b91039 | bellard | static void pci_data_writeb(void* opaque, uint32_t addr, uint32_t val) |
348 | 69b91039 | bellard | { |
349 | 69b91039 | bellard | pci_data_write(opaque, addr, val, 1);
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350 | 69b91039 | bellard | } |
351 | 69b91039 | bellard | |
352 | 69b91039 | bellard | static void pci_data_writew(void* opaque, uint32_t addr, uint32_t val) |
353 | 69b91039 | bellard | { |
354 | 69b91039 | bellard | pci_data_write(opaque, addr, val, 2);
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355 | 69b91039 | bellard | } |
356 | 69b91039 | bellard | |
357 | 69b91039 | bellard | static void pci_data_writel(void* opaque, uint32_t addr, uint32_t val) |
358 | 69b91039 | bellard | { |
359 | 69b91039 | bellard | pci_data_write(opaque, addr, val, 4);
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360 | 69b91039 | bellard | } |
361 | 69b91039 | bellard | |
362 | 69b91039 | bellard | static uint32_t pci_data_readb(void* opaque, uint32_t addr) |
363 | 69b91039 | bellard | { |
364 | 69b91039 | bellard | return pci_data_read(opaque, addr, 1); |
365 | 69b91039 | bellard | } |
366 | 69b91039 | bellard | |
367 | 69b91039 | bellard | static uint32_t pci_data_readw(void* opaque, uint32_t addr) |
368 | 69b91039 | bellard | { |
369 | 69b91039 | bellard | return pci_data_read(opaque, addr, 2); |
370 | 69b91039 | bellard | } |
371 | 69b91039 | bellard | |
372 | 69b91039 | bellard | static uint32_t pci_data_readl(void* opaque, uint32_t addr) |
373 | 69b91039 | bellard | { |
374 | 69b91039 | bellard | return pci_data_read(opaque, addr, 4); |
375 | 69b91039 | bellard | } |
376 | 69b91039 | bellard | |
377 | 69b91039 | bellard | /* i440FX PCI bridge */
|
378 | 69b91039 | bellard | |
379 | 69b91039 | bellard | void i440fx_init(void) |
380 | 69b91039 | bellard | { |
381 | 69b91039 | bellard | PCIBridge *s = &pci_bridge; |
382 | 69b91039 | bellard | PCIDevice *d; |
383 | 69b91039 | bellard | |
384 | 0ac32c83 | bellard | register_ioport_write(0xcf8, 4, 4, pci_addr_writel, s); |
385 | 0ac32c83 | bellard | register_ioport_read(0xcf8, 4, 4, pci_addr_readl, s); |
386 | 69b91039 | bellard | |
387 | 69b91039 | bellard | register_ioport_write(0xcfc, 4, 1, pci_data_writeb, s); |
388 | 69b91039 | bellard | register_ioport_write(0xcfc, 4, 2, pci_data_writew, s); |
389 | 69b91039 | bellard | register_ioport_write(0xcfc, 4, 4, pci_data_writel, s); |
390 | 69b91039 | bellard | register_ioport_read(0xcfc, 4, 1, pci_data_readb, s); |
391 | 69b91039 | bellard | register_ioport_read(0xcfc, 4, 2, pci_data_readw, s); |
392 | 69b91039 | bellard | register_ioport_read(0xcfc, 4, 4, pci_data_readl, s); |
393 | 69b91039 | bellard | |
394 | 69b91039 | bellard | d = pci_register_device("i440FX", sizeof(PCIDevice), 0, 0, |
395 | 0ac32c83 | bellard | NULL, NULL); |
396 | 69b91039 | bellard | |
397 | 69b91039 | bellard | d->config[0x00] = 0x86; // vendor_id |
398 | 69b91039 | bellard | d->config[0x01] = 0x80; |
399 | 69b91039 | bellard | d->config[0x02] = 0x37; // device_id |
400 | 69b91039 | bellard | d->config[0x03] = 0x12; |
401 | 69b91039 | bellard | d->config[0x08] = 0x02; // revision |
402 | 69b91039 | bellard | d->config[0x0a] = 0x04; // class_sub = pci2pci |
403 | 69b91039 | bellard | d->config[0x0b] = 0x06; // class_base = PCI_bridge |
404 | 69b91039 | bellard | d->config[0x0c] = 0x01; // line_size in 32 bit words |
405 | 69b91039 | bellard | d->config[0x0e] = 0x01; // header_type |
406 | 69b91039 | bellard | } |
407 | 69b91039 | bellard | |
408 | 0ac32c83 | bellard | /* PIIX3 PCI to ISA bridge */
|
409 | 0ac32c83 | bellard | |
410 | 0ac32c83 | bellard | typedef struct PIIX3State { |
411 | 0ac32c83 | bellard | PCIDevice dev; |
412 | 0ac32c83 | bellard | } PIIX3State; |
413 | 0ac32c83 | bellard | |
414 | 0ac32c83 | bellard | PIIX3State *piix3_state; |
415 | 0ac32c83 | bellard | |
416 | 0ac32c83 | bellard | static void piix3_reset(PIIX3State *d) |
417 | 0ac32c83 | bellard | { |
418 | 0ac32c83 | bellard | uint8_t *pci_conf = d->dev.config; |
419 | 0ac32c83 | bellard | |
420 | 0ac32c83 | bellard | pci_conf[0x04] = 0x07; // master, memory and I/O |
421 | 0ac32c83 | bellard | pci_conf[0x05] = 0x00; |
422 | 0ac32c83 | bellard | pci_conf[0x06] = 0x00; |
423 | 0ac32c83 | bellard | pci_conf[0x07] = 0x02; // PCI_status_devsel_medium |
424 | 0ac32c83 | bellard | pci_conf[0x4c] = 0x4d; |
425 | 0ac32c83 | bellard | pci_conf[0x4e] = 0x03; |
426 | 0ac32c83 | bellard | pci_conf[0x4f] = 0x00; |
427 | 0ac32c83 | bellard | pci_conf[0x60] = 0x80; |
428 | 0ac32c83 | bellard | pci_conf[0x69] = 0x02; |
429 | 0ac32c83 | bellard | pci_conf[0x70] = 0x80; |
430 | 0ac32c83 | bellard | pci_conf[0x76] = 0x0c; |
431 | 0ac32c83 | bellard | pci_conf[0x77] = 0x0c; |
432 | 0ac32c83 | bellard | pci_conf[0x78] = 0x02; |
433 | 0ac32c83 | bellard | pci_conf[0x79] = 0x00; |
434 | 0ac32c83 | bellard | pci_conf[0x80] = 0x00; |
435 | 0ac32c83 | bellard | pci_conf[0x82] = 0x00; |
436 | 0ac32c83 | bellard | pci_conf[0xa0] = 0x08; |
437 | 0ac32c83 | bellard | pci_conf[0xa0] = 0x08; |
438 | 0ac32c83 | bellard | pci_conf[0xa2] = 0x00; |
439 | 0ac32c83 | bellard | pci_conf[0xa3] = 0x00; |
440 | 0ac32c83 | bellard | pci_conf[0xa4] = 0x00; |
441 | 0ac32c83 | bellard | pci_conf[0xa5] = 0x00; |
442 | 0ac32c83 | bellard | pci_conf[0xa6] = 0x00; |
443 | 0ac32c83 | bellard | pci_conf[0xa7] = 0x00; |
444 | 0ac32c83 | bellard | pci_conf[0xa8] = 0x0f; |
445 | 0ac32c83 | bellard | pci_conf[0xaa] = 0x00; |
446 | 0ac32c83 | bellard | pci_conf[0xab] = 0x00; |
447 | 0ac32c83 | bellard | pci_conf[0xac] = 0x00; |
448 | 0ac32c83 | bellard | pci_conf[0xae] = 0x00; |
449 | 0ac32c83 | bellard | } |
450 | 0ac32c83 | bellard | |
451 | 0ac32c83 | bellard | void piix3_init(void) |
452 | 0ac32c83 | bellard | { |
453 | 0ac32c83 | bellard | PIIX3State *d; |
454 | 0ac32c83 | bellard | uint8_t *pci_conf; |
455 | 0ac32c83 | bellard | |
456 | 0ac32c83 | bellard | d = (PIIX3State *)pci_register_device("PIIX3", sizeof(PIIX3State), |
457 | 0ac32c83 | bellard | 0, -1, |
458 | 0ac32c83 | bellard | NULL, NULL); |
459 | 0ac32c83 | bellard | piix3_state = d; |
460 | 0ac32c83 | bellard | pci_conf = d->dev.config; |
461 | 0ac32c83 | bellard | |
462 | 0ac32c83 | bellard | pci_conf[0x00] = 0x86; // Intel |
463 | 0ac32c83 | bellard | pci_conf[0x01] = 0x80; |
464 | 0ac32c83 | bellard | pci_conf[0x02] = 0x00; // 82371SB PIIX3 PCI-to-ISA bridge (Step A1) |
465 | 0ac32c83 | bellard | pci_conf[0x03] = 0x70; |
466 | 0ac32c83 | bellard | pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA |
467 | 0ac32c83 | bellard | pci_conf[0x0b] = 0x06; // class_base = PCI_bridge |
468 | 0ac32c83 | bellard | pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic |
469 | 0ac32c83 | bellard | |
470 | 0ac32c83 | bellard | piix3_reset(d); |
471 | 0ac32c83 | bellard | } |
472 | 0ac32c83 | bellard | |
473 | 0ac32c83 | bellard | /***********************************************************/
|
474 | 0ac32c83 | bellard | /* generic PCI irq support */
|
475 | 0ac32c83 | bellard | |
476 | 0ac32c83 | bellard | /* return the global irq number corresponding to a given device irq
|
477 | 0ac32c83 | bellard | pin. We could also use the bus number to have a more precise
|
478 | 0ac32c83 | bellard | mapping. */
|
479 | 0ac32c83 | bellard | static inline int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num) |
480 | 0ac32c83 | bellard | { |
481 | 0ac32c83 | bellard | int slot_addend;
|
482 | 0ac32c83 | bellard | slot_addend = (pci_dev->devfn >> 3);
|
483 | 0ac32c83 | bellard | return (irq_num + slot_addend) & 3; |
484 | 0ac32c83 | bellard | } |
485 | 0ac32c83 | bellard | |
486 | 0ac32c83 | bellard | /* 0 <= irq_num <= 3. level must be 0 or 1 */
|
487 | 0ac32c83 | bellard | void pci_set_irq(PCIDevice *pci_dev, int irq_num, int level) |
488 | 0ac32c83 | bellard | { |
489 | 0ac32c83 | bellard | int irq_index, shift, pic_irq, pic_level;
|
490 | 0ac32c83 | bellard | uint32_t *p; |
491 | 0ac32c83 | bellard | |
492 | 0ac32c83 | bellard | irq_num = pci_slot_get_pirq(pci_dev, irq_num); |
493 | 0ac32c83 | bellard | irq_index = pci_dev->irq_index; |
494 | 0ac32c83 | bellard | p = &pci_irq_levels[irq_num][irq_index >> 5];
|
495 | 0ac32c83 | bellard | shift = (irq_index & 0x1f);
|
496 | 0ac32c83 | bellard | *p = (*p & ~(1 << shift)) | (level << shift);
|
497 | 0ac32c83 | bellard | |
498 | 0ac32c83 | bellard | /* now we change the pic irq level according to the piix irq mappings */
|
499 | 0ac32c83 | bellard | pic_irq = piix3_state->dev.config[0x60 + irq_num];
|
500 | 0ac32c83 | bellard | if (pic_irq < 16) { |
501 | 0ac32c83 | bellard | /* the pic level is the logical OR of all the PCI irqs mapped
|
502 | 0ac32c83 | bellard | to it */
|
503 | 0ac32c83 | bellard | pic_level = 0;
|
504 | 0ac32c83 | bellard | #if (PCI_IRQ_WORDS == 2) |
505 | 0ac32c83 | bellard | pic_level = ((pci_irq_levels[irq_num][0] |
|
506 | 0ac32c83 | bellard | pci_irq_levels[irq_num][1]) != 0); |
507 | 0ac32c83 | bellard | #else
|
508 | 0ac32c83 | bellard | { |
509 | 0ac32c83 | bellard | int i;
|
510 | 0ac32c83 | bellard | pic_level = 0;
|
511 | 0ac32c83 | bellard | for(i = 0; i < PCI_IRQ_WORDS; i++) { |
512 | 0ac32c83 | bellard | if (pci_irq_levels[irq_num][i]) {
|
513 | 0ac32c83 | bellard | pic_level = 1;
|
514 | 0ac32c83 | bellard | break;
|
515 | 0ac32c83 | bellard | } |
516 | 0ac32c83 | bellard | } |
517 | 0ac32c83 | bellard | } |
518 | 0ac32c83 | bellard | #endif
|
519 | 0ac32c83 | bellard | pic_set_irq(pic_irq, pic_level); |
520 | 0ac32c83 | bellard | } |
521 | 0ac32c83 | bellard | } |
522 | 0ac32c83 | bellard | |
523 | 0ac32c83 | bellard | /***********************************************************/
|
524 | 0ac32c83 | bellard | /* monitor info on PCI */
|
525 | 0ac32c83 | bellard | |
526 | 0ac32c83 | bellard | static void pci_info_device(PCIDevice *d) |
527 | 0ac32c83 | bellard | { |
528 | 0ac32c83 | bellard | int i, class;
|
529 | 0ac32c83 | bellard | PCIIORegion *r; |
530 | 0ac32c83 | bellard | |
531 | 0ac32c83 | bellard | printf(" Bus %2d, device %3d, function %d:\n",
|
532 | 0ac32c83 | bellard | d->bus_num, d->devfn >> 3, d->devfn & 7); |
533 | 0ac32c83 | bellard | class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE))); |
534 | 0ac32c83 | bellard | printf(" ");
|
535 | 0ac32c83 | bellard | switch(class) {
|
536 | 0ac32c83 | bellard | case 0x0101: |
537 | 0ac32c83 | bellard | printf("IDE controller");
|
538 | 0ac32c83 | bellard | break;
|
539 | 0ac32c83 | bellard | case 0x0200: |
540 | 0ac32c83 | bellard | printf("Ethernet controller");
|
541 | 0ac32c83 | bellard | break;
|
542 | 0ac32c83 | bellard | case 0x0300: |
543 | 0ac32c83 | bellard | printf("VGA controller");
|
544 | 0ac32c83 | bellard | break;
|
545 | 0ac32c83 | bellard | default:
|
546 | 0ac32c83 | bellard | printf("Class %04x", class);
|
547 | 0ac32c83 | bellard | break;
|
548 | 0ac32c83 | bellard | } |
549 | 0ac32c83 | bellard | printf(": PCI device %04x:%04x\n",
|
550 | 0ac32c83 | bellard | le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))), |
551 | 0ac32c83 | bellard | le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID)))); |
552 | 0ac32c83 | bellard | |
553 | 0ac32c83 | bellard | if (d->config[PCI_INTERRUPT_PIN] != 0) { |
554 | 0ac32c83 | bellard | printf(" IRQ %d.\n", d->config[PCI_INTERRUPT_LINE]);
|
555 | 0ac32c83 | bellard | } |
556 | 0ac32c83 | bellard | for(i = 0;i < 6; i++) { |
557 | 0ac32c83 | bellard | r = &d->io_regions[i]; |
558 | 0ac32c83 | bellard | if (r->size != 0) { |
559 | 0ac32c83 | bellard | printf(" BAR%d: ", i);
|
560 | 0ac32c83 | bellard | if (r->type & PCI_ADDRESS_SPACE_IO) {
|
561 | 0ac32c83 | bellard | printf("I/O at 0x%04x [0x%04x].\n",
|
562 | 0ac32c83 | bellard | r->addr, r->addr + r->size - 1);
|
563 | 0ac32c83 | bellard | } else {
|
564 | 0ac32c83 | bellard | printf("32 bit memory at 0x%08x [0x%08x].\n",
|
565 | 0ac32c83 | bellard | r->addr, r->addr + r->size - 1);
|
566 | 0ac32c83 | bellard | } |
567 | 0ac32c83 | bellard | } |
568 | 0ac32c83 | bellard | } |
569 | 0ac32c83 | bellard | } |
570 | 0ac32c83 | bellard | |
571 | 0ac32c83 | bellard | void pci_info(void) |
572 | 0ac32c83 | bellard | { |
573 | 0ac32c83 | bellard | PCIBridge *s = &pci_bridge; |
574 | 0ac32c83 | bellard | PCIDevice **bus; |
575 | 0ac32c83 | bellard | int bus_num, devfn;
|
576 | 0ac32c83 | bellard | |
577 | 0ac32c83 | bellard | for(bus_num = 0; bus_num < 256; bus_num++) { |
578 | 0ac32c83 | bellard | bus = s->pci_bus[bus_num]; |
579 | 0ac32c83 | bellard | if (bus) {
|
580 | 0ac32c83 | bellard | for(devfn = 0; devfn < 256; devfn++) { |
581 | 0ac32c83 | bellard | if (bus[devfn])
|
582 | 0ac32c83 | bellard | pci_info_device(bus[devfn]); |
583 | 0ac32c83 | bellard | } |
584 | 0ac32c83 | bellard | } |
585 | 0ac32c83 | bellard | } |
586 | 0ac32c83 | bellard | } |
587 | 0ac32c83 | bellard | |
588 | 0ac32c83 | bellard | /***********************************************************/
|
589 | 0ac32c83 | bellard | /* XXX: the following should be moved to the PC BIOS */
|
590 | 0ac32c83 | bellard | |
591 | 0ac32c83 | bellard | static uint32_t isa_inb(uint32_t addr)
|
592 | 0ac32c83 | bellard | { |
593 | 0ac32c83 | bellard | return cpu_inb(cpu_single_env, addr);
|
594 | 0ac32c83 | bellard | } |
595 | 0ac32c83 | bellard | |
596 | 0ac32c83 | bellard | static void isa_outb(uint32_t val, uint32_t addr) |
597 | 0ac32c83 | bellard | { |
598 | 0ac32c83 | bellard | cpu_outb(cpu_single_env, addr, val); |
599 | 0ac32c83 | bellard | } |
600 | 0ac32c83 | bellard | |
601 | 0ac32c83 | bellard | static uint32_t isa_inw(uint32_t addr)
|
602 | 0ac32c83 | bellard | { |
603 | 0ac32c83 | bellard | return cpu_inw(cpu_single_env, addr);
|
604 | 0ac32c83 | bellard | } |
605 | 0ac32c83 | bellard | |
606 | 0ac32c83 | bellard | static void isa_outw(uint32_t val, uint32_t addr) |
607 | 0ac32c83 | bellard | { |
608 | 0ac32c83 | bellard | cpu_outw(cpu_single_env, addr, val); |
609 | 0ac32c83 | bellard | } |
610 | 0ac32c83 | bellard | |
611 | 0ac32c83 | bellard | static uint32_t isa_inl(uint32_t addr)
|
612 | 0ac32c83 | bellard | { |
613 | 0ac32c83 | bellard | return cpu_inl(cpu_single_env, addr);
|
614 | 0ac32c83 | bellard | } |
615 | 0ac32c83 | bellard | |
616 | 0ac32c83 | bellard | static void isa_outl(uint32_t val, uint32_t addr) |
617 | 0ac32c83 | bellard | { |
618 | 0ac32c83 | bellard | cpu_outl(cpu_single_env, addr, val); |
619 | 0ac32c83 | bellard | } |
620 | 0ac32c83 | bellard | |
621 | 0ac32c83 | bellard | static void pci_config_writel(PCIDevice *d, uint32_t addr, uint32_t val) |
622 | 0ac32c83 | bellard | { |
623 | 0ac32c83 | bellard | PCIBridge *s = &pci_bridge; |
624 | 0ac32c83 | bellard | s->config_reg = 0x80000000 | (d->bus_num << 16) | |
625 | 0ac32c83 | bellard | (d->devfn << 8) | addr;
|
626 | 0ac32c83 | bellard | pci_data_write(s, 0, val, 4); |
627 | 0ac32c83 | bellard | } |
628 | 0ac32c83 | bellard | |
629 | 0ac32c83 | bellard | static void pci_config_writew(PCIDevice *d, uint32_t addr, uint32_t val) |
630 | 0ac32c83 | bellard | { |
631 | 0ac32c83 | bellard | PCIBridge *s = &pci_bridge; |
632 | 0ac32c83 | bellard | s->config_reg = 0x80000000 | (d->bus_num << 16) | |
633 | 0ac32c83 | bellard | (d->devfn << 8) | (addr & ~3); |
634 | 0ac32c83 | bellard | pci_data_write(s, addr & 3, val, 2); |
635 | 0ac32c83 | bellard | } |
636 | 0ac32c83 | bellard | |
637 | 0ac32c83 | bellard | static void pci_config_writeb(PCIDevice *d, uint32_t addr, uint32_t val) |
638 | 0ac32c83 | bellard | { |
639 | 0ac32c83 | bellard | PCIBridge *s = &pci_bridge; |
640 | 0ac32c83 | bellard | s->config_reg = 0x80000000 | (d->bus_num << 16) | |
641 | 0ac32c83 | bellard | (d->devfn << 8) | (addr & ~3); |
642 | 0ac32c83 | bellard | pci_data_write(s, addr & 3, val, 1); |
643 | 0ac32c83 | bellard | } |
644 | 0ac32c83 | bellard | |
645 | 0ac32c83 | bellard | static uint32_t pci_config_readl(PCIDevice *d, uint32_t addr)
|
646 | 0ac32c83 | bellard | { |
647 | 0ac32c83 | bellard | PCIBridge *s = &pci_bridge; |
648 | 0ac32c83 | bellard | s->config_reg = 0x80000000 | (d->bus_num << 16) | |
649 | 0ac32c83 | bellard | (d->devfn << 8) | addr;
|
650 | 0ac32c83 | bellard | return pci_data_read(s, 0, 4); |
651 | 0ac32c83 | bellard | } |
652 | 0ac32c83 | bellard | |
653 | 0ac32c83 | bellard | static uint32_t pci_config_readw(PCIDevice *d, uint32_t addr)
|
654 | 0ac32c83 | bellard | { |
655 | 0ac32c83 | bellard | PCIBridge *s = &pci_bridge; |
656 | 0ac32c83 | bellard | s->config_reg = 0x80000000 | (d->bus_num << 16) | |
657 | 0ac32c83 | bellard | (d->devfn << 8) | (addr & ~3); |
658 | 0ac32c83 | bellard | return pci_data_read(s, addr & 3, 2); |
659 | 0ac32c83 | bellard | } |
660 | 0ac32c83 | bellard | |
661 | 0ac32c83 | bellard | static uint32_t pci_config_readb(PCIDevice *d, uint32_t addr)
|
662 | 0ac32c83 | bellard | { |
663 | 0ac32c83 | bellard | PCIBridge *s = &pci_bridge; |
664 | 0ac32c83 | bellard | s->config_reg = 0x80000000 | (d->bus_num << 16) | |
665 | 0ac32c83 | bellard | (d->devfn << 8) | (addr & ~3); |
666 | 0ac32c83 | bellard | return pci_data_read(s, addr & 3, 1); |
667 | 0ac32c83 | bellard | } |
668 | 69b91039 | bellard | |
669 | 69b91039 | bellard | static uint32_t pci_bios_io_addr;
|
670 | 69b91039 | bellard | static uint32_t pci_bios_mem_addr;
|
671 | 0ac32c83 | bellard | /* host irqs corresponding to PCI irqs A-D */
|
672 | 0ac32c83 | bellard | static uint8_t pci_irqs[4] = { 11, 9, 11, 9 }; |
673 | 69b91039 | bellard | |
674 | 69b91039 | bellard | static void pci_set_io_region_addr(PCIDevice *d, int region_num, uint32_t addr) |
675 | 69b91039 | bellard | { |
676 | 69b91039 | bellard | PCIIORegion *r; |
677 | 0ac32c83 | bellard | uint16_t cmd; |
678 | 69b91039 | bellard | |
679 | 0ac32c83 | bellard | pci_config_writel(d, 0x10 + region_num * 4, addr); |
680 | 69b91039 | bellard | r = &d->io_regions[region_num]; |
681 | 69b91039 | bellard | |
682 | 69b91039 | bellard | /* enable memory mappings */
|
683 | 0ac32c83 | bellard | cmd = pci_config_readw(d, PCI_COMMAND); |
684 | 69b91039 | bellard | if (r->type & PCI_ADDRESS_SPACE_IO)
|
685 | 0ac32c83 | bellard | cmd |= 1;
|
686 | 69b91039 | bellard | else
|
687 | 0ac32c83 | bellard | cmd |= 2;
|
688 | 0ac32c83 | bellard | pci_config_writew(d, PCI_COMMAND, cmd); |
689 | 69b91039 | bellard | } |
690 | 69b91039 | bellard | |
691 | 69b91039 | bellard | static void pci_bios_init_device(PCIDevice *d) |
692 | 69b91039 | bellard | { |
693 | 69b91039 | bellard | int class;
|
694 | 69b91039 | bellard | PCIIORegion *r; |
695 | 69b91039 | bellard | uint32_t *paddr; |
696 | 63ce9e0a | bellard | int i, pin, pic_irq, vendor_id, device_id;
|
697 | 69b91039 | bellard | |
698 | 63ce9e0a | bellard | class = pci_config_readw(d, PCI_CLASS_DEVICE); |
699 | 69b91039 | bellard | switch(class) {
|
700 | 69b91039 | bellard | case 0x0101: |
701 | 63ce9e0a | bellard | vendor_id = pci_config_readw(d, PCI_VENDOR_ID); |
702 | 63ce9e0a | bellard | device_id = pci_config_readw(d, PCI_DEVICE_ID); |
703 | 63ce9e0a | bellard | if (vendor_id == 0x8086 && device_id == 0x7010) { |
704 | 63ce9e0a | bellard | /* PIIX3 IDE */
|
705 | 63ce9e0a | bellard | pci_config_writew(d, PCI_COMMAND, PCI_COMMAND_IO); |
706 | 63ce9e0a | bellard | pci_config_writew(d, 0x40, 0x8000); // enable IDE0 |
707 | 63ce9e0a | bellard | } else {
|
708 | 63ce9e0a | bellard | /* IDE: we map it as in ISA mode */
|
709 | 63ce9e0a | bellard | pci_set_io_region_addr(d, 0, 0x1f0); |
710 | 63ce9e0a | bellard | pci_set_io_region_addr(d, 1, 0x3f4); |
711 | 63ce9e0a | bellard | pci_set_io_region_addr(d, 2, 0x170); |
712 | 63ce9e0a | bellard | pci_set_io_region_addr(d, 3, 0x374); |
713 | 63ce9e0a | bellard | } |
714 | 69b91039 | bellard | break;
|
715 | 0ac32c83 | bellard | case 0x0300: |
716 | 0ac32c83 | bellard | /* VGA: map frame buffer to default Bochs VBE address */
|
717 | 0ac32c83 | bellard | pci_set_io_region_addr(d, 0, 0xE0000000); |
718 | 0ac32c83 | bellard | break;
|
719 | 69b91039 | bellard | default:
|
720 | 69b91039 | bellard | /* default memory mappings */
|
721 | 69b91039 | bellard | for(i = 0; i < 6; i++) { |
722 | 69b91039 | bellard | r = &d->io_regions[i]; |
723 | 69b91039 | bellard | if (r->size) {
|
724 | 69b91039 | bellard | if (r->type & PCI_ADDRESS_SPACE_IO)
|
725 | 69b91039 | bellard | paddr = &pci_bios_io_addr; |
726 | 69b91039 | bellard | else
|
727 | 69b91039 | bellard | paddr = &pci_bios_mem_addr; |
728 | 69b91039 | bellard | *paddr = (*paddr + r->size - 1) & ~(r->size - 1); |
729 | 69b91039 | bellard | pci_set_io_region_addr(d, i, *paddr); |
730 | 69b91039 | bellard | *paddr += r->size; |
731 | 69b91039 | bellard | } |
732 | 69b91039 | bellard | } |
733 | 69b91039 | bellard | break;
|
734 | 69b91039 | bellard | } |
735 | 0ac32c83 | bellard | |
736 | 0ac32c83 | bellard | /* map the interrupt */
|
737 | 0ac32c83 | bellard | pin = pci_config_readb(d, PCI_INTERRUPT_PIN); |
738 | 0ac32c83 | bellard | if (pin != 0) { |
739 | 0ac32c83 | bellard | pin = pci_slot_get_pirq(d, pin - 1);
|
740 | 0ac32c83 | bellard | pic_irq = pci_irqs[pin]; |
741 | 0ac32c83 | bellard | pci_config_writeb(d, PCI_INTERRUPT_LINE, pic_irq); |
742 | 0ac32c83 | bellard | } |
743 | 69b91039 | bellard | } |
744 | 69b91039 | bellard | |
745 | 69b91039 | bellard | /*
|
746 | 69b91039 | bellard | * This function initializes the PCI devices as a normal PCI BIOS
|
747 | 69b91039 | bellard | * would do. It is provided just in case the BIOS has no support for
|
748 | 69b91039 | bellard | * PCI.
|
749 | 69b91039 | bellard | */
|
750 | 69b91039 | bellard | void pci_bios_init(void) |
751 | 69b91039 | bellard | { |
752 | 69b91039 | bellard | PCIBridge *s = &pci_bridge; |
753 | 69b91039 | bellard | PCIDevice **bus; |
754 | 0ac32c83 | bellard | int bus_num, devfn, i, irq;
|
755 | 0ac32c83 | bellard | uint8_t elcr[2];
|
756 | 69b91039 | bellard | |
757 | 69b91039 | bellard | pci_bios_io_addr = 0xc000;
|
758 | 69b91039 | bellard | pci_bios_mem_addr = 0xf0000000;
|
759 | 69b91039 | bellard | |
760 | 0ac32c83 | bellard | /* activate IRQ mappings */
|
761 | 0ac32c83 | bellard | elcr[0] = 0x00; |
762 | 0ac32c83 | bellard | elcr[1] = 0x00; |
763 | 0ac32c83 | bellard | for(i = 0; i < 4; i++) { |
764 | 0ac32c83 | bellard | irq = pci_irqs[i]; |
765 | 0ac32c83 | bellard | /* set to trigger level */
|
766 | 0ac32c83 | bellard | elcr[irq >> 3] |= (1 << (irq & 7)); |
767 | 0ac32c83 | bellard | /* activate irq remapping in PIIX */
|
768 | 0ac32c83 | bellard | pci_config_writeb((PCIDevice *)piix3_state, 0x60 + i, irq);
|
769 | 0ac32c83 | bellard | } |
770 | 0ac32c83 | bellard | isa_outb(elcr[0], 0x4d0); |
771 | 0ac32c83 | bellard | isa_outb(elcr[1], 0x4d1); |
772 | 0ac32c83 | bellard | |
773 | 69b91039 | bellard | for(bus_num = 0; bus_num < 256; bus_num++) { |
774 | 69b91039 | bellard | bus = s->pci_bus[bus_num]; |
775 | 69b91039 | bellard | if (bus) {
|
776 | 69b91039 | bellard | for(devfn = 0; devfn < 256; devfn++) { |
777 | 69b91039 | bellard | if (bus[devfn])
|
778 | 69b91039 | bellard | pci_bios_init_device(bus[devfn]); |
779 | 69b91039 | bellard | } |
780 | 69b91039 | bellard | } |
781 | 69b91039 | bellard | } |
782 | 69b91039 | bellard | } |