root / hw / pci.c @ 63ce9e0a
History | View | Annotate | Download (22.4 kB)
| 1 |
/*
|
|---|---|
| 2 |
* QEMU PCI bus manager
|
| 3 |
*
|
| 4 |
* Copyright (c) 2004 Fabrice Bellard
|
| 5 |
*
|
| 6 |
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
| 7 |
* of this software and associated documentation files (the "Software"), to deal
|
| 8 |
* in the Software without restriction, including without limitation the rights
|
| 9 |
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
| 10 |
* copies of the Software, and to permit persons to whom the Software is
|
| 11 |
* furnished to do so, subject to the following conditions:
|
| 12 |
*
|
| 13 |
* The above copyright notice and this permission notice shall be included in
|
| 14 |
* all copies or substantial portions of the Software.
|
| 15 |
*
|
| 16 |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
| 17 |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
| 18 |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
| 19 |
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
| 20 |
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
| 21 |
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
| 22 |
* THE SOFTWARE.
|
| 23 |
*/
|
| 24 |
#include "vl.h" |
| 25 |
|
| 26 |
//#define DEBUG_PCI
|
| 27 |
|
| 28 |
#define PCI_VENDOR_ID 0x00 /* 16 bits */ |
| 29 |
#define PCI_DEVICE_ID 0x02 /* 16 bits */ |
| 30 |
#define PCI_COMMAND 0x04 /* 16 bits */ |
| 31 |
#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ |
| 32 |
#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ |
| 33 |
#define PCI_CLASS_DEVICE 0x0a /* Device class */ |
| 34 |
#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ |
| 35 |
#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ |
| 36 |
#define PCI_MIN_GNT 0x3e /* 8 bits */ |
| 37 |
#define PCI_MAX_LAT 0x3f /* 8 bits */ |
| 38 |
|
| 39 |
/* just used for simpler irq handling. */
|
| 40 |
#define PCI_DEVICES_MAX 64 |
| 41 |
#define PCI_IRQ_WORDS ((PCI_DEVICES_MAX + 31) / 32) |
| 42 |
|
| 43 |
typedef struct PCIBridge { |
| 44 |
uint32_t config_reg; |
| 45 |
PCIDevice **pci_bus[256];
|
| 46 |
} PCIBridge; |
| 47 |
|
| 48 |
static PCIBridge pci_bridge;
|
| 49 |
target_phys_addr_t pci_mem_base; |
| 50 |
static int pci_irq_index; |
| 51 |
static uint32_t pci_irq_levels[4][PCI_IRQ_WORDS]; |
| 52 |
|
| 53 |
/* -1 for devfn means auto assign */
|
| 54 |
PCIDevice *pci_register_device(const char *name, int instance_size, |
| 55 |
int bus_num, int devfn, |
| 56 |
PCIConfigReadFunc *config_read, |
| 57 |
PCIConfigWriteFunc *config_write) |
| 58 |
{
|
| 59 |
PCIBridge *s = &pci_bridge; |
| 60 |
PCIDevice *pci_dev, **bus; |
| 61 |
|
| 62 |
if (pci_irq_index >= PCI_DEVICES_MAX)
|
| 63 |
return NULL; |
| 64 |
|
| 65 |
if (!s->pci_bus[bus_num]) {
|
| 66 |
s->pci_bus[bus_num] = qemu_mallocz(256 * sizeof(PCIDevice *)); |
| 67 |
if (!s->pci_bus[bus_num])
|
| 68 |
return NULL; |
| 69 |
} |
| 70 |
bus = s->pci_bus[bus_num]; |
| 71 |
if (devfn < 0) { |
| 72 |
for(devfn = 0 ; devfn < 256; devfn += 8) { |
| 73 |
if (!bus[devfn])
|
| 74 |
goto found;
|
| 75 |
} |
| 76 |
return NULL; |
| 77 |
found: ;
|
| 78 |
} |
| 79 |
pci_dev = qemu_mallocz(instance_size); |
| 80 |
if (!pci_dev)
|
| 81 |
return NULL; |
| 82 |
pci_dev->bus_num = bus_num; |
| 83 |
pci_dev->devfn = devfn; |
| 84 |
pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
|
| 85 |
|
| 86 |
if (!config_read)
|
| 87 |
config_read = pci_default_read_config; |
| 88 |
if (!config_write)
|
| 89 |
config_write = pci_default_write_config; |
| 90 |
pci_dev->config_read = config_read; |
| 91 |
pci_dev->config_write = config_write; |
| 92 |
pci_dev->irq_index = pci_irq_index++; |
| 93 |
bus[devfn] = pci_dev; |
| 94 |
return pci_dev;
|
| 95 |
} |
| 96 |
|
| 97 |
void pci_register_io_region(PCIDevice *pci_dev, int region_num, |
| 98 |
uint32_t size, int type,
|
| 99 |
PCIMapIORegionFunc *map_func) |
| 100 |
{
|
| 101 |
PCIIORegion *r; |
| 102 |
|
| 103 |
if ((unsigned int)region_num >= 6) |
| 104 |
return;
|
| 105 |
r = &pci_dev->io_regions[region_num]; |
| 106 |
r->addr = -1;
|
| 107 |
r->size = size; |
| 108 |
r->type = type; |
| 109 |
r->map_func = map_func; |
| 110 |
} |
| 111 |
|
| 112 |
static void pci_addr_writel(void* opaque, uint32_t addr, uint32_t val) |
| 113 |
{
|
| 114 |
PCIBridge *s = opaque; |
| 115 |
s->config_reg = val; |
| 116 |
} |
| 117 |
|
| 118 |
static uint32_t pci_addr_readl(void* opaque, uint32_t addr) |
| 119 |
{
|
| 120 |
PCIBridge *s = opaque; |
| 121 |
return s->config_reg;
|
| 122 |
} |
| 123 |
|
| 124 |
static void pci_update_mappings(PCIDevice *d) |
| 125 |
{
|
| 126 |
PCIIORegion *r; |
| 127 |
int cmd, i;
|
| 128 |
uint32_t last_addr, new_addr; |
| 129 |
|
| 130 |
cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND)); |
| 131 |
for(i = 0; i < 6; i++) { |
| 132 |
r = &d->io_regions[i]; |
| 133 |
if (r->size != 0) { |
| 134 |
if (r->type & PCI_ADDRESS_SPACE_IO) {
|
| 135 |
if (cmd & PCI_COMMAND_IO) {
|
| 136 |
new_addr = le32_to_cpu(*(uint32_t *)(d->config + |
| 137 |
0x10 + i * 4)); |
| 138 |
new_addr = new_addr & ~(r->size - 1);
|
| 139 |
last_addr = new_addr + r->size - 1;
|
| 140 |
/* NOTE: we have only 64K ioports on PC */
|
| 141 |
if (last_addr <= new_addr || new_addr == 0 || |
| 142 |
last_addr >= 0x10000) {
|
| 143 |
new_addr = -1;
|
| 144 |
} |
| 145 |
} else {
|
| 146 |
new_addr = -1;
|
| 147 |
} |
| 148 |
} else {
|
| 149 |
if (cmd & PCI_COMMAND_MEMORY) {
|
| 150 |
new_addr = le32_to_cpu(*(uint32_t *)(d->config + |
| 151 |
0x10 + i * 4)); |
| 152 |
new_addr = new_addr & ~(r->size - 1);
|
| 153 |
last_addr = new_addr + r->size - 1;
|
| 154 |
/* NOTE: we do not support wrapping */
|
| 155 |
/* XXX: as we cannot support really dynamic
|
| 156 |
mappings, we handle specific values as invalid
|
| 157 |
mappings. */
|
| 158 |
if (last_addr <= new_addr || new_addr == 0 || |
| 159 |
last_addr == -1) {
|
| 160 |
new_addr = -1;
|
| 161 |
} |
| 162 |
} else {
|
| 163 |
new_addr = -1;
|
| 164 |
} |
| 165 |
} |
| 166 |
/* now do the real mapping */
|
| 167 |
if (new_addr != r->addr) {
|
| 168 |
if (r->addr != -1) { |
| 169 |
if (r->type & PCI_ADDRESS_SPACE_IO) {
|
| 170 |
int class;
|
| 171 |
/* NOTE: specific hack for IDE in PC case:
|
| 172 |
only one byte must be mapped. */
|
| 173 |
class = d->config[0x0a] | (d->config[0x0b] << 8); |
| 174 |
if (class == 0x0101 && r->size == 4) { |
| 175 |
isa_unassign_ioport(r->addr + 2, 1); |
| 176 |
} else {
|
| 177 |
isa_unassign_ioport(r->addr, r->size); |
| 178 |
} |
| 179 |
} else {
|
| 180 |
cpu_register_physical_memory(r->addr + pci_mem_base, |
| 181 |
r->size, |
| 182 |
IO_MEM_UNASSIGNED); |
| 183 |
} |
| 184 |
} |
| 185 |
r->addr = new_addr; |
| 186 |
if (r->addr != -1) { |
| 187 |
r->map_func(d, i, r->addr, r->size, r->type); |
| 188 |
} |
| 189 |
} |
| 190 |
} |
| 191 |
} |
| 192 |
} |
| 193 |
|
| 194 |
uint32_t pci_default_read_config(PCIDevice *d, |
| 195 |
uint32_t address, int len)
|
| 196 |
{
|
| 197 |
uint32_t val; |
| 198 |
switch(len) {
|
| 199 |
case 1: |
| 200 |
val = d->config[address]; |
| 201 |
break;
|
| 202 |
case 2: |
| 203 |
val = le16_to_cpu(*(uint16_t *)(d->config + address)); |
| 204 |
break;
|
| 205 |
default:
|
| 206 |
case 4: |
| 207 |
val = le32_to_cpu(*(uint32_t *)(d->config + address)); |
| 208 |
break;
|
| 209 |
} |
| 210 |
return val;
|
| 211 |
} |
| 212 |
|
| 213 |
void pci_default_write_config(PCIDevice *d,
|
| 214 |
uint32_t address, uint32_t val, int len)
|
| 215 |
{
|
| 216 |
int can_write, i;
|
| 217 |
uint32_t end, addr; |
| 218 |
|
| 219 |
if (len == 4 && (address >= 0x10 && address < 0x10 + 4 * 6)) { |
| 220 |
PCIIORegion *r; |
| 221 |
int reg;
|
| 222 |
|
| 223 |
reg = (address - 0x10) >> 2; |
| 224 |
r = &d->io_regions[reg]; |
| 225 |
if (r->size == 0) |
| 226 |
goto default_config;
|
| 227 |
/* compute the stored value */
|
| 228 |
val &= ~(r->size - 1);
|
| 229 |
val |= r->type; |
| 230 |
*(uint32_t *)(d->config + 0x10 + reg * 4) = cpu_to_le32(val); |
| 231 |
pci_update_mappings(d); |
| 232 |
return;
|
| 233 |
} |
| 234 |
default_config:
|
| 235 |
/* not efficient, but simple */
|
| 236 |
addr = address; |
| 237 |
for(i = 0; i < len; i++) { |
| 238 |
/* default read/write accesses */
|
| 239 |
switch(addr) {
|
| 240 |
case 0x00: |
| 241 |
case 0x01: |
| 242 |
case 0x02: |
| 243 |
case 0x03: |
| 244 |
case 0x08: |
| 245 |
case 0x09: |
| 246 |
case 0x0a: |
| 247 |
case 0x0b: |
| 248 |
case 0x0e: |
| 249 |
case 0x3d: |
| 250 |
can_write = 0;
|
| 251 |
break;
|
| 252 |
default:
|
| 253 |
can_write = 1;
|
| 254 |
break;
|
| 255 |
} |
| 256 |
if (can_write) {
|
| 257 |
d->config[addr] = val; |
| 258 |
} |
| 259 |
addr++; |
| 260 |
val >>= 8;
|
| 261 |
} |
| 262 |
|
| 263 |
end = address + len; |
| 264 |
if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) { |
| 265 |
/* if the command register is modified, we must modify the mappings */
|
| 266 |
pci_update_mappings(d); |
| 267 |
} |
| 268 |
} |
| 269 |
|
| 270 |
static void pci_data_write(void *opaque, uint32_t addr, |
| 271 |
uint32_t val, int len)
|
| 272 |
{
|
| 273 |
PCIBridge *s = opaque; |
| 274 |
PCIDevice **bus, *pci_dev; |
| 275 |
int config_addr;
|
| 276 |
|
| 277 |
#if defined(DEBUG_PCI) && 0 |
| 278 |
printf("pci_data_write: addr=%08x val=%08x len=%d\n",
|
| 279 |
s->config_reg, val, len); |
| 280 |
#endif
|
| 281 |
if (!(s->config_reg & (1 << 31))) { |
| 282 |
return;
|
| 283 |
} |
| 284 |
if ((s->config_reg & 0x3) != 0) { |
| 285 |
return;
|
| 286 |
} |
| 287 |
bus = s->pci_bus[(s->config_reg >> 16) & 0xff]; |
| 288 |
if (!bus)
|
| 289 |
return;
|
| 290 |
pci_dev = bus[(s->config_reg >> 8) & 0xff]; |
| 291 |
if (!pci_dev)
|
| 292 |
return;
|
| 293 |
config_addr = (s->config_reg & 0xfc) | (addr & 3); |
| 294 |
#if defined(DEBUG_PCI)
|
| 295 |
printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
|
| 296 |
pci_dev->name, config_addr, val, len); |
| 297 |
#endif
|
| 298 |
pci_dev->config_write(pci_dev, config_addr, val, len); |
| 299 |
} |
| 300 |
|
| 301 |
static uint32_t pci_data_read(void *opaque, uint32_t addr, |
| 302 |
int len)
|
| 303 |
{
|
| 304 |
PCIBridge *s = opaque; |
| 305 |
PCIDevice **bus, *pci_dev; |
| 306 |
int config_addr;
|
| 307 |
uint32_t val; |
| 308 |
|
| 309 |
if (!(s->config_reg & (1 << 31))) |
| 310 |
goto fail;
|
| 311 |
if ((s->config_reg & 0x3) != 0) |
| 312 |
goto fail;
|
| 313 |
bus = s->pci_bus[(s->config_reg >> 16) & 0xff]; |
| 314 |
if (!bus)
|
| 315 |
goto fail;
|
| 316 |
pci_dev = bus[(s->config_reg >> 8) & 0xff]; |
| 317 |
if (!pci_dev) {
|
| 318 |
fail:
|
| 319 |
switch(len) {
|
| 320 |
case 1: |
| 321 |
val = 0xff;
|
| 322 |
break;
|
| 323 |
case 2: |
| 324 |
val = 0xffff;
|
| 325 |
break;
|
| 326 |
default:
|
| 327 |
case 4: |
| 328 |
val = 0xffffffff;
|
| 329 |
break;
|
| 330 |
} |
| 331 |
goto the_end;
|
| 332 |
} |
| 333 |
config_addr = (s->config_reg & 0xfc) | (addr & 3); |
| 334 |
val = pci_dev->config_read(pci_dev, config_addr, len); |
| 335 |
#if defined(DEBUG_PCI)
|
| 336 |
printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
|
| 337 |
pci_dev->name, config_addr, val, len); |
| 338 |
#endif
|
| 339 |
the_end:
|
| 340 |
#if defined(DEBUG_PCI) && 0 |
| 341 |
printf("pci_data_read: addr=%08x val=%08x len=%d\n",
|
| 342 |
s->config_reg, val, len); |
| 343 |
#endif
|
| 344 |
return val;
|
| 345 |
} |
| 346 |
|
| 347 |
static void pci_data_writeb(void* opaque, uint32_t addr, uint32_t val) |
| 348 |
{
|
| 349 |
pci_data_write(opaque, addr, val, 1);
|
| 350 |
} |
| 351 |
|
| 352 |
static void pci_data_writew(void* opaque, uint32_t addr, uint32_t val) |
| 353 |
{
|
| 354 |
pci_data_write(opaque, addr, val, 2);
|
| 355 |
} |
| 356 |
|
| 357 |
static void pci_data_writel(void* opaque, uint32_t addr, uint32_t val) |
| 358 |
{
|
| 359 |
pci_data_write(opaque, addr, val, 4);
|
| 360 |
} |
| 361 |
|
| 362 |
static uint32_t pci_data_readb(void* opaque, uint32_t addr) |
| 363 |
{
|
| 364 |
return pci_data_read(opaque, addr, 1); |
| 365 |
} |
| 366 |
|
| 367 |
static uint32_t pci_data_readw(void* opaque, uint32_t addr) |
| 368 |
{
|
| 369 |
return pci_data_read(opaque, addr, 2); |
| 370 |
} |
| 371 |
|
| 372 |
static uint32_t pci_data_readl(void* opaque, uint32_t addr) |
| 373 |
{
|
| 374 |
return pci_data_read(opaque, addr, 4); |
| 375 |
} |
| 376 |
|
| 377 |
/* i440FX PCI bridge */
|
| 378 |
|
| 379 |
void i440fx_init(void) |
| 380 |
{
|
| 381 |
PCIBridge *s = &pci_bridge; |
| 382 |
PCIDevice *d; |
| 383 |
|
| 384 |
register_ioport_write(0xcf8, 4, 4, pci_addr_writel, s); |
| 385 |
register_ioport_read(0xcf8, 4, 4, pci_addr_readl, s); |
| 386 |
|
| 387 |
register_ioport_write(0xcfc, 4, 1, pci_data_writeb, s); |
| 388 |
register_ioport_write(0xcfc, 4, 2, pci_data_writew, s); |
| 389 |
register_ioport_write(0xcfc, 4, 4, pci_data_writel, s); |
| 390 |
register_ioport_read(0xcfc, 4, 1, pci_data_readb, s); |
| 391 |
register_ioport_read(0xcfc, 4, 2, pci_data_readw, s); |
| 392 |
register_ioport_read(0xcfc, 4, 4, pci_data_readl, s); |
| 393 |
|
| 394 |
d = pci_register_device("i440FX", sizeof(PCIDevice), 0, 0, |
| 395 |
NULL, NULL); |
| 396 |
|
| 397 |
d->config[0x00] = 0x86; // vendor_id |
| 398 |
d->config[0x01] = 0x80; |
| 399 |
d->config[0x02] = 0x37; // device_id |
| 400 |
d->config[0x03] = 0x12; |
| 401 |
d->config[0x08] = 0x02; // revision |
| 402 |
d->config[0x0a] = 0x04; // class_sub = pci2pci |
| 403 |
d->config[0x0b] = 0x06; // class_base = PCI_bridge |
| 404 |
d->config[0x0c] = 0x01; // line_size in 32 bit words |
| 405 |
d->config[0x0e] = 0x01; // header_type |
| 406 |
} |
| 407 |
|
| 408 |
/* PIIX3 PCI to ISA bridge */
|
| 409 |
|
| 410 |
typedef struct PIIX3State { |
| 411 |
PCIDevice dev; |
| 412 |
} PIIX3State; |
| 413 |
|
| 414 |
PIIX3State *piix3_state; |
| 415 |
|
| 416 |
static void piix3_reset(PIIX3State *d) |
| 417 |
{
|
| 418 |
uint8_t *pci_conf = d->dev.config; |
| 419 |
|
| 420 |
pci_conf[0x04] = 0x07; // master, memory and I/O |
| 421 |
pci_conf[0x05] = 0x00; |
| 422 |
pci_conf[0x06] = 0x00; |
| 423 |
pci_conf[0x07] = 0x02; // PCI_status_devsel_medium |
| 424 |
pci_conf[0x4c] = 0x4d; |
| 425 |
pci_conf[0x4e] = 0x03; |
| 426 |
pci_conf[0x4f] = 0x00; |
| 427 |
pci_conf[0x60] = 0x80; |
| 428 |
pci_conf[0x69] = 0x02; |
| 429 |
pci_conf[0x70] = 0x80; |
| 430 |
pci_conf[0x76] = 0x0c; |
| 431 |
pci_conf[0x77] = 0x0c; |
| 432 |
pci_conf[0x78] = 0x02; |
| 433 |
pci_conf[0x79] = 0x00; |
| 434 |
pci_conf[0x80] = 0x00; |
| 435 |
pci_conf[0x82] = 0x00; |
| 436 |
pci_conf[0xa0] = 0x08; |
| 437 |
pci_conf[0xa0] = 0x08; |
| 438 |
pci_conf[0xa2] = 0x00; |
| 439 |
pci_conf[0xa3] = 0x00; |
| 440 |
pci_conf[0xa4] = 0x00; |
| 441 |
pci_conf[0xa5] = 0x00; |
| 442 |
pci_conf[0xa6] = 0x00; |
| 443 |
pci_conf[0xa7] = 0x00; |
| 444 |
pci_conf[0xa8] = 0x0f; |
| 445 |
pci_conf[0xaa] = 0x00; |
| 446 |
pci_conf[0xab] = 0x00; |
| 447 |
pci_conf[0xac] = 0x00; |
| 448 |
pci_conf[0xae] = 0x00; |
| 449 |
} |
| 450 |
|
| 451 |
void piix3_init(void) |
| 452 |
{
|
| 453 |
PIIX3State *d; |
| 454 |
uint8_t *pci_conf; |
| 455 |
|
| 456 |
d = (PIIX3State *)pci_register_device("PIIX3", sizeof(PIIX3State), |
| 457 |
0, -1, |
| 458 |
NULL, NULL); |
| 459 |
piix3_state = d; |
| 460 |
pci_conf = d->dev.config; |
| 461 |
|
| 462 |
pci_conf[0x00] = 0x86; // Intel |
| 463 |
pci_conf[0x01] = 0x80; |
| 464 |
pci_conf[0x02] = 0x00; // 82371SB PIIX3 PCI-to-ISA bridge (Step A1) |
| 465 |
pci_conf[0x03] = 0x70; |
| 466 |
pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA |
| 467 |
pci_conf[0x0b] = 0x06; // class_base = PCI_bridge |
| 468 |
pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic |
| 469 |
|
| 470 |
piix3_reset(d); |
| 471 |
} |
| 472 |
|
| 473 |
/***********************************************************/
|
| 474 |
/* generic PCI irq support */
|
| 475 |
|
| 476 |
/* return the global irq number corresponding to a given device irq
|
| 477 |
pin. We could also use the bus number to have a more precise
|
| 478 |
mapping. */
|
| 479 |
static inline int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num) |
| 480 |
{
|
| 481 |
int slot_addend;
|
| 482 |
slot_addend = (pci_dev->devfn >> 3);
|
| 483 |
return (irq_num + slot_addend) & 3; |
| 484 |
} |
| 485 |
|
| 486 |
/* 0 <= irq_num <= 3. level must be 0 or 1 */
|
| 487 |
void pci_set_irq(PCIDevice *pci_dev, int irq_num, int level) |
| 488 |
{
|
| 489 |
int irq_index, shift, pic_irq, pic_level;
|
| 490 |
uint32_t *p; |
| 491 |
|
| 492 |
irq_num = pci_slot_get_pirq(pci_dev, irq_num); |
| 493 |
irq_index = pci_dev->irq_index; |
| 494 |
p = &pci_irq_levels[irq_num][irq_index >> 5];
|
| 495 |
shift = (irq_index & 0x1f);
|
| 496 |
*p = (*p & ~(1 << shift)) | (level << shift);
|
| 497 |
|
| 498 |
/* now we change the pic irq level according to the piix irq mappings */
|
| 499 |
pic_irq = piix3_state->dev.config[0x60 + irq_num];
|
| 500 |
if (pic_irq < 16) { |
| 501 |
/* the pic level is the logical OR of all the PCI irqs mapped
|
| 502 |
to it */
|
| 503 |
pic_level = 0;
|
| 504 |
#if (PCI_IRQ_WORDS == 2) |
| 505 |
pic_level = ((pci_irq_levels[irq_num][0] |
|
| 506 |
pci_irq_levels[irq_num][1]) != 0); |
| 507 |
#else
|
| 508 |
{
|
| 509 |
int i;
|
| 510 |
pic_level = 0;
|
| 511 |
for(i = 0; i < PCI_IRQ_WORDS; i++) { |
| 512 |
if (pci_irq_levels[irq_num][i]) {
|
| 513 |
pic_level = 1;
|
| 514 |
break;
|
| 515 |
} |
| 516 |
} |
| 517 |
} |
| 518 |
#endif
|
| 519 |
pic_set_irq(pic_irq, pic_level); |
| 520 |
} |
| 521 |
} |
| 522 |
|
| 523 |
/***********************************************************/
|
| 524 |
/* monitor info on PCI */
|
| 525 |
|
| 526 |
static void pci_info_device(PCIDevice *d) |
| 527 |
{
|
| 528 |
int i, class;
|
| 529 |
PCIIORegion *r; |
| 530 |
|
| 531 |
printf(" Bus %2d, device %3d, function %d:\n",
|
| 532 |
d->bus_num, d->devfn >> 3, d->devfn & 7); |
| 533 |
class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE))); |
| 534 |
printf(" ");
|
| 535 |
switch(class) {
|
| 536 |
case 0x0101: |
| 537 |
printf("IDE controller");
|
| 538 |
break;
|
| 539 |
case 0x0200: |
| 540 |
printf("Ethernet controller");
|
| 541 |
break;
|
| 542 |
case 0x0300: |
| 543 |
printf("VGA controller");
|
| 544 |
break;
|
| 545 |
default:
|
| 546 |
printf("Class %04x", class);
|
| 547 |
break;
|
| 548 |
} |
| 549 |
printf(": PCI device %04x:%04x\n",
|
| 550 |
le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))), |
| 551 |
le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID)))); |
| 552 |
|
| 553 |
if (d->config[PCI_INTERRUPT_PIN] != 0) { |
| 554 |
printf(" IRQ %d.\n", d->config[PCI_INTERRUPT_LINE]);
|
| 555 |
} |
| 556 |
for(i = 0;i < 6; i++) { |
| 557 |
r = &d->io_regions[i]; |
| 558 |
if (r->size != 0) { |
| 559 |
printf(" BAR%d: ", i);
|
| 560 |
if (r->type & PCI_ADDRESS_SPACE_IO) {
|
| 561 |
printf("I/O at 0x%04x [0x%04x].\n",
|
| 562 |
r->addr, r->addr + r->size - 1);
|
| 563 |
} else {
|
| 564 |
printf("32 bit memory at 0x%08x [0x%08x].\n",
|
| 565 |
r->addr, r->addr + r->size - 1);
|
| 566 |
} |
| 567 |
} |
| 568 |
} |
| 569 |
} |
| 570 |
|
| 571 |
void pci_info(void) |
| 572 |
{
|
| 573 |
PCIBridge *s = &pci_bridge; |
| 574 |
PCIDevice **bus; |
| 575 |
int bus_num, devfn;
|
| 576 |
|
| 577 |
for(bus_num = 0; bus_num < 256; bus_num++) { |
| 578 |
bus = s->pci_bus[bus_num]; |
| 579 |
if (bus) {
|
| 580 |
for(devfn = 0; devfn < 256; devfn++) { |
| 581 |
if (bus[devfn])
|
| 582 |
pci_info_device(bus[devfn]); |
| 583 |
} |
| 584 |
} |
| 585 |
} |
| 586 |
} |
| 587 |
|
| 588 |
/***********************************************************/
|
| 589 |
/* XXX: the following should be moved to the PC BIOS */
|
| 590 |
|
| 591 |
static uint32_t isa_inb(uint32_t addr)
|
| 592 |
{
|
| 593 |
return cpu_inb(cpu_single_env, addr);
|
| 594 |
} |
| 595 |
|
| 596 |
static void isa_outb(uint32_t val, uint32_t addr) |
| 597 |
{
|
| 598 |
cpu_outb(cpu_single_env, addr, val); |
| 599 |
} |
| 600 |
|
| 601 |
static uint32_t isa_inw(uint32_t addr)
|
| 602 |
{
|
| 603 |
return cpu_inw(cpu_single_env, addr);
|
| 604 |
} |
| 605 |
|
| 606 |
static void isa_outw(uint32_t val, uint32_t addr) |
| 607 |
{
|
| 608 |
cpu_outw(cpu_single_env, addr, val); |
| 609 |
} |
| 610 |
|
| 611 |
static uint32_t isa_inl(uint32_t addr)
|
| 612 |
{
|
| 613 |
return cpu_inl(cpu_single_env, addr);
|
| 614 |
} |
| 615 |
|
| 616 |
static void isa_outl(uint32_t val, uint32_t addr) |
| 617 |
{
|
| 618 |
cpu_outl(cpu_single_env, addr, val); |
| 619 |
} |
| 620 |
|
| 621 |
static void pci_config_writel(PCIDevice *d, uint32_t addr, uint32_t val) |
| 622 |
{
|
| 623 |
PCIBridge *s = &pci_bridge; |
| 624 |
s->config_reg = 0x80000000 | (d->bus_num << 16) | |
| 625 |
(d->devfn << 8) | addr;
|
| 626 |
pci_data_write(s, 0, val, 4); |
| 627 |
} |
| 628 |
|
| 629 |
static void pci_config_writew(PCIDevice *d, uint32_t addr, uint32_t val) |
| 630 |
{
|
| 631 |
PCIBridge *s = &pci_bridge; |
| 632 |
s->config_reg = 0x80000000 | (d->bus_num << 16) | |
| 633 |
(d->devfn << 8) | (addr & ~3); |
| 634 |
pci_data_write(s, addr & 3, val, 2); |
| 635 |
} |
| 636 |
|
| 637 |
static void pci_config_writeb(PCIDevice *d, uint32_t addr, uint32_t val) |
| 638 |
{
|
| 639 |
PCIBridge *s = &pci_bridge; |
| 640 |
s->config_reg = 0x80000000 | (d->bus_num << 16) | |
| 641 |
(d->devfn << 8) | (addr & ~3); |
| 642 |
pci_data_write(s, addr & 3, val, 1); |
| 643 |
} |
| 644 |
|
| 645 |
static uint32_t pci_config_readl(PCIDevice *d, uint32_t addr)
|
| 646 |
{
|
| 647 |
PCIBridge *s = &pci_bridge; |
| 648 |
s->config_reg = 0x80000000 | (d->bus_num << 16) | |
| 649 |
(d->devfn << 8) | addr;
|
| 650 |
return pci_data_read(s, 0, 4); |
| 651 |
} |
| 652 |
|
| 653 |
static uint32_t pci_config_readw(PCIDevice *d, uint32_t addr)
|
| 654 |
{
|
| 655 |
PCIBridge *s = &pci_bridge; |
| 656 |
s->config_reg = 0x80000000 | (d->bus_num << 16) | |
| 657 |
(d->devfn << 8) | (addr & ~3); |
| 658 |
return pci_data_read(s, addr & 3, 2); |
| 659 |
} |
| 660 |
|
| 661 |
static uint32_t pci_config_readb(PCIDevice *d, uint32_t addr)
|
| 662 |
{
|
| 663 |
PCIBridge *s = &pci_bridge; |
| 664 |
s->config_reg = 0x80000000 | (d->bus_num << 16) | |
| 665 |
(d->devfn << 8) | (addr & ~3); |
| 666 |
return pci_data_read(s, addr & 3, 1); |
| 667 |
} |
| 668 |
|
| 669 |
static uint32_t pci_bios_io_addr;
|
| 670 |
static uint32_t pci_bios_mem_addr;
|
| 671 |
/* host irqs corresponding to PCI irqs A-D */
|
| 672 |
static uint8_t pci_irqs[4] = { 11, 9, 11, 9 }; |
| 673 |
|
| 674 |
static void pci_set_io_region_addr(PCIDevice *d, int region_num, uint32_t addr) |
| 675 |
{
|
| 676 |
PCIIORegion *r; |
| 677 |
uint16_t cmd; |
| 678 |
|
| 679 |
pci_config_writel(d, 0x10 + region_num * 4, addr); |
| 680 |
r = &d->io_regions[region_num]; |
| 681 |
|
| 682 |
/* enable memory mappings */
|
| 683 |
cmd = pci_config_readw(d, PCI_COMMAND); |
| 684 |
if (r->type & PCI_ADDRESS_SPACE_IO)
|
| 685 |
cmd |= 1;
|
| 686 |
else
|
| 687 |
cmd |= 2;
|
| 688 |
pci_config_writew(d, PCI_COMMAND, cmd); |
| 689 |
} |
| 690 |
|
| 691 |
static void pci_bios_init_device(PCIDevice *d) |
| 692 |
{
|
| 693 |
int class;
|
| 694 |
PCIIORegion *r; |
| 695 |
uint32_t *paddr; |
| 696 |
int i, pin, pic_irq, vendor_id, device_id;
|
| 697 |
|
| 698 |
class = pci_config_readw(d, PCI_CLASS_DEVICE); |
| 699 |
switch(class) {
|
| 700 |
case 0x0101: |
| 701 |
vendor_id = pci_config_readw(d, PCI_VENDOR_ID); |
| 702 |
device_id = pci_config_readw(d, PCI_DEVICE_ID); |
| 703 |
if (vendor_id == 0x8086 && device_id == 0x7010) { |
| 704 |
/* PIIX3 IDE */
|
| 705 |
pci_config_writew(d, PCI_COMMAND, PCI_COMMAND_IO); |
| 706 |
pci_config_writew(d, 0x40, 0x8000); // enable IDE0 |
| 707 |
} else {
|
| 708 |
/* IDE: we map it as in ISA mode */
|
| 709 |
pci_set_io_region_addr(d, 0, 0x1f0); |
| 710 |
pci_set_io_region_addr(d, 1, 0x3f4); |
| 711 |
pci_set_io_region_addr(d, 2, 0x170); |
| 712 |
pci_set_io_region_addr(d, 3, 0x374); |
| 713 |
} |
| 714 |
break;
|
| 715 |
case 0x0300: |
| 716 |
/* VGA: map frame buffer to default Bochs VBE address */
|
| 717 |
pci_set_io_region_addr(d, 0, 0xE0000000); |
| 718 |
break;
|
| 719 |
default:
|
| 720 |
/* default memory mappings */
|
| 721 |
for(i = 0; i < 6; i++) { |
| 722 |
r = &d->io_regions[i]; |
| 723 |
if (r->size) {
|
| 724 |
if (r->type & PCI_ADDRESS_SPACE_IO)
|
| 725 |
paddr = &pci_bios_io_addr; |
| 726 |
else
|
| 727 |
paddr = &pci_bios_mem_addr; |
| 728 |
*paddr = (*paddr + r->size - 1) & ~(r->size - 1); |
| 729 |
pci_set_io_region_addr(d, i, *paddr); |
| 730 |
*paddr += r->size; |
| 731 |
} |
| 732 |
} |
| 733 |
break;
|
| 734 |
} |
| 735 |
|
| 736 |
/* map the interrupt */
|
| 737 |
pin = pci_config_readb(d, PCI_INTERRUPT_PIN); |
| 738 |
if (pin != 0) { |
| 739 |
pin = pci_slot_get_pirq(d, pin - 1);
|
| 740 |
pic_irq = pci_irqs[pin]; |
| 741 |
pci_config_writeb(d, PCI_INTERRUPT_LINE, pic_irq); |
| 742 |
} |
| 743 |
} |
| 744 |
|
| 745 |
/*
|
| 746 |
* This function initializes the PCI devices as a normal PCI BIOS
|
| 747 |
* would do. It is provided just in case the BIOS has no support for
|
| 748 |
* PCI.
|
| 749 |
*/
|
| 750 |
void pci_bios_init(void) |
| 751 |
{
|
| 752 |
PCIBridge *s = &pci_bridge; |
| 753 |
PCIDevice **bus; |
| 754 |
int bus_num, devfn, i, irq;
|
| 755 |
uint8_t elcr[2];
|
| 756 |
|
| 757 |
pci_bios_io_addr = 0xc000;
|
| 758 |
pci_bios_mem_addr = 0xf0000000;
|
| 759 |
|
| 760 |
/* activate IRQ mappings */
|
| 761 |
elcr[0] = 0x00; |
| 762 |
elcr[1] = 0x00; |
| 763 |
for(i = 0; i < 4; i++) { |
| 764 |
irq = pci_irqs[i]; |
| 765 |
/* set to trigger level */
|
| 766 |
elcr[irq >> 3] |= (1 << (irq & 7)); |
| 767 |
/* activate irq remapping in PIIX */
|
| 768 |
pci_config_writeb((PCIDevice *)piix3_state, 0x60 + i, irq);
|
| 769 |
} |
| 770 |
isa_outb(elcr[0], 0x4d0); |
| 771 |
isa_outb(elcr[1], 0x4d1); |
| 772 |
|
| 773 |
for(bus_num = 0; bus_num < 256; bus_num++) { |
| 774 |
bus = s->pci_bus[bus_num]; |
| 775 |
if (bus) {
|
| 776 |
for(devfn = 0; devfn < 256; devfn++) { |
| 777 |
if (bus[devfn])
|
| 778 |
pci_bios_init_device(bus[devfn]); |
| 779 |
} |
| 780 |
} |
| 781 |
} |
| 782 |
} |