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/*
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* internal execution defines for qemu
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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/* allow to see translation results - the slowdown should be negligible, so we leave it */
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#define DEBUG_DISAS
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#ifndef glue
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#define xglue(x, y) x ## y |
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#define glue(x, y) xglue(x, y)
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#define stringify(s) tostring(s)
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#define tostring(s) #s |
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#endif
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#ifndef likely
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#if __GNUC__ < 3 |
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#define __builtin_expect(x, n) (x)
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#endif
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#define likely(x) __builtin_expect(!!(x), 1) |
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#define unlikely(x) __builtin_expect(!!(x), 0) |
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#endif
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#ifndef always_inline
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#if (__GNUC__ < 3) || defined(__APPLE__) |
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#define always_inline inline |
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#else
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#define always_inline __attribute__ (( always_inline )) inline |
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#endif
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#endif
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#ifdef __i386__
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#define REGPARM(n) __attribute((regparm(n)))
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#else
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#define REGPARM(n)
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#endif
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/* is_jmp field values */
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#define DISAS_NEXT 0 /* next instruction can be analyzed */ |
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#define DISAS_JUMP 1 /* only pc was modified dynamically */ |
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#define DISAS_UPDATE 2 /* cpu state was modified dynamically */ |
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#define DISAS_TB_JUMP 3 /* only pc was modified statically */ |
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struct TranslationBlock;
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/* XXX: make safe guess about sizes */
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#define MAX_OP_PER_INSTR 32 |
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#define OPC_BUF_SIZE 512 |
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#define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
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#define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * 3) |
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extern uint16_t gen_opc_buf[OPC_BUF_SIZE];
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extern uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE];
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extern long gen_labels[OPC_BUF_SIZE]; |
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extern int nb_gen_labels; |
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extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
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extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
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extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
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extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
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extern target_ulong gen_opc_jump_pc[2]; |
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extern uint32_t gen_opc_hflags[OPC_BUF_SIZE];
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typedef void (GenOpFunc)(void); |
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typedef void (GenOpFunc1)(long); |
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typedef void (GenOpFunc2)(long, long); |
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typedef void (GenOpFunc3)(long, long, long); |
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#if defined(TARGET_I386)
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void optimize_flags_init(void); |
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#endif
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extern FILE *logfile;
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extern int loglevel; |
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void muls64(int64_t *phigh, int64_t *plow, int64_t a, int64_t b);
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void mulu64(uint64_t *phigh, uint64_t *plow, uint64_t a, uint64_t b);
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int gen_intermediate_code(CPUState *env, struct TranslationBlock *tb); |
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int gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb); |
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void dump_ops(const uint16_t *opc_buf, const uint32_t *opparam_buf); |
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int cpu_gen_code(CPUState *env, struct TranslationBlock *tb, |
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int max_code_size, int *gen_code_size_ptr); |
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int cpu_restore_state(struct TranslationBlock *tb, |
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CPUState *env, unsigned long searched_pc, |
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void *puc);
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int cpu_gen_code_copy(CPUState *env, struct TranslationBlock *tb, |
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int max_code_size, int *gen_code_size_ptr); |
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int cpu_restore_state_copy(struct TranslationBlock *tb, |
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CPUState *env, unsigned long searched_pc, |
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void *puc);
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void cpu_resume_from_signal(CPUState *env1, void *puc); |
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void cpu_exec_init(CPUState *env);
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int page_unprotect(target_ulong address, unsigned long pc, void *puc); |
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void tb_invalidate_phys_page_range(target_ulong start, target_ulong end,
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int is_cpu_write_access);
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void tb_invalidate_page_range(target_ulong start, target_ulong end);
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void tlb_flush_page(CPUState *env, target_ulong addr);
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void tlb_flush(CPUState *env, int flush_global); |
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int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
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target_phys_addr_t paddr, int prot,
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int mmu_idx, int is_softmmu); |
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static inline int tlb_set_page(CPUState *env, target_ulong vaddr, |
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target_phys_addr_t paddr, int prot,
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int mmu_idx, int is_softmmu) |
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{
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if (prot & PAGE_READ)
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prot |= PAGE_EXEC; |
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return tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
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} |
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#define CODE_GEN_MAX_SIZE 65536 |
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#define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ |
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#define CODE_GEN_PHYS_HASH_BITS 15 |
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#define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS) |
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/* maximum total translate dcode allocated */
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/* NOTE: the translated code area cannot be too big because on some
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archs the range of "fast" function calls is limited. Here is a
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summary of the ranges:
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i386 : signed 32 bits
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arm : signed 26 bits
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ppc : signed 24 bits
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sparc : signed 32 bits
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alpha : signed 23 bits
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*/
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#if defined(__alpha__)
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#define CODE_GEN_BUFFER_SIZE (2 * 1024 * 1024) |
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#elif defined(__ia64)
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#define CODE_GEN_BUFFER_SIZE (4 * 1024 * 1024) /* range of addl */ |
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#elif defined(__powerpc__)
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#define CODE_GEN_BUFFER_SIZE (6 * 1024 * 1024) |
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#else
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#define CODE_GEN_BUFFER_SIZE (16 * 1024 * 1024) |
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#endif
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//#define CODE_GEN_BUFFER_SIZE (128 * 1024)
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/* estimated block size for TB allocation */
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/* XXX: use a per code average code fragment size and modulate it
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according to the host CPU */
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#if defined(CONFIG_SOFTMMU)
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#define CODE_GEN_AVG_BLOCK_SIZE 128 |
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#else
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#define CODE_GEN_AVG_BLOCK_SIZE 64 |
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#endif
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#define CODE_GEN_MAX_BLOCKS (CODE_GEN_BUFFER_SIZE / CODE_GEN_AVG_BLOCK_SIZE)
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#if defined(__powerpc__)
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#define USE_DIRECT_JUMP
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#endif
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#if defined(__i386__) && !defined(_WIN32)
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#define USE_DIRECT_JUMP
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#endif
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typedef struct TranslationBlock { |
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target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
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target_ulong cs_base; /* CS base for this block */
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uint64_t flags; /* flags defining in which context the code was generated */
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uint16_t size; /* size of target code for this block (1 <=
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size <= TARGET_PAGE_SIZE) */
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uint16_t cflags; /* compile flags */
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#define CF_CODE_COPY 0x0001 /* block was generated in code copy mode */ |
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#define CF_TB_FP_USED 0x0002 /* fp ops are used in the TB */ |
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#define CF_FP_USED 0x0004 /* fp ops are used in the TB or in a chained TB */ |
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#define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */ |
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uint8_t *tc_ptr; /* pointer to the translated code */
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/* next matching tb for physical address. */
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struct TranslationBlock *phys_hash_next;
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/* first and second physical page containing code. The lower bit
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of the pointer tells the index in page_next[] */
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struct TranslationBlock *page_next[2]; |
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target_ulong page_addr[2];
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/* the following data are used to directly call another TB from
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the code of this one. */
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uint16_t tb_next_offset[2]; /* offset of original jump target */ |
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#ifdef USE_DIRECT_JUMP
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uint16_t tb_jmp_offset[4]; /* offset of jump instruction */ |
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#else
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uint32_t tb_next[2]; /* address of jump generated code */ |
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#endif
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/* list of TBs jumping to this one. This is a circular list using
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the two least significant bits of the pointers to tell what is
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the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
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jmp_first */
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struct TranslationBlock *jmp_next[2]; |
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struct TranslationBlock *jmp_first;
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} TranslationBlock; |
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static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc) |
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{
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target_ulong tmp; |
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tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)); |
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return (tmp >> TB_JMP_PAGE_BITS) & TB_JMP_PAGE_MASK;
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} |
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static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc) |
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{
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target_ulong tmp; |
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tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)); |
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return (((tmp >> TB_JMP_PAGE_BITS) & TB_JMP_PAGE_MASK) |
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(tmp & TB_JMP_ADDR_MASK)); |
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} |
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static inline unsigned int tb_phys_hash_func(unsigned long pc) |
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{
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return pc & (CODE_GEN_PHYS_HASH_SIZE - 1); |
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} |
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TranslationBlock *tb_alloc(target_ulong pc); |
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void tb_flush(CPUState *env);
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void tb_link_phys(TranslationBlock *tb,
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target_ulong phys_pc, target_ulong phys_page2); |
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extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
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extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
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extern uint8_t *code_gen_ptr;
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#if defined(USE_DIRECT_JUMP)
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#if defined(__powerpc__)
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static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) |
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{
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uint32_t val, *ptr; |
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/* patch the branch destination */
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ptr = (uint32_t *)jmp_addr; |
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val = *ptr; |
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val = (val & ~0x03fffffc) | ((addr - jmp_addr) & 0x03fffffc); |
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*ptr = val; |
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/* flush icache */
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asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory"); |
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asm volatile ("sync" : : : "memory"); |
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asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory"); |
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asm volatile ("sync" : : : "memory"); |
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asm volatile ("isync" : : : "memory"); |
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} |
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#elif defined(__i386__)
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static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) |
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{
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/* patch the branch destination */
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*(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
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/* no need to flush icache explicitely */
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} |
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#endif
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static inline void tb_set_jmp_target(TranslationBlock *tb, |
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int n, unsigned long addr) |
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{
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unsigned long offset; |
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offset = tb->tb_jmp_offset[n]; |
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tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr); |
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offset = tb->tb_jmp_offset[n + 2];
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if (offset != 0xffff) |
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tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr); |
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} |
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#else
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/* set the jump target */
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static inline void tb_set_jmp_target(TranslationBlock *tb, |
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int n, unsigned long addr) |
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{
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tb->tb_next[n] = addr; |
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} |
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#endif
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static inline void tb_add_jump(TranslationBlock *tb, int n, |
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TranslationBlock *tb_next) |
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{
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/* NOTE: this test is only needed for thread safety */
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if (!tb->jmp_next[n]) {
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/* patch the native jump address */
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tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr); |
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|
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/* add in TB jmp circular list */
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tb->jmp_next[n] = tb_next->jmp_first; |
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tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
|
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} |
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} |
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|
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TranslationBlock *tb_find_pc(unsigned long pc_ptr); |
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|
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#ifndef offsetof
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#define offsetof(type, field) ((size_t) &((type *)0)->field) |
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#endif
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|
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#if defined(_WIN32)
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#define ASM_DATA_SECTION ".section \".data\"\n" |
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#define ASM_PREVIOUS_SECTION ".section .text\n" |
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#elif defined(__APPLE__)
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#define ASM_DATA_SECTION ".data\n" |
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#define ASM_PREVIOUS_SECTION ".text\n" |
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#else
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#define ASM_DATA_SECTION ".section \".data\"\n" |
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#define ASM_PREVIOUS_SECTION ".previous\n" |
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#endif
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|
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#define ASM_OP_LABEL_NAME(n, opname) \
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ASM_NAME(__op_label) #n "." ASM_NAME(opname) |
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|
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#if defined(__powerpc__)
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/* we patch the jump instruction directly */
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#define GOTO_TB(opname, tbparam, n)\
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do {\
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asm volatile (ASM_DATA_SECTION\ |
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ASM_OP_LABEL_NAME(n, opname) ":\n"\
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".long 1f\n"\
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ASM_PREVIOUS_SECTION \ |
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"b " ASM_NAME(__op_jmp) #n "\n"\ |
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"1:\n");\
|
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} while (0) |
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|
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#elif defined(__i386__) && defined(USE_DIRECT_JUMP)
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|
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/* we patch the jump instruction directly */
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#define GOTO_TB(opname, tbparam, n)\
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do {\
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asm volatile (".section .data\n"\ |
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ASM_OP_LABEL_NAME(n, opname) ":\n"\
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".long 1f\n"\
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ASM_PREVIOUS_SECTION \ |
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"jmp " ASM_NAME(__op_jmp) #n "\n"\ |
| 353 |
"1:\n");\
|
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} while (0) |
| 355 |
|
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#elif defined(__s390__)
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/* GCC spills R13, so we have to restore it before branching away */
|
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|
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#define GOTO_TB(opname, tbparam, n)\
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do {\
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static void __attribute__((used)) *dummy ## n = &&dummy_label ## n;\ |
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static void __attribute__((used)) *__op_label ## n \ |
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__asm__(ASM_OP_LABEL_NAME(n, opname)) = &&label ## n;\ |
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__asm__ __volatile__ ( \ |
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"l %%r13,52(%%r15)\n" \
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"br %0\n" \
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: : "r" (((TranslationBlock*)tbparam)->tb_next[n]));\
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\ |
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for(;*((int*)0);); /* just to keep GCC busy */ \ |
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label ## n: ;\ |
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dummy_label ## n: ;\ |
| 372 |
} while(0) |
| 373 |
|
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#else
|
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|
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/* jump to next block operations (more portable code, does not need
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cache flushing, but slower because of indirect jump) */
|
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#define GOTO_TB(opname, tbparam, n)\
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do {\
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static void __attribute__((used)) *dummy ## n = &&dummy_label ## n;\ |
| 381 |
static void __attribute__((used)) *__op_label ## n \ |
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__asm__(ASM_OP_LABEL_NAME(n, opname)) = &&label ## n;\ |
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goto *(void *)(((TranslationBlock *)tbparam)->tb_next[n]);\ |
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label ## n: ;\ |
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dummy_label ## n: ;\ |
| 386 |
} while (0) |
| 387 |
|
| 388 |
#endif
|
| 389 |
|
| 390 |
extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4]; |
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extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4]; |
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extern void *io_mem_opaque[IO_MEM_NB_ENTRIES]; |
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|
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#if defined(__powerpc__)
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static inline int testandset (int *p) |
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{
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int ret;
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__asm__ __volatile__ ( |
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"0: lwarx %0,0,%1\n"
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" xor. %0,%3,%0\n"
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" bne 1f\n"
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" stwcx. %2,0,%1\n"
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" bne- 0b\n"
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"1: "
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: "=&r" (ret)
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: "r" (p), "r" (1), "r" (0) |
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: "cr0", "memory"); |
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return ret;
|
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} |
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#elif defined(__i386__)
|
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static inline int testandset (int *p) |
| 412 |
{
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long int readval = 0; |
| 414 |
|
| 415 |
__asm__ __volatile__ ("lock; cmpxchgl %2, %0"
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| 416 |
: "+m" (*p), "+a" (readval) |
| 417 |
: "r" (1) |
| 418 |
: "cc");
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return readval;
|
| 420 |
} |
| 421 |
#elif defined(__x86_64__)
|
| 422 |
static inline int testandset (int *p) |
| 423 |
{
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| 424 |
long int readval = 0; |
| 425 |
|
| 426 |
__asm__ __volatile__ ("lock; cmpxchgl %2, %0"
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: "+m" (*p), "+a" (readval) |
| 428 |
: "r" (1) |
| 429 |
: "cc");
|
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return readval;
|
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} |
| 432 |
#elif defined(__s390__)
|
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static inline int testandset (int *p) |
| 434 |
{
|
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int ret;
|
| 436 |
|
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__asm__ __volatile__ ("0: cs %0,%1,0(%2)\n"
|
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" jl 0b"
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: "=&d" (ret)
|
| 440 |
: "r" (1), "a" (p), "0" (*p) |
| 441 |
: "cc", "memory" ); |
| 442 |
return ret;
|
| 443 |
} |
| 444 |
#elif defined(__alpha__)
|
| 445 |
static inline int testandset (int *p) |
| 446 |
{
|
| 447 |
int ret;
|
| 448 |
unsigned long one; |
| 449 |
|
| 450 |
__asm__ __volatile__ ("0: mov 1,%2\n"
|
| 451 |
" ldl_l %0,%1\n"
|
| 452 |
" stl_c %2,%1\n"
|
| 453 |
" beq %2,1f\n"
|
| 454 |
".subsection 2\n"
|
| 455 |
"1: br 0b\n"
|
| 456 |
".previous"
|
| 457 |
: "=r" (ret), "=m" (*p), "=r" (one) |
| 458 |
: "m" (*p));
|
| 459 |
return ret;
|
| 460 |
} |
| 461 |
#elif defined(__sparc__)
|
| 462 |
static inline int testandset (int *p) |
| 463 |
{
|
| 464 |
int ret;
|
| 465 |
|
| 466 |
__asm__ __volatile__("ldstub [%1], %0"
|
| 467 |
: "=r" (ret)
|
| 468 |
: "r" (p)
|
| 469 |
: "memory");
|
| 470 |
|
| 471 |
return (ret ? 1 : 0); |
| 472 |
} |
| 473 |
#elif defined(__arm__)
|
| 474 |
static inline int testandset (int *spinlock) |
| 475 |
{
|
| 476 |
register unsigned int ret; |
| 477 |
__asm__ __volatile__("swp %0, %1, [%2]"
|
| 478 |
: "=r"(ret)
|
| 479 |
: "0"(1), "r"(spinlock)); |
| 480 |
|
| 481 |
return ret;
|
| 482 |
} |
| 483 |
#elif defined(__mc68000)
|
| 484 |
static inline int testandset (int *p) |
| 485 |
{
|
| 486 |
char ret;
|
| 487 |
__asm__ __volatile__("tas %1; sne %0"
|
| 488 |
: "=r" (ret)
|
| 489 |
: "m" (p)
|
| 490 |
: "cc","memory"); |
| 491 |
return ret;
|
| 492 |
} |
| 493 |
#elif defined(__ia64)
|
| 494 |
|
| 495 |
#include <ia64intrin.h> |
| 496 |
|
| 497 |
static inline int testandset (int *p) |
| 498 |
{
|
| 499 |
return __sync_lock_test_and_set (p, 1); |
| 500 |
} |
| 501 |
#elif defined(__mips__)
|
| 502 |
static inline int testandset (int *p) |
| 503 |
{
|
| 504 |
int ret;
|
| 505 |
|
| 506 |
__asm__ __volatile__ ( |
| 507 |
" .set push \n"
|
| 508 |
" .set noat \n"
|
| 509 |
" .set mips2 \n"
|
| 510 |
"1: li $1, 1 \n"
|
| 511 |
" ll %0, %1 \n"
|
| 512 |
" sc $1, %1 \n"
|
| 513 |
" beqz $1, 1b \n"
|
| 514 |
" .set pop "
|
| 515 |
: "=r" (ret), "+R" (*p) |
| 516 |
: |
| 517 |
: "memory");
|
| 518 |
|
| 519 |
return ret;
|
| 520 |
} |
| 521 |
#else
|
| 522 |
#error unimplemented CPU support
|
| 523 |
#endif
|
| 524 |
|
| 525 |
typedef int spinlock_t; |
| 526 |
|
| 527 |
#define SPIN_LOCK_UNLOCKED 0 |
| 528 |
|
| 529 |
#if defined(CONFIG_USER_ONLY)
|
| 530 |
static inline void spin_lock(spinlock_t *lock) |
| 531 |
{
|
| 532 |
while (testandset(lock));
|
| 533 |
} |
| 534 |
|
| 535 |
static inline void spin_unlock(spinlock_t *lock) |
| 536 |
{
|
| 537 |
*lock = 0;
|
| 538 |
} |
| 539 |
|
| 540 |
static inline int spin_trylock(spinlock_t *lock) |
| 541 |
{
|
| 542 |
return !testandset(lock);
|
| 543 |
} |
| 544 |
#else
|
| 545 |
static inline void spin_lock(spinlock_t *lock) |
| 546 |
{
|
| 547 |
} |
| 548 |
|
| 549 |
static inline void spin_unlock(spinlock_t *lock) |
| 550 |
{
|
| 551 |
} |
| 552 |
|
| 553 |
static inline int spin_trylock(spinlock_t *lock) |
| 554 |
{
|
| 555 |
return 1; |
| 556 |
} |
| 557 |
#endif
|
| 558 |
|
| 559 |
extern spinlock_t tb_lock;
|
| 560 |
|
| 561 |
extern int tb_invalidated_flag; |
| 562 |
|
| 563 |
#if !defined(CONFIG_USER_ONLY)
|
| 564 |
|
| 565 |
void tlb_fill(target_ulong addr, int is_write, int mmu_idx, |
| 566 |
void *retaddr);
|
| 567 |
|
| 568 |
#define ACCESS_TYPE (NB_MMU_MODES + 1) |
| 569 |
#define MEMSUFFIX _code
|
| 570 |
#define env cpu_single_env
|
| 571 |
|
| 572 |
#define DATA_SIZE 1 |
| 573 |
#include "softmmu_header.h" |
| 574 |
|
| 575 |
#define DATA_SIZE 2 |
| 576 |
#include "softmmu_header.h" |
| 577 |
|
| 578 |
#define DATA_SIZE 4 |
| 579 |
#include "softmmu_header.h" |
| 580 |
|
| 581 |
#define DATA_SIZE 8 |
| 582 |
#include "softmmu_header.h" |
| 583 |
|
| 584 |
#undef ACCESS_TYPE
|
| 585 |
#undef MEMSUFFIX
|
| 586 |
#undef env
|
| 587 |
|
| 588 |
#endif
|
| 589 |
|
| 590 |
#if defined(CONFIG_USER_ONLY)
|
| 591 |
static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr) |
| 592 |
{
|
| 593 |
return addr;
|
| 594 |
} |
| 595 |
#else
|
| 596 |
/* NOTE: this function can trigger an exception */
|
| 597 |
/* NOTE2: the returned address is not exactly the physical address: it
|
| 598 |
is the offset relative to phys_ram_base */
|
| 599 |
static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr) |
| 600 |
{
|
| 601 |
int mmu_idx, index, pd;
|
| 602 |
|
| 603 |
index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
|
| 604 |
mmu_idx = cpu_mmu_index(env); |
| 605 |
if (__builtin_expect(env->tlb_table[mmu_idx][index].addr_code !=
|
| 606 |
(addr & TARGET_PAGE_MASK), 0)) {
|
| 607 |
ldub_code(addr); |
| 608 |
} |
| 609 |
pd = env->tlb_table[mmu_idx][index].addr_code & ~TARGET_PAGE_MASK; |
| 610 |
if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
|
| 611 |
#if defined(TARGET_SPARC) || defined(TARGET_MIPS)
|
| 612 |
do_unassigned_access(addr, 0, 1, 0); |
| 613 |
#else
|
| 614 |
cpu_abort(env, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr); |
| 615 |
#endif
|
| 616 |
} |
| 617 |
return addr + env->tlb_table[mmu_idx][index].addend - (unsigned long)phys_ram_base; |
| 618 |
} |
| 619 |
#endif
|
| 620 |
|
| 621 |
#ifdef USE_KQEMU
|
| 622 |
#define KQEMU_MODIFY_PAGE_MASK (0xff & ~(VGA_DIRTY_FLAG | CODE_DIRTY_FLAG)) |
| 623 |
|
| 624 |
int kqemu_init(CPUState *env);
|
| 625 |
int kqemu_cpu_exec(CPUState *env);
|
| 626 |
void kqemu_flush_page(CPUState *env, target_ulong addr);
|
| 627 |
void kqemu_flush(CPUState *env, int global); |
| 628 |
void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr);
|
| 629 |
void kqemu_modify_page(CPUState *env, ram_addr_t ram_addr);
|
| 630 |
void kqemu_cpu_interrupt(CPUState *env);
|
| 631 |
void kqemu_record_dump(void); |
| 632 |
|
| 633 |
static inline int kqemu_is_ok(CPUState *env) |
| 634 |
{
|
| 635 |
return(env->kqemu_enabled &&
|
| 636 |
(env->cr[0] & CR0_PE_MASK) &&
|
| 637 |
!(env->hflags & HF_INHIBIT_IRQ_MASK) && |
| 638 |
(env->eflags & IF_MASK) && |
| 639 |
!(env->eflags & VM_MASK) && |
| 640 |
(env->kqemu_enabled == 2 ||
|
| 641 |
((env->hflags & HF_CPL_MASK) == 3 &&
|
| 642 |
(env->eflags & IOPL_MASK) != IOPL_MASK))); |
| 643 |
} |
| 644 |
|
| 645 |
#endif
|