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root / target-ppc @ 651721b2

Name Size
STATUS 10.6 kB
cpu.h 59.4 kB
exec.h 1.5 kB
helper.c 93.7 kB
helper.h 13.7 kB
helper_regs.h 3.4 kB
kvm.c 4.8 kB
kvm_ppc.c 2.6 kB
kvm_ppc.h 434 Bytes
machine.c 5.8 kB
mfrom_table.c 3.3 kB
mfrom_table_gen.c 652 Bytes
op_helper.c 123.8 kB
translate.c 310.6 kB
translate_init.c 413.3 kB

Latest revisions

# Date Author Comment
651721b2 03/09/2009 08:50 pm aurel32

targe-ppc: optimize mfcr and mtcrf

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6793 c046a42c-6fe2-441c-8c8c-71466251a162
69bd5820 03/09/2009 08:27 am aurel32

target-ppc: free a tcg temp variable

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6790 c046a42c-6fe2-441c-8c8c-71466251a162
d34defbc 03/09/2009 08:27 am aurel32

target-ppc: add support for reading/writing spefscr

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6789 c046a42c-6fe2-441c-8c8c-71466251a162
70976a79 03/08/2009 12:00 am aurel32

Fix off-by-one errors for Altivec and SPE registers

Altivec and SPE both have 34 registers in their register sets, not 35
with a missing register 32.

GDB would ask for register 32 of the Altivec (resp. SPE) registers and
the code would claim it had zero width. The QEMU GDB stub code would...
94855937 03/07/2009 10:58 pm blueswir1

Disable BAT for 970

The 970 doesn't know BAT, so let's not search BATs there.
This was only in as a hack for OpenHackWare so it would
work on PPC64.

Signed-off-by: Alexander Graf <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6759 c046a42c-6fe2-441c-8c8c-71466251a162
0497d2f4 03/07/2009 10:57 pm aurel32

Fix mfcr on ppc64-softmmu

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6758 c046a42c-6fe2-441c-8c8c-71466251a162
8eee0af9 03/07/2009 10:57 pm blueswir1

Keep SLB in-CPU

Real 970 CPUs have the SLB not memory backed, but inside the CPU.
This breaks bridge mode for 970 for now, but at least keeps us from
overwriting physical addresses 0x0 - 0x300, rendering our interrupt
handlers useless.

I put in a stub for bridge mode operation that could be enabled...
29c8ca6f 03/07/2009 10:57 pm blueswir1

Fix NX bit

ctx->nx only got ORed, but never reset. So when one page in the
lifetime of the VM was ever NX, all later pages were too.

Signed-off-by: Alexander Graf <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6755 c046a42c-6fe2-441c-8c8c-71466251a162
2ada0ed7 03/07/2009 10:56 pm blueswir1

Fix RFI

The current implementation masks some MSR bits from SRR1 as it is
given on rfi(d). This looks pretty wrong and breaks Altivec.

Signed-off-by: Alexander Graf <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6754 c046a42c-6fe2-441c-8c8c-71466251a162
4911012d 03/07/2009 10:55 pm blueswir1

Implement mtfsf.L encoding

Mtfsf can have the L bit set, so all the register contents get stored
in FPSCR. Linux uses it, so let's implement it.

Signed-off-by: Alexander Graf <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6753 c046a42c-6fe2-441c-8c8c-71466251a162

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