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1 | 80cabfad | bellard | /*
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2 | 80cabfad | bellard | * QEMU NE2000 emulation
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3 | 5fafdf24 | ths | *
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4 | 80cabfad | bellard | * Copyright (c) 2003-2004 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 80cabfad | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 80cabfad | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 80cabfad | bellard | * in the Software without restriction, including without limitation the rights
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9 | 80cabfad | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 80cabfad | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 80cabfad | bellard | * furnished to do so, subject to the following conditions:
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12 | 80cabfad | bellard | *
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13 | 80cabfad | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 80cabfad | bellard | * all copies or substantial portions of the Software.
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15 | 80cabfad | bellard | *
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16 | 80cabfad | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 80cabfad | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 80cabfad | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 80cabfad | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 80cabfad | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 80cabfad | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 80cabfad | bellard | * THE SOFTWARE.
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23 | 80cabfad | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "pci.h" |
26 | 87ecb68b | pbrook | #include "net.h" |
27 | 9453c5bc | Gerd Hoffmann | #include "ne2000.h" |
28 | a783cc3e | Gerd Hoffmann | #include "loader.h" |
29 | 1ca4d09a | Gleb Natapov | #include "sysemu.h" |
30 | 80cabfad | bellard | |
31 | 80cabfad | bellard | /* debug NE2000 card */
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32 | 80cabfad | bellard | //#define DEBUG_NE2000
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33 | 80cabfad | bellard | |
34 | b41a2cd1 | bellard | #define MAX_ETH_FRAME_SIZE 1514 |
35 | 80cabfad | bellard | |
36 | 80cabfad | bellard | #define E8390_CMD 0x00 /* The command register (for all pages) */ |
37 | 80cabfad | bellard | /* Page 0 register offsets. */
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38 | 80cabfad | bellard | #define EN0_CLDALO 0x01 /* Low byte of current local dma addr RD */ |
39 | 80cabfad | bellard | #define EN0_STARTPG 0x01 /* Starting page of ring bfr WR */ |
40 | 80cabfad | bellard | #define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */ |
41 | 80cabfad | bellard | #define EN0_STOPPG 0x02 /* Ending page +1 of ring bfr WR */ |
42 | 80cabfad | bellard | #define EN0_BOUNDARY 0x03 /* Boundary page of ring bfr RD WR */ |
43 | 80cabfad | bellard | #define EN0_TSR 0x04 /* Transmit status reg RD */ |
44 | 80cabfad | bellard | #define EN0_TPSR 0x04 /* Transmit starting page WR */ |
45 | 80cabfad | bellard | #define EN0_NCR 0x05 /* Number of collision reg RD */ |
46 | 80cabfad | bellard | #define EN0_TCNTLO 0x05 /* Low byte of tx byte count WR */ |
47 | 80cabfad | bellard | #define EN0_FIFO 0x06 /* FIFO RD */ |
48 | 80cabfad | bellard | #define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */ |
49 | 80cabfad | bellard | #define EN0_ISR 0x07 /* Interrupt status reg RD WR */ |
50 | 80cabfad | bellard | #define EN0_CRDALO 0x08 /* low byte of current remote dma address RD */ |
51 | 80cabfad | bellard | #define EN0_RSARLO 0x08 /* Remote start address reg 0 */ |
52 | 80cabfad | bellard | #define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */ |
53 | 80cabfad | bellard | #define EN0_RSARHI 0x09 /* Remote start address reg 1 */ |
54 | 80cabfad | bellard | #define EN0_RCNTLO 0x0a /* Remote byte count reg WR */ |
55 | 089af991 | bellard | #define EN0_RTL8029ID0 0x0a /* Realtek ID byte #1 RD */ |
56 | 80cabfad | bellard | #define EN0_RCNTHI 0x0b /* Remote byte count reg WR */ |
57 | 089af991 | bellard | #define EN0_RTL8029ID1 0x0b /* Realtek ID byte #2 RD */ |
58 | 80cabfad | bellard | #define EN0_RSR 0x0c /* rx status reg RD */ |
59 | 80cabfad | bellard | #define EN0_RXCR 0x0c /* RX configuration reg WR */ |
60 | 80cabfad | bellard | #define EN0_TXCR 0x0d /* TX configuration reg WR */ |
61 | 80cabfad | bellard | #define EN0_COUNTER0 0x0d /* Rcv alignment error counter RD */ |
62 | 80cabfad | bellard | #define EN0_DCFG 0x0e /* Data configuration reg WR */ |
63 | 80cabfad | bellard | #define EN0_COUNTER1 0x0e /* Rcv CRC error counter RD */ |
64 | 80cabfad | bellard | #define EN0_IMR 0x0f /* Interrupt mask reg WR */ |
65 | 80cabfad | bellard | #define EN0_COUNTER2 0x0f /* Rcv missed frame error counter RD */ |
66 | 80cabfad | bellard | |
67 | 80cabfad | bellard | #define EN1_PHYS 0x11 |
68 | 80cabfad | bellard | #define EN1_CURPAG 0x17 |
69 | 80cabfad | bellard | #define EN1_MULT 0x18 |
70 | 80cabfad | bellard | |
71 | a343df16 | bellard | #define EN2_STARTPG 0x21 /* Starting page of ring bfr RD */ |
72 | a343df16 | bellard | #define EN2_STOPPG 0x22 /* Ending page +1 of ring bfr RD */ |
73 | a343df16 | bellard | |
74 | 089af991 | bellard | #define EN3_CONFIG0 0x33 |
75 | 089af991 | bellard | #define EN3_CONFIG1 0x34 |
76 | 089af991 | bellard | #define EN3_CONFIG2 0x35 |
77 | 089af991 | bellard | #define EN3_CONFIG3 0x36 |
78 | 089af991 | bellard | |
79 | 80cabfad | bellard | /* Register accessed at EN_CMD, the 8390 base addr. */
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80 | 80cabfad | bellard | #define E8390_STOP 0x01 /* Stop and reset the chip */ |
81 | 80cabfad | bellard | #define E8390_START 0x02 /* Start the chip, clear reset */ |
82 | 80cabfad | bellard | #define E8390_TRANS 0x04 /* Transmit a frame */ |
83 | 80cabfad | bellard | #define E8390_RREAD 0x08 /* Remote read */ |
84 | 80cabfad | bellard | #define E8390_RWRITE 0x10 /* Remote write */ |
85 | 80cabfad | bellard | #define E8390_NODMA 0x20 /* Remote DMA */ |
86 | 80cabfad | bellard | #define E8390_PAGE0 0x00 /* Select page chip registers */ |
87 | 80cabfad | bellard | #define E8390_PAGE1 0x40 /* using the two high-order bits */ |
88 | 80cabfad | bellard | #define E8390_PAGE2 0x80 /* Page 3 is invalid. */ |
89 | 80cabfad | bellard | |
90 | 80cabfad | bellard | /* Bits in EN0_ISR - Interrupt status register */
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91 | 80cabfad | bellard | #define ENISR_RX 0x01 /* Receiver, no error */ |
92 | 80cabfad | bellard | #define ENISR_TX 0x02 /* Transmitter, no error */ |
93 | 80cabfad | bellard | #define ENISR_RX_ERR 0x04 /* Receiver, with error */ |
94 | 80cabfad | bellard | #define ENISR_TX_ERR 0x08 /* Transmitter, with error */ |
95 | 80cabfad | bellard | #define ENISR_OVER 0x10 /* Receiver overwrote the ring */ |
96 | 80cabfad | bellard | #define ENISR_COUNTERS 0x20 /* Counters need emptying */ |
97 | 80cabfad | bellard | #define ENISR_RDC 0x40 /* remote dma complete */ |
98 | 80cabfad | bellard | #define ENISR_RESET 0x80 /* Reset completed */ |
99 | 80cabfad | bellard | #define ENISR_ALL 0x3f /* Interrupts we will enable */ |
100 | 80cabfad | bellard | |
101 | 80cabfad | bellard | /* Bits in received packet status byte and EN0_RSR*/
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102 | 80cabfad | bellard | #define ENRSR_RXOK 0x01 /* Received a good packet */ |
103 | 80cabfad | bellard | #define ENRSR_CRC 0x02 /* CRC error */ |
104 | 80cabfad | bellard | #define ENRSR_FAE 0x04 /* frame alignment error */ |
105 | 80cabfad | bellard | #define ENRSR_FO 0x08 /* FIFO overrun */ |
106 | 80cabfad | bellard | #define ENRSR_MPA 0x10 /* missed pkt */ |
107 | 80cabfad | bellard | #define ENRSR_PHY 0x20 /* physical/multicast address */ |
108 | 80cabfad | bellard | #define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */ |
109 | 80cabfad | bellard | #define ENRSR_DEF 0x80 /* deferring */ |
110 | 80cabfad | bellard | |
111 | 80cabfad | bellard | /* Transmitted packet status, EN0_TSR. */
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112 | 80cabfad | bellard | #define ENTSR_PTX 0x01 /* Packet transmitted without error */ |
113 | 80cabfad | bellard | #define ENTSR_ND 0x02 /* The transmit wasn't deferred. */ |
114 | 80cabfad | bellard | #define ENTSR_COL 0x04 /* The transmit collided at least once. */ |
115 | 80cabfad | bellard | #define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */ |
116 | 80cabfad | bellard | #define ENTSR_CRS 0x10 /* The carrier sense was lost. */ |
117 | 80cabfad | bellard | #define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */ |
118 | 80cabfad | bellard | #define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */ |
119 | 80cabfad | bellard | #define ENTSR_OWC 0x80 /* There was an out-of-window collision. */ |
120 | 80cabfad | bellard | |
121 | 2b7a050a | Juan Quintela | typedef struct PCINE2000State { |
122 | 2b7a050a | Juan Quintela | PCIDevice dev; |
123 | 2b7a050a | Juan Quintela | NE2000State ne2000; |
124 | 2b7a050a | Juan Quintela | } PCINE2000State; |
125 | 2b7a050a | Juan Quintela | |
126 | 9453c5bc | Gerd Hoffmann | void ne2000_reset(NE2000State *s)
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127 | 80cabfad | bellard | { |
128 | 80cabfad | bellard | int i;
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129 | 80cabfad | bellard | |
130 | 80cabfad | bellard | s->isr = ENISR_RESET; |
131 | 93db6685 | Gerd Hoffmann | memcpy(s->mem, &s->c.macaddr, 6);
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132 | 80cabfad | bellard | s->mem[14] = 0x57; |
133 | 80cabfad | bellard | s->mem[15] = 0x57; |
134 | 80cabfad | bellard | |
135 | 80cabfad | bellard | /* duplicate prom data */
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136 | 80cabfad | bellard | for(i = 15;i >= 0; i--) { |
137 | 80cabfad | bellard | s->mem[2 * i] = s->mem[i];
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138 | 80cabfad | bellard | s->mem[2 * i + 1] = s->mem[i]; |
139 | 80cabfad | bellard | } |
140 | 80cabfad | bellard | } |
141 | 80cabfad | bellard | |
142 | 80cabfad | bellard | static void ne2000_update_irq(NE2000State *s) |
143 | 80cabfad | bellard | { |
144 | 80cabfad | bellard | int isr;
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145 | a343df16 | bellard | isr = (s->isr & s->imr) & 0x7f;
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146 | a541f297 | bellard | #if defined(DEBUG_NE2000)
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147 | d537cf6c | pbrook | printf("NE2000: Set IRQ to %d (%02x %02x)\n",
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148 | d537cf6c | pbrook | isr ? 1 : 0, s->isr, s->imr); |
149 | a541f297 | bellard | #endif
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150 | d537cf6c | pbrook | qemu_set_irq(s->irq, (isr != 0));
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151 | 80cabfad | bellard | } |
152 | 80cabfad | bellard | |
153 | 7c9d8e07 | bellard | #define POLYNOMIAL 0x04c11db6 |
154 | 7c9d8e07 | bellard | |
155 | 7c9d8e07 | bellard | /* From FreeBSD */
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156 | 7c9d8e07 | bellard | /* XXX: optimize */
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157 | 7c9d8e07 | bellard | static int compute_mcast_idx(const uint8_t *ep) |
158 | 7c9d8e07 | bellard | { |
159 | 7c9d8e07 | bellard | uint32_t crc; |
160 | 7c9d8e07 | bellard | int carry, i, j;
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161 | 7c9d8e07 | bellard | uint8_t b; |
162 | 7c9d8e07 | bellard | |
163 | 7c9d8e07 | bellard | crc = 0xffffffff;
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164 | 7c9d8e07 | bellard | for (i = 0; i < 6; i++) { |
165 | 7c9d8e07 | bellard | b = *ep++; |
166 | 7c9d8e07 | bellard | for (j = 0; j < 8; j++) { |
167 | 7c9d8e07 | bellard | carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01); |
168 | 7c9d8e07 | bellard | crc <<= 1;
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169 | 7c9d8e07 | bellard | b >>= 1;
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170 | 7c9d8e07 | bellard | if (carry)
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171 | 7c9d8e07 | bellard | crc = ((crc ^ POLYNOMIAL) | carry); |
172 | 7c9d8e07 | bellard | } |
173 | 7c9d8e07 | bellard | } |
174 | 7c9d8e07 | bellard | return (crc >> 26); |
175 | 7c9d8e07 | bellard | } |
176 | 7c9d8e07 | bellard | |
177 | d861b05e | pbrook | static int ne2000_buffer_full(NE2000State *s) |
178 | 80cabfad | bellard | { |
179 | 80cabfad | bellard | int avail, index, boundary;
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180 | d861b05e | pbrook | |
181 | 80cabfad | bellard | index = s->curpag << 8;
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182 | 80cabfad | bellard | boundary = s->boundary << 8;
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183 | 28c1c656 | ths | if (index < boundary)
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184 | 80cabfad | bellard | avail = boundary - index; |
185 | 80cabfad | bellard | else
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186 | 80cabfad | bellard | avail = (s->stop - s->start) - (index - boundary); |
187 | 80cabfad | bellard | if (avail < (MAX_ETH_FRAME_SIZE + 4)) |
188 | d861b05e | pbrook | return 1; |
189 | d861b05e | pbrook | return 0; |
190 | d861b05e | pbrook | } |
191 | d861b05e | pbrook | |
192 | 1c2045b5 | Mark McLoughlin | int ne2000_can_receive(VLANClientState *nc)
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193 | d861b05e | pbrook | { |
194 | 1c2045b5 | Mark McLoughlin | NE2000State *s = DO_UPCAST(NICState, nc, nc)->opaque; |
195 | 3b46e624 | ths | |
196 | d861b05e | pbrook | if (s->cmd & E8390_STOP)
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197 | e89f00e6 | aurel32 | return 1; |
198 | d861b05e | pbrook | return !ne2000_buffer_full(s);
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199 | 80cabfad | bellard | } |
200 | 80cabfad | bellard | |
201 | b41a2cd1 | bellard | #define MIN_BUF_SIZE 60 |
202 | b41a2cd1 | bellard | |
203 | 1c2045b5 | Mark McLoughlin | ssize_t ne2000_receive(VLANClientState *nc, const uint8_t *buf, size_t size_)
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204 | 80cabfad | bellard | { |
205 | 1c2045b5 | Mark McLoughlin | NE2000State *s = DO_UPCAST(NICState, nc, nc)->opaque; |
206 | 4f1c942b | Mark McLoughlin | int size = size_;
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207 | 80cabfad | bellard | uint8_t *p; |
208 | 0ae045ae | ths | unsigned int total_len, next, avail, len, index, mcast_idx; |
209 | b41a2cd1 | bellard | uint8_t buf1[60];
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210 | 5fafdf24 | ths | static const uint8_t broadcast_macaddr[6] = |
211 | 7c9d8e07 | bellard | { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; |
212 | 3b46e624 | ths | |
213 | 80cabfad | bellard | #if defined(DEBUG_NE2000)
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214 | 80cabfad | bellard | printf("NE2000: received len=%d\n", size);
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215 | 80cabfad | bellard | #endif
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216 | 80cabfad | bellard | |
217 | d861b05e | pbrook | if (s->cmd & E8390_STOP || ne2000_buffer_full(s))
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218 | 4f1c942b | Mark McLoughlin | return -1; |
219 | 3b46e624 | ths | |
220 | 7c9d8e07 | bellard | /* XXX: check this */
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221 | 7c9d8e07 | bellard | if (s->rxcr & 0x10) { |
222 | 7c9d8e07 | bellard | /* promiscuous: receive all */
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223 | 7c9d8e07 | bellard | } else {
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224 | 7c9d8e07 | bellard | if (!memcmp(buf, broadcast_macaddr, 6)) { |
225 | 7c9d8e07 | bellard | /* broadcast address */
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226 | 7c9d8e07 | bellard | if (!(s->rxcr & 0x04)) |
227 | 4f1c942b | Mark McLoughlin | return size;
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228 | 7c9d8e07 | bellard | } else if (buf[0] & 0x01) { |
229 | 7c9d8e07 | bellard | /* multicast */
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230 | 7c9d8e07 | bellard | if (!(s->rxcr & 0x08)) |
231 | 4f1c942b | Mark McLoughlin | return size;
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232 | 7c9d8e07 | bellard | mcast_idx = compute_mcast_idx(buf); |
233 | 7c9d8e07 | bellard | if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7)))) |
234 | 4f1c942b | Mark McLoughlin | return size;
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235 | 7c9d8e07 | bellard | } else if (s->mem[0] == buf[0] && |
236 | 3b46e624 | ths | s->mem[2] == buf[1] && |
237 | 3b46e624 | ths | s->mem[4] == buf[2] && |
238 | 3b46e624 | ths | s->mem[6] == buf[3] && |
239 | 3b46e624 | ths | s->mem[8] == buf[4] && |
240 | 7c9d8e07 | bellard | s->mem[10] == buf[5]) { |
241 | 7c9d8e07 | bellard | /* match */
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242 | 7c9d8e07 | bellard | } else {
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243 | 4f1c942b | Mark McLoughlin | return size;
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244 | 7c9d8e07 | bellard | } |
245 | 7c9d8e07 | bellard | } |
246 | 7c9d8e07 | bellard | |
247 | 7c9d8e07 | bellard | |
248 | b41a2cd1 | bellard | /* if too small buffer, then expand it */
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249 | b41a2cd1 | bellard | if (size < MIN_BUF_SIZE) {
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250 | b41a2cd1 | bellard | memcpy(buf1, buf, size); |
251 | b41a2cd1 | bellard | memset(buf1 + size, 0, MIN_BUF_SIZE - size);
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252 | b41a2cd1 | bellard | buf = buf1; |
253 | b41a2cd1 | bellard | size = MIN_BUF_SIZE; |
254 | b41a2cd1 | bellard | } |
255 | b41a2cd1 | bellard | |
256 | 80cabfad | bellard | index = s->curpag << 8;
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257 | 80cabfad | bellard | /* 4 bytes for header */
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258 | 80cabfad | bellard | total_len = size + 4;
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259 | 80cabfad | bellard | /* address for next packet (4 bytes for CRC) */
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260 | 80cabfad | bellard | next = index + ((total_len + 4 + 255) & ~0xff); |
261 | 80cabfad | bellard | if (next >= s->stop)
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262 | 80cabfad | bellard | next -= (s->stop - s->start); |
263 | 80cabfad | bellard | /* prepare packet header */
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264 | 80cabfad | bellard | p = s->mem + index; |
265 | 8d6c7eb8 | bellard | s->rsr = ENRSR_RXOK; /* receive status */
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266 | 8d6c7eb8 | bellard | /* XXX: check this */
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267 | 8d6c7eb8 | bellard | if (buf[0] & 0x01) |
268 | 8d6c7eb8 | bellard | s->rsr |= ENRSR_PHY; |
269 | 8d6c7eb8 | bellard | p[0] = s->rsr;
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270 | 80cabfad | bellard | p[1] = next >> 8; |
271 | 80cabfad | bellard | p[2] = total_len;
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272 | 80cabfad | bellard | p[3] = total_len >> 8; |
273 | 80cabfad | bellard | index += 4;
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274 | 80cabfad | bellard | |
275 | 80cabfad | bellard | /* write packet data */
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276 | 80cabfad | bellard | while (size > 0) { |
277 | 0ae045ae | ths | if (index <= s->stop)
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278 | 0ae045ae | ths | avail = s->stop - index; |
279 | 0ae045ae | ths | else
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280 | 0ae045ae | ths | avail = 0;
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281 | 80cabfad | bellard | len = size; |
282 | 80cabfad | bellard | if (len > avail)
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283 | 80cabfad | bellard | len = avail; |
284 | 80cabfad | bellard | memcpy(s->mem + index, buf, len); |
285 | 80cabfad | bellard | buf += len; |
286 | 80cabfad | bellard | index += len; |
287 | 80cabfad | bellard | if (index == s->stop)
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288 | 80cabfad | bellard | index = s->start; |
289 | 80cabfad | bellard | size -= len; |
290 | 80cabfad | bellard | } |
291 | 80cabfad | bellard | s->curpag = next >> 8;
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292 | 8d6c7eb8 | bellard | |
293 | 9f083493 | ths | /* now we can signal we have received something */
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294 | 80cabfad | bellard | s->isr |= ENISR_RX; |
295 | 80cabfad | bellard | ne2000_update_irq(s); |
296 | 4f1c942b | Mark McLoughlin | |
297 | 4f1c942b | Mark McLoughlin | return size_;
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298 | 80cabfad | bellard | } |
299 | 80cabfad | bellard | |
300 | 9453c5bc | Gerd Hoffmann | void ne2000_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
301 | 80cabfad | bellard | { |
302 | b41a2cd1 | bellard | NE2000State *s = opaque; |
303 | 40545f84 | bellard | int offset, page, index;
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304 | 80cabfad | bellard | |
305 | 80cabfad | bellard | addr &= 0xf;
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306 | 80cabfad | bellard | #ifdef DEBUG_NE2000
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307 | 80cabfad | bellard | printf("NE2000: write addr=0x%x val=0x%02x\n", addr, val);
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308 | 80cabfad | bellard | #endif
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309 | 80cabfad | bellard | if (addr == E8390_CMD) {
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310 | 80cabfad | bellard | /* control register */
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311 | 80cabfad | bellard | s->cmd = val; |
312 | a343df16 | bellard | if (!(val & E8390_STOP)) { /* START bit makes no sense on RTL8029... */ |
313 | ee9dbb29 | bellard | s->isr &= ~ENISR_RESET; |
314 | e91c8a77 | ths | /* test specific case: zero length transfer */
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315 | 80cabfad | bellard | if ((val & (E8390_RREAD | E8390_RWRITE)) &&
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316 | 80cabfad | bellard | s->rcnt == 0) {
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317 | 80cabfad | bellard | s->isr |= ENISR_RDC; |
318 | 80cabfad | bellard | ne2000_update_irq(s); |
319 | 80cabfad | bellard | } |
320 | 80cabfad | bellard | if (val & E8390_TRANS) {
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321 | 40545f84 | bellard | index = (s->tpsr << 8);
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322 | 5fafdf24 | ths | /* XXX: next 2 lines are a hack to make netware 3.11 work */
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323 | 40545f84 | bellard | if (index >= NE2000_PMEM_END)
|
324 | 40545f84 | bellard | index -= NE2000_PMEM_SIZE; |
325 | 40545f84 | bellard | /* fail safe: check range on the transmitted length */
|
326 | 40545f84 | bellard | if (index + s->tcnt <= NE2000_PMEM_END) {
|
327 | 1c2045b5 | Mark McLoughlin | qemu_send_packet(&s->nic->nc, s->mem + index, s->tcnt); |
328 | 40545f84 | bellard | } |
329 | e91c8a77 | ths | /* signal end of transfer */
|
330 | 80cabfad | bellard | s->tsr = ENTSR_PTX; |
331 | 80cabfad | bellard | s->isr |= ENISR_TX; |
332 | 5fafdf24 | ths | s->cmd &= ~E8390_TRANS; |
333 | 80cabfad | bellard | ne2000_update_irq(s); |
334 | 80cabfad | bellard | } |
335 | 80cabfad | bellard | } |
336 | 80cabfad | bellard | } else {
|
337 | 80cabfad | bellard | page = s->cmd >> 6;
|
338 | 80cabfad | bellard | offset = addr | (page << 4);
|
339 | 80cabfad | bellard | switch(offset) {
|
340 | 80cabfad | bellard | case EN0_STARTPG:
|
341 | 80cabfad | bellard | s->start = val << 8;
|
342 | 80cabfad | bellard | break;
|
343 | 80cabfad | bellard | case EN0_STOPPG:
|
344 | 80cabfad | bellard | s->stop = val << 8;
|
345 | 80cabfad | bellard | break;
|
346 | 80cabfad | bellard | case EN0_BOUNDARY:
|
347 | 80cabfad | bellard | s->boundary = val; |
348 | 80cabfad | bellard | break;
|
349 | 80cabfad | bellard | case EN0_IMR:
|
350 | 80cabfad | bellard | s->imr = val; |
351 | 80cabfad | bellard | ne2000_update_irq(s); |
352 | 80cabfad | bellard | break;
|
353 | 80cabfad | bellard | case EN0_TPSR:
|
354 | 80cabfad | bellard | s->tpsr = val; |
355 | 80cabfad | bellard | break;
|
356 | 80cabfad | bellard | case EN0_TCNTLO:
|
357 | 80cabfad | bellard | s->tcnt = (s->tcnt & 0xff00) | val;
|
358 | 80cabfad | bellard | break;
|
359 | 80cabfad | bellard | case EN0_TCNTHI:
|
360 | 80cabfad | bellard | s->tcnt = (s->tcnt & 0x00ff) | (val << 8); |
361 | 80cabfad | bellard | break;
|
362 | 80cabfad | bellard | case EN0_RSARLO:
|
363 | 80cabfad | bellard | s->rsar = (s->rsar & 0xff00) | val;
|
364 | 80cabfad | bellard | break;
|
365 | 80cabfad | bellard | case EN0_RSARHI:
|
366 | 80cabfad | bellard | s->rsar = (s->rsar & 0x00ff) | (val << 8); |
367 | 80cabfad | bellard | break;
|
368 | 80cabfad | bellard | case EN0_RCNTLO:
|
369 | 80cabfad | bellard | s->rcnt = (s->rcnt & 0xff00) | val;
|
370 | 80cabfad | bellard | break;
|
371 | 80cabfad | bellard | case EN0_RCNTHI:
|
372 | 80cabfad | bellard | s->rcnt = (s->rcnt & 0x00ff) | (val << 8); |
373 | 80cabfad | bellard | break;
|
374 | 7c9d8e07 | bellard | case EN0_RXCR:
|
375 | 7c9d8e07 | bellard | s->rxcr = val; |
376 | 7c9d8e07 | bellard | break;
|
377 | 80cabfad | bellard | case EN0_DCFG:
|
378 | 80cabfad | bellard | s->dcfg = val; |
379 | 80cabfad | bellard | break;
|
380 | 80cabfad | bellard | case EN0_ISR:
|
381 | ee9dbb29 | bellard | s->isr &= ~(val & 0x7f);
|
382 | 80cabfad | bellard | ne2000_update_irq(s); |
383 | 80cabfad | bellard | break;
|
384 | 80cabfad | bellard | case EN1_PHYS ... EN1_PHYS + 5: |
385 | 80cabfad | bellard | s->phys[offset - EN1_PHYS] = val; |
386 | 80cabfad | bellard | break;
|
387 | 80cabfad | bellard | case EN1_CURPAG:
|
388 | 80cabfad | bellard | s->curpag = val; |
389 | 80cabfad | bellard | break;
|
390 | 80cabfad | bellard | case EN1_MULT ... EN1_MULT + 7: |
391 | 80cabfad | bellard | s->mult[offset - EN1_MULT] = val; |
392 | 80cabfad | bellard | break;
|
393 | 80cabfad | bellard | } |
394 | 80cabfad | bellard | } |
395 | 80cabfad | bellard | } |
396 | 80cabfad | bellard | |
397 | 9453c5bc | Gerd Hoffmann | uint32_t ne2000_ioport_read(void *opaque, uint32_t addr)
|
398 | 80cabfad | bellard | { |
399 | b41a2cd1 | bellard | NE2000State *s = opaque; |
400 | 80cabfad | bellard | int offset, page, ret;
|
401 | 80cabfad | bellard | |
402 | 80cabfad | bellard | addr &= 0xf;
|
403 | 80cabfad | bellard | if (addr == E8390_CMD) {
|
404 | 80cabfad | bellard | ret = s->cmd; |
405 | 80cabfad | bellard | } else {
|
406 | 80cabfad | bellard | page = s->cmd >> 6;
|
407 | 80cabfad | bellard | offset = addr | (page << 4);
|
408 | 80cabfad | bellard | switch(offset) {
|
409 | 80cabfad | bellard | case EN0_TSR:
|
410 | 80cabfad | bellard | ret = s->tsr; |
411 | 80cabfad | bellard | break;
|
412 | 80cabfad | bellard | case EN0_BOUNDARY:
|
413 | 80cabfad | bellard | ret = s->boundary; |
414 | 80cabfad | bellard | break;
|
415 | 80cabfad | bellard | case EN0_ISR:
|
416 | 80cabfad | bellard | ret = s->isr; |
417 | 80cabfad | bellard | break;
|
418 | ee9dbb29 | bellard | case EN0_RSARLO:
|
419 | ee9dbb29 | bellard | ret = s->rsar & 0x00ff;
|
420 | ee9dbb29 | bellard | break;
|
421 | ee9dbb29 | bellard | case EN0_RSARHI:
|
422 | ee9dbb29 | bellard | ret = s->rsar >> 8;
|
423 | ee9dbb29 | bellard | break;
|
424 | 80cabfad | bellard | case EN1_PHYS ... EN1_PHYS + 5: |
425 | 80cabfad | bellard | ret = s->phys[offset - EN1_PHYS]; |
426 | 80cabfad | bellard | break;
|
427 | 80cabfad | bellard | case EN1_CURPAG:
|
428 | 80cabfad | bellard | ret = s->curpag; |
429 | 80cabfad | bellard | break;
|
430 | 80cabfad | bellard | case EN1_MULT ... EN1_MULT + 7: |
431 | 80cabfad | bellard | ret = s->mult[offset - EN1_MULT]; |
432 | 80cabfad | bellard | break;
|
433 | 8d6c7eb8 | bellard | case EN0_RSR:
|
434 | 8d6c7eb8 | bellard | ret = s->rsr; |
435 | 8d6c7eb8 | bellard | break;
|
436 | a343df16 | bellard | case EN2_STARTPG:
|
437 | a343df16 | bellard | ret = s->start >> 8;
|
438 | a343df16 | bellard | break;
|
439 | a343df16 | bellard | case EN2_STOPPG:
|
440 | a343df16 | bellard | ret = s->stop >> 8;
|
441 | a343df16 | bellard | break;
|
442 | 089af991 | bellard | case EN0_RTL8029ID0:
|
443 | 089af991 | bellard | ret = 0x50;
|
444 | 089af991 | bellard | break;
|
445 | 089af991 | bellard | case EN0_RTL8029ID1:
|
446 | 089af991 | bellard | ret = 0x43;
|
447 | 089af991 | bellard | break;
|
448 | 089af991 | bellard | case EN3_CONFIG0:
|
449 | 089af991 | bellard | ret = 0; /* 10baseT media */ |
450 | 089af991 | bellard | break;
|
451 | 089af991 | bellard | case EN3_CONFIG2:
|
452 | 089af991 | bellard | ret = 0x40; /* 10baseT active */ |
453 | 089af991 | bellard | break;
|
454 | 089af991 | bellard | case EN3_CONFIG3:
|
455 | 089af991 | bellard | ret = 0x40; /* Full duplex */ |
456 | 089af991 | bellard | break;
|
457 | 80cabfad | bellard | default:
|
458 | 80cabfad | bellard | ret = 0x00;
|
459 | 80cabfad | bellard | break;
|
460 | 80cabfad | bellard | } |
461 | 80cabfad | bellard | } |
462 | 80cabfad | bellard | #ifdef DEBUG_NE2000
|
463 | 80cabfad | bellard | printf("NE2000: read addr=0x%x val=%02x\n", addr, ret);
|
464 | 80cabfad | bellard | #endif
|
465 | 80cabfad | bellard | return ret;
|
466 | 80cabfad | bellard | } |
467 | 80cabfad | bellard | |
468 | 5fafdf24 | ths | static inline void ne2000_mem_writeb(NE2000State *s, uint32_t addr, |
469 | 69b91039 | bellard | uint32_t val) |
470 | ee9dbb29 | bellard | { |
471 | 5fafdf24 | ths | if (addr < 32 || |
472 | ee9dbb29 | bellard | (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { |
473 | ee9dbb29 | bellard | s->mem[addr] = val; |
474 | ee9dbb29 | bellard | } |
475 | ee9dbb29 | bellard | } |
476 | ee9dbb29 | bellard | |
477 | 5fafdf24 | ths | static inline void ne2000_mem_writew(NE2000State *s, uint32_t addr, |
478 | ee9dbb29 | bellard | uint32_t val) |
479 | ee9dbb29 | bellard | { |
480 | ee9dbb29 | bellard | addr &= ~1; /* XXX: check exact behaviour if not even */ |
481 | 5fafdf24 | ths | if (addr < 32 || |
482 | ee9dbb29 | bellard | (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { |
483 | 69b91039 | bellard | *(uint16_t *)(s->mem + addr) = cpu_to_le16(val); |
484 | 69b91039 | bellard | } |
485 | 69b91039 | bellard | } |
486 | 69b91039 | bellard | |
487 | 5fafdf24 | ths | static inline void ne2000_mem_writel(NE2000State *s, uint32_t addr, |
488 | 69b91039 | bellard | uint32_t val) |
489 | 69b91039 | bellard | { |
490 | 57ccbabe | bellard | addr &= ~1; /* XXX: check exact behaviour if not even */ |
491 | 5fafdf24 | ths | if (addr < 32 || |
492 | 69b91039 | bellard | (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { |
493 | 57ccbabe | bellard | cpu_to_le32wu((uint32_t *)(s->mem + addr), val); |
494 | ee9dbb29 | bellard | } |
495 | ee9dbb29 | bellard | } |
496 | ee9dbb29 | bellard | |
497 | ee9dbb29 | bellard | static inline uint32_t ne2000_mem_readb(NE2000State *s, uint32_t addr) |
498 | ee9dbb29 | bellard | { |
499 | 5fafdf24 | ths | if (addr < 32 || |
500 | ee9dbb29 | bellard | (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { |
501 | ee9dbb29 | bellard | return s->mem[addr];
|
502 | ee9dbb29 | bellard | } else {
|
503 | ee9dbb29 | bellard | return 0xff; |
504 | ee9dbb29 | bellard | } |
505 | ee9dbb29 | bellard | } |
506 | ee9dbb29 | bellard | |
507 | ee9dbb29 | bellard | static inline uint32_t ne2000_mem_readw(NE2000State *s, uint32_t addr) |
508 | ee9dbb29 | bellard | { |
509 | ee9dbb29 | bellard | addr &= ~1; /* XXX: check exact behaviour if not even */ |
510 | 5fafdf24 | ths | if (addr < 32 || |
511 | ee9dbb29 | bellard | (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { |
512 | 69b91039 | bellard | return le16_to_cpu(*(uint16_t *)(s->mem + addr));
|
513 | ee9dbb29 | bellard | } else {
|
514 | ee9dbb29 | bellard | return 0xffff; |
515 | ee9dbb29 | bellard | } |
516 | ee9dbb29 | bellard | } |
517 | ee9dbb29 | bellard | |
518 | 69b91039 | bellard | static inline uint32_t ne2000_mem_readl(NE2000State *s, uint32_t addr) |
519 | 69b91039 | bellard | { |
520 | 57ccbabe | bellard | addr &= ~1; /* XXX: check exact behaviour if not even */ |
521 | 5fafdf24 | ths | if (addr < 32 || |
522 | 69b91039 | bellard | (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { |
523 | 57ccbabe | bellard | return le32_to_cpupu((uint32_t *)(s->mem + addr));
|
524 | 69b91039 | bellard | } else {
|
525 | 69b91039 | bellard | return 0xffffffff; |
526 | 69b91039 | bellard | } |
527 | 69b91039 | bellard | } |
528 | 69b91039 | bellard | |
529 | 3df3f6fd | bellard | static inline void ne2000_dma_update(NE2000State *s, int len) |
530 | 3df3f6fd | bellard | { |
531 | 3df3f6fd | bellard | s->rsar += len; |
532 | 3df3f6fd | bellard | /* wrap */
|
533 | 3df3f6fd | bellard | /* XXX: check what to do if rsar > stop */
|
534 | 3df3f6fd | bellard | if (s->rsar == s->stop)
|
535 | 3df3f6fd | bellard | s->rsar = s->start; |
536 | 3df3f6fd | bellard | |
537 | 3df3f6fd | bellard | if (s->rcnt <= len) {
|
538 | 3df3f6fd | bellard | s->rcnt = 0;
|
539 | e91c8a77 | ths | /* signal end of transfer */
|
540 | 3df3f6fd | bellard | s->isr |= ENISR_RDC; |
541 | 3df3f6fd | bellard | ne2000_update_irq(s); |
542 | 3df3f6fd | bellard | } else {
|
543 | 3df3f6fd | bellard | s->rcnt -= len; |
544 | 3df3f6fd | bellard | } |
545 | 3df3f6fd | bellard | } |
546 | 3df3f6fd | bellard | |
547 | 9453c5bc | Gerd Hoffmann | void ne2000_asic_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
548 | 80cabfad | bellard | { |
549 | b41a2cd1 | bellard | NE2000State *s = opaque; |
550 | 80cabfad | bellard | |
551 | 80cabfad | bellard | #ifdef DEBUG_NE2000
|
552 | 80cabfad | bellard | printf("NE2000: asic write val=0x%04x\n", val);
|
553 | 80cabfad | bellard | #endif
|
554 | ee9dbb29 | bellard | if (s->rcnt == 0) |
555 | 3df3f6fd | bellard | return;
|
556 | 80cabfad | bellard | if (s->dcfg & 0x01) { |
557 | 80cabfad | bellard | /* 16 bit access */
|
558 | ee9dbb29 | bellard | ne2000_mem_writew(s, s->rsar, val); |
559 | 3df3f6fd | bellard | ne2000_dma_update(s, 2);
|
560 | 80cabfad | bellard | } else {
|
561 | 80cabfad | bellard | /* 8 bit access */
|
562 | ee9dbb29 | bellard | ne2000_mem_writeb(s, s->rsar, val); |
563 | 3df3f6fd | bellard | ne2000_dma_update(s, 1);
|
564 | 80cabfad | bellard | } |
565 | 80cabfad | bellard | } |
566 | 80cabfad | bellard | |
567 | 9453c5bc | Gerd Hoffmann | uint32_t ne2000_asic_ioport_read(void *opaque, uint32_t addr)
|
568 | 80cabfad | bellard | { |
569 | b41a2cd1 | bellard | NE2000State *s = opaque; |
570 | 80cabfad | bellard | int ret;
|
571 | 80cabfad | bellard | |
572 | 80cabfad | bellard | if (s->dcfg & 0x01) { |
573 | 80cabfad | bellard | /* 16 bit access */
|
574 | ee9dbb29 | bellard | ret = ne2000_mem_readw(s, s->rsar); |
575 | 3df3f6fd | bellard | ne2000_dma_update(s, 2);
|
576 | 80cabfad | bellard | } else {
|
577 | 80cabfad | bellard | /* 8 bit access */
|
578 | ee9dbb29 | bellard | ret = ne2000_mem_readb(s, s->rsar); |
579 | 3df3f6fd | bellard | ne2000_dma_update(s, 1);
|
580 | 80cabfad | bellard | } |
581 | 80cabfad | bellard | #ifdef DEBUG_NE2000
|
582 | 80cabfad | bellard | printf("NE2000: asic read val=0x%04x\n", ret);
|
583 | 80cabfad | bellard | #endif
|
584 | 80cabfad | bellard | return ret;
|
585 | 80cabfad | bellard | } |
586 | 80cabfad | bellard | |
587 | 69b91039 | bellard | static void ne2000_asic_ioport_writel(void *opaque, uint32_t addr, uint32_t val) |
588 | 69b91039 | bellard | { |
589 | 69b91039 | bellard | NE2000State *s = opaque; |
590 | 69b91039 | bellard | |
591 | 69b91039 | bellard | #ifdef DEBUG_NE2000
|
592 | 69b91039 | bellard | printf("NE2000: asic writel val=0x%04x\n", val);
|
593 | 69b91039 | bellard | #endif
|
594 | 69b91039 | bellard | if (s->rcnt == 0) |
595 | 3df3f6fd | bellard | return;
|
596 | 69b91039 | bellard | /* 32 bit access */
|
597 | 69b91039 | bellard | ne2000_mem_writel(s, s->rsar, val); |
598 | 3df3f6fd | bellard | ne2000_dma_update(s, 4);
|
599 | 69b91039 | bellard | } |
600 | 69b91039 | bellard | |
601 | 69b91039 | bellard | static uint32_t ne2000_asic_ioport_readl(void *opaque, uint32_t addr) |
602 | 69b91039 | bellard | { |
603 | 69b91039 | bellard | NE2000State *s = opaque; |
604 | 69b91039 | bellard | int ret;
|
605 | 69b91039 | bellard | |
606 | 69b91039 | bellard | /* 32 bit access */
|
607 | 69b91039 | bellard | ret = ne2000_mem_readl(s, s->rsar); |
608 | 3df3f6fd | bellard | ne2000_dma_update(s, 4);
|
609 | 69b91039 | bellard | #ifdef DEBUG_NE2000
|
610 | 69b91039 | bellard | printf("NE2000: asic readl val=0x%04x\n", ret);
|
611 | 69b91039 | bellard | #endif
|
612 | 69b91039 | bellard | return ret;
|
613 | 69b91039 | bellard | } |
614 | 69b91039 | bellard | |
615 | 9453c5bc | Gerd Hoffmann | void ne2000_reset_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
616 | 80cabfad | bellard | { |
617 | 80cabfad | bellard | /* nothing to do (end of reset pulse) */
|
618 | 80cabfad | bellard | } |
619 | 80cabfad | bellard | |
620 | 9453c5bc | Gerd Hoffmann | uint32_t ne2000_reset_ioport_read(void *opaque, uint32_t addr)
|
621 | 80cabfad | bellard | { |
622 | b41a2cd1 | bellard | NE2000State *s = opaque; |
623 | 80cabfad | bellard | ne2000_reset(s); |
624 | 80cabfad | bellard | return 0; |
625 | 80cabfad | bellard | } |
626 | 80cabfad | bellard | |
627 | 7c131dd5 | Juan Quintela | static int ne2000_post_load(void* opaque, int version_id) |
628 | 30ca2aab | bellard | { |
629 | 7c131dd5 | Juan Quintela | NE2000State* s = opaque; |
630 | a60380a5 | Juan Quintela | |
631 | 7c131dd5 | Juan Quintela | if (version_id < 2) { |
632 | 7c131dd5 | Juan Quintela | s->rxcr = 0x0c;
|
633 | 7c131dd5 | Juan Quintela | } |
634 | 7c131dd5 | Juan Quintela | return 0; |
635 | a60380a5 | Juan Quintela | } |
636 | a60380a5 | Juan Quintela | |
637 | 7c131dd5 | Juan Quintela | const VMStateDescription vmstate_ne2000 = {
|
638 | 7c131dd5 | Juan Quintela | .name = "ne2000",
|
639 | 7c131dd5 | Juan Quintela | .version_id = 2,
|
640 | 7c131dd5 | Juan Quintela | .minimum_version_id = 0,
|
641 | 7c131dd5 | Juan Quintela | .minimum_version_id_old = 0,
|
642 | 7c131dd5 | Juan Quintela | .post_load = ne2000_post_load, |
643 | 7c131dd5 | Juan Quintela | .fields = (VMStateField []) { |
644 | 7c131dd5 | Juan Quintela | VMSTATE_UINT8_V(rxcr, NE2000State, 2),
|
645 | 7c131dd5 | Juan Quintela | VMSTATE_UINT8(cmd, NE2000State), |
646 | 7c131dd5 | Juan Quintela | VMSTATE_UINT32(start, NE2000State), |
647 | 7c131dd5 | Juan Quintela | VMSTATE_UINT32(stop, NE2000State), |
648 | 7c131dd5 | Juan Quintela | VMSTATE_UINT8(boundary, NE2000State), |
649 | 7c131dd5 | Juan Quintela | VMSTATE_UINT8(tsr, NE2000State), |
650 | 7c131dd5 | Juan Quintela | VMSTATE_UINT8(tpsr, NE2000State), |
651 | 7c131dd5 | Juan Quintela | VMSTATE_UINT16(tcnt, NE2000State), |
652 | 7c131dd5 | Juan Quintela | VMSTATE_UINT16(rcnt, NE2000State), |
653 | 7c131dd5 | Juan Quintela | VMSTATE_UINT32(rsar, NE2000State), |
654 | 7c131dd5 | Juan Quintela | VMSTATE_UINT8(rsr, NE2000State), |
655 | 7c131dd5 | Juan Quintela | VMSTATE_UINT8(isr, NE2000State), |
656 | 7c131dd5 | Juan Quintela | VMSTATE_UINT8(dcfg, NE2000State), |
657 | 7c131dd5 | Juan Quintela | VMSTATE_UINT8(imr, NE2000State), |
658 | 7c131dd5 | Juan Quintela | VMSTATE_BUFFER(phys, NE2000State), |
659 | 7c131dd5 | Juan Quintela | VMSTATE_UINT8(curpag, NE2000State), |
660 | 7c131dd5 | Juan Quintela | VMSTATE_BUFFER(mult, NE2000State), |
661 | 7c131dd5 | Juan Quintela | VMSTATE_UNUSED(4), /* was irq */ |
662 | 7c131dd5 | Juan Quintela | VMSTATE_BUFFER(mem, NE2000State), |
663 | 7c131dd5 | Juan Quintela | VMSTATE_END_OF_LIST() |
664 | 7c131dd5 | Juan Quintela | } |
665 | 7c131dd5 | Juan Quintela | }; |
666 | a60380a5 | Juan Quintela | |
667 | d05ac8fa | Blue Swirl | static const VMStateDescription vmstate_pci_ne2000 = { |
668 | 7c131dd5 | Juan Quintela | .name = "ne2000",
|
669 | 7c131dd5 | Juan Quintela | .version_id = 3,
|
670 | 7c131dd5 | Juan Quintela | .minimum_version_id = 3,
|
671 | 7c131dd5 | Juan Quintela | .minimum_version_id_old = 3,
|
672 | 7c131dd5 | Juan Quintela | .fields = (VMStateField []) { |
673 | 7c131dd5 | Juan Quintela | VMSTATE_PCI_DEVICE(dev, PCINE2000State), |
674 | 7c131dd5 | Juan Quintela | VMSTATE_STRUCT(ne2000, PCINE2000State, 0, vmstate_ne2000, NE2000State),
|
675 | 7c131dd5 | Juan Quintela | VMSTATE_END_OF_LIST() |
676 | 7c131dd5 | Juan Quintela | } |
677 | 7c131dd5 | Juan Quintela | }; |
678 | a60380a5 | Juan Quintela | |
679 | 69b91039 | bellard | /***********************************************************/
|
680 | 69b91039 | bellard | /* PCI NE2000 definitions */
|
681 | 69b91039 | bellard | |
682 | 5fafdf24 | ths | static void ne2000_map(PCIDevice *pci_dev, int region_num, |
683 | 6e355d90 | Isaku Yamahata | pcibus_t addr, pcibus_t size, int type)
|
684 | 69b91039 | bellard | { |
685 | 377a7f06 | Juan Quintela | PCINE2000State *d = DO_UPCAST(PCINE2000State, dev, pci_dev); |
686 | 69b91039 | bellard | NE2000State *s = &d->ne2000; |
687 | 69b91039 | bellard | |
688 | 69b91039 | bellard | register_ioport_write(addr, 16, 1, ne2000_ioport_write, s); |
689 | 69b91039 | bellard | register_ioport_read(addr, 16, 1, ne2000_ioport_read, s); |
690 | 69b91039 | bellard | |
691 | 69b91039 | bellard | register_ioport_write(addr + 0x10, 1, 1, ne2000_asic_ioport_write, s); |
692 | 69b91039 | bellard | register_ioport_read(addr + 0x10, 1, 1, ne2000_asic_ioport_read, s); |
693 | 69b91039 | bellard | register_ioport_write(addr + 0x10, 2, 2, ne2000_asic_ioport_write, s); |
694 | 69b91039 | bellard | register_ioport_read(addr + 0x10, 2, 2, ne2000_asic_ioport_read, s); |
695 | 69b91039 | bellard | register_ioport_write(addr + 0x10, 4, 4, ne2000_asic_ioport_writel, s); |
696 | 69b91039 | bellard | register_ioport_read(addr + 0x10, 4, 4, ne2000_asic_ioport_readl, s); |
697 | 69b91039 | bellard | |
698 | 69b91039 | bellard | register_ioport_write(addr + 0x1f, 1, 1, ne2000_reset_ioport_write, s); |
699 | 69b91039 | bellard | register_ioport_read(addr + 0x1f, 1, 1, ne2000_reset_ioport_read, s); |
700 | 69b91039 | bellard | } |
701 | 69b91039 | bellard | |
702 | 1c2045b5 | Mark McLoughlin | static void ne2000_cleanup(VLANClientState *nc) |
703 | b946a153 | aliguori | { |
704 | 1c2045b5 | Mark McLoughlin | NE2000State *s = DO_UPCAST(NICState, nc, nc)->opaque; |
705 | b946a153 | aliguori | |
706 | 1c2045b5 | Mark McLoughlin | s->nic = NULL;
|
707 | b946a153 | aliguori | } |
708 | b946a153 | aliguori | |
709 | 1c2045b5 | Mark McLoughlin | static NetClientInfo net_ne2000_info = {
|
710 | 1c2045b5 | Mark McLoughlin | .type = NET_CLIENT_TYPE_NIC, |
711 | 1c2045b5 | Mark McLoughlin | .size = sizeof(NICState),
|
712 | 1c2045b5 | Mark McLoughlin | .can_receive = ne2000_can_receive, |
713 | 1c2045b5 | Mark McLoughlin | .receive = ne2000_receive, |
714 | 1c2045b5 | Mark McLoughlin | .cleanup = ne2000_cleanup, |
715 | 1c2045b5 | Mark McLoughlin | }; |
716 | 1c2045b5 | Mark McLoughlin | |
717 | 81a322d4 | Gerd Hoffmann | static int pci_ne2000_init(PCIDevice *pci_dev) |
718 | 69b91039 | bellard | { |
719 | 377a7f06 | Juan Quintela | PCINE2000State *d = DO_UPCAST(PCINE2000State, dev, pci_dev); |
720 | 69b91039 | bellard | NE2000State *s; |
721 | 69b91039 | bellard | uint8_t *pci_conf; |
722 | 3b46e624 | ths | |
723 | 69b91039 | bellard | pci_conf = d->dev.config; |
724 | deb54399 | aliguori | pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_REALTEK); |
725 | a770dc7e | aliguori | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_REALTEK_8029); |
726 | 173a543b | blueswir1 | pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET); |
727 | e6c4cfd5 | Michael S. Tsirkin | /* TODO: RST# value should be 0. PCI spec 6.2.4 */
|
728 | e6c4cfd5 | Michael S. Tsirkin | pci_conf[PCI_INTERRUPT_PIN] = 1; // interrupt pin 0 |
729 | 3b46e624 | ths | |
730 | 28c2c264 | Avi Kivity | pci_register_bar(&d->dev, 0, 0x100, |
731 | 0392a017 | Isaku Yamahata | PCI_BASE_ADDRESS_SPACE_IO, ne2000_map); |
732 | 69b91039 | bellard | s = &d->ne2000; |
733 | d537cf6c | pbrook | s->irq = d->dev.irq[0];
|
734 | a783cc3e | Gerd Hoffmann | |
735 | a783cc3e | Gerd Hoffmann | qemu_macaddr_default_if_unset(&s->c.macaddr); |
736 | 69b91039 | bellard | ne2000_reset(s); |
737 | 1c2045b5 | Mark McLoughlin | |
738 | 1c2045b5 | Mark McLoughlin | s->nic = qemu_new_nic(&net_ne2000_info, &s->c, |
739 | 1c2045b5 | Mark McLoughlin | pci_dev->qdev.info->name, pci_dev->qdev.id, s); |
740 | 1c2045b5 | Mark McLoughlin | qemu_format_nic_info_str(&s->nic->nc, s->c.macaddr.a); |
741 | 3b46e624 | ths | |
742 | a783cc3e | Gerd Hoffmann | if (!pci_dev->qdev.hotplugged) {
|
743 | a783cc3e | Gerd Hoffmann | static int loaded = 0; |
744 | a783cc3e | Gerd Hoffmann | if (!loaded) {
|
745 | 5ee8ad71 | Alex Williamson | rom_add_option("pxe-ne2k_pci.rom", -1); |
746 | a783cc3e | Gerd Hoffmann | loaded = 1;
|
747 | a783cc3e | Gerd Hoffmann | } |
748 | a783cc3e | Gerd Hoffmann | } |
749 | a783cc3e | Gerd Hoffmann | |
750 | 1ca4d09a | Gleb Natapov | add_boot_device_path(s->c.bootindex, &pci_dev->qdev, "/ethernet-phy@0");
|
751 | 1ca4d09a | Gleb Natapov | |
752 | 81a322d4 | Gerd Hoffmann | return 0; |
753 | 9d07d757 | Paul Brook | } |
754 | 72da4208 | aliguori | |
755 | a783cc3e | Gerd Hoffmann | static int pci_ne2000_exit(PCIDevice *pci_dev) |
756 | a783cc3e | Gerd Hoffmann | { |
757 | a783cc3e | Gerd Hoffmann | PCINE2000State *d = DO_UPCAST(PCINE2000State, dev, pci_dev); |
758 | a783cc3e | Gerd Hoffmann | NE2000State *s = &d->ne2000; |
759 | a783cc3e | Gerd Hoffmann | |
760 | 1c2045b5 | Mark McLoughlin | qemu_del_vlan_client(&s->nic->nc); |
761 | a783cc3e | Gerd Hoffmann | return 0; |
762 | a783cc3e | Gerd Hoffmann | } |
763 | a783cc3e | Gerd Hoffmann | |
764 | 0aab0d3a | Gerd Hoffmann | static PCIDeviceInfo ne2000_info = {
|
765 | a783cc3e | Gerd Hoffmann | .qdev.name = "ne2k_pci",
|
766 | a783cc3e | Gerd Hoffmann | .qdev.size = sizeof(PCINE2000State),
|
767 | be73cfe2 | Juan Quintela | .qdev.vmsd = &vmstate_pci_ne2000, |
768 | a783cc3e | Gerd Hoffmann | .init = pci_ne2000_init, |
769 | a783cc3e | Gerd Hoffmann | .exit = pci_ne2000_exit, |
770 | a783cc3e | Gerd Hoffmann | .qdev.props = (Property[]) { |
771 | a783cc3e | Gerd Hoffmann | DEFINE_NIC_PROPERTIES(PCINE2000State, ne2000.c), |
772 | a783cc3e | Gerd Hoffmann | DEFINE_PROP_END_OF_LIST(), |
773 | a783cc3e | Gerd Hoffmann | } |
774 | 0aab0d3a | Gerd Hoffmann | }; |
775 | 0aab0d3a | Gerd Hoffmann | |
776 | 9d07d757 | Paul Brook | static void ne2000_register_devices(void) |
777 | 9d07d757 | Paul Brook | { |
778 | 0aab0d3a | Gerd Hoffmann | pci_qdev_register(&ne2000_info); |
779 | 69b91039 | bellard | } |
780 | 9d07d757 | Paul Brook | |
781 | 9d07d757 | Paul Brook | device_init(ne2000_register_devices) |