ich/ahci: fix uninitialized memory use
The commit 667bb59d2358daeef179583c944becba3f1f9680uses d->ahci.mem before it is initialized byahci_init(). Fix this by calling ahci_init() first thingso that it's safe to use all fields in the ahci state struct....
Merge remote branch 'origin/master' into pci
Conflicts: exec.c
pci: Add class 0x403 as 'audio controller'
Used by HD audio controllers like our intel-hda.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
MSI: Robust resource release
msi_init may fail, so we need to check on uninit if the cap wasactually installed. This also avoids that the users need to check.
eepro100: Support byte/word writes to pointer register
pointer is a 32 bit register, but may be written using 8 or 16 bit writes.Add support for byte/word writes.
Signed-off-by: Stefan Weil <weil@mail.berlios.de>Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
eepro100: Support byte/word read/write access to MDI control register
MDI control is a 32 bit register, but may be read or written using8 or 16 bit access. Data is latched when the MSB is written.
Add support for byte/word read/write access.
Signed-off-by: Stefan Weil <weil@mail.berlios.de>...
eepro100: Support byte read access to general control register
The general control register is a byte register.Add support for byte reads.
eepro100: Support 32 bit read/write access to flash register
eepro100: Fix endianness issues
Like other Intel devices, e100 (eepro100) uses little endian byte order.
This patch was tested with these combinations:
i386 host, i386 + mipsel guests (le-le)mipsel host, i386 guest (le-le)i386 host, mips + ppc guests (le-be)...
eepro100: Support byte/word writes to port address
port is a 32 bit register, but may be written using 8 or 16 bit writes.Add support for byte/word writes.
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