tcg-ppc64: Don't implement rem
Reviewed-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg: Split rem requirement from div requirement
There are several hosts with only a "div" insn. Remainder is computedmanually from the quotient and inputs. We can do this generically.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: bswap64 rotates output 32 bits
If our input and output is in the same register, bswap64 tries toundo a rotate of the input. This just ends up rotating the output.
Cc: qemu-stable@nongnu.orgSigned-off-by: Anton Blanchard <anton@samba.org>Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Fix add2_i64
add2_i64 was adding the lower double word to the upper double wordof each input. Fix this so we add the lower double words, then theupper double words with carry propagation.
Cc: qemu-stable@nongnu.orgSigned-off-by: Anton Blanchard <anton@samba.org>...
tcg-ppc64: rotr_i32 rotates wrong amount
rotr_i32 calculates the amount to left shift and puts it into atemporary, but then doesn't use it when doing the shift.
tcg-ppc64: Fix RLDCL opcode
The rldcl instruction doesn't have an sh field, so the minor opcodeis shifted 1 bit. We were using the XO30 macro which shifted theminor opcode 2 bits.
Remove XO30 and add MD30 and MDS30 macros which match thePower ISA categories....
tcg-ppc64: Handle deposit of zero
The TCG optimizer does great work when inserting constants, being ableto fold the open-coded deposit expansion to just an AND or an OR. Avoida bit the regression caused by having the deposit opcode by expandingdeposit of zero as an AND....
tcg-ppc64: Use getauxval for ISA detection
Glibc 2.16 includes an easy way to get feature bits previouslyburied in /proc or the program startup auxiliary vector. Use it.
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Implement add2/sub2_i64
tcg-ppc64: Implement mulu2/muls2_i64
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