root / hw / piix_pci.c @ 6c009fa4
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1 | 502a5395 | pbrook | /*
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2 | 502a5395 | pbrook | * QEMU i440FX/PIIX3 PCI Bridge Emulation
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3 | 502a5395 | pbrook | *
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4 | 502a5395 | pbrook | * Copyright (c) 2006 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 502a5395 | pbrook | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 502a5395 | pbrook | * of this software and associated documentation files (the "Software"), to deal
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8 | 502a5395 | pbrook | * in the Software without restriction, including without limitation the rights
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9 | 502a5395 | pbrook | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 502a5395 | pbrook | * copies of the Software, and to permit persons to whom the Software is
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11 | 502a5395 | pbrook | * furnished to do so, subject to the following conditions:
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12 | 502a5395 | pbrook | *
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13 | 502a5395 | pbrook | * The above copyright notice and this permission notice shall be included in
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14 | 502a5395 | pbrook | * all copies or substantial portions of the Software.
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15 | 502a5395 | pbrook | *
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16 | 502a5395 | pbrook | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 502a5395 | pbrook | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 502a5395 | pbrook | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 502a5395 | pbrook | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 502a5395 | pbrook | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 502a5395 | pbrook | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 502a5395 | pbrook | * THE SOFTWARE.
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23 | 502a5395 | pbrook | */
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24 | 502a5395 | pbrook | |
25 | 87ecb68b | pbrook | #include "hw.h" |
26 | 87ecb68b | pbrook | #include "pc.h" |
27 | 87ecb68b | pbrook | #include "pci.h" |
28 | f75247f1 | Gerd Hoffmann | #include "isa.h" |
29 | 8a14daa5 | Gerd Hoffmann | #include "sysbus.h" |
30 | 87ecb68b | pbrook | |
31 | 502a5395 | pbrook | typedef uint32_t pci_addr_t;
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32 | 502a5395 | pbrook | #include "pci_host.h" |
33 | 502a5395 | pbrook | |
34 | 502a5395 | pbrook | typedef PCIHostState I440FXState;
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35 | 502a5395 | pbrook | |
36 | 0a3bacf3 | Juan Quintela | struct PCII440FXState {
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37 | 0a3bacf3 | Juan Quintela | PCIDevice dev; |
38 | 6c009fa4 | Juan Quintela | target_phys_addr_t isa_page_descs[384 / 4]; |
39 | 6c009fa4 | Juan Quintela | uint8_t smm_enabled; |
40 | 0a3bacf3 | Juan Quintela | }; |
41 | 0a3bacf3 | Juan Quintela | |
42 | 502a5395 | pbrook | static void i440fx_addr_writel(void* opaque, uint32_t addr, uint32_t val) |
43 | 502a5395 | pbrook | { |
44 | 502a5395 | pbrook | I440FXState *s = opaque; |
45 | 502a5395 | pbrook | s->config_reg = val; |
46 | 502a5395 | pbrook | } |
47 | 502a5395 | pbrook | |
48 | 502a5395 | pbrook | static uint32_t i440fx_addr_readl(void* opaque, uint32_t addr) |
49 | 502a5395 | pbrook | { |
50 | 502a5395 | pbrook | I440FXState *s = opaque; |
51 | 502a5395 | pbrook | return s->config_reg;
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52 | 502a5395 | pbrook | } |
53 | 502a5395 | pbrook | |
54 | d537cf6c | pbrook | static void piix3_set_irq(qemu_irq *pic, int irq_num, int level); |
55 | d2b59317 | pbrook | |
56 | d2b59317 | pbrook | /* return the global irq number corresponding to a given device irq
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57 | d2b59317 | pbrook | pin. We could also use the bus number to have a more precise
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58 | d2b59317 | pbrook | mapping. */
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59 | d2b59317 | pbrook | static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num) |
60 | d2b59317 | pbrook | { |
61 | d2b59317 | pbrook | int slot_addend;
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62 | d2b59317 | pbrook | slot_addend = (pci_dev->devfn >> 3) - 1; |
63 | d2b59317 | pbrook | return (irq_num + slot_addend) & 3; |
64 | d2b59317 | pbrook | } |
65 | 502a5395 | pbrook | |
66 | 52fc1d83 | balrog | static int pci_irq_levels[4]; |
67 | ee0ea1d0 | bellard | |
68 | 0a3bacf3 | Juan Quintela | static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r) |
69 | 84631fd7 | bellard | { |
70 | 84631fd7 | bellard | uint32_t addr; |
71 | 84631fd7 | bellard | |
72 | 84631fd7 | bellard | // printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
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73 | 84631fd7 | bellard | switch(r) {
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74 | 84631fd7 | bellard | case 3: |
75 | 84631fd7 | bellard | /* RAM */
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76 | 5fafdf24 | ths | cpu_register_physical_memory(start, end - start, |
77 | 84631fd7 | bellard | start); |
78 | 84631fd7 | bellard | break;
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79 | 84631fd7 | bellard | case 1: |
80 | 84631fd7 | bellard | /* ROM (XXX: not quite correct) */
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81 | 5fafdf24 | ths | cpu_register_physical_memory(start, end - start, |
82 | 84631fd7 | bellard | start | IO_MEM_ROM); |
83 | 84631fd7 | bellard | break;
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84 | 84631fd7 | bellard | case 2: |
85 | 84631fd7 | bellard | case 0: |
86 | 84631fd7 | bellard | /* XXX: should distinguish read/write cases */
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87 | 84631fd7 | bellard | for(addr = start; addr < end; addr += 4096) { |
88 | 5fafdf24 | ths | cpu_register_physical_memory(addr, 4096,
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89 | 6c009fa4 | Juan Quintela | d->isa_page_descs[(addr - 0xa0000) >> 12]); |
90 | 84631fd7 | bellard | } |
91 | 84631fd7 | bellard | break;
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92 | 84631fd7 | bellard | } |
93 | 84631fd7 | bellard | } |
94 | ee0ea1d0 | bellard | |
95 | 0a3bacf3 | Juan Quintela | static void i440fx_update_memory_mappings(PCII440FXState *d) |
96 | ee0ea1d0 | bellard | { |
97 | ee0ea1d0 | bellard | int i, r;
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98 | 84631fd7 | bellard | uint32_t smram, addr; |
99 | 84631fd7 | bellard | |
100 | 0a3bacf3 | Juan Quintela | update_pam(d, 0xf0000, 0x100000, (d->dev.config[0x59] >> 4) & 3); |
101 | 84631fd7 | bellard | for(i = 0; i < 12; i++) { |
102 | 0a3bacf3 | Juan Quintela | r = (d->dev.config[(i >> 1) + 0x5a] >> ((i & 1) * 4)) & 3; |
103 | 84631fd7 | bellard | update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r); |
104 | ee0ea1d0 | bellard | } |
105 | 0a3bacf3 | Juan Quintela | smram = d->dev.config[0x72];
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106 | 6c009fa4 | Juan Quintela | if ((d->smm_enabled && (smram & 0x08)) || (smram & 0x40)) { |
107 | 84631fd7 | bellard | cpu_register_physical_memory(0xa0000, 0x20000, 0xa0000); |
108 | 84631fd7 | bellard | } else {
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109 | 84631fd7 | bellard | for(addr = 0xa0000; addr < 0xc0000; addr += 4096) { |
110 | 5fafdf24 | ths | cpu_register_physical_memory(addr, 4096,
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111 | 6c009fa4 | Juan Quintela | d->isa_page_descs[(addr - 0xa0000) >> 12]); |
112 | ee0ea1d0 | bellard | } |
113 | ee0ea1d0 | bellard | } |
114 | ee0ea1d0 | bellard | } |
115 | ee0ea1d0 | bellard | |
116 | 0a3bacf3 | Juan Quintela | void i440fx_set_smm(PCII440FXState *d, int val) |
117 | ee0ea1d0 | bellard | { |
118 | ee0ea1d0 | bellard | val = (val != 0);
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119 | 6c009fa4 | Juan Quintela | if (d->smm_enabled != val) {
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120 | 6c009fa4 | Juan Quintela | d->smm_enabled = val; |
121 | ee0ea1d0 | bellard | i440fx_update_memory_mappings(d); |
122 | ee0ea1d0 | bellard | } |
123 | ee0ea1d0 | bellard | } |
124 | ee0ea1d0 | bellard | |
125 | ee0ea1d0 | bellard | |
126 | ee0ea1d0 | bellard | /* XXX: suppress when better memory API. We make the assumption that
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127 | ee0ea1d0 | bellard | no device (in particular the VGA) changes the memory mappings in
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128 | ee0ea1d0 | bellard | the 0xa0000-0x100000 range */
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129 | 0a3bacf3 | Juan Quintela | void i440fx_init_memory_mappings(PCII440FXState *d)
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130 | ee0ea1d0 | bellard | { |
131 | ee0ea1d0 | bellard | int i;
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132 | ee0ea1d0 | bellard | for(i = 0; i < 96; i++) { |
133 | 6c009fa4 | Juan Quintela | d->isa_page_descs[i] = cpu_get_physical_page_desc(0xa0000 + i * 0x1000); |
134 | ee0ea1d0 | bellard | } |
135 | ee0ea1d0 | bellard | } |
136 | ee0ea1d0 | bellard | |
137 | 0a3bacf3 | Juan Quintela | static void i440fx_write_config(PCIDevice *dev, |
138 | ee0ea1d0 | bellard | uint32_t address, uint32_t val, int len)
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139 | ee0ea1d0 | bellard | { |
140 | 0a3bacf3 | Juan Quintela | PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev); |
141 | 0a3bacf3 | Juan Quintela | |
142 | ee0ea1d0 | bellard | /* XXX: implement SMRAM.D_LOCK */
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143 | 0a3bacf3 | Juan Quintela | pci_default_write_config(dev, address, val, len); |
144 | 84631fd7 | bellard | if ((address >= 0x59 && address <= 0x5f) || address == 0x72) |
145 | ee0ea1d0 | bellard | i440fx_update_memory_mappings(d); |
146 | ee0ea1d0 | bellard | } |
147 | ee0ea1d0 | bellard | |
148 | ee0ea1d0 | bellard | static void i440fx_save(QEMUFile* f, void *opaque) |
149 | ee0ea1d0 | bellard | { |
150 | 0a3bacf3 | Juan Quintela | PCII440FXState *d = opaque; |
151 | 52fc1d83 | balrog | int i;
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152 | 52fc1d83 | balrog | |
153 | 0a3bacf3 | Juan Quintela | pci_device_save(&d->dev, f); |
154 | 6c009fa4 | Juan Quintela | qemu_put_8s(f, &d->smm_enabled); |
155 | 52fc1d83 | balrog | |
156 | 52fc1d83 | balrog | for (i = 0; i < 4; i++) |
157 | 52fc1d83 | balrog | qemu_put_be32(f, pci_irq_levels[i]); |
158 | ee0ea1d0 | bellard | } |
159 | ee0ea1d0 | bellard | |
160 | ee0ea1d0 | bellard | static int i440fx_load(QEMUFile* f, void *opaque, int version_id) |
161 | ee0ea1d0 | bellard | { |
162 | 0a3bacf3 | Juan Quintela | PCII440FXState *d = opaque; |
163 | 52fc1d83 | balrog | int ret, i;
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164 | ee0ea1d0 | bellard | |
165 | 52fc1d83 | balrog | if (version_id > 2) |
166 | ee0ea1d0 | bellard | return -EINVAL;
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167 | 0a3bacf3 | Juan Quintela | ret = pci_device_load(&d->dev, f); |
168 | ee0ea1d0 | bellard | if (ret < 0) |
169 | ee0ea1d0 | bellard | return ret;
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170 | ee0ea1d0 | bellard | i440fx_update_memory_mappings(d); |
171 | 6c009fa4 | Juan Quintela | qemu_get_8s(f, &d->smm_enabled); |
172 | 52fc1d83 | balrog | |
173 | 52fc1d83 | balrog | if (version_id >= 2) |
174 | 52fc1d83 | balrog | for (i = 0; i < 4; i++) |
175 | 52fc1d83 | balrog | pci_irq_levels[i] = qemu_get_be32(f); |
176 | 52fc1d83 | balrog | |
177 | ee0ea1d0 | bellard | return 0; |
178 | ee0ea1d0 | bellard | } |
179 | ee0ea1d0 | bellard | |
180 | 81a322d4 | Gerd Hoffmann | static int i440fx_pcihost_initfn(SysBusDevice *dev) |
181 | 502a5395 | pbrook | { |
182 | 8a14daa5 | Gerd Hoffmann | I440FXState *s = FROM_SYSBUS(I440FXState, dev); |
183 | 502a5395 | pbrook | |
184 | 502a5395 | pbrook | register_ioport_write(0xcf8, 4, 4, i440fx_addr_writel, s); |
185 | 502a5395 | pbrook | register_ioport_read(0xcf8, 4, 4, i440fx_addr_readl, s); |
186 | 502a5395 | pbrook | |
187 | 502a5395 | pbrook | register_ioport_write(0xcfc, 4, 1, pci_host_data_writeb, s); |
188 | 502a5395 | pbrook | register_ioport_write(0xcfc, 4, 2, pci_host_data_writew, s); |
189 | 502a5395 | pbrook | register_ioport_write(0xcfc, 4, 4, pci_host_data_writel, s); |
190 | 502a5395 | pbrook | register_ioport_read(0xcfc, 4, 1, pci_host_data_readb, s); |
191 | 502a5395 | pbrook | register_ioport_read(0xcfc, 4, 2, pci_host_data_readw, s); |
192 | 502a5395 | pbrook | register_ioport_read(0xcfc, 4, 4, pci_host_data_readl, s); |
193 | 81a322d4 | Gerd Hoffmann | return 0; |
194 | 8a14daa5 | Gerd Hoffmann | } |
195 | 502a5395 | pbrook | |
196 | 0a3bacf3 | Juan Quintela | static int i440fx_initfn(PCIDevice *dev) |
197 | 8a14daa5 | Gerd Hoffmann | { |
198 | 0a3bacf3 | Juan Quintela | PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev); |
199 | ee0ea1d0 | bellard | |
200 | 0a3bacf3 | Juan Quintela | pci_config_set_vendor_id(d->dev.config, PCI_VENDOR_ID_INTEL); |
201 | 0a3bacf3 | Juan Quintela | pci_config_set_device_id(d->dev.config, PCI_DEVICE_ID_INTEL_82441); |
202 | 0a3bacf3 | Juan Quintela | d->dev.config[0x08] = 0x02; // revision |
203 | 0a3bacf3 | Juan Quintela | pci_config_set_class(d->dev.config, PCI_CLASS_BRIDGE_HOST); |
204 | 0a3bacf3 | Juan Quintela | d->dev.config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
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205 | 0a3bacf3 | Juan Quintela | |
206 | 0a3bacf3 | Juan Quintela | d->dev.config[0x72] = 0x02; /* SMRAM */ |
207 | ee0ea1d0 | bellard | |
208 | 52fc1d83 | balrog | register_savevm("I440FX", 0, 2, i440fx_save, i440fx_load, d); |
209 | 81a322d4 | Gerd Hoffmann | return 0; |
210 | 8a14daa5 | Gerd Hoffmann | } |
211 | 8a14daa5 | Gerd Hoffmann | |
212 | 0a3bacf3 | Juan Quintela | PCIBus *i440fx_init(PCII440FXState **pi440fx_state, qemu_irq *pic) |
213 | 8a14daa5 | Gerd Hoffmann | { |
214 | 8a14daa5 | Gerd Hoffmann | DeviceState *dev; |
215 | 8a14daa5 | Gerd Hoffmann | PCIBus *b; |
216 | 8a14daa5 | Gerd Hoffmann | PCIDevice *d; |
217 | 8a14daa5 | Gerd Hoffmann | I440FXState *s; |
218 | 8a14daa5 | Gerd Hoffmann | |
219 | 8a14daa5 | Gerd Hoffmann | dev = qdev_create(NULL, "i440FX-pcihost"); |
220 | 8a14daa5 | Gerd Hoffmann | s = FROM_SYSBUS(I440FXState, sysbus_from_qdev(dev)); |
221 | 8a14daa5 | Gerd Hoffmann | b = pci_register_bus(&s->busdev.qdev, "pci.0",
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222 | 8a14daa5 | Gerd Hoffmann | piix3_set_irq, pci_slot_get_pirq, pic, 0, 4); |
223 | 8a14daa5 | Gerd Hoffmann | s->bus = b; |
224 | 8a14daa5 | Gerd Hoffmann | qdev_init(dev); |
225 | 8a14daa5 | Gerd Hoffmann | |
226 | 8a14daa5 | Gerd Hoffmann | d = pci_create_simple(b, 0, "i440FX"); |
227 | 0a3bacf3 | Juan Quintela | *pi440fx_state = DO_UPCAST(PCII440FXState, dev, d); |
228 | 8a14daa5 | Gerd Hoffmann | |
229 | 502a5395 | pbrook | return b;
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230 | 502a5395 | pbrook | } |
231 | 502a5395 | pbrook | |
232 | 502a5395 | pbrook | /* PIIX3 PCI to ISA bridge */
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233 | 502a5395 | pbrook | |
234 | b1d8e52e | blueswir1 | static PCIDevice *piix3_dev;
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235 | 502a5395 | pbrook | |
236 | d537cf6c | pbrook | static void piix3_set_irq(qemu_irq *pic, int irq_num, int level) |
237 | 502a5395 | pbrook | { |
238 | d2b59317 | pbrook | int i, pic_irq, pic_level;
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239 | 502a5395 | pbrook | |
240 | d2b59317 | pbrook | pci_irq_levels[irq_num] = level; |
241 | 502a5395 | pbrook | |
242 | 502a5395 | pbrook | /* now we change the pic irq level according to the piix irq mappings */
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243 | 502a5395 | pbrook | /* XXX: optimize */
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244 | 502a5395 | pbrook | pic_irq = piix3_dev->config[0x60 + irq_num];
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245 | 502a5395 | pbrook | if (pic_irq < 16) { |
246 | d2b59317 | pbrook | /* The pic level is the logical OR of all the PCI irqs mapped
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247 | 502a5395 | pbrook | to it */
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248 | 502a5395 | pbrook | pic_level = 0;
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249 | d2b59317 | pbrook | for (i = 0; i < 4; i++) { |
250 | d2b59317 | pbrook | if (pic_irq == piix3_dev->config[0x60 + i]) |
251 | d2b59317 | pbrook | pic_level |= pci_irq_levels[i]; |
252 | d2b59317 | pbrook | } |
253 | d537cf6c | pbrook | qemu_set_irq(pic[pic_irq], pic_level); |
254 | 502a5395 | pbrook | } |
255 | 502a5395 | pbrook | } |
256 | 502a5395 | pbrook | |
257 | 15a1956a | Gleb Natapov | static void piix3_reset(void *opaque) |
258 | 502a5395 | pbrook | { |
259 | 15a1956a | Gleb Natapov | PCIDevice *d = opaque; |
260 | 502a5395 | pbrook | uint8_t *pci_conf = d->config; |
261 | 502a5395 | pbrook | |
262 | 502a5395 | pbrook | pci_conf[0x04] = 0x07; // master, memory and I/O |
263 | 502a5395 | pbrook | pci_conf[0x05] = 0x00; |
264 | 502a5395 | pbrook | pci_conf[0x06] = 0x00; |
265 | 502a5395 | pbrook | pci_conf[0x07] = 0x02; // PCI_status_devsel_medium |
266 | 502a5395 | pbrook | pci_conf[0x4c] = 0x4d; |
267 | 502a5395 | pbrook | pci_conf[0x4e] = 0x03; |
268 | 502a5395 | pbrook | pci_conf[0x4f] = 0x00; |
269 | 502a5395 | pbrook | pci_conf[0x60] = 0x80; |
270 | 477afee3 | aurel32 | pci_conf[0x61] = 0x80; |
271 | 477afee3 | aurel32 | pci_conf[0x62] = 0x80; |
272 | 477afee3 | aurel32 | pci_conf[0x63] = 0x80; |
273 | 502a5395 | pbrook | pci_conf[0x69] = 0x02; |
274 | 502a5395 | pbrook | pci_conf[0x70] = 0x80; |
275 | 502a5395 | pbrook | pci_conf[0x76] = 0x0c; |
276 | 502a5395 | pbrook | pci_conf[0x77] = 0x0c; |
277 | 502a5395 | pbrook | pci_conf[0x78] = 0x02; |
278 | 502a5395 | pbrook | pci_conf[0x79] = 0x00; |
279 | 502a5395 | pbrook | pci_conf[0x80] = 0x00; |
280 | 502a5395 | pbrook | pci_conf[0x82] = 0x00; |
281 | 502a5395 | pbrook | pci_conf[0xa0] = 0x08; |
282 | 502a5395 | pbrook | pci_conf[0xa2] = 0x00; |
283 | 502a5395 | pbrook | pci_conf[0xa3] = 0x00; |
284 | 502a5395 | pbrook | pci_conf[0xa4] = 0x00; |
285 | 502a5395 | pbrook | pci_conf[0xa5] = 0x00; |
286 | 502a5395 | pbrook | pci_conf[0xa6] = 0x00; |
287 | 502a5395 | pbrook | pci_conf[0xa7] = 0x00; |
288 | 502a5395 | pbrook | pci_conf[0xa8] = 0x0f; |
289 | 502a5395 | pbrook | pci_conf[0xaa] = 0x00; |
290 | 502a5395 | pbrook | pci_conf[0xab] = 0x00; |
291 | 502a5395 | pbrook | pci_conf[0xac] = 0x00; |
292 | 502a5395 | pbrook | pci_conf[0xae] = 0x00; |
293 | 15a1956a | Gleb Natapov | |
294 | 15a1956a | Gleb Natapov | memset(pci_irq_levels, 0, sizeof(pci_irq_levels)); |
295 | 502a5395 | pbrook | } |
296 | 502a5395 | pbrook | |
297 | 1941d19c | bellard | static void piix_save(QEMUFile* f, void *opaque) |
298 | 1941d19c | bellard | { |
299 | 1941d19c | bellard | PCIDevice *d = opaque; |
300 | 1941d19c | bellard | pci_device_save(d, f); |
301 | 1941d19c | bellard | } |
302 | 1941d19c | bellard | |
303 | 1941d19c | bellard | static int piix_load(QEMUFile* f, void *opaque, int version_id) |
304 | 1941d19c | bellard | { |
305 | 1941d19c | bellard | PCIDevice *d = opaque; |
306 | 1941d19c | bellard | if (version_id != 2) |
307 | 1941d19c | bellard | return -EINVAL;
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308 | 1941d19c | bellard | return pci_device_load(d, f);
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309 | 1941d19c | bellard | } |
310 | 1941d19c | bellard | |
311 | 81a322d4 | Gerd Hoffmann | static int piix3_initfn(PCIDevice *d) |
312 | 502a5395 | pbrook | { |
313 | 502a5395 | pbrook | uint8_t *pci_conf; |
314 | 502a5395 | pbrook | |
315 | f75247f1 | Gerd Hoffmann | isa_bus_new(&d->qdev); |
316 | 1941d19c | bellard | register_savevm("PIIX3", 0, 2, piix_save, piix_load, d); |
317 | 502a5395 | pbrook | |
318 | 502a5395 | pbrook | pci_conf = d->config; |
319 | deb54399 | aliguori | pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); |
320 | deb54399 | aliguori | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_0); // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
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321 | 173a543b | blueswir1 | pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA); |
322 | 6407f373 | Isaku Yamahata | pci_conf[PCI_HEADER_TYPE] = |
323 | 6407f373 | Isaku Yamahata | PCI_HEADER_TYPE_NORMAL | PCI_HEADER_TYPE_MULTI_FUNCTION; // header_type = PCI_multifunction, generic
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324 | 502a5395 | pbrook | |
325 | 8a14daa5 | Gerd Hoffmann | piix3_dev = d; |
326 | 502a5395 | pbrook | piix3_reset(d); |
327 | a08d4367 | Jan Kiszka | qemu_register_reset(piix3_reset, d); |
328 | 81a322d4 | Gerd Hoffmann | return 0; |
329 | 502a5395 | pbrook | } |
330 | 5c2b87e3 | ths | |
331 | 8a14daa5 | Gerd Hoffmann | int piix3_init(PCIBus *bus, int devfn) |
332 | 8a14daa5 | Gerd Hoffmann | { |
333 | 8a14daa5 | Gerd Hoffmann | PCIDevice *d; |
334 | 8a14daa5 | Gerd Hoffmann | |
335 | 8a14daa5 | Gerd Hoffmann | d = pci_create_simple(bus, devfn, "PIIX3");
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336 | 5c2b87e3 | ths | return d->devfn;
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337 | 5c2b87e3 | ths | } |
338 | 8a14daa5 | Gerd Hoffmann | |
339 | 8a14daa5 | Gerd Hoffmann | static PCIDeviceInfo i440fx_info[] = {
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340 | 8a14daa5 | Gerd Hoffmann | { |
341 | 8a14daa5 | Gerd Hoffmann | .qdev.name = "i440FX",
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342 | 8a14daa5 | Gerd Hoffmann | .qdev.desc = "Host bridge",
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343 | 0a3bacf3 | Juan Quintela | .qdev.size = sizeof(PCII440FXState),
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344 | 8a14daa5 | Gerd Hoffmann | .qdev.no_user = 1,
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345 | 8a14daa5 | Gerd Hoffmann | .init = i440fx_initfn, |
346 | 8a14daa5 | Gerd Hoffmann | .config_write = i440fx_write_config, |
347 | 8a14daa5 | Gerd Hoffmann | },{ |
348 | 8a14daa5 | Gerd Hoffmann | .qdev.name = "PIIX3",
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349 | 8a14daa5 | Gerd Hoffmann | .qdev.desc = "ISA bridge",
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350 | 8a14daa5 | Gerd Hoffmann | .qdev.size = sizeof(PCIDevice),
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351 | 8a14daa5 | Gerd Hoffmann | .qdev.no_user = 1,
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352 | 8a14daa5 | Gerd Hoffmann | .init = piix3_initfn, |
353 | 8a14daa5 | Gerd Hoffmann | },{ |
354 | 8a14daa5 | Gerd Hoffmann | /* end of list */
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355 | 8a14daa5 | Gerd Hoffmann | } |
356 | 8a14daa5 | Gerd Hoffmann | }; |
357 | 8a14daa5 | Gerd Hoffmann | |
358 | 8a14daa5 | Gerd Hoffmann | static SysBusDeviceInfo i440fx_pcihost_info = {
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359 | 8a14daa5 | Gerd Hoffmann | .init = i440fx_pcihost_initfn, |
360 | 8a14daa5 | Gerd Hoffmann | .qdev.name = "i440FX-pcihost",
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361 | 8a14daa5 | Gerd Hoffmann | .qdev.size = sizeof(I440FXState),
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362 | 8a14daa5 | Gerd Hoffmann | .qdev.no_user = 1,
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363 | 8a14daa5 | Gerd Hoffmann | }; |
364 | 8a14daa5 | Gerd Hoffmann | |
365 | 8a14daa5 | Gerd Hoffmann | static void i440fx_register(void) |
366 | 8a14daa5 | Gerd Hoffmann | { |
367 | 8a14daa5 | Gerd Hoffmann | sysbus_register_withprop(&i440fx_pcihost_info); |
368 | 8a14daa5 | Gerd Hoffmann | pci_qdev_register_many(i440fx_info); |
369 | 8a14daa5 | Gerd Hoffmann | } |
370 | 8a14daa5 | Gerd Hoffmann | device_init(i440fx_register); |