Use temporaries instead of fixed registers for some instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4784 c046a42c-6fe2-441c-8c8c-71466251a162
Make mixer emulation a configure option (Jan Kiszka)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4783 c046a42c-6fe2-441c-8c8c-71466251a162
Fix some compiler signed/unsigned char warnings
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4782 c046a42c-6fe2-441c-8c8c-71466251a162
Fix compiler warning (Jan Kiszka)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4781 c046a42c-6fe2-441c-8c8c-71466251a162
Pass T0/T1 explicitly to helper functions, and clean up a few dyngenleftovers.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4780 c046a42c-6fe2-441c-8c8c-71466251a162
According to gcc-4.3.0/gcc/config/rs6000/crtsavres.asm R13 is volatile
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4779 c046a42c-6fe2-441c-8c8c-71466251a162
Shuffle contents of tcg_target_reg_alloc_order
Move reserved/volatile registers down. Currently qemu_ld/stXX aremarked with TCG_OPF_CALL_CLOBBER and since memory accesses arefrequent and R3 through R12 are volatile moving this down results inless spills and tighter generated code....
Add missing [SU]32
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4777 c046a42c-6fe2-441c-8c8c-71466251a162
Eliminate cpu_T0
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4776 c046a42c-6fe2-441c-8c8c-71466251a162
Eliminate cpu_T1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4775 c046a42c-6fe2-441c-8c8c-71466251a162
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