root / target-ppc / helper.c @ 6ce0ca12
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1 | 79aceca5 | bellard | /*
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2 | 3fc6c082 | bellard | * PowerPC emulation helpers for qemu.
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3 | 5fafdf24 | ths | *
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4 | 76a66253 | j_mayer | * Copyright (c) 2003-2007 Jocelyn Mayer
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5 | 79aceca5 | bellard | *
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6 | 79aceca5 | bellard | * This library is free software; you can redistribute it and/or
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7 | 79aceca5 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 79aceca5 | bellard | * License as published by the Free Software Foundation; either
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9 | 79aceca5 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 79aceca5 | bellard | *
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11 | 79aceca5 | bellard | * This library is distributed in the hope that it will be useful,
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12 | 79aceca5 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 79aceca5 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 79aceca5 | bellard | * Lesser General Public License for more details.
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15 | 79aceca5 | bellard | *
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16 | 79aceca5 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 79aceca5 | bellard | * License along with this library; if not, write to the Free Software
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18 | fad6cb1a | aurel32 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
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19 | 79aceca5 | bellard | */
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20 | fdabc366 | bellard | #include <stdarg.h> |
21 | fdabc366 | bellard | #include <stdlib.h> |
22 | fdabc366 | bellard | #include <stdio.h> |
23 | fdabc366 | bellard | #include <string.h> |
24 | fdabc366 | bellard | #include <inttypes.h> |
25 | fdabc366 | bellard | #include <signal.h> |
26 | fdabc366 | bellard | #include <assert.h> |
27 | fdabc366 | bellard | |
28 | fdabc366 | bellard | #include "cpu.h" |
29 | fdabc366 | bellard | #include "exec-all.h" |
30 | 0411a972 | j_mayer | #include "helper_regs.h" |
31 | ca10f867 | aurel32 | #include "qemu-common.h" |
32 | d76d1650 | aurel32 | #include "kvm.h" |
33 | 9a64fbe4 | bellard | |
34 | 9a64fbe4 | bellard | //#define DEBUG_MMU
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35 | 9a64fbe4 | bellard | //#define DEBUG_BATS
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36 | 6b542af7 | j_mayer | //#define DEBUG_SLB
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37 | 76a66253 | j_mayer | //#define DEBUG_SOFTWARE_TLB
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38 | 0411a972 | j_mayer | //#define DUMP_PAGE_TABLES
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39 | 9a64fbe4 | bellard | //#define DEBUG_EXCEPTIONS
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40 | fdabc366 | bellard | //#define FLUSH_ALL_TLBS
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41 | 9a64fbe4 | bellard | |
42 | d12d51d5 | aliguori | #ifdef DEBUG_MMU
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43 | 93fcfe39 | aliguori | # define LOG_MMU(...) qemu_log(__VA_ARGS__)
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44 | 93fcfe39 | aliguori | # define LOG_MMU_STATE(env) log_cpu_state((env), 0) |
45 | d12d51d5 | aliguori | #else
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46 | d12d51d5 | aliguori | # define LOG_MMU(...) do { } while (0) |
47 | d12d51d5 | aliguori | # define LOG_MMU_STATE(...) do { } while (0) |
48 | d12d51d5 | aliguori | #endif
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49 | d12d51d5 | aliguori | |
50 | d12d51d5 | aliguori | |
51 | d12d51d5 | aliguori | #ifdef DEBUG_SOFTWARE_TLB
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52 | 93fcfe39 | aliguori | # define LOG_SWTLB(...) qemu_log(__VA_ARGS__)
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53 | d12d51d5 | aliguori | #else
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54 | d12d51d5 | aliguori | # define LOG_SWTLB(...) do { } while (0) |
55 | d12d51d5 | aliguori | #endif
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56 | d12d51d5 | aliguori | |
57 | d12d51d5 | aliguori | #ifdef DEBUG_BATS
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58 | 93fcfe39 | aliguori | # define LOG_BATS(...) qemu_log(__VA_ARGS__)
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59 | d12d51d5 | aliguori | #else
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60 | d12d51d5 | aliguori | # define LOG_BATS(...) do { } while (0) |
61 | d12d51d5 | aliguori | #endif
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62 | d12d51d5 | aliguori | |
63 | d12d51d5 | aliguori | #ifdef DEBUG_SLB
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64 | 93fcfe39 | aliguori | # define LOG_SLB(...) qemu_log(__VA_ARGS__)
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65 | d12d51d5 | aliguori | #else
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66 | d12d51d5 | aliguori | # define LOG_SLB(...) do { } while (0) |
67 | d12d51d5 | aliguori | #endif
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68 | d12d51d5 | aliguori | |
69 | d12d51d5 | aliguori | #ifdef DEBUG_EXCEPTIONS
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70 | 93fcfe39 | aliguori | # define LOG_EXCP(...) qemu_log(__VA_ARGS__)
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71 | d12d51d5 | aliguori | #else
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72 | d12d51d5 | aliguori | # define LOG_EXCP(...) do { } while (0) |
73 | d12d51d5 | aliguori | #endif
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74 | d12d51d5 | aliguori | |
75 | d12d51d5 | aliguori | |
76 | 9a64fbe4 | bellard | /*****************************************************************************/
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77 | 3fc6c082 | bellard | /* PowerPC MMU emulation */
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78 | a541f297 | bellard | |
79 | d9bce9d9 | j_mayer | #if defined(CONFIG_USER_ONLY)
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80 | e96efcfc | j_mayer | int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
81 | 6ebbf390 | j_mayer | int mmu_idx, int is_softmmu) |
82 | 24741ef3 | bellard | { |
83 | 24741ef3 | bellard | int exception, error_code;
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84 | d9bce9d9 | j_mayer | |
85 | 24741ef3 | bellard | if (rw == 2) { |
86 | e1833e1f | j_mayer | exception = POWERPC_EXCP_ISI; |
87 | 8f793433 | j_mayer | error_code = 0x40000000;
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88 | 24741ef3 | bellard | } else {
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89 | e1833e1f | j_mayer | exception = POWERPC_EXCP_DSI; |
90 | 8f793433 | j_mayer | error_code = 0x40000000;
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91 | 24741ef3 | bellard | if (rw)
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92 | 24741ef3 | bellard | error_code |= 0x02000000;
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93 | 24741ef3 | bellard | env->spr[SPR_DAR] = address; |
94 | 24741ef3 | bellard | env->spr[SPR_DSISR] = error_code; |
95 | 24741ef3 | bellard | } |
96 | 24741ef3 | bellard | env->exception_index = exception; |
97 | 24741ef3 | bellard | env->error_code = error_code; |
98 | 76a66253 | j_mayer | |
99 | 24741ef3 | bellard | return 1; |
100 | 24741ef3 | bellard | } |
101 | 76a66253 | j_mayer | |
102 | 9b3c35e0 | j_mayer | target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr) |
103 | 24741ef3 | bellard | { |
104 | 24741ef3 | bellard | return addr;
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105 | 24741ef3 | bellard | } |
106 | 36081602 | j_mayer | |
107 | 24741ef3 | bellard | #else
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108 | 76a66253 | j_mayer | /* Common routines used by software and hardware TLBs emulation */
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109 | b068d6a7 | j_mayer | static always_inline int pte_is_valid (target_ulong pte0) |
110 | 76a66253 | j_mayer | { |
111 | 76a66253 | j_mayer | return pte0 & 0x80000000 ? 1 : 0; |
112 | 76a66253 | j_mayer | } |
113 | 76a66253 | j_mayer | |
114 | b068d6a7 | j_mayer | static always_inline void pte_invalidate (target_ulong *pte0) |
115 | 76a66253 | j_mayer | { |
116 | 76a66253 | j_mayer | *pte0 &= ~0x80000000;
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117 | 76a66253 | j_mayer | } |
118 | 76a66253 | j_mayer | |
119 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
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120 | b068d6a7 | j_mayer | static always_inline int pte64_is_valid (target_ulong pte0) |
121 | caa4039c | j_mayer | { |
122 | caa4039c | j_mayer | return pte0 & 0x0000000000000001ULL ? 1 : 0; |
123 | caa4039c | j_mayer | } |
124 | caa4039c | j_mayer | |
125 | b068d6a7 | j_mayer | static always_inline void pte64_invalidate (target_ulong *pte0) |
126 | caa4039c | j_mayer | { |
127 | caa4039c | j_mayer | *pte0 &= ~0x0000000000000001ULL;
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128 | caa4039c | j_mayer | } |
129 | caa4039c | j_mayer | #endif
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130 | caa4039c | j_mayer | |
131 | 76a66253 | j_mayer | #define PTE_PTEM_MASK 0x7FFFFFBF |
132 | 76a66253 | j_mayer | #define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B) |
133 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
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134 | caa4039c | j_mayer | #define PTE64_PTEM_MASK 0xFFFFFFFFFFFFFF80ULL |
135 | caa4039c | j_mayer | #define PTE64_CHECK_MASK (TARGET_PAGE_MASK | 0x7F) |
136 | caa4039c | j_mayer | #endif
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137 | 76a66253 | j_mayer | |
138 | b227a8e9 | j_mayer | static always_inline int pp_check (int key, int pp, int nx) |
139 | b227a8e9 | j_mayer | { |
140 | b227a8e9 | j_mayer | int access;
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141 | b227a8e9 | j_mayer | |
142 | b227a8e9 | j_mayer | /* Compute access rights */
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143 | b227a8e9 | j_mayer | /* When pp is 3/7, the result is undefined. Set it to noaccess */
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144 | b227a8e9 | j_mayer | access = 0;
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145 | b227a8e9 | j_mayer | if (key == 0) { |
146 | b227a8e9 | j_mayer | switch (pp) {
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147 | b227a8e9 | j_mayer | case 0x0: |
148 | b227a8e9 | j_mayer | case 0x1: |
149 | b227a8e9 | j_mayer | case 0x2: |
150 | b227a8e9 | j_mayer | access |= PAGE_WRITE; |
151 | b227a8e9 | j_mayer | /* No break here */
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152 | b227a8e9 | j_mayer | case 0x3: |
153 | b227a8e9 | j_mayer | case 0x6: |
154 | b227a8e9 | j_mayer | access |= PAGE_READ; |
155 | b227a8e9 | j_mayer | break;
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156 | b227a8e9 | j_mayer | } |
157 | b227a8e9 | j_mayer | } else {
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158 | b227a8e9 | j_mayer | switch (pp) {
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159 | b227a8e9 | j_mayer | case 0x0: |
160 | b227a8e9 | j_mayer | case 0x6: |
161 | b227a8e9 | j_mayer | access = 0;
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162 | b227a8e9 | j_mayer | break;
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163 | b227a8e9 | j_mayer | case 0x1: |
164 | b227a8e9 | j_mayer | case 0x3: |
165 | b227a8e9 | j_mayer | access = PAGE_READ; |
166 | b227a8e9 | j_mayer | break;
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167 | b227a8e9 | j_mayer | case 0x2: |
168 | b227a8e9 | j_mayer | access = PAGE_READ | PAGE_WRITE; |
169 | b227a8e9 | j_mayer | break;
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170 | b227a8e9 | j_mayer | } |
171 | b227a8e9 | j_mayer | } |
172 | b227a8e9 | j_mayer | if (nx == 0) |
173 | b227a8e9 | j_mayer | access |= PAGE_EXEC; |
174 | b227a8e9 | j_mayer | |
175 | b227a8e9 | j_mayer | return access;
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176 | b227a8e9 | j_mayer | } |
177 | b227a8e9 | j_mayer | |
178 | b227a8e9 | j_mayer | static always_inline int check_prot (int prot, int rw, int access_type) |
179 | b227a8e9 | j_mayer | { |
180 | b227a8e9 | j_mayer | int ret;
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181 | b227a8e9 | j_mayer | |
182 | b227a8e9 | j_mayer | if (access_type == ACCESS_CODE) {
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183 | b227a8e9 | j_mayer | if (prot & PAGE_EXEC)
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184 | b227a8e9 | j_mayer | ret = 0;
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185 | b227a8e9 | j_mayer | else
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186 | b227a8e9 | j_mayer | ret = -2;
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187 | b227a8e9 | j_mayer | } else if (rw) { |
188 | b227a8e9 | j_mayer | if (prot & PAGE_WRITE)
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189 | b227a8e9 | j_mayer | ret = 0;
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190 | b227a8e9 | j_mayer | else
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191 | b227a8e9 | j_mayer | ret = -2;
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192 | b227a8e9 | j_mayer | } else {
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193 | b227a8e9 | j_mayer | if (prot & PAGE_READ)
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194 | b227a8e9 | j_mayer | ret = 0;
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195 | b227a8e9 | j_mayer | else
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196 | b227a8e9 | j_mayer | ret = -2;
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197 | b227a8e9 | j_mayer | } |
198 | b227a8e9 | j_mayer | |
199 | b227a8e9 | j_mayer | return ret;
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200 | b227a8e9 | j_mayer | } |
201 | b227a8e9 | j_mayer | |
202 | b068d6a7 | j_mayer | static always_inline int _pte_check (mmu_ctx_t *ctx, int is_64b, |
203 | b068d6a7 | j_mayer | target_ulong pte0, target_ulong pte1, |
204 | b227a8e9 | j_mayer | int h, int rw, int type) |
205 | 76a66253 | j_mayer | { |
206 | caa4039c | j_mayer | target_ulong ptem, mmask; |
207 | b227a8e9 | j_mayer | int access, ret, pteh, ptev, pp;
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208 | 76a66253 | j_mayer | |
209 | 76a66253 | j_mayer | access = 0;
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210 | 76a66253 | j_mayer | ret = -1;
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211 | 76a66253 | j_mayer | /* Check validity and table match */
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212 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
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213 | caa4039c | j_mayer | if (is_64b) {
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214 | caa4039c | j_mayer | ptev = pte64_is_valid(pte0); |
215 | caa4039c | j_mayer | pteh = (pte0 >> 1) & 1; |
216 | caa4039c | j_mayer | } else
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217 | caa4039c | j_mayer | #endif
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218 | caa4039c | j_mayer | { |
219 | caa4039c | j_mayer | ptev = pte_is_valid(pte0); |
220 | caa4039c | j_mayer | pteh = (pte0 >> 6) & 1; |
221 | caa4039c | j_mayer | } |
222 | caa4039c | j_mayer | if (ptev && h == pteh) {
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223 | 76a66253 | j_mayer | /* Check vsid & api */
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224 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
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225 | caa4039c | j_mayer | if (is_64b) {
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226 | caa4039c | j_mayer | ptem = pte0 & PTE64_PTEM_MASK; |
227 | caa4039c | j_mayer | mmask = PTE64_CHECK_MASK; |
228 | b227a8e9 | j_mayer | pp = (pte1 & 0x00000003) | ((pte1 >> 61) & 0x00000004); |
229 | b227a8e9 | j_mayer | ctx->nx |= (pte1 >> 2) & 1; /* No execute bit */ |
230 | b227a8e9 | j_mayer | ctx->nx |= (pte1 >> 3) & 1; /* Guarded bit */ |
231 | caa4039c | j_mayer | } else
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232 | caa4039c | j_mayer | #endif
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233 | caa4039c | j_mayer | { |
234 | caa4039c | j_mayer | ptem = pte0 & PTE_PTEM_MASK; |
235 | caa4039c | j_mayer | mmask = PTE_CHECK_MASK; |
236 | b227a8e9 | j_mayer | pp = pte1 & 0x00000003;
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237 | caa4039c | j_mayer | } |
238 | caa4039c | j_mayer | if (ptem == ctx->ptem) {
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239 | 6f2d8978 | j_mayer | if (ctx->raddr != (target_phys_addr_t)-1ULL) { |
240 | 76a66253 | j_mayer | /* all matches should have equal RPN, WIMG & PP */
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241 | caa4039c | j_mayer | if ((ctx->raddr & mmask) != (pte1 & mmask)) {
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242 | 93fcfe39 | aliguori | qemu_log("Bad RPN/WIMG/PP\n");
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243 | 76a66253 | j_mayer | return -3; |
244 | 76a66253 | j_mayer | } |
245 | 76a66253 | j_mayer | } |
246 | 76a66253 | j_mayer | /* Compute access rights */
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247 | b227a8e9 | j_mayer | access = pp_check(ctx->key, pp, ctx->nx); |
248 | 76a66253 | j_mayer | /* Keep the matching PTE informations */
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249 | 76a66253 | j_mayer | ctx->raddr = pte1; |
250 | 76a66253 | j_mayer | ctx->prot = access; |
251 | b227a8e9 | j_mayer | ret = check_prot(ctx->prot, rw, type); |
252 | b227a8e9 | j_mayer | if (ret == 0) { |
253 | 76a66253 | j_mayer | /* Access granted */
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254 | d12d51d5 | aliguori | LOG_MMU("PTE access granted !\n");
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255 | 76a66253 | j_mayer | } else {
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256 | 76a66253 | j_mayer | /* Access right violation */
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257 | d12d51d5 | aliguori | LOG_MMU("PTE access rejected\n");
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258 | 76a66253 | j_mayer | } |
259 | 76a66253 | j_mayer | } |
260 | 76a66253 | j_mayer | } |
261 | 76a66253 | j_mayer | |
262 | 76a66253 | j_mayer | return ret;
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263 | 76a66253 | j_mayer | } |
264 | 76a66253 | j_mayer | |
265 | a11b8151 | j_mayer | static always_inline int pte32_check (mmu_ctx_t *ctx, |
266 | a11b8151 | j_mayer | target_ulong pte0, target_ulong pte1, |
267 | a11b8151 | j_mayer | int h, int rw, int type) |
268 | caa4039c | j_mayer | { |
269 | b227a8e9 | j_mayer | return _pte_check(ctx, 0, pte0, pte1, h, rw, type); |
270 | caa4039c | j_mayer | } |
271 | caa4039c | j_mayer | |
272 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
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273 | a11b8151 | j_mayer | static always_inline int pte64_check (mmu_ctx_t *ctx, |
274 | a11b8151 | j_mayer | target_ulong pte0, target_ulong pte1, |
275 | a11b8151 | j_mayer | int h, int rw, int type) |
276 | caa4039c | j_mayer | { |
277 | b227a8e9 | j_mayer | return _pte_check(ctx, 1, pte0, pte1, h, rw, type); |
278 | caa4039c | j_mayer | } |
279 | caa4039c | j_mayer | #endif
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280 | caa4039c | j_mayer | |
281 | a11b8151 | j_mayer | static always_inline int pte_update_flags (mmu_ctx_t *ctx, target_ulong *pte1p, |
282 | a11b8151 | j_mayer | int ret, int rw) |
283 | 76a66253 | j_mayer | { |
284 | 76a66253 | j_mayer | int store = 0; |
285 | 76a66253 | j_mayer | |
286 | 76a66253 | j_mayer | /* Update page flags */
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287 | 76a66253 | j_mayer | if (!(*pte1p & 0x00000100)) { |
288 | 76a66253 | j_mayer | /* Update accessed flag */
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289 | 76a66253 | j_mayer | *pte1p |= 0x00000100;
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290 | 76a66253 | j_mayer | store = 1;
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291 | 76a66253 | j_mayer | } |
292 | 76a66253 | j_mayer | if (!(*pte1p & 0x00000080)) { |
293 | 76a66253 | j_mayer | if (rw == 1 && ret == 0) { |
294 | 76a66253 | j_mayer | /* Update changed flag */
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295 | 76a66253 | j_mayer | *pte1p |= 0x00000080;
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296 | 76a66253 | j_mayer | store = 1;
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297 | 76a66253 | j_mayer | } else {
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298 | 76a66253 | j_mayer | /* Force page fault for first write access */
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299 | 76a66253 | j_mayer | ctx->prot &= ~PAGE_WRITE; |
300 | 76a66253 | j_mayer | } |
301 | 76a66253 | j_mayer | } |
302 | 76a66253 | j_mayer | |
303 | 76a66253 | j_mayer | return store;
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304 | 76a66253 | j_mayer | } |
305 | 76a66253 | j_mayer | |
306 | 76a66253 | j_mayer | /* Software driven TLB helpers */
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307 | a11b8151 | j_mayer | static always_inline int ppc6xx_tlb_getnum (CPUState *env, target_ulong eaddr, |
308 | a11b8151 | j_mayer | int way, int is_code) |
309 | 76a66253 | j_mayer | { |
310 | 76a66253 | j_mayer | int nr;
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311 | 76a66253 | j_mayer | |
312 | 76a66253 | j_mayer | /* Select TLB num in a way from address */
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313 | 76a66253 | j_mayer | nr = (eaddr >> TARGET_PAGE_BITS) & (env->tlb_per_way - 1);
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314 | 76a66253 | j_mayer | /* Select TLB way */
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315 | 76a66253 | j_mayer | nr += env->tlb_per_way * way; |
316 | 76a66253 | j_mayer | /* 6xx have separate TLBs for instructions and data */
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317 | 76a66253 | j_mayer | if (is_code && env->id_tlbs == 1) |
318 | 76a66253 | j_mayer | nr += env->nb_tlb; |
319 | 76a66253 | j_mayer | |
320 | 76a66253 | j_mayer | return nr;
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321 | 76a66253 | j_mayer | } |
322 | 76a66253 | j_mayer | |
323 | a11b8151 | j_mayer | static always_inline void ppc6xx_tlb_invalidate_all (CPUState *env) |
324 | 76a66253 | j_mayer | { |
325 | 1d0a48fb | j_mayer | ppc6xx_tlb_t *tlb; |
326 | 76a66253 | j_mayer | int nr, max;
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327 | 76a66253 | j_mayer | |
328 | d12d51d5 | aliguori | //LOG_SWTLB("Invalidate all TLBs\n");
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329 | 76a66253 | j_mayer | /* Invalidate all defined software TLB */
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330 | 76a66253 | j_mayer | max = env->nb_tlb; |
331 | 76a66253 | j_mayer | if (env->id_tlbs == 1) |
332 | 76a66253 | j_mayer | max *= 2;
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333 | 76a66253 | j_mayer | for (nr = 0; nr < max; nr++) { |
334 | 1d0a48fb | j_mayer | tlb = &env->tlb[nr].tlb6; |
335 | 76a66253 | j_mayer | pte_invalidate(&tlb->pte0); |
336 | 76a66253 | j_mayer | } |
337 | 76a66253 | j_mayer | tlb_flush(env, 1);
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338 | 76a66253 | j_mayer | } |
339 | 76a66253 | j_mayer | |
340 | b068d6a7 | j_mayer | static always_inline void __ppc6xx_tlb_invalidate_virt (CPUState *env, |
341 | b068d6a7 | j_mayer | target_ulong eaddr, |
342 | b068d6a7 | j_mayer | int is_code,
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343 | b068d6a7 | j_mayer | int match_epn)
|
344 | 76a66253 | j_mayer | { |
345 | 4a057712 | j_mayer | #if !defined(FLUSH_ALL_TLBS)
|
346 | 1d0a48fb | j_mayer | ppc6xx_tlb_t *tlb; |
347 | 76a66253 | j_mayer | int way, nr;
|
348 | 76a66253 | j_mayer | |
349 | 76a66253 | j_mayer | /* Invalidate ITLB + DTLB, all ways */
|
350 | 76a66253 | j_mayer | for (way = 0; way < env->nb_ways; way++) { |
351 | 76a66253 | j_mayer | nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code); |
352 | 1d0a48fb | j_mayer | tlb = &env->tlb[nr].tlb6; |
353 | 76a66253 | j_mayer | if (pte_is_valid(tlb->pte0) && (match_epn == 0 || eaddr == tlb->EPN)) { |
354 | d12d51d5 | aliguori | LOG_SWTLB("TLB invalidate %d/%d " ADDRX "\n", |
355 | 76a66253 | j_mayer | nr, env->nb_tlb, eaddr); |
356 | 76a66253 | j_mayer | pte_invalidate(&tlb->pte0); |
357 | 76a66253 | j_mayer | tlb_flush_page(env, tlb->EPN); |
358 | 76a66253 | j_mayer | } |
359 | 76a66253 | j_mayer | } |
360 | 76a66253 | j_mayer | #else
|
361 | 76a66253 | j_mayer | /* XXX: PowerPC specification say this is valid as well */
|
362 | 76a66253 | j_mayer | ppc6xx_tlb_invalidate_all(env); |
363 | 76a66253 | j_mayer | #endif
|
364 | 76a66253 | j_mayer | } |
365 | 76a66253 | j_mayer | |
366 | a11b8151 | j_mayer | static always_inline void ppc6xx_tlb_invalidate_virt (CPUState *env, |
367 | a11b8151 | j_mayer | target_ulong eaddr, |
368 | a11b8151 | j_mayer | int is_code)
|
369 | 76a66253 | j_mayer | { |
370 | 76a66253 | j_mayer | __ppc6xx_tlb_invalidate_virt(env, eaddr, is_code, 0);
|
371 | 76a66253 | j_mayer | } |
372 | 76a66253 | j_mayer | |
373 | 76a66253 | j_mayer | void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code, |
374 | 76a66253 | j_mayer | target_ulong pte0, target_ulong pte1) |
375 | 76a66253 | j_mayer | { |
376 | 1d0a48fb | j_mayer | ppc6xx_tlb_t *tlb; |
377 | 76a66253 | j_mayer | int nr;
|
378 | 76a66253 | j_mayer | |
379 | 76a66253 | j_mayer | nr = ppc6xx_tlb_getnum(env, EPN, way, is_code); |
380 | 1d0a48fb | j_mayer | tlb = &env->tlb[nr].tlb6; |
381 | d12d51d5 | aliguori | LOG_SWTLB("Set TLB %d/%d EPN " ADDRX " PTE0 " ADDRX |
382 | 1b9eb036 | j_mayer | " PTE1 " ADDRX "\n", nr, env->nb_tlb, EPN, pte0, pte1); |
383 | 76a66253 | j_mayer | /* Invalidate any pending reference in Qemu for this virtual address */
|
384 | 76a66253 | j_mayer | __ppc6xx_tlb_invalidate_virt(env, EPN, is_code, 1);
|
385 | 76a66253 | j_mayer | tlb->pte0 = pte0; |
386 | 76a66253 | j_mayer | tlb->pte1 = pte1; |
387 | 76a66253 | j_mayer | tlb->EPN = EPN; |
388 | 76a66253 | j_mayer | /* Store last way for LRU mechanism */
|
389 | 76a66253 | j_mayer | env->last_way = way; |
390 | 76a66253 | j_mayer | } |
391 | 76a66253 | j_mayer | |
392 | a11b8151 | j_mayer | static always_inline int ppc6xx_tlb_check (CPUState *env, mmu_ctx_t *ctx, |
393 | a11b8151 | j_mayer | target_ulong eaddr, int rw,
|
394 | a11b8151 | j_mayer | int access_type)
|
395 | 76a66253 | j_mayer | { |
396 | 1d0a48fb | j_mayer | ppc6xx_tlb_t *tlb; |
397 | 76a66253 | j_mayer | int nr, best, way;
|
398 | 76a66253 | j_mayer | int ret;
|
399 | d9bce9d9 | j_mayer | |
400 | 76a66253 | j_mayer | best = -1;
|
401 | 76a66253 | j_mayer | ret = -1; /* No TLB found */ |
402 | 76a66253 | j_mayer | for (way = 0; way < env->nb_ways; way++) { |
403 | 76a66253 | j_mayer | nr = ppc6xx_tlb_getnum(env, eaddr, way, |
404 | 76a66253 | j_mayer | access_type == ACCESS_CODE ? 1 : 0); |
405 | 1d0a48fb | j_mayer | tlb = &env->tlb[nr].tlb6; |
406 | 76a66253 | j_mayer | /* This test "emulates" the PTE index match for hardware TLBs */
|
407 | 76a66253 | j_mayer | if ((eaddr & TARGET_PAGE_MASK) != tlb->EPN) {
|
408 | d12d51d5 | aliguori | LOG_SWTLB("TLB %d/%d %s [" ADDRX " " ADDRX |
409 | 1b9eb036 | j_mayer | "] <> " ADDRX "\n", |
410 | 76a66253 | j_mayer | nr, env->nb_tlb, |
411 | 76a66253 | j_mayer | pte_is_valid(tlb->pte0) ? "valid" : "inval", |
412 | 76a66253 | j_mayer | tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr); |
413 | 76a66253 | j_mayer | continue;
|
414 | 76a66253 | j_mayer | } |
415 | d12d51d5 | aliguori | LOG_SWTLB("TLB %d/%d %s " ADDRX " <> " ADDRX " " ADDRX |
416 | 1b9eb036 | j_mayer | " %c %c\n",
|
417 | 76a66253 | j_mayer | nr, env->nb_tlb, |
418 | 76a66253 | j_mayer | pte_is_valid(tlb->pte0) ? "valid" : "inval", |
419 | 76a66253 | j_mayer | tlb->EPN, eaddr, tlb->pte1, |
420 | 76a66253 | j_mayer | rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D'); |
421 | b227a8e9 | j_mayer | switch (pte32_check(ctx, tlb->pte0, tlb->pte1, 0, rw, access_type)) { |
422 | 76a66253 | j_mayer | case -3: |
423 | 76a66253 | j_mayer | /* TLB inconsistency */
|
424 | 76a66253 | j_mayer | return -1; |
425 | 76a66253 | j_mayer | case -2: |
426 | 76a66253 | j_mayer | /* Access violation */
|
427 | 76a66253 | j_mayer | ret = -2;
|
428 | 76a66253 | j_mayer | best = nr; |
429 | 76a66253 | j_mayer | break;
|
430 | 76a66253 | j_mayer | case -1: |
431 | 76a66253 | j_mayer | default:
|
432 | 76a66253 | j_mayer | /* No match */
|
433 | 76a66253 | j_mayer | break;
|
434 | 76a66253 | j_mayer | case 0: |
435 | 76a66253 | j_mayer | /* access granted */
|
436 | 76a66253 | j_mayer | /* XXX: we should go on looping to check all TLBs consistency
|
437 | 76a66253 | j_mayer | * but we can speed-up the whole thing as the
|
438 | 76a66253 | j_mayer | * result would be undefined if TLBs are not consistent.
|
439 | 76a66253 | j_mayer | */
|
440 | 76a66253 | j_mayer | ret = 0;
|
441 | 76a66253 | j_mayer | best = nr; |
442 | 76a66253 | j_mayer | goto done;
|
443 | 76a66253 | j_mayer | } |
444 | 76a66253 | j_mayer | } |
445 | 76a66253 | j_mayer | if (best != -1) { |
446 | 76a66253 | j_mayer | done:
|
447 | d12d51d5 | aliguori | LOG_SWTLB("found TLB at addr " PADDRX " prot=%01x ret=%d\n", |
448 | 76a66253 | j_mayer | ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret); |
449 | 76a66253 | j_mayer | /* Update page flags */
|
450 | 1d0a48fb | j_mayer | pte_update_flags(ctx, &env->tlb[best].tlb6.pte1, ret, rw); |
451 | 76a66253 | j_mayer | } |
452 | 76a66253 | j_mayer | |
453 | 76a66253 | j_mayer | return ret;
|
454 | 76a66253 | j_mayer | } |
455 | 76a66253 | j_mayer | |
456 | 9a64fbe4 | bellard | /* Perform BAT hit & translation */
|
457 | faadf50e | j_mayer | static always_inline void bat_size_prot (CPUState *env, target_ulong *blp, |
458 | faadf50e | j_mayer | int *validp, int *protp, |
459 | faadf50e | j_mayer | target_ulong *BATu, target_ulong *BATl) |
460 | faadf50e | j_mayer | { |
461 | faadf50e | j_mayer | target_ulong bl; |
462 | faadf50e | j_mayer | int pp, valid, prot;
|
463 | faadf50e | j_mayer | |
464 | faadf50e | j_mayer | bl = (*BATu & 0x00001FFC) << 15; |
465 | faadf50e | j_mayer | valid = 0;
|
466 | faadf50e | j_mayer | prot = 0;
|
467 | faadf50e | j_mayer | if (((msr_pr == 0) && (*BATu & 0x00000002)) || |
468 | faadf50e | j_mayer | ((msr_pr != 0) && (*BATu & 0x00000001))) { |
469 | faadf50e | j_mayer | valid = 1;
|
470 | faadf50e | j_mayer | pp = *BATl & 0x00000003;
|
471 | faadf50e | j_mayer | if (pp != 0) { |
472 | faadf50e | j_mayer | prot = PAGE_READ | PAGE_EXEC; |
473 | faadf50e | j_mayer | if (pp == 0x2) |
474 | faadf50e | j_mayer | prot |= PAGE_WRITE; |
475 | faadf50e | j_mayer | } |
476 | faadf50e | j_mayer | } |
477 | faadf50e | j_mayer | *blp = bl; |
478 | faadf50e | j_mayer | *validp = valid; |
479 | faadf50e | j_mayer | *protp = prot; |
480 | faadf50e | j_mayer | } |
481 | faadf50e | j_mayer | |
482 | faadf50e | j_mayer | static always_inline void bat_601_size_prot (CPUState *env,target_ulong *blp, |
483 | faadf50e | j_mayer | int *validp, int *protp, |
484 | faadf50e | j_mayer | target_ulong *BATu, |
485 | faadf50e | j_mayer | target_ulong *BATl) |
486 | faadf50e | j_mayer | { |
487 | faadf50e | j_mayer | target_ulong bl; |
488 | faadf50e | j_mayer | int key, pp, valid, prot;
|
489 | faadf50e | j_mayer | |
490 | faadf50e | j_mayer | bl = (*BATl & 0x0000003F) << 17; |
491 | d12d51d5 | aliguori | LOG_BATS("b %02x ==> bl " ADDRX " msk " ADDRX "\n", |
492 | 6b542af7 | j_mayer | (uint8_t)(*BATl & 0x0000003F), bl, ~bl);
|
493 | faadf50e | j_mayer | prot = 0;
|
494 | faadf50e | j_mayer | valid = (*BATl >> 6) & 1; |
495 | faadf50e | j_mayer | if (valid) {
|
496 | faadf50e | j_mayer | pp = *BATu & 0x00000003;
|
497 | faadf50e | j_mayer | if (msr_pr == 0) |
498 | faadf50e | j_mayer | key = (*BATu >> 3) & 1; |
499 | faadf50e | j_mayer | else
|
500 | faadf50e | j_mayer | key = (*BATu >> 2) & 1; |
501 | faadf50e | j_mayer | prot = pp_check(key, pp, 0);
|
502 | faadf50e | j_mayer | } |
503 | faadf50e | j_mayer | *blp = bl; |
504 | faadf50e | j_mayer | *validp = valid; |
505 | faadf50e | j_mayer | *protp = prot; |
506 | faadf50e | j_mayer | } |
507 | faadf50e | j_mayer | |
508 | a11b8151 | j_mayer | static always_inline int get_bat (CPUState *env, mmu_ctx_t *ctx, |
509 | a11b8151 | j_mayer | target_ulong virtual, int rw, int type) |
510 | 9a64fbe4 | bellard | { |
511 | 76a66253 | j_mayer | target_ulong *BATlt, *BATut, *BATu, *BATl; |
512 | 76a66253 | j_mayer | target_ulong base, BEPIl, BEPIu, bl; |
513 | faadf50e | j_mayer | int i, valid, prot;
|
514 | 9a64fbe4 | bellard | int ret = -1; |
515 | 9a64fbe4 | bellard | |
516 | d12d51d5 | aliguori | LOG_BATS("%s: %cBAT v " ADDRX "\n", __func__, |
517 | 76a66253 | j_mayer | type == ACCESS_CODE ? 'I' : 'D', virtual); |
518 | 9a64fbe4 | bellard | switch (type) {
|
519 | 9a64fbe4 | bellard | case ACCESS_CODE:
|
520 | 9a64fbe4 | bellard | BATlt = env->IBAT[1];
|
521 | 9a64fbe4 | bellard | BATut = env->IBAT[0];
|
522 | 9a64fbe4 | bellard | break;
|
523 | 9a64fbe4 | bellard | default:
|
524 | 9a64fbe4 | bellard | BATlt = env->DBAT[1];
|
525 | 9a64fbe4 | bellard | BATut = env->DBAT[0];
|
526 | 9a64fbe4 | bellard | break;
|
527 | 9a64fbe4 | bellard | } |
528 | 9a64fbe4 | bellard | base = virtual & 0xFFFC0000;
|
529 | faadf50e | j_mayer | for (i = 0; i < env->nb_BATs; i++) { |
530 | 9a64fbe4 | bellard | BATu = &BATut[i]; |
531 | 9a64fbe4 | bellard | BATl = &BATlt[i]; |
532 | 9a64fbe4 | bellard | BEPIu = *BATu & 0xF0000000;
|
533 | 9a64fbe4 | bellard | BEPIl = *BATu & 0x0FFE0000;
|
534 | faadf50e | j_mayer | if (unlikely(env->mmu_model == POWERPC_MMU_601)) {
|
535 | faadf50e | j_mayer | bat_601_size_prot(env, &bl, &valid, &prot, BATu, BATl); |
536 | faadf50e | j_mayer | } else {
|
537 | faadf50e | j_mayer | bat_size_prot(env, &bl, &valid, &prot, BATu, BATl); |
538 | faadf50e | j_mayer | } |
539 | d12d51d5 | aliguori | LOG_BATS("%s: %cBAT%d v " ADDRX " BATu " ADDRX |
540 | 6b542af7 | j_mayer | " BATl " ADDRX "\n", __func__, |
541 | 6b542af7 | j_mayer | type == ACCESS_CODE ? 'I' : 'D', i, virtual, *BATu, *BATl); |
542 | 9a64fbe4 | bellard | if ((virtual & 0xF0000000) == BEPIu && |
543 | 9a64fbe4 | bellard | ((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
|
544 | 9a64fbe4 | bellard | /* BAT matches */
|
545 | faadf50e | j_mayer | if (valid != 0) { |
546 | 9a64fbe4 | bellard | /* Get physical address */
|
547 | 76a66253 | j_mayer | ctx->raddr = (*BATl & 0xF0000000) |
|
548 | 9a64fbe4 | bellard | ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) | |
549 | a541f297 | bellard | (virtual & 0x0001F000);
|
550 | b227a8e9 | j_mayer | /* Compute access rights */
|
551 | faadf50e | j_mayer | ctx->prot = prot; |
552 | b227a8e9 | j_mayer | ret = check_prot(ctx->prot, rw, type); |
553 | d12d51d5 | aliguori | if (ret == 0) |
554 | d12d51d5 | aliguori | LOG_BATS("BAT %d match: r " PADDRX " prot=%c%c\n", |
555 | d12d51d5 | aliguori | i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-', |
556 | d12d51d5 | aliguori | ctx->prot & PAGE_WRITE ? 'W' : '-'); |
557 | 9a64fbe4 | bellard | break;
|
558 | 9a64fbe4 | bellard | } |
559 | 9a64fbe4 | bellard | } |
560 | 9a64fbe4 | bellard | } |
561 | 9a64fbe4 | bellard | if (ret < 0) { |
562 | d12d51d5 | aliguori | #if defined(DEBUG_BATS)
|
563 | d12d51d5 | aliguori | if (IS_LOGGING) {
|
564 | d12d51d5 | aliguori | QEMU_LOG0("no BAT match for " ADDRX ":\n", virtual); |
565 | 4a057712 | j_mayer | for (i = 0; i < 4; i++) { |
566 | 4a057712 | j_mayer | BATu = &BATut[i]; |
567 | 4a057712 | j_mayer | BATl = &BATlt[i]; |
568 | 4a057712 | j_mayer | BEPIu = *BATu & 0xF0000000;
|
569 | 4a057712 | j_mayer | BEPIl = *BATu & 0x0FFE0000;
|
570 | 4a057712 | j_mayer | bl = (*BATu & 0x00001FFC) << 15; |
571 | d12d51d5 | aliguori | QEMU_LOG0("%s: %cBAT%d v " ADDRX " BATu " ADDRX |
572 | 6b542af7 | j_mayer | " BATl " ADDRX " \n\t" ADDRX " " ADDRX " " ADDRX "\n", |
573 | 4a057712 | j_mayer | __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual, |
574 | 4a057712 | j_mayer | *BATu, *BATl, BEPIu, BEPIl, bl); |
575 | 4a057712 | j_mayer | } |
576 | 9a64fbe4 | bellard | } |
577 | 9a64fbe4 | bellard | #endif
|
578 | 9a64fbe4 | bellard | } |
579 | 9a64fbe4 | bellard | /* No hit */
|
580 | 9a64fbe4 | bellard | return ret;
|
581 | 9a64fbe4 | bellard | } |
582 | 9a64fbe4 | bellard | |
583 | 9a64fbe4 | bellard | /* PTE table lookup */
|
584 | b227a8e9 | j_mayer | static always_inline int _find_pte (mmu_ctx_t *ctx, int is_64b, int h, |
585 | 5b5aba4f | blueswir1 | int rw, int type, |
586 | 5b5aba4f | blueswir1 | int target_page_bits)
|
587 | 9a64fbe4 | bellard | { |
588 | 76a66253 | j_mayer | target_ulong base, pte0, pte1; |
589 | 76a66253 | j_mayer | int i, good = -1; |
590 | caa4039c | j_mayer | int ret, r;
|
591 | 9a64fbe4 | bellard | |
592 | 76a66253 | j_mayer | ret = -1; /* No entry found */ |
593 | 76a66253 | j_mayer | base = ctx->pg_addr[h]; |
594 | 9a64fbe4 | bellard | for (i = 0; i < 8; i++) { |
595 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
596 | caa4039c | j_mayer | if (is_64b) {
|
597 | caa4039c | j_mayer | pte0 = ldq_phys(base + (i * 16));
|
598 | 5b5aba4f | blueswir1 | pte1 = ldq_phys(base + (i * 16) + 8); |
599 | 5b5aba4f | blueswir1 | |
600 | 5b5aba4f | blueswir1 | /* We have a TLB that saves 4K pages, so let's
|
601 | 5b5aba4f | blueswir1 | * split a huge page to 4k chunks */
|
602 | 5b5aba4f | blueswir1 | if (target_page_bits != TARGET_PAGE_BITS)
|
603 | 5b5aba4f | blueswir1 | pte1 |= (ctx->eaddr & (( 1 << target_page_bits ) - 1)) |
604 | 5b5aba4f | blueswir1 | & TARGET_PAGE_MASK; |
605 | 5b5aba4f | blueswir1 | |
606 | b227a8e9 | j_mayer | r = pte64_check(ctx, pte0, pte1, h, rw, type); |
607 | d12d51d5 | aliguori | LOG_MMU("Load pte from " ADDRX " => " ADDRX " " ADDRX |
608 | 6b542af7 | j_mayer | " %d %d %d " ADDRX "\n", |
609 | 12de9a39 | j_mayer | base + (i * 16), pte0, pte1,
|
610 | 12de9a39 | j_mayer | (int)(pte0 & 1), h, (int)((pte0 >> 1) & 1), |
611 | 12de9a39 | j_mayer | ctx->ptem); |
612 | caa4039c | j_mayer | } else
|
613 | caa4039c | j_mayer | #endif
|
614 | caa4039c | j_mayer | { |
615 | caa4039c | j_mayer | pte0 = ldl_phys(base + (i * 8));
|
616 | caa4039c | j_mayer | pte1 = ldl_phys(base + (i * 8) + 4); |
617 | b227a8e9 | j_mayer | r = pte32_check(ctx, pte0, pte1, h, rw, type); |
618 | d12d51d5 | aliguori | LOG_MMU("Load pte from " ADDRX " => " ADDRX " " ADDRX |
619 | 6b542af7 | j_mayer | " %d %d %d " ADDRX "\n", |
620 | 12de9a39 | j_mayer | base + (i * 8), pte0, pte1,
|
621 | 12de9a39 | j_mayer | (int)(pte0 >> 31), h, (int)((pte0 >> 6) & 1), |
622 | 12de9a39 | j_mayer | ctx->ptem); |
623 | 12de9a39 | j_mayer | } |
624 | caa4039c | j_mayer | switch (r) {
|
625 | 76a66253 | j_mayer | case -3: |
626 | 76a66253 | j_mayer | /* PTE inconsistency */
|
627 | 76a66253 | j_mayer | return -1; |
628 | 76a66253 | j_mayer | case -2: |
629 | 76a66253 | j_mayer | /* Access violation */
|
630 | 76a66253 | j_mayer | ret = -2;
|
631 | 76a66253 | j_mayer | good = i; |
632 | 76a66253 | j_mayer | break;
|
633 | 76a66253 | j_mayer | case -1: |
634 | 76a66253 | j_mayer | default:
|
635 | 76a66253 | j_mayer | /* No PTE match */
|
636 | 76a66253 | j_mayer | break;
|
637 | 76a66253 | j_mayer | case 0: |
638 | 76a66253 | j_mayer | /* access granted */
|
639 | 76a66253 | j_mayer | /* XXX: we should go on looping to check all PTEs consistency
|
640 | 76a66253 | j_mayer | * but if we can speed-up the whole thing as the
|
641 | 76a66253 | j_mayer | * result would be undefined if PTEs are not consistent.
|
642 | 76a66253 | j_mayer | */
|
643 | 76a66253 | j_mayer | ret = 0;
|
644 | 76a66253 | j_mayer | good = i; |
645 | 76a66253 | j_mayer | goto done;
|
646 | 9a64fbe4 | bellard | } |
647 | 9a64fbe4 | bellard | } |
648 | 9a64fbe4 | bellard | if (good != -1) { |
649 | 76a66253 | j_mayer | done:
|
650 | d12d51d5 | aliguori | LOG_MMU("found PTE at addr " PADDRX " prot=%01x ret=%d\n", |
651 | 76a66253 | j_mayer | ctx->raddr, ctx->prot, ret); |
652 | 9a64fbe4 | bellard | /* Update page flags */
|
653 | 76a66253 | j_mayer | pte1 = ctx->raddr; |
654 | caa4039c | j_mayer | if (pte_update_flags(ctx, &pte1, ret, rw) == 1) { |
655 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
656 | caa4039c | j_mayer | if (is_64b) {
|
657 | caa4039c | j_mayer | stq_phys_notdirty(base + (good * 16) + 8, pte1); |
658 | caa4039c | j_mayer | } else
|
659 | caa4039c | j_mayer | #endif
|
660 | caa4039c | j_mayer | { |
661 | caa4039c | j_mayer | stl_phys_notdirty(base + (good * 8) + 4, pte1); |
662 | caa4039c | j_mayer | } |
663 | caa4039c | j_mayer | } |
664 | 9a64fbe4 | bellard | } |
665 | 9a64fbe4 | bellard | |
666 | 9a64fbe4 | bellard | return ret;
|
667 | 79aceca5 | bellard | } |
668 | 79aceca5 | bellard | |
669 | 5b5aba4f | blueswir1 | static always_inline int find_pte32 (mmu_ctx_t *ctx, int h, int rw, |
670 | 5b5aba4f | blueswir1 | int type, int target_page_bits) |
671 | caa4039c | j_mayer | { |
672 | 5b5aba4f | blueswir1 | return _find_pte(ctx, 0, h, rw, type, target_page_bits); |
673 | caa4039c | j_mayer | } |
674 | caa4039c | j_mayer | |
675 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
676 | 5b5aba4f | blueswir1 | static always_inline int find_pte64 (mmu_ctx_t *ctx, int h, int rw, |
677 | 5b5aba4f | blueswir1 | int type, int target_page_bits) |
678 | caa4039c | j_mayer | { |
679 | 5b5aba4f | blueswir1 | return _find_pte(ctx, 1, h, rw, type, target_page_bits); |
680 | caa4039c | j_mayer | } |
681 | caa4039c | j_mayer | #endif
|
682 | caa4039c | j_mayer | |
683 | b068d6a7 | j_mayer | static always_inline int find_pte (CPUState *env, mmu_ctx_t *ctx, |
684 | 5b5aba4f | blueswir1 | int h, int rw, int type, |
685 | 5b5aba4f | blueswir1 | int target_page_bits)
|
686 | caa4039c | j_mayer | { |
687 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
688 | add78955 | j_mayer | if (env->mmu_model & POWERPC_MMU_64)
|
689 | 5b5aba4f | blueswir1 | return find_pte64(ctx, h, rw, type, target_page_bits);
|
690 | caa4039c | j_mayer | #endif
|
691 | caa4039c | j_mayer | |
692 | 5b5aba4f | blueswir1 | return find_pte32(ctx, h, rw, type, target_page_bits);
|
693 | caa4039c | j_mayer | } |
694 | caa4039c | j_mayer | |
695 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
696 | a11b8151 | j_mayer | static always_inline int slb_is_valid (uint64_t slb64) |
697 | eacc3249 | j_mayer | { |
698 | eacc3249 | j_mayer | return slb64 & 0x0000000008000000ULL ? 1 : 0; |
699 | eacc3249 | j_mayer | } |
700 | eacc3249 | j_mayer | |
701 | a11b8151 | j_mayer | static always_inline void slb_invalidate (uint64_t *slb64) |
702 | eacc3249 | j_mayer | { |
703 | eacc3249 | j_mayer | *slb64 &= ~0x0000000008000000ULL;
|
704 | eacc3249 | j_mayer | } |
705 | eacc3249 | j_mayer | |
706 | a11b8151 | j_mayer | static always_inline int slb_lookup (CPUPPCState *env, target_ulong eaddr, |
707 | a11b8151 | j_mayer | target_ulong *vsid, |
708 | 5b5aba4f | blueswir1 | target_ulong *page_mask, int *attr,
|
709 | 5b5aba4f | blueswir1 | int *target_page_bits)
|
710 | caa4039c | j_mayer | { |
711 | caa4039c | j_mayer | target_phys_addr_t sr_base; |
712 | caa4039c | j_mayer | target_ulong mask; |
713 | caa4039c | j_mayer | uint64_t tmp64; |
714 | caa4039c | j_mayer | uint32_t tmp; |
715 | caa4039c | j_mayer | int n, ret;
|
716 | caa4039c | j_mayer | |
717 | caa4039c | j_mayer | ret = -5;
|
718 | caa4039c | j_mayer | sr_base = env->spr[SPR_ASR]; |
719 | d12d51d5 | aliguori | LOG_SLB("%s: eaddr " ADDRX " base " PADDRX "\n", |
720 | 12de9a39 | j_mayer | __func__, eaddr, sr_base); |
721 | caa4039c | j_mayer | mask = 0x0000000000000000ULL; /* Avoid gcc warning */ |
722 | eacc3249 | j_mayer | for (n = 0; n < env->slb_nr; n++) { |
723 | caa4039c | j_mayer | tmp64 = ldq_phys(sr_base); |
724 | 12de9a39 | j_mayer | tmp = ldl_phys(sr_base + 8);
|
725 | d12d51d5 | aliguori | LOG_SLB("%s: seg %d " PADDRX " %016" PRIx64 " %08" |
726 | b33c17e1 | j_mayer | PRIx32 "\n", __func__, n, sr_base, tmp64, tmp);
|
727 | eacc3249 | j_mayer | if (slb_is_valid(tmp64)) {
|
728 | caa4039c | j_mayer | /* SLB entry is valid */
|
729 | 5b5aba4f | blueswir1 | if (tmp & 0x8) { |
730 | 5b5aba4f | blueswir1 | /* 1 TB Segment */
|
731 | caa4039c | j_mayer | mask = 0xFFFF000000000000ULL;
|
732 | 5b5aba4f | blueswir1 | if (target_page_bits)
|
733 | 5b5aba4f | blueswir1 | *target_page_bits = 24; // XXX 16M pages? |
734 | 5b5aba4f | blueswir1 | } else {
|
735 | 5b5aba4f | blueswir1 | /* 256MB Segment */
|
736 | 5b5aba4f | blueswir1 | mask = 0xFFFFFFFFF0000000ULL;
|
737 | 5b5aba4f | blueswir1 | if (target_page_bits)
|
738 | 5b5aba4f | blueswir1 | *target_page_bits = TARGET_PAGE_BITS; |
739 | caa4039c | j_mayer | } |
740 | caa4039c | j_mayer | if ((eaddr & mask) == (tmp64 & mask)) {
|
741 | caa4039c | j_mayer | /* SLB match */
|
742 | caa4039c | j_mayer | *vsid = ((tmp64 << 24) | (tmp >> 8)) & 0x0003FFFFFFFFFFFFULL; |
743 | caa4039c | j_mayer | *page_mask = ~mask; |
744 | caa4039c | j_mayer | *attr = tmp & 0xFF;
|
745 | eacc3249 | j_mayer | ret = n; |
746 | caa4039c | j_mayer | break;
|
747 | caa4039c | j_mayer | } |
748 | caa4039c | j_mayer | } |
749 | caa4039c | j_mayer | sr_base += 12;
|
750 | caa4039c | j_mayer | } |
751 | caa4039c | j_mayer | |
752 | caa4039c | j_mayer | return ret;
|
753 | 79aceca5 | bellard | } |
754 | 12de9a39 | j_mayer | |
755 | eacc3249 | j_mayer | void ppc_slb_invalidate_all (CPUPPCState *env)
|
756 | eacc3249 | j_mayer | { |
757 | eacc3249 | j_mayer | target_phys_addr_t sr_base; |
758 | eacc3249 | j_mayer | uint64_t tmp64; |
759 | eacc3249 | j_mayer | int n, do_invalidate;
|
760 | eacc3249 | j_mayer | |
761 | eacc3249 | j_mayer | do_invalidate = 0;
|
762 | eacc3249 | j_mayer | sr_base = env->spr[SPR_ASR]; |
763 | 2c1ee068 | j_mayer | /* XXX: Warning: slbia never invalidates the first segment */
|
764 | 2c1ee068 | j_mayer | for (n = 1; n < env->slb_nr; n++) { |
765 | eacc3249 | j_mayer | tmp64 = ldq_phys(sr_base); |
766 | eacc3249 | j_mayer | if (slb_is_valid(tmp64)) {
|
767 | eacc3249 | j_mayer | slb_invalidate(&tmp64); |
768 | eacc3249 | j_mayer | stq_phys(sr_base, tmp64); |
769 | eacc3249 | j_mayer | /* XXX: given the fact that segment size is 256 MB or 1TB,
|
770 | eacc3249 | j_mayer | * and we still don't have a tlb_flush_mask(env, n, mask)
|
771 | eacc3249 | j_mayer | * in Qemu, we just invalidate all TLBs
|
772 | eacc3249 | j_mayer | */
|
773 | eacc3249 | j_mayer | do_invalidate = 1;
|
774 | eacc3249 | j_mayer | } |
775 | eacc3249 | j_mayer | sr_base += 12;
|
776 | eacc3249 | j_mayer | } |
777 | eacc3249 | j_mayer | if (do_invalidate)
|
778 | eacc3249 | j_mayer | tlb_flush(env, 1);
|
779 | eacc3249 | j_mayer | } |
780 | eacc3249 | j_mayer | |
781 | eacc3249 | j_mayer | void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0)
|
782 | eacc3249 | j_mayer | { |
783 | eacc3249 | j_mayer | target_phys_addr_t sr_base; |
784 | eacc3249 | j_mayer | target_ulong vsid, page_mask; |
785 | eacc3249 | j_mayer | uint64_t tmp64; |
786 | eacc3249 | j_mayer | int attr;
|
787 | eacc3249 | j_mayer | int n;
|
788 | eacc3249 | j_mayer | |
789 | 5b5aba4f | blueswir1 | n = slb_lookup(env, T0, &vsid, &page_mask, &attr, NULL);
|
790 | eacc3249 | j_mayer | if (n >= 0) { |
791 | eacc3249 | j_mayer | sr_base = env->spr[SPR_ASR]; |
792 | eacc3249 | j_mayer | sr_base += 12 * n;
|
793 | eacc3249 | j_mayer | tmp64 = ldq_phys(sr_base); |
794 | eacc3249 | j_mayer | if (slb_is_valid(tmp64)) {
|
795 | eacc3249 | j_mayer | slb_invalidate(&tmp64); |
796 | eacc3249 | j_mayer | stq_phys(sr_base, tmp64); |
797 | eacc3249 | j_mayer | /* XXX: given the fact that segment size is 256 MB or 1TB,
|
798 | eacc3249 | j_mayer | * and we still don't have a tlb_flush_mask(env, n, mask)
|
799 | eacc3249 | j_mayer | * in Qemu, we just invalidate all TLBs
|
800 | eacc3249 | j_mayer | */
|
801 | eacc3249 | j_mayer | tlb_flush(env, 1);
|
802 | eacc3249 | j_mayer | } |
803 | eacc3249 | j_mayer | } |
804 | eacc3249 | j_mayer | } |
805 | eacc3249 | j_mayer | |
806 | 12de9a39 | j_mayer | target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr)
|
807 | 12de9a39 | j_mayer | { |
808 | 12de9a39 | j_mayer | target_phys_addr_t sr_base; |
809 | 12de9a39 | j_mayer | target_ulong rt; |
810 | 12de9a39 | j_mayer | uint64_t tmp64; |
811 | 12de9a39 | j_mayer | uint32_t tmp; |
812 | 12de9a39 | j_mayer | |
813 | 12de9a39 | j_mayer | sr_base = env->spr[SPR_ASR]; |
814 | 12de9a39 | j_mayer | sr_base += 12 * slb_nr;
|
815 | 12de9a39 | j_mayer | tmp64 = ldq_phys(sr_base); |
816 | 12de9a39 | j_mayer | tmp = ldl_phys(sr_base + 8);
|
817 | 12de9a39 | j_mayer | if (tmp64 & 0x0000000008000000ULL) { |
818 | 12de9a39 | j_mayer | /* SLB entry is valid */
|
819 | 12de9a39 | j_mayer | /* Copy SLB bits 62:88 to Rt 37:63 (VSID 23:49) */
|
820 | 12de9a39 | j_mayer | rt = tmp >> 8; /* 65:88 => 40:63 */ |
821 | 12de9a39 | j_mayer | rt |= (tmp64 & 0x7) << 24; /* 62:64 => 37:39 */ |
822 | 12de9a39 | j_mayer | /* Copy SLB bits 89:92 to Rt 33:36 (KsKpNL) */
|
823 | 12de9a39 | j_mayer | rt |= ((tmp >> 4) & 0xF) << 27; |
824 | 12de9a39 | j_mayer | } else {
|
825 | 12de9a39 | j_mayer | rt = 0;
|
826 | 12de9a39 | j_mayer | } |
827 | d12d51d5 | aliguori | LOG_SLB("%s: " PADDRX " %016" PRIx64 " %08" PRIx32 " => %d " |
828 | 12de9a39 | j_mayer | ADDRX "\n", __func__, sr_base, tmp64, tmp, slb_nr, rt);
|
829 | 12de9a39 | j_mayer | |
830 | 12de9a39 | j_mayer | return rt;
|
831 | 12de9a39 | j_mayer | } |
832 | 12de9a39 | j_mayer | |
833 | f6b868fc | blueswir1 | void ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs)
|
834 | 12de9a39 | j_mayer | { |
835 | 12de9a39 | j_mayer | target_phys_addr_t sr_base; |
836 | 12de9a39 | j_mayer | uint64_t tmp64; |
837 | 12de9a39 | j_mayer | uint32_t tmp; |
838 | 12de9a39 | j_mayer | |
839 | f6b868fc | blueswir1 | uint64_t vsid; |
840 | f6b868fc | blueswir1 | uint64_t esid; |
841 | f6b868fc | blueswir1 | int flags, valid, slb_nr;
|
842 | f6b868fc | blueswir1 | |
843 | f6b868fc | blueswir1 | vsid = rs >> 12;
|
844 | f6b868fc | blueswir1 | flags = ((rs >> 8) & 0xf); |
845 | f6b868fc | blueswir1 | |
846 | f6b868fc | blueswir1 | esid = rb >> 28;
|
847 | f6b868fc | blueswir1 | valid = (rb & (1 << 27)); |
848 | f6b868fc | blueswir1 | slb_nr = rb & 0xfff;
|
849 | f6b868fc | blueswir1 | |
850 | f6b868fc | blueswir1 | tmp64 = (esid << 28) | valid | (vsid >> 24); |
851 | f6b868fc | blueswir1 | tmp = (vsid << 8) | (flags << 3); |
852 | f6b868fc | blueswir1 | |
853 | f6b868fc | blueswir1 | /* Write SLB entry to memory */
|
854 | 12de9a39 | j_mayer | sr_base = env->spr[SPR_ASR]; |
855 | 12de9a39 | j_mayer | sr_base += 12 * slb_nr;
|
856 | f6b868fc | blueswir1 | |
857 | f6b868fc | blueswir1 | LOG_SLB("%s: %d " ADDRX " - " ADDRX " => " PADDRX " %016" PRIx64 |
858 | 6b542af7 | j_mayer | " %08" PRIx32 "\n", __func__, |
859 | f6b868fc | blueswir1 | slb_nr, rb, rs, sr_base, tmp64, tmp); |
860 | f6b868fc | blueswir1 | |
861 | 12de9a39 | j_mayer | stq_phys(sr_base, tmp64); |
862 | 12de9a39 | j_mayer | stl_phys(sr_base + 8, tmp);
|
863 | 12de9a39 | j_mayer | } |
864 | caa4039c | j_mayer | #endif /* defined(TARGET_PPC64) */ |
865 | 79aceca5 | bellard | |
866 | 9a64fbe4 | bellard | /* Perform segment based translation */
|
867 | b068d6a7 | j_mayer | static always_inline target_phys_addr_t get_pgaddr (target_phys_addr_t sdr1,
|
868 | b068d6a7 | j_mayer | int sdr_sh,
|
869 | b068d6a7 | j_mayer | target_phys_addr_t hash, |
870 | b068d6a7 | j_mayer | target_phys_addr_t mask) |
871 | 12de9a39 | j_mayer | { |
872 | 6f2d8978 | j_mayer | return (sdr1 & ((target_phys_addr_t)(-1ULL) << sdr_sh)) | (hash & mask); |
873 | 12de9a39 | j_mayer | } |
874 | 12de9a39 | j_mayer | |
875 | a11b8151 | j_mayer | static always_inline int get_segment (CPUState *env, mmu_ctx_t *ctx, |
876 | a11b8151 | j_mayer | target_ulong eaddr, int rw, int type) |
877 | 79aceca5 | bellard | { |
878 | 12de9a39 | j_mayer | target_phys_addr_t sdr, hash, mask, sdr_mask, htab_mask; |
879 | caa4039c | j_mayer | target_ulong sr, vsid, vsid_mask, pgidx, page_mask; |
880 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
881 | caa4039c | j_mayer | int attr;
|
882 | 9a64fbe4 | bellard | #endif
|
883 | 5b5aba4f | blueswir1 | int ds, vsid_sh, sdr_sh, pr, target_page_bits;
|
884 | caa4039c | j_mayer | int ret, ret2;
|
885 | caa4039c | j_mayer | |
886 | 0411a972 | j_mayer | pr = msr_pr; |
887 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
888 | add78955 | j_mayer | if (env->mmu_model & POWERPC_MMU_64) {
|
889 | d12d51d5 | aliguori | LOG_MMU("Check SLBs\n");
|
890 | 5b5aba4f | blueswir1 | ret = slb_lookup(env, eaddr, &vsid, &page_mask, &attr, |
891 | 5b5aba4f | blueswir1 | &target_page_bits); |
892 | caa4039c | j_mayer | if (ret < 0) |
893 | caa4039c | j_mayer | return ret;
|
894 | 0411a972 | j_mayer | ctx->key = ((attr & 0x40) && (pr != 0)) || |
895 | 0411a972 | j_mayer | ((attr & 0x80) && (pr == 0)) ? 1 : 0; |
896 | caa4039c | j_mayer | ds = 0;
|
897 | 5b5aba4f | blueswir1 | ctx->nx = attr & 0x10 ? 1 : 0; |
898 | 5b5aba4f | blueswir1 | ctx->eaddr = eaddr; |
899 | caa4039c | j_mayer | vsid_mask = 0x00003FFFFFFFFF80ULL;
|
900 | caa4039c | j_mayer | vsid_sh = 7;
|
901 | caa4039c | j_mayer | sdr_sh = 18;
|
902 | caa4039c | j_mayer | sdr_mask = 0x3FF80;
|
903 | caa4039c | j_mayer | } else
|
904 | caa4039c | j_mayer | #endif /* defined(TARGET_PPC64) */ |
905 | caa4039c | j_mayer | { |
906 | caa4039c | j_mayer | sr = env->sr[eaddr >> 28];
|
907 | caa4039c | j_mayer | page_mask = 0x0FFFFFFF;
|
908 | 0411a972 | j_mayer | ctx->key = (((sr & 0x20000000) && (pr != 0)) || |
909 | 0411a972 | j_mayer | ((sr & 0x40000000) && (pr == 0))) ? 1 : 0; |
910 | caa4039c | j_mayer | ds = sr & 0x80000000 ? 1 : 0; |
911 | b227a8e9 | j_mayer | ctx->nx = sr & 0x10000000 ? 1 : 0; |
912 | caa4039c | j_mayer | vsid = sr & 0x00FFFFFF;
|
913 | caa4039c | j_mayer | vsid_mask = 0x01FFFFC0;
|
914 | caa4039c | j_mayer | vsid_sh = 6;
|
915 | caa4039c | j_mayer | sdr_sh = 16;
|
916 | caa4039c | j_mayer | sdr_mask = 0xFFC0;
|
917 | 5b5aba4f | blueswir1 | target_page_bits = TARGET_PAGE_BITS; |
918 | d12d51d5 | aliguori | LOG_MMU("Check segment v=" ADDRX " %d " ADDRX |
919 | 6b542af7 | j_mayer | " nip=" ADDRX " lr=" ADDRX " ir=%d dr=%d pr=%d %d t=%d\n", |
920 | caa4039c | j_mayer | eaddr, (int)(eaddr >> 28), sr, env->nip, |
921 | 0411a972 | j_mayer | env->lr, (int)msr_ir, (int)msr_dr, pr != 0 ? 1 : 0, |
922 | 0411a972 | j_mayer | rw, type); |
923 | caa4039c | j_mayer | } |
924 | d12d51d5 | aliguori | LOG_MMU("pte segment: key=%d ds %d nx %d vsid " ADDRX "\n", |
925 | b227a8e9 | j_mayer | ctx->key, ds, ctx->nx, vsid); |
926 | caa4039c | j_mayer | ret = -1;
|
927 | caa4039c | j_mayer | if (!ds) {
|
928 | 9a64fbe4 | bellard | /* Check if instruction fetch is allowed, if needed */
|
929 | b227a8e9 | j_mayer | if (type != ACCESS_CODE || ctx->nx == 0) { |
930 | 9a64fbe4 | bellard | /* Page address translation */
|
931 | 76a66253 | j_mayer | /* Primary table address */
|
932 | 76a66253 | j_mayer | sdr = env->sdr1; |
933 | 5b5aba4f | blueswir1 | pgidx = (eaddr & page_mask) >> target_page_bits; |
934 | 12de9a39 | j_mayer | #if defined(TARGET_PPC64)
|
935 | add78955 | j_mayer | if (env->mmu_model & POWERPC_MMU_64) {
|
936 | 12de9a39 | j_mayer | htab_mask = 0x0FFFFFFF >> (28 - (sdr & 0x1F)); |
937 | 12de9a39 | j_mayer | /* XXX: this is false for 1 TB segments */
|
938 | 12de9a39 | j_mayer | hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask; |
939 | 12de9a39 | j_mayer | } else
|
940 | 12de9a39 | j_mayer | #endif
|
941 | 12de9a39 | j_mayer | { |
942 | 12de9a39 | j_mayer | htab_mask = sdr & 0x000001FF;
|
943 | 12de9a39 | j_mayer | hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask; |
944 | 12de9a39 | j_mayer | } |
945 | 12de9a39 | j_mayer | mask = (htab_mask << sdr_sh) | sdr_mask; |
946 | d12d51d5 | aliguori | LOG_MMU("sdr " PADDRX " sh %d hash " PADDRX |
947 | 6b542af7 | j_mayer | " mask " PADDRX " " ADDRX "\n", |
948 | 6b542af7 | j_mayer | sdr, sdr_sh, hash, mask, page_mask); |
949 | caa4039c | j_mayer | ctx->pg_addr[0] = get_pgaddr(sdr, sdr_sh, hash, mask);
|
950 | 76a66253 | j_mayer | /* Secondary table address */
|
951 | caa4039c | j_mayer | hash = (~hash) & vsid_mask; |
952 | d12d51d5 | aliguori | LOG_MMU("sdr " PADDRX " sh %d hash " PADDRX |
953 | 6b542af7 | j_mayer | " mask " PADDRX "\n", |
954 | 6b542af7 | j_mayer | sdr, sdr_sh, hash, mask); |
955 | caa4039c | j_mayer | ctx->pg_addr[1] = get_pgaddr(sdr, sdr_sh, hash, mask);
|
956 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
957 | add78955 | j_mayer | if (env->mmu_model & POWERPC_MMU_64) {
|
958 | caa4039c | j_mayer | /* Only 5 bits of the page index are used in the AVPN */
|
959 | 5b5aba4f | blueswir1 | if (target_page_bits > 23) { |
960 | 5b5aba4f | blueswir1 | ctx->ptem = (vsid << 12) |
|
961 | 5b5aba4f | blueswir1 | ((pgidx << (target_page_bits - 16)) & 0xF80); |
962 | 5b5aba4f | blueswir1 | } else {
|
963 | 5b5aba4f | blueswir1 | ctx->ptem = (vsid << 12) | ((pgidx >> 4) & 0x0F80); |
964 | 5b5aba4f | blueswir1 | } |
965 | caa4039c | j_mayer | } else
|
966 | caa4039c | j_mayer | #endif
|
967 | caa4039c | j_mayer | { |
968 | caa4039c | j_mayer | ctx->ptem = (vsid << 7) | (pgidx >> 10); |
969 | caa4039c | j_mayer | } |
970 | 76a66253 | j_mayer | /* Initialize real address with an invalid value */
|
971 | 6f2d8978 | j_mayer | ctx->raddr = (target_phys_addr_t)-1ULL;
|
972 | 7dbe11ac | j_mayer | if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_6xx ||
|
973 | 7dbe11ac | j_mayer | env->mmu_model == POWERPC_MMU_SOFT_74xx)) { |
974 | 76a66253 | j_mayer | /* Software TLB search */
|
975 | 76a66253 | j_mayer | ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type); |
976 | 76a66253 | j_mayer | } else {
|
977 | d12d51d5 | aliguori | LOG_MMU("0 sdr1=" PADDRX " vsid=" ADDRX " " |
978 | 6b542af7 | j_mayer | "api=" ADDRX " hash=" PADDRX |
979 | 6b542af7 | j_mayer | " pg_addr=" PADDRX "\n", |
980 | 6b542af7 | j_mayer | sdr, vsid, pgidx, hash, ctx->pg_addr[0]);
|
981 | 76a66253 | j_mayer | /* Primary table lookup */
|
982 | 5b5aba4f | blueswir1 | ret = find_pte(env, ctx, 0, rw, type, target_page_bits);
|
983 | 76a66253 | j_mayer | if (ret < 0) { |
984 | 76a66253 | j_mayer | /* Secondary table lookup */
|
985 | d12d51d5 | aliguori | if (eaddr != 0xEFFFFFFF) |
986 | d12d51d5 | aliguori | LOG_MMU("1 sdr1=" PADDRX " vsid=" ADDRX " " |
987 | 6b542af7 | j_mayer | "api=" ADDRX " hash=" PADDRX |
988 | 6b542af7 | j_mayer | " pg_addr=" PADDRX "\n", |
989 | 6b542af7 | j_mayer | sdr, vsid, pgidx, hash, ctx->pg_addr[1]);
|
990 | 5b5aba4f | blueswir1 | ret2 = find_pte(env, ctx, 1, rw, type,
|
991 | 5b5aba4f | blueswir1 | target_page_bits); |
992 | 76a66253 | j_mayer | if (ret2 != -1) |
993 | 76a66253 | j_mayer | ret = ret2; |
994 | 76a66253 | j_mayer | } |
995 | 9a64fbe4 | bellard | } |
996 | 0411a972 | j_mayer | #if defined (DUMP_PAGE_TABLES)
|
997 | 93fcfe39 | aliguori | if (qemu_log_enabled()) {
|
998 | b33c17e1 | j_mayer | target_phys_addr_t curaddr; |
999 | b33c17e1 | j_mayer | uint32_t a0, a1, a2, a3; |
1000 | 93fcfe39 | aliguori | qemu_log("Page table: " PADDRX " len " PADDRX "\n", |
1001 | 93fcfe39 | aliguori | sdr, mask + 0x80);
|
1002 | b33c17e1 | j_mayer | for (curaddr = sdr; curaddr < (sdr + mask + 0x80); |
1003 | b33c17e1 | j_mayer | curaddr += 16) {
|
1004 | b33c17e1 | j_mayer | a0 = ldl_phys(curaddr); |
1005 | b33c17e1 | j_mayer | a1 = ldl_phys(curaddr + 4);
|
1006 | b33c17e1 | j_mayer | a2 = ldl_phys(curaddr + 8);
|
1007 | b33c17e1 | j_mayer | a3 = ldl_phys(curaddr + 12);
|
1008 | b33c17e1 | j_mayer | if (a0 != 0 || a1 != 0 || a2 != 0 || a3 != 0) { |
1009 | 93fcfe39 | aliguori | qemu_log(PADDRX ": %08x %08x %08x %08x\n",
|
1010 | 93fcfe39 | aliguori | curaddr, a0, a1, a2, a3); |
1011 | 12de9a39 | j_mayer | } |
1012 | b33c17e1 | j_mayer | } |
1013 | b33c17e1 | j_mayer | } |
1014 | 12de9a39 | j_mayer | #endif
|
1015 | 9a64fbe4 | bellard | } else {
|
1016 | d12d51d5 | aliguori | LOG_MMU("No access allowed\n");
|
1017 | 76a66253 | j_mayer | ret = -3;
|
1018 | 9a64fbe4 | bellard | } |
1019 | 9a64fbe4 | bellard | } else {
|
1020 | d12d51d5 | aliguori | LOG_MMU("direct store...\n");
|
1021 | 9a64fbe4 | bellard | /* Direct-store segment : absolutely *BUGGY* for now */
|
1022 | 9a64fbe4 | bellard | switch (type) {
|
1023 | 9a64fbe4 | bellard | case ACCESS_INT:
|
1024 | 9a64fbe4 | bellard | /* Integer load/store : only access allowed */
|
1025 | 9a64fbe4 | bellard | break;
|
1026 | 9a64fbe4 | bellard | case ACCESS_CODE:
|
1027 | 9a64fbe4 | bellard | /* No code fetch is allowed in direct-store areas */
|
1028 | 9a64fbe4 | bellard | return -4; |
1029 | 9a64fbe4 | bellard | case ACCESS_FLOAT:
|
1030 | 9a64fbe4 | bellard | /* Floating point load/store */
|
1031 | 9a64fbe4 | bellard | return -4; |
1032 | 9a64fbe4 | bellard | case ACCESS_RES:
|
1033 | 9a64fbe4 | bellard | /* lwarx, ldarx or srwcx. */
|
1034 | 9a64fbe4 | bellard | return -4; |
1035 | 9a64fbe4 | bellard | case ACCESS_CACHE:
|
1036 | 9a64fbe4 | bellard | /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
|
1037 | 9a64fbe4 | bellard | /* Should make the instruction do no-op.
|
1038 | 9a64fbe4 | bellard | * As it already do no-op, it's quite easy :-)
|
1039 | 9a64fbe4 | bellard | */
|
1040 | 76a66253 | j_mayer | ctx->raddr = eaddr; |
1041 | 9a64fbe4 | bellard | return 0; |
1042 | 9a64fbe4 | bellard | case ACCESS_EXT:
|
1043 | 9a64fbe4 | bellard | /* eciwx or ecowx */
|
1044 | 9a64fbe4 | bellard | return -4; |
1045 | 9a64fbe4 | bellard | default:
|
1046 | 93fcfe39 | aliguori | qemu_log("ERROR: instruction should not need "
|
1047 | 9a64fbe4 | bellard | "address translation\n");
|
1048 | 9a64fbe4 | bellard | return -4; |
1049 | 9a64fbe4 | bellard | } |
1050 | 76a66253 | j_mayer | if ((rw == 1 || ctx->key != 1) && (rw == 0 || ctx->key != 0)) { |
1051 | 76a66253 | j_mayer | ctx->raddr = eaddr; |
1052 | 9a64fbe4 | bellard | ret = 2;
|
1053 | 9a64fbe4 | bellard | } else {
|
1054 | 9a64fbe4 | bellard | ret = -2;
|
1055 | 9a64fbe4 | bellard | } |
1056 | 79aceca5 | bellard | } |
1057 | 9a64fbe4 | bellard | |
1058 | 9a64fbe4 | bellard | return ret;
|
1059 | 79aceca5 | bellard | } |
1060 | 79aceca5 | bellard | |
1061 | c294fc58 | j_mayer | /* Generic TLB check function for embedded PowerPC implementations */
|
1062 | a11b8151 | j_mayer | static always_inline int ppcemb_tlb_check (CPUState *env, ppcemb_tlb_t *tlb, |
1063 | a11b8151 | j_mayer | target_phys_addr_t *raddrp, |
1064 | a11b8151 | j_mayer | target_ulong address, |
1065 | a11b8151 | j_mayer | uint32_t pid, int ext, int i) |
1066 | c294fc58 | j_mayer | { |
1067 | c294fc58 | j_mayer | target_ulong mask; |
1068 | c294fc58 | j_mayer | |
1069 | c294fc58 | j_mayer | /* Check valid flag */
|
1070 | c294fc58 | j_mayer | if (!(tlb->prot & PAGE_VALID)) {
|
1071 | 93fcfe39 | aliguori | qemu_log("%s: TLB %d not valid\n", __func__, i);
|
1072 | c294fc58 | j_mayer | return -1; |
1073 | c294fc58 | j_mayer | } |
1074 | c294fc58 | j_mayer | mask = ~(tlb->size - 1);
|
1075 | d12d51d5 | aliguori | LOG_SWTLB("%s: TLB %d address " ADDRX " PID %u <=> " ADDRX |
1076 | 6b542af7 | j_mayer | " " ADDRX " %u\n", |
1077 | 6b542af7 | j_mayer | __func__, i, address, pid, tlb->EPN, mask, (uint32_t)tlb->PID); |
1078 | c294fc58 | j_mayer | /* Check PID */
|
1079 | 36081602 | j_mayer | if (tlb->PID != 0 && tlb->PID != pid) |
1080 | c294fc58 | j_mayer | return -1; |
1081 | c294fc58 | j_mayer | /* Check effective address */
|
1082 | c294fc58 | j_mayer | if ((address & mask) != tlb->EPN)
|
1083 | c294fc58 | j_mayer | return -1; |
1084 | c294fc58 | j_mayer | *raddrp = (tlb->RPN & mask) | (address & ~mask); |
1085 | 9706285b | j_mayer | #if (TARGET_PHYS_ADDR_BITS >= 36) |
1086 | 36081602 | j_mayer | if (ext) {
|
1087 | 36081602 | j_mayer | /* Extend the physical address to 36 bits */
|
1088 | 36081602 | j_mayer | *raddrp |= (target_phys_addr_t)(tlb->RPN & 0xF) << 32; |
1089 | 36081602 | j_mayer | } |
1090 | 9706285b | j_mayer | #endif
|
1091 | c294fc58 | j_mayer | |
1092 | c294fc58 | j_mayer | return 0; |
1093 | c294fc58 | j_mayer | } |
1094 | c294fc58 | j_mayer | |
1095 | c294fc58 | j_mayer | /* Generic TLB search function for PowerPC embedded implementations */
|
1096 | 36081602 | j_mayer | int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid)
|
1097 | c294fc58 | j_mayer | { |
1098 | c294fc58 | j_mayer | ppcemb_tlb_t *tlb; |
1099 | c294fc58 | j_mayer | target_phys_addr_t raddr; |
1100 | c294fc58 | j_mayer | int i, ret;
|
1101 | c294fc58 | j_mayer | |
1102 | c294fc58 | j_mayer | /* Default return value is no match */
|
1103 | c294fc58 | j_mayer | ret = -1;
|
1104 | a750fc0b | j_mayer | for (i = 0; i < env->nb_tlb; i++) { |
1105 | c294fc58 | j_mayer | tlb = &env->tlb[i].tlbe; |
1106 | 36081602 | j_mayer | if (ppcemb_tlb_check(env, tlb, &raddr, address, pid, 0, i) == 0) { |
1107 | c294fc58 | j_mayer | ret = i; |
1108 | c294fc58 | j_mayer | break;
|
1109 | c294fc58 | j_mayer | } |
1110 | c294fc58 | j_mayer | } |
1111 | c294fc58 | j_mayer | |
1112 | c294fc58 | j_mayer | return ret;
|
1113 | c294fc58 | j_mayer | } |
1114 | c294fc58 | j_mayer | |
1115 | daf4f96e | j_mayer | /* Helpers specific to PowerPC 40x implementations */
|
1116 | a11b8151 | j_mayer | static always_inline void ppc4xx_tlb_invalidate_all (CPUState *env) |
1117 | a750fc0b | j_mayer | { |
1118 | a750fc0b | j_mayer | ppcemb_tlb_t *tlb; |
1119 | a750fc0b | j_mayer | int i;
|
1120 | a750fc0b | j_mayer | |
1121 | a750fc0b | j_mayer | for (i = 0; i < env->nb_tlb; i++) { |
1122 | a750fc0b | j_mayer | tlb = &env->tlb[i].tlbe; |
1123 | daf4f96e | j_mayer | tlb->prot &= ~PAGE_VALID; |
1124 | a750fc0b | j_mayer | } |
1125 | daf4f96e | j_mayer | tlb_flush(env, 1);
|
1126 | a750fc0b | j_mayer | } |
1127 | a750fc0b | j_mayer | |
1128 | a11b8151 | j_mayer | static always_inline void ppc4xx_tlb_invalidate_virt (CPUState *env, |
1129 | a11b8151 | j_mayer | target_ulong eaddr, |
1130 | a11b8151 | j_mayer | uint32_t pid) |
1131 | 0a032cbe | j_mayer | { |
1132 | daf4f96e | j_mayer | #if !defined(FLUSH_ALL_TLBS)
|
1133 | 0a032cbe | j_mayer | ppcemb_tlb_t *tlb; |
1134 | daf4f96e | j_mayer | target_phys_addr_t raddr; |
1135 | daf4f96e | j_mayer | target_ulong page, end; |
1136 | 0a032cbe | j_mayer | int i;
|
1137 | 0a032cbe | j_mayer | |
1138 | 0a032cbe | j_mayer | for (i = 0; i < env->nb_tlb; i++) { |
1139 | 0a032cbe | j_mayer | tlb = &env->tlb[i].tlbe; |
1140 | daf4f96e | j_mayer | if (ppcemb_tlb_check(env, tlb, &raddr, eaddr, pid, 0, i) == 0) { |
1141 | 0a032cbe | j_mayer | end = tlb->EPN + tlb->size; |
1142 | 0a032cbe | j_mayer | for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
|
1143 | 0a032cbe | j_mayer | tlb_flush_page(env, page); |
1144 | 0a032cbe | j_mayer | tlb->prot &= ~PAGE_VALID; |
1145 | daf4f96e | j_mayer | break;
|
1146 | 0a032cbe | j_mayer | } |
1147 | 0a032cbe | j_mayer | } |
1148 | daf4f96e | j_mayer | #else
|
1149 | daf4f96e | j_mayer | ppc4xx_tlb_invalidate_all(env); |
1150 | daf4f96e | j_mayer | #endif
|
1151 | 0a032cbe | j_mayer | } |
1152 | 0a032cbe | j_mayer | |
1153 | 93220573 | aurel32 | static int mmu40x_get_physical_address (CPUState *env, mmu_ctx_t *ctx, |
1154 | e96efcfc | j_mayer | target_ulong address, int rw, int access_type) |
1155 | a8dea12f | j_mayer | { |
1156 | a8dea12f | j_mayer | ppcemb_tlb_t *tlb; |
1157 | a8dea12f | j_mayer | target_phys_addr_t raddr; |
1158 | 0411a972 | j_mayer | int i, ret, zsel, zpr, pr;
|
1159 | 3b46e624 | ths | |
1160 | c55e9aef | j_mayer | ret = -1;
|
1161 | 6f2d8978 | j_mayer | raddr = (target_phys_addr_t)-1ULL;
|
1162 | 0411a972 | j_mayer | pr = msr_pr; |
1163 | a8dea12f | j_mayer | for (i = 0; i < env->nb_tlb; i++) { |
1164 | a8dea12f | j_mayer | tlb = &env->tlb[i].tlbe; |
1165 | 36081602 | j_mayer | if (ppcemb_tlb_check(env, tlb, &raddr, address,
|
1166 | 36081602 | j_mayer | env->spr[SPR_40x_PID], 0, i) < 0) |
1167 | a8dea12f | j_mayer | continue;
|
1168 | a8dea12f | j_mayer | zsel = (tlb->attr >> 4) & 0xF; |
1169 | a8dea12f | j_mayer | zpr = (env->spr[SPR_40x_ZPR] >> (28 - (2 * zsel))) & 0x3; |
1170 | d12d51d5 | aliguori | LOG_SWTLB("%s: TLB %d zsel %d zpr %d rw %d attr %08x\n",
|
1171 | a8dea12f | j_mayer | __func__, i, zsel, zpr, rw, tlb->attr); |
1172 | b227a8e9 | j_mayer | /* Check execute enable bit */
|
1173 | b227a8e9 | j_mayer | switch (zpr) {
|
1174 | b227a8e9 | j_mayer | case 0x2: |
1175 | 0411a972 | j_mayer | if (pr != 0) |
1176 | b227a8e9 | j_mayer | goto check_perms;
|
1177 | b227a8e9 | j_mayer | /* No break here */
|
1178 | b227a8e9 | j_mayer | case 0x3: |
1179 | b227a8e9 | j_mayer | /* All accesses granted */
|
1180 | b227a8e9 | j_mayer | ctx->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
1181 | b227a8e9 | j_mayer | ret = 0;
|
1182 | b227a8e9 | j_mayer | break;
|
1183 | b227a8e9 | j_mayer | case 0x0: |
1184 | 0411a972 | j_mayer | if (pr != 0) { |
1185 | b227a8e9 | j_mayer | ctx->prot = 0;
|
1186 | b227a8e9 | j_mayer | ret = -2;
|
1187 | a8dea12f | j_mayer | break;
|
1188 | a8dea12f | j_mayer | } |
1189 | b227a8e9 | j_mayer | /* No break here */
|
1190 | b227a8e9 | j_mayer | case 0x1: |
1191 | b227a8e9 | j_mayer | check_perms:
|
1192 | b227a8e9 | j_mayer | /* Check from TLB entry */
|
1193 | b227a8e9 | j_mayer | /* XXX: there is a problem here or in the TLB fill code... */
|
1194 | b227a8e9 | j_mayer | ctx->prot = tlb->prot; |
1195 | b227a8e9 | j_mayer | ctx->prot |= PAGE_EXEC; |
1196 | b227a8e9 | j_mayer | ret = check_prot(ctx->prot, rw, access_type); |
1197 | b227a8e9 | j_mayer | break;
|
1198 | a8dea12f | j_mayer | } |
1199 | a8dea12f | j_mayer | if (ret >= 0) { |
1200 | a8dea12f | j_mayer | ctx->raddr = raddr; |
1201 | d12d51d5 | aliguori | LOG_SWTLB("%s: access granted " ADDRX " => " PADDRX |
1202 | c55e9aef | j_mayer | " %d %d\n", __func__, address, ctx->raddr, ctx->prot,
|
1203 | c55e9aef | j_mayer | ret); |
1204 | c55e9aef | j_mayer | return 0; |
1205 | a8dea12f | j_mayer | } |
1206 | a8dea12f | j_mayer | } |
1207 | d12d51d5 | aliguori | LOG_SWTLB("%s: access refused " ADDRX " => " PADDRX |
1208 | c55e9aef | j_mayer | " %d %d\n", __func__, address, raddr, ctx->prot,
|
1209 | c55e9aef | j_mayer | ret); |
1210 | 3b46e624 | ths | |
1211 | a8dea12f | j_mayer | return ret;
|
1212 | a8dea12f | j_mayer | } |
1213 | a8dea12f | j_mayer | |
1214 | c294fc58 | j_mayer | void store_40x_sler (CPUPPCState *env, uint32_t val)
|
1215 | c294fc58 | j_mayer | { |
1216 | c294fc58 | j_mayer | /* XXX: TO BE FIXED */
|
1217 | c294fc58 | j_mayer | if (val != 0x00000000) { |
1218 | c294fc58 | j_mayer | cpu_abort(env, "Little-endian regions are not supported by now\n");
|
1219 | c294fc58 | j_mayer | } |
1220 | c294fc58 | j_mayer | env->spr[SPR_405_SLER] = val; |
1221 | c294fc58 | j_mayer | } |
1222 | c294fc58 | j_mayer | |
1223 | 93220573 | aurel32 | static int mmubooke_get_physical_address (CPUState *env, mmu_ctx_t *ctx, |
1224 | 93220573 | aurel32 | target_ulong address, int rw,
|
1225 | 93220573 | aurel32 | int access_type)
|
1226 | 5eb7995e | j_mayer | { |
1227 | 5eb7995e | j_mayer | ppcemb_tlb_t *tlb; |
1228 | 5eb7995e | j_mayer | target_phys_addr_t raddr; |
1229 | 5eb7995e | j_mayer | int i, prot, ret;
|
1230 | 5eb7995e | j_mayer | |
1231 | 5eb7995e | j_mayer | ret = -1;
|
1232 | 6f2d8978 | j_mayer | raddr = (target_phys_addr_t)-1ULL;
|
1233 | 5eb7995e | j_mayer | for (i = 0; i < env->nb_tlb; i++) { |
1234 | 5eb7995e | j_mayer | tlb = &env->tlb[i].tlbe; |
1235 | 5eb7995e | j_mayer | if (ppcemb_tlb_check(env, tlb, &raddr, address,
|
1236 | 5eb7995e | j_mayer | env->spr[SPR_BOOKE_PID], 1, i) < 0) |
1237 | 5eb7995e | j_mayer | continue;
|
1238 | 0411a972 | j_mayer | if (msr_pr != 0) |
1239 | 5eb7995e | j_mayer | prot = tlb->prot & 0xF;
|
1240 | 5eb7995e | j_mayer | else
|
1241 | 5eb7995e | j_mayer | prot = (tlb->prot >> 4) & 0xF; |
1242 | 5eb7995e | j_mayer | /* Check the address space */
|
1243 | 5eb7995e | j_mayer | if (access_type == ACCESS_CODE) {
|
1244 | d26bfc9a | j_mayer | if (msr_ir != (tlb->attr & 1)) |
1245 | 5eb7995e | j_mayer | continue;
|
1246 | 5eb7995e | j_mayer | ctx->prot = prot; |
1247 | 5eb7995e | j_mayer | if (prot & PAGE_EXEC) {
|
1248 | 5eb7995e | j_mayer | ret = 0;
|
1249 | 5eb7995e | j_mayer | break;
|
1250 | 5eb7995e | j_mayer | } |
1251 | 5eb7995e | j_mayer | ret = -3;
|
1252 | 5eb7995e | j_mayer | } else {
|
1253 | d26bfc9a | j_mayer | if (msr_dr != (tlb->attr & 1)) |
1254 | 5eb7995e | j_mayer | continue;
|
1255 | 5eb7995e | j_mayer | ctx->prot = prot; |
1256 | 5eb7995e | j_mayer | if ((!rw && prot & PAGE_READ) || (rw && (prot & PAGE_WRITE))) {
|
1257 | 5eb7995e | j_mayer | ret = 0;
|
1258 | 5eb7995e | j_mayer | break;
|
1259 | 5eb7995e | j_mayer | } |
1260 | 5eb7995e | j_mayer | ret = -2;
|
1261 | 5eb7995e | j_mayer | } |
1262 | 5eb7995e | j_mayer | } |
1263 | 5eb7995e | j_mayer | if (ret >= 0) |
1264 | 5eb7995e | j_mayer | ctx->raddr = raddr; |
1265 | 5eb7995e | j_mayer | |
1266 | 5eb7995e | j_mayer | return ret;
|
1267 | 5eb7995e | j_mayer | } |
1268 | 5eb7995e | j_mayer | |
1269 | a11b8151 | j_mayer | static always_inline int check_physical (CPUState *env, mmu_ctx_t *ctx, |
1270 | a11b8151 | j_mayer | target_ulong eaddr, int rw)
|
1271 | 76a66253 | j_mayer | { |
1272 | 76a66253 | j_mayer | int in_plb, ret;
|
1273 | 3b46e624 | ths | |
1274 | 76a66253 | j_mayer | ctx->raddr = eaddr; |
1275 | b227a8e9 | j_mayer | ctx->prot = PAGE_READ | PAGE_EXEC; |
1276 | 76a66253 | j_mayer | ret = 0;
|
1277 | a750fc0b | j_mayer | switch (env->mmu_model) {
|
1278 | a750fc0b | j_mayer | case POWERPC_MMU_32B:
|
1279 | faadf50e | j_mayer | case POWERPC_MMU_601:
|
1280 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_6xx:
|
1281 | 7dbe11ac | j_mayer | case POWERPC_MMU_SOFT_74xx:
|
1282 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_4xx:
|
1283 | b4095fed | j_mayer | case POWERPC_MMU_REAL:
|
1284 | 7dbe11ac | j_mayer | case POWERPC_MMU_BOOKE:
|
1285 | caa4039c | j_mayer | ctx->prot |= PAGE_WRITE; |
1286 | caa4039c | j_mayer | break;
|
1287 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
1288 | add78955 | j_mayer | case POWERPC_MMU_620:
|
1289 | a750fc0b | j_mayer | case POWERPC_MMU_64B:
|
1290 | caa4039c | j_mayer | /* Real address are 60 bits long */
|
1291 | a750fc0b | j_mayer | ctx->raddr &= 0x0FFFFFFFFFFFFFFFULL;
|
1292 | caa4039c | j_mayer | ctx->prot |= PAGE_WRITE; |
1293 | caa4039c | j_mayer | break;
|
1294 | 9706285b | j_mayer | #endif
|
1295 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_4xx_Z:
|
1296 | caa4039c | j_mayer | if (unlikely(msr_pe != 0)) { |
1297 | caa4039c | j_mayer | /* 403 family add some particular protections,
|
1298 | caa4039c | j_mayer | * using PBL/PBU registers for accesses with no translation.
|
1299 | caa4039c | j_mayer | */
|
1300 | caa4039c | j_mayer | in_plb = |
1301 | caa4039c | j_mayer | /* Check PLB validity */
|
1302 | caa4039c | j_mayer | (env->pb[0] < env->pb[1] && |
1303 | caa4039c | j_mayer | /* and address in plb area */
|
1304 | caa4039c | j_mayer | eaddr >= env->pb[0] && eaddr < env->pb[1]) || |
1305 | caa4039c | j_mayer | (env->pb[2] < env->pb[3] && |
1306 | caa4039c | j_mayer | eaddr >= env->pb[2] && eaddr < env->pb[3]) ? 1 : 0; |
1307 | caa4039c | j_mayer | if (in_plb ^ msr_px) {
|
1308 | caa4039c | j_mayer | /* Access in protected area */
|
1309 | caa4039c | j_mayer | if (rw == 1) { |
1310 | caa4039c | j_mayer | /* Access is not allowed */
|
1311 | caa4039c | j_mayer | ret = -2;
|
1312 | caa4039c | j_mayer | } |
1313 | caa4039c | j_mayer | } else {
|
1314 | caa4039c | j_mayer | /* Read-write access is allowed */
|
1315 | caa4039c | j_mayer | ctx->prot |= PAGE_WRITE; |
1316 | 76a66253 | j_mayer | } |
1317 | 76a66253 | j_mayer | } |
1318 | e1833e1f | j_mayer | break;
|
1319 | b4095fed | j_mayer | case POWERPC_MMU_MPC8xx:
|
1320 | b4095fed | j_mayer | /* XXX: TODO */
|
1321 | b4095fed | j_mayer | cpu_abort(env, "MPC8xx MMU model is not implemented\n");
|
1322 | b4095fed | j_mayer | break;
|
1323 | a750fc0b | j_mayer | case POWERPC_MMU_BOOKE_FSL:
|
1324 | caa4039c | j_mayer | /* XXX: TODO */
|
1325 | caa4039c | j_mayer | cpu_abort(env, "BookE FSL MMU model not implemented\n");
|
1326 | caa4039c | j_mayer | break;
|
1327 | caa4039c | j_mayer | default:
|
1328 | caa4039c | j_mayer | cpu_abort(env, "Unknown or invalid MMU model\n");
|
1329 | caa4039c | j_mayer | return -1; |
1330 | 76a66253 | j_mayer | } |
1331 | 76a66253 | j_mayer | |
1332 | 76a66253 | j_mayer | return ret;
|
1333 | 76a66253 | j_mayer | } |
1334 | 76a66253 | j_mayer | |
1335 | 76a66253 | j_mayer | int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr,
|
1336 | faadf50e | j_mayer | int rw, int access_type) |
1337 | 9a64fbe4 | bellard | { |
1338 | 9a64fbe4 | bellard | int ret;
|
1339 | 0411a972 | j_mayer | |
1340 | 514fb8c1 | bellard | #if 0
|
1341 | 93fcfe39 | aliguori | qemu_log("%s\n", __func__);
|
1342 | d9bce9d9 | j_mayer | #endif
|
1343 | 4b3686fa | bellard | if ((access_type == ACCESS_CODE && msr_ir == 0) || |
1344 | 4b3686fa | bellard | (access_type != ACCESS_CODE && msr_dr == 0)) {
|
1345 | 9a64fbe4 | bellard | /* No address translation */
|
1346 | 76a66253 | j_mayer | ret = check_physical(env, ctx, eaddr, rw); |
1347 | 9a64fbe4 | bellard | } else {
|
1348 | c55e9aef | j_mayer | ret = -1;
|
1349 | a750fc0b | j_mayer | switch (env->mmu_model) {
|
1350 | a750fc0b | j_mayer | case POWERPC_MMU_32B:
|
1351 | faadf50e | j_mayer | case POWERPC_MMU_601:
|
1352 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_6xx:
|
1353 | 7dbe11ac | j_mayer | case POWERPC_MMU_SOFT_74xx:
|
1354 | c55e9aef | j_mayer | #if defined(TARGET_PPC64)
|
1355 | add78955 | j_mayer | case POWERPC_MMU_620:
|
1356 | a750fc0b | j_mayer | case POWERPC_MMU_64B:
|
1357 | c55e9aef | j_mayer | #endif
|
1358 | faadf50e | j_mayer | /* Try to find a BAT */
|
1359 | faadf50e | j_mayer | if (env->nb_BATs != 0) |
1360 | faadf50e | j_mayer | ret = get_bat(env, ctx, eaddr, rw, access_type); |
1361 | a8dea12f | j_mayer | if (ret < 0) { |
1362 | c55e9aef | j_mayer | /* We didn't match any BAT entry or don't have BATs */
|
1363 | a8dea12f | j_mayer | ret = get_segment(env, ctx, eaddr, rw, access_type); |
1364 | a8dea12f | j_mayer | } |
1365 | a8dea12f | j_mayer | break;
|
1366 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_4xx:
|
1367 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_4xx_Z:
|
1368 | 36081602 | j_mayer | ret = mmu40x_get_physical_address(env, ctx, eaddr, |
1369 | a8dea12f | j_mayer | rw, access_type); |
1370 | a8dea12f | j_mayer | break;
|
1371 | a750fc0b | j_mayer | case POWERPC_MMU_BOOKE:
|
1372 | 5eb7995e | j_mayer | ret = mmubooke_get_physical_address(env, ctx, eaddr, |
1373 | 5eb7995e | j_mayer | rw, access_type); |
1374 | 5eb7995e | j_mayer | break;
|
1375 | b4095fed | j_mayer | case POWERPC_MMU_MPC8xx:
|
1376 | b4095fed | j_mayer | /* XXX: TODO */
|
1377 | b4095fed | j_mayer | cpu_abort(env, "MPC8xx MMU model is not implemented\n");
|
1378 | b4095fed | j_mayer | break;
|
1379 | a750fc0b | j_mayer | case POWERPC_MMU_BOOKE_FSL:
|
1380 | c55e9aef | j_mayer | /* XXX: TODO */
|
1381 | c55e9aef | j_mayer | cpu_abort(env, "BookE FSL MMU model not implemented\n");
|
1382 | c55e9aef | j_mayer | return -1; |
1383 | b4095fed | j_mayer | case POWERPC_MMU_REAL:
|
1384 | b4095fed | j_mayer | cpu_abort(env, "PowerPC in real mode do not do any translation\n");
|
1385 | 2662a059 | j_mayer | return -1; |
1386 | c55e9aef | j_mayer | default:
|
1387 | c55e9aef | j_mayer | cpu_abort(env, "Unknown or invalid MMU model\n");
|
1388 | a8dea12f | j_mayer | return -1; |
1389 | 9a64fbe4 | bellard | } |
1390 | 9a64fbe4 | bellard | } |
1391 | 514fb8c1 | bellard | #if 0
|
1392 | 93fcfe39 | aliguori | qemu_log("%s address " ADDRX " => %d " PADDRX "\n",
|
1393 | c55e9aef | j_mayer | __func__, eaddr, ret, ctx->raddr);
|
1394 | 76a66253 | j_mayer | #endif
|
1395 | d9bce9d9 | j_mayer | |
1396 | 9a64fbe4 | bellard | return ret;
|
1397 | 9a64fbe4 | bellard | } |
1398 | 9a64fbe4 | bellard | |
1399 | 9b3c35e0 | j_mayer | target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr) |
1400 | a6b025d3 | bellard | { |
1401 | 76a66253 | j_mayer | mmu_ctx_t ctx; |
1402 | a6b025d3 | bellard | |
1403 | faadf50e | j_mayer | if (unlikely(get_physical_address(env, &ctx, addr, 0, ACCESS_INT) != 0)) |
1404 | a6b025d3 | bellard | return -1; |
1405 | 76a66253 | j_mayer | |
1406 | 76a66253 | j_mayer | return ctx.raddr & TARGET_PAGE_MASK;
|
1407 | a6b025d3 | bellard | } |
1408 | 9a64fbe4 | bellard | |
1409 | 9a64fbe4 | bellard | /* Perform address translation */
|
1410 | e96efcfc | j_mayer | int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
1411 | 6ebbf390 | j_mayer | int mmu_idx, int is_softmmu) |
1412 | 9a64fbe4 | bellard | { |
1413 | 76a66253 | j_mayer | mmu_ctx_t ctx; |
1414 | a541f297 | bellard | int access_type;
|
1415 | 9a64fbe4 | bellard | int ret = 0; |
1416 | d9bce9d9 | j_mayer | |
1417 | b769d8fe | bellard | if (rw == 2) { |
1418 | b769d8fe | bellard | /* code access */
|
1419 | b769d8fe | bellard | rw = 0;
|
1420 | b769d8fe | bellard | access_type = ACCESS_CODE; |
1421 | b769d8fe | bellard | } else {
|
1422 | b769d8fe | bellard | /* data access */
|
1423 | b4cec7b4 | aurel32 | access_type = env->access_type; |
1424 | b769d8fe | bellard | } |
1425 | faadf50e | j_mayer | ret = get_physical_address(env, &ctx, address, rw, access_type); |
1426 | 9a64fbe4 | bellard | if (ret == 0) { |
1427 | b227a8e9 | j_mayer | ret = tlb_set_page_exec(env, address & TARGET_PAGE_MASK, |
1428 | b227a8e9 | j_mayer | ctx.raddr & TARGET_PAGE_MASK, ctx.prot, |
1429 | b227a8e9 | j_mayer | mmu_idx, is_softmmu); |
1430 | 9a64fbe4 | bellard | } else if (ret < 0) { |
1431 | d12d51d5 | aliguori | LOG_MMU_STATE(env); |
1432 | 9a64fbe4 | bellard | if (access_type == ACCESS_CODE) {
|
1433 | 9a64fbe4 | bellard | switch (ret) {
|
1434 | 9a64fbe4 | bellard | case -1: |
1435 | 76a66253 | j_mayer | /* No matches in page tables or TLB */
|
1436 | a750fc0b | j_mayer | switch (env->mmu_model) {
|
1437 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_6xx:
|
1438 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_IFTLB; |
1439 | 8f793433 | j_mayer | env->error_code = 1 << 18; |
1440 | 76a66253 | j_mayer | env->spr[SPR_IMISS] = address; |
1441 | 76a66253 | j_mayer | env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem;
|
1442 | 76a66253 | j_mayer | goto tlb_miss;
|
1443 | 7dbe11ac | j_mayer | case POWERPC_MMU_SOFT_74xx:
|
1444 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_IFTLB; |
1445 | 7dbe11ac | j_mayer | goto tlb_miss_74xx;
|
1446 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_4xx:
|
1447 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_4xx_Z:
|
1448 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_ITLB; |
1449 | 8f793433 | j_mayer | env->error_code = 0;
|
1450 | a8dea12f | j_mayer | env->spr[SPR_40x_DEAR] = address; |
1451 | a8dea12f | j_mayer | env->spr[SPR_40x_ESR] = 0x00000000;
|
1452 | c55e9aef | j_mayer | break;
|
1453 | a750fc0b | j_mayer | case POWERPC_MMU_32B:
|
1454 | faadf50e | j_mayer | case POWERPC_MMU_601:
|
1455 | c55e9aef | j_mayer | #if defined(TARGET_PPC64)
|
1456 | add78955 | j_mayer | case POWERPC_MMU_620:
|
1457 | a750fc0b | j_mayer | case POWERPC_MMU_64B:
|
1458 | c55e9aef | j_mayer | #endif
|
1459 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_ISI; |
1460 | 8f793433 | j_mayer | env->error_code = 0x40000000;
|
1461 | 8f793433 | j_mayer | break;
|
1462 | a750fc0b | j_mayer | case POWERPC_MMU_BOOKE:
|
1463 | c55e9aef | j_mayer | /* XXX: TODO */
|
1464 | b4095fed | j_mayer | cpu_abort(env, "BookE MMU model is not implemented\n");
|
1465 | c55e9aef | j_mayer | return -1; |
1466 | a750fc0b | j_mayer | case POWERPC_MMU_BOOKE_FSL:
|
1467 | c55e9aef | j_mayer | /* XXX: TODO */
|
1468 | b4095fed | j_mayer | cpu_abort(env, "BookE FSL MMU model is not implemented\n");
|
1469 | c55e9aef | j_mayer | return -1; |
1470 | b4095fed | j_mayer | case POWERPC_MMU_MPC8xx:
|
1471 | b4095fed | j_mayer | /* XXX: TODO */
|
1472 | b4095fed | j_mayer | cpu_abort(env, "MPC8xx MMU model is not implemented\n");
|
1473 | b4095fed | j_mayer | break;
|
1474 | b4095fed | j_mayer | case POWERPC_MMU_REAL:
|
1475 | b4095fed | j_mayer | cpu_abort(env, "PowerPC in real mode should never raise "
|
1476 | b4095fed | j_mayer | "any MMU exceptions\n");
|
1477 | 2662a059 | j_mayer | return -1; |
1478 | c55e9aef | j_mayer | default:
|
1479 | c55e9aef | j_mayer | cpu_abort(env, "Unknown or invalid MMU model\n");
|
1480 | c55e9aef | j_mayer | return -1; |
1481 | 76a66253 | j_mayer | } |
1482 | 9a64fbe4 | bellard | break;
|
1483 | 9a64fbe4 | bellard | case -2: |
1484 | 9a64fbe4 | bellard | /* Access rights violation */
|
1485 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_ISI; |
1486 | 8f793433 | j_mayer | env->error_code = 0x08000000;
|
1487 | 9a64fbe4 | bellard | break;
|
1488 | 9a64fbe4 | bellard | case -3: |
1489 | 76a66253 | j_mayer | /* No execute protection violation */
|
1490 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_ISI; |
1491 | 8f793433 | j_mayer | env->error_code = 0x10000000;
|
1492 | 9a64fbe4 | bellard | break;
|
1493 | 9a64fbe4 | bellard | case -4: |
1494 | 9a64fbe4 | bellard | /* Direct store exception */
|
1495 | 9a64fbe4 | bellard | /* No code fetch is allowed in direct-store areas */
|
1496 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_ISI; |
1497 | 8f793433 | j_mayer | env->error_code = 0x10000000;
|
1498 | 2be0071f | bellard | break;
|
1499 | e1833e1f | j_mayer | #if defined(TARGET_PPC64)
|
1500 | 2be0071f | bellard | case -5: |
1501 | 2be0071f | bellard | /* No match in segment table */
|
1502 | add78955 | j_mayer | if (env->mmu_model == POWERPC_MMU_620) {
|
1503 | add78955 | j_mayer | env->exception_index = POWERPC_EXCP_ISI; |
1504 | add78955 | j_mayer | /* XXX: this might be incorrect */
|
1505 | add78955 | j_mayer | env->error_code = 0x40000000;
|
1506 | add78955 | j_mayer | } else {
|
1507 | add78955 | j_mayer | env->exception_index = POWERPC_EXCP_ISEG; |
1508 | add78955 | j_mayer | env->error_code = 0;
|
1509 | add78955 | j_mayer | } |
1510 | 9a64fbe4 | bellard | break;
|
1511 | e1833e1f | j_mayer | #endif
|
1512 | 9a64fbe4 | bellard | } |
1513 | 9a64fbe4 | bellard | } else {
|
1514 | 9a64fbe4 | bellard | switch (ret) {
|
1515 | 9a64fbe4 | bellard | case -1: |
1516 | 76a66253 | j_mayer | /* No matches in page tables or TLB */
|
1517 | a750fc0b | j_mayer | switch (env->mmu_model) {
|
1518 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_6xx:
|
1519 | 76a66253 | j_mayer | if (rw == 1) { |
1520 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_DSTLB; |
1521 | 8f793433 | j_mayer | env->error_code = 1 << 16; |
1522 | 76a66253 | j_mayer | } else {
|
1523 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_DLTLB; |
1524 | 8f793433 | j_mayer | env->error_code = 0;
|
1525 | 76a66253 | j_mayer | } |
1526 | 76a66253 | j_mayer | env->spr[SPR_DMISS] = address; |
1527 | 76a66253 | j_mayer | env->spr[SPR_DCMP] = 0x80000000 | ctx.ptem;
|
1528 | 76a66253 | j_mayer | tlb_miss:
|
1529 | 8f793433 | j_mayer | env->error_code |= ctx.key << 19;
|
1530 | 76a66253 | j_mayer | env->spr[SPR_HASH1] = ctx.pg_addr[0];
|
1531 | 76a66253 | j_mayer | env->spr[SPR_HASH2] = ctx.pg_addr[1];
|
1532 | 8f793433 | j_mayer | break;
|
1533 | 7dbe11ac | j_mayer | case POWERPC_MMU_SOFT_74xx:
|
1534 | 7dbe11ac | j_mayer | if (rw == 1) { |
1535 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_DSTLB; |
1536 | 7dbe11ac | j_mayer | } else {
|
1537 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_DLTLB; |
1538 | 7dbe11ac | j_mayer | } |
1539 | 7dbe11ac | j_mayer | tlb_miss_74xx:
|
1540 | 7dbe11ac | j_mayer | /* Implement LRU algorithm */
|
1541 | 8f793433 | j_mayer | env->error_code = ctx.key << 19;
|
1542 | 7dbe11ac | j_mayer | env->spr[SPR_TLBMISS] = (address & ~((target_ulong)0x3)) |
|
1543 | 7dbe11ac | j_mayer | ((env->last_way + 1) & (env->nb_ways - 1)); |
1544 | 7dbe11ac | j_mayer | env->spr[SPR_PTEHI] = 0x80000000 | ctx.ptem;
|
1545 | 7dbe11ac | j_mayer | break;
|
1546 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_4xx:
|
1547 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_4xx_Z:
|
1548 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_DTLB; |
1549 | 8f793433 | j_mayer | env->error_code = 0;
|
1550 | a8dea12f | j_mayer | env->spr[SPR_40x_DEAR] = address; |
1551 | a8dea12f | j_mayer | if (rw)
|
1552 | a8dea12f | j_mayer | env->spr[SPR_40x_ESR] = 0x00800000;
|
1553 | a8dea12f | j_mayer | else
|
1554 | a8dea12f | j_mayer | env->spr[SPR_40x_ESR] = 0x00000000;
|
1555 | c55e9aef | j_mayer | break;
|
1556 | a750fc0b | j_mayer | case POWERPC_MMU_32B:
|
1557 | faadf50e | j_mayer | case POWERPC_MMU_601:
|
1558 | c55e9aef | j_mayer | #if defined(TARGET_PPC64)
|
1559 | add78955 | j_mayer | case POWERPC_MMU_620:
|
1560 | a750fc0b | j_mayer | case POWERPC_MMU_64B:
|
1561 | c55e9aef | j_mayer | #endif
|
1562 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_DSI; |
1563 | 8f793433 | j_mayer | env->error_code = 0;
|
1564 | 8f793433 | j_mayer | env->spr[SPR_DAR] = address; |
1565 | 8f793433 | j_mayer | if (rw == 1) |
1566 | 8f793433 | j_mayer | env->spr[SPR_DSISR] = 0x42000000;
|
1567 | 8f793433 | j_mayer | else
|
1568 | 8f793433 | j_mayer | env->spr[SPR_DSISR] = 0x40000000;
|
1569 | 8f793433 | j_mayer | break;
|
1570 | b4095fed | j_mayer | case POWERPC_MMU_MPC8xx:
|
1571 | b4095fed | j_mayer | /* XXX: TODO */
|
1572 | b4095fed | j_mayer | cpu_abort(env, "MPC8xx MMU model is not implemented\n");
|
1573 | b4095fed | j_mayer | break;
|
1574 | a750fc0b | j_mayer | case POWERPC_MMU_BOOKE:
|
1575 | c55e9aef | j_mayer | /* XXX: TODO */
|
1576 | b4095fed | j_mayer | cpu_abort(env, "BookE MMU model is not implemented\n");
|
1577 | c55e9aef | j_mayer | return -1; |
1578 | a750fc0b | j_mayer | case POWERPC_MMU_BOOKE_FSL:
|
1579 | c55e9aef | j_mayer | /* XXX: TODO */
|
1580 | b4095fed | j_mayer | cpu_abort(env, "BookE FSL MMU model is not implemented\n");
|
1581 | c55e9aef | j_mayer | return -1; |
1582 | b4095fed | j_mayer | case POWERPC_MMU_REAL:
|
1583 | b4095fed | j_mayer | cpu_abort(env, "PowerPC in real mode should never raise "
|
1584 | b4095fed | j_mayer | "any MMU exceptions\n");
|
1585 | 2662a059 | j_mayer | return -1; |
1586 | c55e9aef | j_mayer | default:
|
1587 | c55e9aef | j_mayer | cpu_abort(env, "Unknown or invalid MMU model\n");
|
1588 | c55e9aef | j_mayer | return -1; |
1589 | 76a66253 | j_mayer | } |
1590 | 9a64fbe4 | bellard | break;
|
1591 | 9a64fbe4 | bellard | case -2: |
1592 | 9a64fbe4 | bellard | /* Access rights violation */
|
1593 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_DSI; |
1594 | 8f793433 | j_mayer | env->error_code = 0;
|
1595 | 8f793433 | j_mayer | env->spr[SPR_DAR] = address; |
1596 | 8f793433 | j_mayer | if (rw == 1) |
1597 | 8f793433 | j_mayer | env->spr[SPR_DSISR] = 0x0A000000;
|
1598 | 8f793433 | j_mayer | else
|
1599 | 8f793433 | j_mayer | env->spr[SPR_DSISR] = 0x08000000;
|
1600 | 9a64fbe4 | bellard | break;
|
1601 | 9a64fbe4 | bellard | case -4: |
1602 | 9a64fbe4 | bellard | /* Direct store exception */
|
1603 | 9a64fbe4 | bellard | switch (access_type) {
|
1604 | 9a64fbe4 | bellard | case ACCESS_FLOAT:
|
1605 | 9a64fbe4 | bellard | /* Floating point load/store */
|
1606 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_ALIGN; |
1607 | 8f793433 | j_mayer | env->error_code = POWERPC_EXCP_ALIGN_FP; |
1608 | 8f793433 | j_mayer | env->spr[SPR_DAR] = address; |
1609 | 9a64fbe4 | bellard | break;
|
1610 | 9a64fbe4 | bellard | case ACCESS_RES:
|
1611 | 8f793433 | j_mayer | /* lwarx, ldarx or stwcx. */
|
1612 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_DSI; |
1613 | 8f793433 | j_mayer | env->error_code = 0;
|
1614 | 8f793433 | j_mayer | env->spr[SPR_DAR] = address; |
1615 | 8f793433 | j_mayer | if (rw == 1) |
1616 | 8f793433 | j_mayer | env->spr[SPR_DSISR] = 0x06000000;
|
1617 | 8f793433 | j_mayer | else
|
1618 | 8f793433 | j_mayer | env->spr[SPR_DSISR] = 0x04000000;
|
1619 | 9a64fbe4 | bellard | break;
|
1620 | 9a64fbe4 | bellard | case ACCESS_EXT:
|
1621 | 9a64fbe4 | bellard | /* eciwx or ecowx */
|
1622 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_DSI; |
1623 | 8f793433 | j_mayer | env->error_code = 0;
|
1624 | 8f793433 | j_mayer | env->spr[SPR_DAR] = address; |
1625 | 8f793433 | j_mayer | if (rw == 1) |
1626 | 8f793433 | j_mayer | env->spr[SPR_DSISR] = 0x06100000;
|
1627 | 8f793433 | j_mayer | else
|
1628 | 8f793433 | j_mayer | env->spr[SPR_DSISR] = 0x04100000;
|
1629 | 9a64fbe4 | bellard | break;
|
1630 | 9a64fbe4 | bellard | default:
|
1631 | 76a66253 | j_mayer | printf("DSI: invalid exception (%d)\n", ret);
|
1632 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_PROGRAM; |
1633 | 8f793433 | j_mayer | env->error_code = |
1634 | 8f793433 | j_mayer | POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL; |
1635 | 8f793433 | j_mayer | env->spr[SPR_DAR] = address; |
1636 | 9a64fbe4 | bellard | break;
|
1637 | 9a64fbe4 | bellard | } |
1638 | fdabc366 | bellard | break;
|
1639 | e1833e1f | j_mayer | #if defined(TARGET_PPC64)
|
1640 | 2be0071f | bellard | case -5: |
1641 | 2be0071f | bellard | /* No match in segment table */
|
1642 | add78955 | j_mayer | if (env->mmu_model == POWERPC_MMU_620) {
|
1643 | add78955 | j_mayer | env->exception_index = POWERPC_EXCP_DSI; |
1644 | add78955 | j_mayer | env->error_code = 0;
|
1645 | add78955 | j_mayer | env->spr[SPR_DAR] = address; |
1646 | add78955 | j_mayer | /* XXX: this might be incorrect */
|
1647 | add78955 | j_mayer | if (rw == 1) |
1648 | add78955 | j_mayer | env->spr[SPR_DSISR] = 0x42000000;
|
1649 | add78955 | j_mayer | else
|
1650 | add78955 | j_mayer | env->spr[SPR_DSISR] = 0x40000000;
|
1651 | add78955 | j_mayer | } else {
|
1652 | add78955 | j_mayer | env->exception_index = POWERPC_EXCP_DSEG; |
1653 | add78955 | j_mayer | env->error_code = 0;
|
1654 | add78955 | j_mayer | env->spr[SPR_DAR] = address; |
1655 | add78955 | j_mayer | } |
1656 | 2be0071f | bellard | break;
|
1657 | e1833e1f | j_mayer | #endif
|
1658 | 9a64fbe4 | bellard | } |
1659 | 9a64fbe4 | bellard | } |
1660 | 9a64fbe4 | bellard | #if 0
|
1661 | 8f793433 | j_mayer | printf("%s: set exception to %d %02x\n", __func__,
|
1662 | 8f793433 | j_mayer | env->exception, env->error_code);
|
1663 | 9a64fbe4 | bellard | #endif
|
1664 | 9a64fbe4 | bellard | ret = 1;
|
1665 | 9a64fbe4 | bellard | } |
1666 | 76a66253 | j_mayer | |
1667 | 9a64fbe4 | bellard | return ret;
|
1668 | 9a64fbe4 | bellard | } |
1669 | 9a64fbe4 | bellard | |
1670 | 3fc6c082 | bellard | /*****************************************************************************/
|
1671 | 3fc6c082 | bellard | /* BATs management */
|
1672 | 3fc6c082 | bellard | #if !defined(FLUSH_ALL_TLBS)
|
1673 | b068d6a7 | j_mayer | static always_inline void do_invalidate_BAT (CPUPPCState *env, |
1674 | b068d6a7 | j_mayer | target_ulong BATu, |
1675 | b068d6a7 | j_mayer | target_ulong mask) |
1676 | 3fc6c082 | bellard | { |
1677 | 3fc6c082 | bellard | target_ulong base, end, page; |
1678 | 76a66253 | j_mayer | |
1679 | 3fc6c082 | bellard | base = BATu & ~0x0001FFFF;
|
1680 | 3fc6c082 | bellard | end = base + mask + 0x00020000;
|
1681 | d12d51d5 | aliguori | LOG_BATS("Flush BAT from " ADDRX " to " ADDRX " (" ADDRX ")\n", |
1682 | 76a66253 | j_mayer | base, end, mask); |
1683 | 3fc6c082 | bellard | for (page = base; page != end; page += TARGET_PAGE_SIZE)
|
1684 | 3fc6c082 | bellard | tlb_flush_page(env, page); |
1685 | d12d51d5 | aliguori | LOG_BATS("Flush done\n");
|
1686 | 3fc6c082 | bellard | } |
1687 | 3fc6c082 | bellard | #endif
|
1688 | 3fc6c082 | bellard | |
1689 | b068d6a7 | j_mayer | static always_inline void dump_store_bat (CPUPPCState *env, char ID, |
1690 | b068d6a7 | j_mayer | int ul, int nr, target_ulong value) |
1691 | 3fc6c082 | bellard | { |
1692 | d12d51d5 | aliguori | LOG_BATS("Set %cBAT%d%c to " ADDRX " (" ADDRX ")\n", |
1693 | 1b9eb036 | j_mayer | ID, nr, ul == 0 ? 'u' : 'l', value, env->nip); |
1694 | 3fc6c082 | bellard | } |
1695 | 3fc6c082 | bellard | |
1696 | 45d827d2 | aurel32 | void ppc_store_ibatu (CPUPPCState *env, int nr, target_ulong value) |
1697 | 3fc6c082 | bellard | { |
1698 | 3fc6c082 | bellard | target_ulong mask; |
1699 | 3fc6c082 | bellard | |
1700 | 3fc6c082 | bellard | dump_store_bat(env, 'I', 0, nr, value); |
1701 | 3fc6c082 | bellard | if (env->IBAT[0][nr] != value) { |
1702 | 3fc6c082 | bellard | mask = (value << 15) & 0x0FFE0000UL; |
1703 | 3fc6c082 | bellard | #if !defined(FLUSH_ALL_TLBS)
|
1704 | 3fc6c082 | bellard | do_invalidate_BAT(env, env->IBAT[0][nr], mask);
|
1705 | 3fc6c082 | bellard | #endif
|
1706 | 3fc6c082 | bellard | /* When storing valid upper BAT, mask BEPI and BRPN
|
1707 | 3fc6c082 | bellard | * and invalidate all TLBs covered by this BAT
|
1708 | 3fc6c082 | bellard | */
|
1709 | 3fc6c082 | bellard | mask = (value << 15) & 0x0FFE0000UL; |
1710 | 3fc6c082 | bellard | env->IBAT[0][nr] = (value & 0x00001FFFUL) | |
1711 | 3fc6c082 | bellard | (value & ~0x0001FFFFUL & ~mask);
|
1712 | 3fc6c082 | bellard | env->IBAT[1][nr] = (env->IBAT[1][nr] & 0x0000007B) | |
1713 | 3fc6c082 | bellard | (env->IBAT[1][nr] & ~0x0001FFFF & ~mask); |
1714 | 3fc6c082 | bellard | #if !defined(FLUSH_ALL_TLBS)
|
1715 | 3fc6c082 | bellard | do_invalidate_BAT(env, env->IBAT[0][nr], mask);
|
1716 | 76a66253 | j_mayer | #else
|
1717 | 3fc6c082 | bellard | tlb_flush(env, 1);
|
1718 | 3fc6c082 | bellard | #endif
|
1719 | 3fc6c082 | bellard | } |
1720 | 3fc6c082 | bellard | } |
1721 | 3fc6c082 | bellard | |
1722 | 45d827d2 | aurel32 | void ppc_store_ibatl (CPUPPCState *env, int nr, target_ulong value) |
1723 | 3fc6c082 | bellard | { |
1724 | 3fc6c082 | bellard | dump_store_bat(env, 'I', 1, nr, value); |
1725 | 3fc6c082 | bellard | env->IBAT[1][nr] = value;
|
1726 | 3fc6c082 | bellard | } |
1727 | 3fc6c082 | bellard | |
1728 | 45d827d2 | aurel32 | void ppc_store_dbatu (CPUPPCState *env, int nr, target_ulong value) |
1729 | 3fc6c082 | bellard | { |
1730 | 3fc6c082 | bellard | target_ulong mask; |
1731 | 3fc6c082 | bellard | |
1732 | 3fc6c082 | bellard | dump_store_bat(env, 'D', 0, nr, value); |
1733 | 3fc6c082 | bellard | if (env->DBAT[0][nr] != value) { |
1734 | 3fc6c082 | bellard | /* When storing valid upper BAT, mask BEPI and BRPN
|
1735 | 3fc6c082 | bellard | * and invalidate all TLBs covered by this BAT
|
1736 | 3fc6c082 | bellard | */
|
1737 | 3fc6c082 | bellard | mask = (value << 15) & 0x0FFE0000UL; |
1738 | 3fc6c082 | bellard | #if !defined(FLUSH_ALL_TLBS)
|
1739 | 3fc6c082 | bellard | do_invalidate_BAT(env, env->DBAT[0][nr], mask);
|
1740 | 3fc6c082 | bellard | #endif
|
1741 | 3fc6c082 | bellard | mask = (value << 15) & 0x0FFE0000UL; |
1742 | 3fc6c082 | bellard | env->DBAT[0][nr] = (value & 0x00001FFFUL) | |
1743 | 3fc6c082 | bellard | (value & ~0x0001FFFFUL & ~mask);
|
1744 | 3fc6c082 | bellard | env->DBAT[1][nr] = (env->DBAT[1][nr] & 0x0000007B) | |
1745 | 3fc6c082 | bellard | (env->DBAT[1][nr] & ~0x0001FFFF & ~mask); |
1746 | 3fc6c082 | bellard | #if !defined(FLUSH_ALL_TLBS)
|
1747 | 3fc6c082 | bellard | do_invalidate_BAT(env, env->DBAT[0][nr], mask);
|
1748 | 3fc6c082 | bellard | #else
|
1749 | 3fc6c082 | bellard | tlb_flush(env, 1);
|
1750 | 3fc6c082 | bellard | #endif
|
1751 | 3fc6c082 | bellard | } |
1752 | 3fc6c082 | bellard | } |
1753 | 3fc6c082 | bellard | |
1754 | 45d827d2 | aurel32 | void ppc_store_dbatl (CPUPPCState *env, int nr, target_ulong value) |
1755 | 3fc6c082 | bellard | { |
1756 | 3fc6c082 | bellard | dump_store_bat(env, 'D', 1, nr, value); |
1757 | 3fc6c082 | bellard | env->DBAT[1][nr] = value;
|
1758 | 3fc6c082 | bellard | } |
1759 | 3fc6c082 | bellard | |
1760 | 45d827d2 | aurel32 | void ppc_store_ibatu_601 (CPUPPCState *env, int nr, target_ulong value) |
1761 | 056401ea | j_mayer | { |
1762 | 056401ea | j_mayer | target_ulong mask; |
1763 | 056401ea | j_mayer | int do_inval;
|
1764 | 056401ea | j_mayer | |
1765 | 056401ea | j_mayer | dump_store_bat(env, 'I', 0, nr, value); |
1766 | 056401ea | j_mayer | if (env->IBAT[0][nr] != value) { |
1767 | 056401ea | j_mayer | do_inval = 0;
|
1768 | 056401ea | j_mayer | mask = (env->IBAT[1][nr] << 17) & 0x0FFE0000UL; |
1769 | 056401ea | j_mayer | if (env->IBAT[1][nr] & 0x40) { |
1770 | 056401ea | j_mayer | /* Invalidate BAT only if it is valid */
|
1771 | 056401ea | j_mayer | #if !defined(FLUSH_ALL_TLBS)
|
1772 | 056401ea | j_mayer | do_invalidate_BAT(env, env->IBAT[0][nr], mask);
|
1773 | 056401ea | j_mayer | #else
|
1774 | 056401ea | j_mayer | do_inval = 1;
|
1775 | 056401ea | j_mayer | #endif
|
1776 | 056401ea | j_mayer | } |
1777 | 056401ea | j_mayer | /* When storing valid upper BAT, mask BEPI and BRPN
|
1778 | 056401ea | j_mayer | * and invalidate all TLBs covered by this BAT
|
1779 | 056401ea | j_mayer | */
|
1780 | 056401ea | j_mayer | env->IBAT[0][nr] = (value & 0x00001FFFUL) | |
1781 | 056401ea | j_mayer | (value & ~0x0001FFFFUL & ~mask);
|
1782 | 056401ea | j_mayer | env->DBAT[0][nr] = env->IBAT[0][nr]; |
1783 | 056401ea | j_mayer | if (env->IBAT[1][nr] & 0x40) { |
1784 | 056401ea | j_mayer | #if !defined(FLUSH_ALL_TLBS)
|
1785 | 056401ea | j_mayer | do_invalidate_BAT(env, env->IBAT[0][nr], mask);
|
1786 | 056401ea | j_mayer | #else
|
1787 | 056401ea | j_mayer | do_inval = 1;
|
1788 | 056401ea | j_mayer | #endif
|
1789 | 056401ea | j_mayer | } |
1790 | 056401ea | j_mayer | #if defined(FLUSH_ALL_TLBS)
|
1791 | 056401ea | j_mayer | if (do_inval)
|
1792 | 056401ea | j_mayer | tlb_flush(env, 1);
|
1793 | 056401ea | j_mayer | #endif
|
1794 | 056401ea | j_mayer | } |
1795 | 056401ea | j_mayer | } |
1796 | 056401ea | j_mayer | |
1797 | 45d827d2 | aurel32 | void ppc_store_ibatl_601 (CPUPPCState *env, int nr, target_ulong value) |
1798 | 056401ea | j_mayer | { |
1799 | 056401ea | j_mayer | target_ulong mask; |
1800 | 056401ea | j_mayer | int do_inval;
|
1801 | 056401ea | j_mayer | |
1802 | 056401ea | j_mayer | dump_store_bat(env, 'I', 1, nr, value); |
1803 | 056401ea | j_mayer | if (env->IBAT[1][nr] != value) { |
1804 | 056401ea | j_mayer | do_inval = 0;
|
1805 | 056401ea | j_mayer | if (env->IBAT[1][nr] & 0x40) { |
1806 | 056401ea | j_mayer | #if !defined(FLUSH_ALL_TLBS)
|
1807 | 056401ea | j_mayer | mask = (env->IBAT[1][nr] << 17) & 0x0FFE0000UL; |
1808 | 056401ea | j_mayer | do_invalidate_BAT(env, env->IBAT[0][nr], mask);
|
1809 | 056401ea | j_mayer | #else
|
1810 | 056401ea | j_mayer | do_inval = 1;
|
1811 | 056401ea | j_mayer | #endif
|
1812 | 056401ea | j_mayer | } |
1813 | 056401ea | j_mayer | if (value & 0x40) { |
1814 | 056401ea | j_mayer | #if !defined(FLUSH_ALL_TLBS)
|
1815 | 056401ea | j_mayer | mask = (value << 17) & 0x0FFE0000UL; |
1816 | 056401ea | j_mayer | do_invalidate_BAT(env, env->IBAT[0][nr], mask);
|
1817 | 056401ea | j_mayer | #else
|
1818 | 056401ea | j_mayer | do_inval = 1;
|
1819 | 056401ea | j_mayer | #endif
|
1820 | 056401ea | j_mayer | } |
1821 | 056401ea | j_mayer | env->IBAT[1][nr] = value;
|
1822 | 056401ea | j_mayer | env->DBAT[1][nr] = value;
|
1823 | 056401ea | j_mayer | #if defined(FLUSH_ALL_TLBS)
|
1824 | 056401ea | j_mayer | if (do_inval)
|
1825 | 056401ea | j_mayer | tlb_flush(env, 1);
|
1826 | 056401ea | j_mayer | #endif
|
1827 | 056401ea | j_mayer | } |
1828 | 056401ea | j_mayer | } |
1829 | 056401ea | j_mayer | |
1830 | 0a032cbe | j_mayer | /*****************************************************************************/
|
1831 | 0a032cbe | j_mayer | /* TLB management */
|
1832 | 0a032cbe | j_mayer | void ppc_tlb_invalidate_all (CPUPPCState *env)
|
1833 | 0a032cbe | j_mayer | { |
1834 | daf4f96e | j_mayer | switch (env->mmu_model) {
|
1835 | daf4f96e | j_mayer | case POWERPC_MMU_SOFT_6xx:
|
1836 | 7dbe11ac | j_mayer | case POWERPC_MMU_SOFT_74xx:
|
1837 | 0a032cbe | j_mayer | ppc6xx_tlb_invalidate_all(env); |
1838 | daf4f96e | j_mayer | break;
|
1839 | daf4f96e | j_mayer | case POWERPC_MMU_SOFT_4xx:
|
1840 | daf4f96e | j_mayer | case POWERPC_MMU_SOFT_4xx_Z:
|
1841 | 0a032cbe | j_mayer | ppc4xx_tlb_invalidate_all(env); |
1842 | daf4f96e | j_mayer | break;
|
1843 | b4095fed | j_mayer | case POWERPC_MMU_REAL:
|
1844 | 7dbe11ac | j_mayer | cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n");
|
1845 | 7dbe11ac | j_mayer | break;
|
1846 | b4095fed | j_mayer | case POWERPC_MMU_MPC8xx:
|
1847 | b4095fed | j_mayer | /* XXX: TODO */
|
1848 | b4095fed | j_mayer | cpu_abort(env, "MPC8xx MMU model is not implemented\n");
|
1849 | b4095fed | j_mayer | break;
|
1850 | 7dbe11ac | j_mayer | case POWERPC_MMU_BOOKE:
|
1851 | 7dbe11ac | j_mayer | /* XXX: TODO */
|
1852 | b4095fed | j_mayer | cpu_abort(env, "BookE MMU model is not implemented\n");
|
1853 | 7dbe11ac | j_mayer | break;
|
1854 | 7dbe11ac | j_mayer | case POWERPC_MMU_BOOKE_FSL:
|
1855 | 7dbe11ac | j_mayer | /* XXX: TODO */
|
1856 | da07cf59 | aliguori | if (!kvm_enabled())
|
1857 | da07cf59 | aliguori | cpu_abort(env, "BookE MMU model is not implemented\n");
|
1858 | 7dbe11ac | j_mayer | break;
|
1859 | 7dbe11ac | j_mayer | case POWERPC_MMU_32B:
|
1860 | faadf50e | j_mayer | case POWERPC_MMU_601:
|
1861 | 00af685f | j_mayer | #if defined(TARGET_PPC64)
|
1862 | add78955 | j_mayer | case POWERPC_MMU_620:
|
1863 | 7dbe11ac | j_mayer | case POWERPC_MMU_64B:
|
1864 | 00af685f | j_mayer | #endif /* defined(TARGET_PPC64) */ |
1865 | 0a032cbe | j_mayer | tlb_flush(env, 1);
|
1866 | daf4f96e | j_mayer | break;
|
1867 | 00af685f | j_mayer | default:
|
1868 | 00af685f | j_mayer | /* XXX: TODO */
|
1869 | 12de9a39 | j_mayer | cpu_abort(env, "Unknown MMU model\n");
|
1870 | 00af685f | j_mayer | break;
|
1871 | 0a032cbe | j_mayer | } |
1872 | 0a032cbe | j_mayer | } |
1873 | 0a032cbe | j_mayer | |
1874 | daf4f96e | j_mayer | void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr)
|
1875 | daf4f96e | j_mayer | { |
1876 | daf4f96e | j_mayer | #if !defined(FLUSH_ALL_TLBS)
|
1877 | daf4f96e | j_mayer | addr &= TARGET_PAGE_MASK; |
1878 | daf4f96e | j_mayer | switch (env->mmu_model) {
|
1879 | daf4f96e | j_mayer | case POWERPC_MMU_SOFT_6xx:
|
1880 | 7dbe11ac | j_mayer | case POWERPC_MMU_SOFT_74xx:
|
1881 | daf4f96e | j_mayer | ppc6xx_tlb_invalidate_virt(env, addr, 0);
|
1882 | daf4f96e | j_mayer | if (env->id_tlbs == 1) |
1883 | daf4f96e | j_mayer | ppc6xx_tlb_invalidate_virt(env, addr, 1);
|
1884 | daf4f96e | j_mayer | break;
|
1885 | daf4f96e | j_mayer | case POWERPC_MMU_SOFT_4xx:
|
1886 | daf4f96e | j_mayer | case POWERPC_MMU_SOFT_4xx_Z:
|
1887 | daf4f96e | j_mayer | ppc4xx_tlb_invalidate_virt(env, addr, env->spr[SPR_40x_PID]); |
1888 | daf4f96e | j_mayer | break;
|
1889 | b4095fed | j_mayer | case POWERPC_MMU_REAL:
|
1890 | 7dbe11ac | j_mayer | cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n");
|
1891 | 7dbe11ac | j_mayer | break;
|
1892 | b4095fed | j_mayer | case POWERPC_MMU_MPC8xx:
|
1893 | b4095fed | j_mayer | /* XXX: TODO */
|
1894 | b4095fed | j_mayer | cpu_abort(env, "MPC8xx MMU model is not implemented\n");
|
1895 | b4095fed | j_mayer | break;
|
1896 | 7dbe11ac | j_mayer | case POWERPC_MMU_BOOKE:
|
1897 | 7dbe11ac | j_mayer | /* XXX: TODO */
|
1898 | b4095fed | j_mayer | cpu_abort(env, "BookE MMU model is not implemented\n");
|
1899 | 7dbe11ac | j_mayer | break;
|
1900 | 7dbe11ac | j_mayer | case POWERPC_MMU_BOOKE_FSL:
|
1901 | 7dbe11ac | j_mayer | /* XXX: TODO */
|
1902 | b4095fed | j_mayer | cpu_abort(env, "BookE FSL MMU model is not implemented\n");
|
1903 | 7dbe11ac | j_mayer | break;
|
1904 | 7dbe11ac | j_mayer | case POWERPC_MMU_32B:
|
1905 | faadf50e | j_mayer | case POWERPC_MMU_601:
|
1906 | daf4f96e | j_mayer | /* tlbie invalidate TLBs for all segments */
|
1907 | 6f2d8978 | j_mayer | addr &= ~((target_ulong)-1ULL << 28); |
1908 | daf4f96e | j_mayer | /* XXX: this case should be optimized,
|
1909 | daf4f96e | j_mayer | * giving a mask to tlb_flush_page
|
1910 | daf4f96e | j_mayer | */
|
1911 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x0 << 28)); |
1912 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x1 << 28)); |
1913 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x2 << 28)); |
1914 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x3 << 28)); |
1915 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x4 << 28)); |
1916 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x5 << 28)); |
1917 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x6 << 28)); |
1918 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x7 << 28)); |
1919 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x8 << 28)); |
1920 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x9 << 28)); |
1921 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0xA << 28)); |
1922 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0xB << 28)); |
1923 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0xC << 28)); |
1924 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0xD << 28)); |
1925 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0xE << 28)); |
1926 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0xF << 28)); |
1927 | 7dbe11ac | j_mayer | break;
|
1928 | 00af685f | j_mayer | #if defined(TARGET_PPC64)
|
1929 | add78955 | j_mayer | case POWERPC_MMU_620:
|
1930 | 7dbe11ac | j_mayer | case POWERPC_MMU_64B:
|
1931 | 7dbe11ac | j_mayer | /* tlbie invalidate TLBs for all segments */
|
1932 | 7dbe11ac | j_mayer | /* XXX: given the fact that there are too many segments to invalidate,
|
1933 | 00af685f | j_mayer | * and we still don't have a tlb_flush_mask(env, n, mask) in Qemu,
|
1934 | 7dbe11ac | j_mayer | * we just invalidate all TLBs
|
1935 | 7dbe11ac | j_mayer | */
|
1936 | 7dbe11ac | j_mayer | tlb_flush(env, 1);
|
1937 | 7dbe11ac | j_mayer | break;
|
1938 | 00af685f | j_mayer | #endif /* defined(TARGET_PPC64) */ |
1939 | 00af685f | j_mayer | default:
|
1940 | 00af685f | j_mayer | /* XXX: TODO */
|
1941 | 12de9a39 | j_mayer | cpu_abort(env, "Unknown MMU model\n");
|
1942 | 00af685f | j_mayer | break;
|
1943 | daf4f96e | j_mayer | } |
1944 | daf4f96e | j_mayer | #else
|
1945 | daf4f96e | j_mayer | ppc_tlb_invalidate_all(env); |
1946 | daf4f96e | j_mayer | #endif
|
1947 | daf4f96e | j_mayer | } |
1948 | daf4f96e | j_mayer | |
1949 | 3fc6c082 | bellard | /*****************************************************************************/
|
1950 | 3fc6c082 | bellard | /* Special registers manipulation */
|
1951 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
1952 | d9bce9d9 | j_mayer | void ppc_store_asr (CPUPPCState *env, target_ulong value)
|
1953 | d9bce9d9 | j_mayer | { |
1954 | d9bce9d9 | j_mayer | if (env->asr != value) {
|
1955 | d9bce9d9 | j_mayer | env->asr = value; |
1956 | d9bce9d9 | j_mayer | tlb_flush(env, 1);
|
1957 | d9bce9d9 | j_mayer | } |
1958 | d9bce9d9 | j_mayer | } |
1959 | d9bce9d9 | j_mayer | #endif
|
1960 | d9bce9d9 | j_mayer | |
1961 | 45d827d2 | aurel32 | void ppc_store_sdr1 (CPUPPCState *env, target_ulong value)
|
1962 | 3fc6c082 | bellard | { |
1963 | d12d51d5 | aliguori | LOG_MMU("%s: " ADDRX "\n", __func__, value); |
1964 | 3fc6c082 | bellard | if (env->sdr1 != value) {
|
1965 | 12de9a39 | j_mayer | /* XXX: for PowerPC 64, should check that the HTABSIZE value
|
1966 | 12de9a39 | j_mayer | * is <= 28
|
1967 | 12de9a39 | j_mayer | */
|
1968 | 3fc6c082 | bellard | env->sdr1 = value; |
1969 | 76a66253 | j_mayer | tlb_flush(env, 1);
|
1970 | 3fc6c082 | bellard | } |
1971 | 3fc6c082 | bellard | } |
1972 | 3fc6c082 | bellard | |
1973 | f6b868fc | blueswir1 | #if defined(TARGET_PPC64)
|
1974 | f6b868fc | blueswir1 | target_ulong ppc_load_sr (CPUPPCState *env, int slb_nr)
|
1975 | f6b868fc | blueswir1 | { |
1976 | f6b868fc | blueswir1 | // XXX
|
1977 | f6b868fc | blueswir1 | return 0; |
1978 | f6b868fc | blueswir1 | } |
1979 | f6b868fc | blueswir1 | #endif
|
1980 | f6b868fc | blueswir1 | |
1981 | 45d827d2 | aurel32 | void ppc_store_sr (CPUPPCState *env, int srnum, target_ulong value) |
1982 | 3fc6c082 | bellard | { |
1983 | d12d51d5 | aliguori | LOG_MMU("%s: reg=%d " ADDRX " " ADDRX "\n", |
1984 | 1b9eb036 | j_mayer | __func__, srnum, value, env->sr[srnum]); |
1985 | f6b868fc | blueswir1 | #if defined(TARGET_PPC64)
|
1986 | f6b868fc | blueswir1 | if (env->mmu_model & POWERPC_MMU_64) {
|
1987 | f6b868fc | blueswir1 | uint64_t rb = 0, rs = 0; |
1988 | f6b868fc | blueswir1 | |
1989 | f6b868fc | blueswir1 | /* ESID = srnum */
|
1990 | f6b868fc | blueswir1 | rb |= ((uint32_t)srnum & 0xf) << 28; |
1991 | f6b868fc | blueswir1 | /* Set the valid bit */
|
1992 | f6b868fc | blueswir1 | rb |= 1 << 27; |
1993 | f6b868fc | blueswir1 | /* Index = ESID */
|
1994 | f6b868fc | blueswir1 | rb |= (uint32_t)srnum; |
1995 | f6b868fc | blueswir1 | |
1996 | f6b868fc | blueswir1 | /* VSID = VSID */
|
1997 | f6b868fc | blueswir1 | rs |= (value & 0xfffffff) << 12; |
1998 | f6b868fc | blueswir1 | /* flags = flags */
|
1999 | f6b868fc | blueswir1 | rs |= ((value >> 27) & 0xf) << 9; |
2000 | f6b868fc | blueswir1 | |
2001 | f6b868fc | blueswir1 | ppc_store_slb(env, rb, rs); |
2002 | f6b868fc | blueswir1 | } else
|
2003 | f6b868fc | blueswir1 | #endif
|
2004 | 3fc6c082 | bellard | if (env->sr[srnum] != value) {
|
2005 | 3fc6c082 | bellard | env->sr[srnum] = value; |
2006 | 3fc6c082 | bellard | #if !defined(FLUSH_ALL_TLBS) && 0 |
2007 | 3fc6c082 | bellard | { |
2008 | 3fc6c082 | bellard | target_ulong page, end; |
2009 | 3fc6c082 | bellard | /* Invalidate 256 MB of virtual memory */
|
2010 | 3fc6c082 | bellard | page = (16 << 20) * srnum; |
2011 | 3fc6c082 | bellard | end = page + (16 << 20); |
2012 | 3fc6c082 | bellard | for (; page != end; page += TARGET_PAGE_SIZE)
|
2013 | 3fc6c082 | bellard | tlb_flush_page(env, page); |
2014 | 3fc6c082 | bellard | } |
2015 | 3fc6c082 | bellard | #else
|
2016 | 76a66253 | j_mayer | tlb_flush(env, 1);
|
2017 | 3fc6c082 | bellard | #endif
|
2018 | 3fc6c082 | bellard | } |
2019 | 3fc6c082 | bellard | } |
2020 | 76a66253 | j_mayer | #endif /* !defined (CONFIG_USER_ONLY) */ |
2021 | 3fc6c082 | bellard | |
2022 | 76a66253 | j_mayer | /* GDBstub can read and write MSR... */
|
2023 | 0411a972 | j_mayer | void ppc_store_msr (CPUPPCState *env, target_ulong value)
|
2024 | 3fc6c082 | bellard | { |
2025 | a4f30719 | j_mayer | hreg_store_msr(env, value, 0);
|
2026 | 3fc6c082 | bellard | } |
2027 | 3fc6c082 | bellard | |
2028 | 3fc6c082 | bellard | /*****************************************************************************/
|
2029 | 3fc6c082 | bellard | /* Exception processing */
|
2030 | 18fba28c | bellard | #if defined (CONFIG_USER_ONLY)
|
2031 | 9a64fbe4 | bellard | void do_interrupt (CPUState *env)
|
2032 | 79aceca5 | bellard | { |
2033 | e1833e1f | j_mayer | env->exception_index = POWERPC_EXCP_NONE; |
2034 | e1833e1f | j_mayer | env->error_code = 0;
|
2035 | 18fba28c | bellard | } |
2036 | 47103572 | j_mayer | |
2037 | e9df014c | j_mayer | void ppc_hw_interrupt (CPUState *env)
|
2038 | 47103572 | j_mayer | { |
2039 | e1833e1f | j_mayer | env->exception_index = POWERPC_EXCP_NONE; |
2040 | e1833e1f | j_mayer | env->error_code = 0;
|
2041 | 47103572 | j_mayer | } |
2042 | 76a66253 | j_mayer | #else /* defined (CONFIG_USER_ONLY) */ |
2043 | a11b8151 | j_mayer | static always_inline void dump_syscall (CPUState *env) |
2044 | d094807b | bellard | { |
2045 | 93fcfe39 | aliguori | qemu_log_mask(CPU_LOG_INT, "syscall r0=" REGX " r3=" REGX " r4=" REGX |
2046 | 6b542af7 | j_mayer | " r5=" REGX " r6=" REGX " nip=" ADDRX "\n", |
2047 | 6b542af7 | j_mayer | ppc_dump_gpr(env, 0), ppc_dump_gpr(env, 3), ppc_dump_gpr(env, 4), |
2048 | 6b542af7 | j_mayer | ppc_dump_gpr(env, 5), ppc_dump_gpr(env, 6), env->nip); |
2049 | d094807b | bellard | } |
2050 | d094807b | bellard | |
2051 | e1833e1f | j_mayer | /* Note that this function should be greatly optimized
|
2052 | e1833e1f | j_mayer | * when called with a constant excp, from ppc_hw_interrupt
|
2053 | e1833e1f | j_mayer | */
|
2054 | e1833e1f | j_mayer | static always_inline void powerpc_excp (CPUState *env, |
2055 | e1833e1f | j_mayer | int excp_model, int excp) |
2056 | 18fba28c | bellard | { |
2057 | 0411a972 | j_mayer | target_ulong msr, new_msr, vector; |
2058 | e1833e1f | j_mayer | int srr0, srr1, asrr0, asrr1;
|
2059 | a4f30719 | j_mayer | int lpes0, lpes1, lev;
|
2060 | 79aceca5 | bellard | |
2061 | b172c56a | j_mayer | if (0) { |
2062 | b172c56a | j_mayer | /* XXX: find a suitable condition to enable the hypervisor mode */
|
2063 | b172c56a | j_mayer | lpes0 = (env->spr[SPR_LPCR] >> 1) & 1; |
2064 | b172c56a | j_mayer | lpes1 = (env->spr[SPR_LPCR] >> 2) & 1; |
2065 | b172c56a | j_mayer | } else {
|
2066 | b172c56a | j_mayer | /* Those values ensure we won't enter the hypervisor mode */
|
2067 | b172c56a | j_mayer | lpes0 = 0;
|
2068 | b172c56a | j_mayer | lpes1 = 1;
|
2069 | b172c56a | j_mayer | } |
2070 | b172c56a | j_mayer | |
2071 | 93fcfe39 | aliguori | qemu_log_mask(CPU_LOG_INT, "Raise exception at " ADDRX " => %08x (%02x)\n", |
2072 | 93fcfe39 | aliguori | env->nip, excp, env->error_code); |
2073 | 0411a972 | j_mayer | msr = env->msr; |
2074 | 0411a972 | j_mayer | new_msr = msr; |
2075 | e1833e1f | j_mayer | srr0 = SPR_SRR0; |
2076 | e1833e1f | j_mayer | srr1 = SPR_SRR1; |
2077 | e1833e1f | j_mayer | asrr0 = -1;
|
2078 | e1833e1f | j_mayer | asrr1 = -1;
|
2079 | e1833e1f | j_mayer | msr &= ~((target_ulong)0x783F0000);
|
2080 | 9a64fbe4 | bellard | switch (excp) {
|
2081 | e1833e1f | j_mayer | case POWERPC_EXCP_NONE:
|
2082 | e1833e1f | j_mayer | /* Should never happen */
|
2083 | e1833e1f | j_mayer | return;
|
2084 | e1833e1f | j_mayer | case POWERPC_EXCP_CRITICAL: /* Critical input */ |
2085 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
2086 | e1833e1f | j_mayer | switch (excp_model) {
|
2087 | a750fc0b | j_mayer | case POWERPC_EXCP_40x:
|
2088 | e1833e1f | j_mayer | srr0 = SPR_40x_SRR2; |
2089 | e1833e1f | j_mayer | srr1 = SPR_40x_SRR3; |
2090 | c62db105 | j_mayer | break;
|
2091 | a750fc0b | j_mayer | case POWERPC_EXCP_BOOKE:
|
2092 | e1833e1f | j_mayer | srr0 = SPR_BOOKE_CSRR0; |
2093 | e1833e1f | j_mayer | srr1 = SPR_BOOKE_CSRR1; |
2094 | c62db105 | j_mayer | break;
|
2095 | e1833e1f | j_mayer | case POWERPC_EXCP_G2:
|
2096 | c62db105 | j_mayer | break;
|
2097 | e1833e1f | j_mayer | default:
|
2098 | e1833e1f | j_mayer | goto excp_invalid;
|
2099 | 2be0071f | bellard | } |
2100 | 9a64fbe4 | bellard | goto store_next;
|
2101 | e1833e1f | j_mayer | case POWERPC_EXCP_MCHECK: /* Machine check exception */ |
2102 | e1833e1f | j_mayer | if (msr_me == 0) { |
2103 | e63ecc6f | j_mayer | /* Machine check exception is not enabled.
|
2104 | e63ecc6f | j_mayer | * Enter checkstop state.
|
2105 | e63ecc6f | j_mayer | */
|
2106 | 93fcfe39 | aliguori | if (qemu_log_enabled()) {
|
2107 | 93fcfe39 | aliguori | qemu_log("Machine check while not allowed. "
|
2108 | e63ecc6f | j_mayer | "Entering checkstop state\n");
|
2109 | e63ecc6f | j_mayer | } else {
|
2110 | e63ecc6f | j_mayer | fprintf(stderr, "Machine check while not allowed. "
|
2111 | e63ecc6f | j_mayer | "Entering checkstop state\n");
|
2112 | e63ecc6f | j_mayer | } |
2113 | e63ecc6f | j_mayer | env->halted = 1;
|
2114 | e63ecc6f | j_mayer | env->interrupt_request |= CPU_INTERRUPT_EXITTB; |
2115 | e1833e1f | j_mayer | } |
2116 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2117 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_ME);
|
2118 | b172c56a | j_mayer | if (0) { |
2119 | b172c56a | j_mayer | /* XXX: find a suitable condition to enable the hypervisor mode */
|
2120 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2121 | b172c56a | j_mayer | } |
2122 | e1833e1f | j_mayer | /* XXX: should also have something loaded in DAR / DSISR */
|
2123 | e1833e1f | j_mayer | switch (excp_model) {
|
2124 | a750fc0b | j_mayer | case POWERPC_EXCP_40x:
|
2125 | e1833e1f | j_mayer | srr0 = SPR_40x_SRR2; |
2126 | e1833e1f | j_mayer | srr1 = SPR_40x_SRR3; |
2127 | c62db105 | j_mayer | break;
|
2128 | a750fc0b | j_mayer | case POWERPC_EXCP_BOOKE:
|
2129 | e1833e1f | j_mayer | srr0 = SPR_BOOKE_MCSRR0; |
2130 | e1833e1f | j_mayer | srr1 = SPR_BOOKE_MCSRR1; |
2131 | e1833e1f | j_mayer | asrr0 = SPR_BOOKE_CSRR0; |
2132 | e1833e1f | j_mayer | asrr1 = SPR_BOOKE_CSRR1; |
2133 | c62db105 | j_mayer | break;
|
2134 | c62db105 | j_mayer | default:
|
2135 | c62db105 | j_mayer | break;
|
2136 | 2be0071f | bellard | } |
2137 | e1833e1f | j_mayer | goto store_next;
|
2138 | e1833e1f | j_mayer | case POWERPC_EXCP_DSI: /* Data storage exception */ |
2139 | d12d51d5 | aliguori | LOG_EXCP("DSI exception: DSISR=" ADDRX" DAR=" ADDRX "\n", |
2140 | 6b542af7 | j_mayer | env->spr[SPR_DSISR], env->spr[SPR_DAR]); |
2141 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2142 | e1833e1f | j_mayer | if (lpes1 == 0) |
2143 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2144 | a541f297 | bellard | goto store_next;
|
2145 | e1833e1f | j_mayer | case POWERPC_EXCP_ISI: /* Instruction storage exception */ |
2146 | d12d51d5 | aliguori | LOG_EXCP("ISI exception: msr=" ADDRX ", nip=" ADDRX "\n", |
2147 | 6b542af7 | j_mayer | msr, env->nip); |
2148 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2149 | e1833e1f | j_mayer | if (lpes1 == 0) |
2150 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2151 | e1833e1f | j_mayer | msr |= env->error_code; |
2152 | 9a64fbe4 | bellard | goto store_next;
|
2153 | e1833e1f | j_mayer | case POWERPC_EXCP_EXTERNAL: /* External input */ |
2154 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2155 | e1833e1f | j_mayer | if (lpes0 == 1) |
2156 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2157 | 9a64fbe4 | bellard | goto store_next;
|
2158 | e1833e1f | j_mayer | case POWERPC_EXCP_ALIGN: /* Alignment exception */ |
2159 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2160 | e1833e1f | j_mayer | if (lpes1 == 0) |
2161 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2162 | e1833e1f | j_mayer | /* XXX: this is false */
|
2163 | e1833e1f | j_mayer | /* Get rS/rD and rA from faulting opcode */
|
2164 | e1833e1f | j_mayer | env->spr[SPR_DSISR] |= (ldl_code((env->nip - 4)) & 0x03FF0000) >> 16; |
2165 | 9a64fbe4 | bellard | goto store_current;
|
2166 | e1833e1f | j_mayer | case POWERPC_EXCP_PROGRAM: /* Program exception */ |
2167 | 9a64fbe4 | bellard | switch (env->error_code & ~0xF) { |
2168 | e1833e1f | j_mayer | case POWERPC_EXCP_FP:
|
2169 | e1833e1f | j_mayer | if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) { |
2170 | d12d51d5 | aliguori | LOG_EXCP("Ignore floating point exception\n");
|
2171 | 7c58044c | j_mayer | env->exception_index = POWERPC_EXCP_NONE; |
2172 | 7c58044c | j_mayer | env->error_code = 0;
|
2173 | 9a64fbe4 | bellard | return;
|
2174 | 76a66253 | j_mayer | } |
2175 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2176 | e1833e1f | j_mayer | if (lpes1 == 0) |
2177 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2178 | 9a64fbe4 | bellard | msr |= 0x00100000;
|
2179 | 5b52b991 | j_mayer | if (msr_fe0 == msr_fe1)
|
2180 | 5b52b991 | j_mayer | goto store_next;
|
2181 | 5b52b991 | j_mayer | msr |= 0x00010000;
|
2182 | 76a66253 | j_mayer | break;
|
2183 | e1833e1f | j_mayer | case POWERPC_EXCP_INVAL:
|
2184 | d12d51d5 | aliguori | LOG_EXCP("Invalid instruction at " ADDRX "\n", |
2185 | a496775f | j_mayer | env->nip); |
2186 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2187 | e1833e1f | j_mayer | if (lpes1 == 0) |
2188 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2189 | 9a64fbe4 | bellard | msr |= 0x00080000;
|
2190 | 76a66253 | j_mayer | break;
|
2191 | e1833e1f | j_mayer | case POWERPC_EXCP_PRIV:
|
2192 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2193 | e1833e1f | j_mayer | if (lpes1 == 0) |
2194 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2195 | 9a64fbe4 | bellard | msr |= 0x00040000;
|
2196 | 76a66253 | j_mayer | break;
|
2197 | e1833e1f | j_mayer | case POWERPC_EXCP_TRAP:
|
2198 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2199 | e1833e1f | j_mayer | if (lpes1 == 0) |
2200 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2201 | 9a64fbe4 | bellard | msr |= 0x00020000;
|
2202 | 9a64fbe4 | bellard | break;
|
2203 | 9a64fbe4 | bellard | default:
|
2204 | 9a64fbe4 | bellard | /* Should never occur */
|
2205 | e1833e1f | j_mayer | cpu_abort(env, "Invalid program exception %d. Aborting\n",
|
2206 | e1833e1f | j_mayer | env->error_code); |
2207 | 76a66253 | j_mayer | break;
|
2208 | 76a66253 | j_mayer | } |
2209 | 5b52b991 | j_mayer | goto store_current;
|
2210 | e1833e1f | j_mayer | case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */ |
2211 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2212 | e1833e1f | j_mayer | if (lpes1 == 0) |
2213 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2214 | e1833e1f | j_mayer | goto store_current;
|
2215 | e1833e1f | j_mayer | case POWERPC_EXCP_SYSCALL: /* System call exception */ |
2216 | d094807b | bellard | /* NOTE: this is a temporary hack to support graphics OSI
|
2217 | d094807b | bellard | calls from the MOL driver */
|
2218 | e1833e1f | j_mayer | /* XXX: To be removed */
|
2219 | d094807b | bellard | if (env->gpr[3] == 0x113724fa && env->gpr[4] == 0x77810f9b && |
2220 | d094807b | bellard | env->osi_call) { |
2221 | 7c58044c | j_mayer | if (env->osi_call(env) != 0) { |
2222 | 7c58044c | j_mayer | env->exception_index = POWERPC_EXCP_NONE; |
2223 | 7c58044c | j_mayer | env->error_code = 0;
|
2224 | d094807b | bellard | return;
|
2225 | 7c58044c | j_mayer | } |
2226 | d094807b | bellard | } |
2227 | 93fcfe39 | aliguori | dump_syscall(env); |
2228 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2229 | f9fdea6b | j_mayer | lev = env->error_code; |
2230 | e1833e1f | j_mayer | if (lev == 1 || (lpes0 == 0 && lpes1 == 0)) |
2231 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2232 | e1833e1f | j_mayer | goto store_next;
|
2233 | e1833e1f | j_mayer | case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */ |
2234 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2235 | e1833e1f | j_mayer | goto store_current;
|
2236 | e1833e1f | j_mayer | case POWERPC_EXCP_DECR: /* Decrementer exception */ |
2237 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2238 | e1833e1f | j_mayer | if (lpes1 == 0) |
2239 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2240 | e1833e1f | j_mayer | goto store_next;
|
2241 | e1833e1f | j_mayer | case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */ |
2242 | e1833e1f | j_mayer | /* FIT on 4xx */
|
2243 | d12d51d5 | aliguori | LOG_EXCP("FIT exception\n");
|
2244 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
2245 | 9a64fbe4 | bellard | goto store_next;
|
2246 | e1833e1f | j_mayer | case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */ |
2247 | d12d51d5 | aliguori | LOG_EXCP("WDT exception\n");
|
2248 | e1833e1f | j_mayer | switch (excp_model) {
|
2249 | e1833e1f | j_mayer | case POWERPC_EXCP_BOOKE:
|
2250 | e1833e1f | j_mayer | srr0 = SPR_BOOKE_CSRR0; |
2251 | e1833e1f | j_mayer | srr1 = SPR_BOOKE_CSRR1; |
2252 | e1833e1f | j_mayer | break;
|
2253 | e1833e1f | j_mayer | default:
|
2254 | e1833e1f | j_mayer | break;
|
2255 | e1833e1f | j_mayer | } |
2256 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
2257 | 2be0071f | bellard | goto store_next;
|
2258 | e1833e1f | j_mayer | case POWERPC_EXCP_DTLB: /* Data TLB error */ |
2259 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
2260 | e1833e1f | j_mayer | goto store_next;
|
2261 | e1833e1f | j_mayer | case POWERPC_EXCP_ITLB: /* Instruction TLB error */ |
2262 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
2263 | e1833e1f | j_mayer | goto store_next;
|
2264 | e1833e1f | j_mayer | case POWERPC_EXCP_DEBUG: /* Debug interrupt */ |
2265 | e1833e1f | j_mayer | switch (excp_model) {
|
2266 | e1833e1f | j_mayer | case POWERPC_EXCP_BOOKE:
|
2267 | e1833e1f | j_mayer | srr0 = SPR_BOOKE_DSRR0; |
2268 | e1833e1f | j_mayer | srr1 = SPR_BOOKE_DSRR1; |
2269 | e1833e1f | j_mayer | asrr0 = SPR_BOOKE_CSRR0; |
2270 | e1833e1f | j_mayer | asrr1 = SPR_BOOKE_CSRR1; |
2271 | e1833e1f | j_mayer | break;
|
2272 | e1833e1f | j_mayer | default:
|
2273 | e1833e1f | j_mayer | break;
|
2274 | e1833e1f | j_mayer | } |
2275 | 2be0071f | bellard | /* XXX: TODO */
|
2276 | e1833e1f | j_mayer | cpu_abort(env, "Debug exception is not implemented yet !\n");
|
2277 | 2be0071f | bellard | goto store_next;
|
2278 | e1833e1f | j_mayer | case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable */ |
2279 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
2280 | e1833e1f | j_mayer | goto store_current;
|
2281 | e1833e1f | j_mayer | case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */ |
2282 | 2be0071f | bellard | /* XXX: TODO */
|
2283 | e1833e1f | j_mayer | cpu_abort(env, "Embedded floating point data exception "
|
2284 | 2be0071f | bellard | "is not implemented yet !\n");
|
2285 | 2be0071f | bellard | goto store_next;
|
2286 | e1833e1f | j_mayer | case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */ |
2287 | 2be0071f | bellard | /* XXX: TODO */
|
2288 | e1833e1f | j_mayer | cpu_abort(env, "Embedded floating point round exception "
|
2289 | e1833e1f | j_mayer | "is not implemented yet !\n");
|
2290 | 9a64fbe4 | bellard | goto store_next;
|
2291 | e1833e1f | j_mayer | case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */ |
2292 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2293 | 2be0071f | bellard | /* XXX: TODO */
|
2294 | 2be0071f | bellard | cpu_abort(env, |
2295 | e1833e1f | j_mayer | "Performance counter exception is not implemented yet !\n");
|
2296 | 9a64fbe4 | bellard | goto store_next;
|
2297 | e1833e1f | j_mayer | case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */ |
2298 | 76a66253 | j_mayer | /* XXX: TODO */
|
2299 | e1833e1f | j_mayer | cpu_abort(env, |
2300 | e1833e1f | j_mayer | "Embedded doorbell interrupt is not implemented yet !\n");
|
2301 | 2be0071f | bellard | goto store_next;
|
2302 | e1833e1f | j_mayer | case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */ |
2303 | e1833e1f | j_mayer | switch (excp_model) {
|
2304 | e1833e1f | j_mayer | case POWERPC_EXCP_BOOKE:
|
2305 | e1833e1f | j_mayer | srr0 = SPR_BOOKE_CSRR0; |
2306 | e1833e1f | j_mayer | srr1 = SPR_BOOKE_CSRR1; |
2307 | a750fc0b | j_mayer | break;
|
2308 | 2be0071f | bellard | default:
|
2309 | 2be0071f | bellard | break;
|
2310 | 2be0071f | bellard | } |
2311 | e1833e1f | j_mayer | /* XXX: TODO */
|
2312 | e1833e1f | j_mayer | cpu_abort(env, "Embedded doorbell critical interrupt "
|
2313 | e1833e1f | j_mayer | "is not implemented yet !\n");
|
2314 | e1833e1f | j_mayer | goto store_next;
|
2315 | e1833e1f | j_mayer | case POWERPC_EXCP_RESET: /* System reset exception */ |
2316 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2317 | a4f30719 | j_mayer | if (0) { |
2318 | a4f30719 | j_mayer | /* XXX: find a suitable condition to enable the hypervisor mode */
|
2319 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2320 | a4f30719 | j_mayer | } |
2321 | e1833e1f | j_mayer | goto store_next;
|
2322 | e1833e1f | j_mayer | case POWERPC_EXCP_DSEG: /* Data segment exception */ |
2323 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2324 | e1833e1f | j_mayer | if (lpes1 == 0) |
2325 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2326 | e1833e1f | j_mayer | goto store_next;
|
2327 | e1833e1f | j_mayer | case POWERPC_EXCP_ISEG: /* Instruction segment exception */ |
2328 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2329 | e1833e1f | j_mayer | if (lpes1 == 0) |
2330 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2331 | e1833e1f | j_mayer | goto store_next;
|
2332 | e1833e1f | j_mayer | case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */ |
2333 | e1833e1f | j_mayer | srr0 = SPR_HSRR0; |
2334 | f9fdea6b | j_mayer | srr1 = SPR_HSRR1; |
2335 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2336 | b172c56a | j_mayer | goto store_next;
|
2337 | e1833e1f | j_mayer | case POWERPC_EXCP_TRACE: /* Trace exception */ |
2338 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2339 | e1833e1f | j_mayer | if (lpes1 == 0) |
2340 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2341 | e1833e1f | j_mayer | goto store_next;
|
2342 | e1833e1f | j_mayer | case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */ |
2343 | e1833e1f | j_mayer | srr0 = SPR_HSRR0; |
2344 | f9fdea6b | j_mayer | srr1 = SPR_HSRR1; |
2345 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2346 | e1833e1f | j_mayer | goto store_next;
|
2347 | e1833e1f | j_mayer | case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */ |
2348 | e1833e1f | j_mayer | srr0 = SPR_HSRR0; |
2349 | f9fdea6b | j_mayer | srr1 = SPR_HSRR1; |
2350 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2351 | e1833e1f | j_mayer | goto store_next;
|
2352 | e1833e1f | j_mayer | case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */ |
2353 | e1833e1f | j_mayer | srr0 = SPR_HSRR0; |
2354 | f9fdea6b | j_mayer | srr1 = SPR_HSRR1; |
2355 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2356 | e1833e1f | j_mayer | goto store_next;
|
2357 | e1833e1f | j_mayer | case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */ |
2358 | e1833e1f | j_mayer | srr0 = SPR_HSRR0; |
2359 | f9fdea6b | j_mayer | srr1 = SPR_HSRR1; |
2360 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2361 | e1833e1f | j_mayer | goto store_next;
|
2362 | e1833e1f | j_mayer | case POWERPC_EXCP_VPU: /* Vector unavailable exception */ |
2363 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2364 | e1833e1f | j_mayer | if (lpes1 == 0) |
2365 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2366 | e1833e1f | j_mayer | goto store_current;
|
2367 | e1833e1f | j_mayer | case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */ |
2368 | d12d51d5 | aliguori | LOG_EXCP("PIT exception\n");
|
2369 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
2370 | e1833e1f | j_mayer | goto store_next;
|
2371 | e1833e1f | j_mayer | case POWERPC_EXCP_IO: /* IO error exception */ |
2372 | e1833e1f | j_mayer | /* XXX: TODO */
|
2373 | e1833e1f | j_mayer | cpu_abort(env, "601 IO error exception is not implemented yet !\n");
|
2374 | e1833e1f | j_mayer | goto store_next;
|
2375 | e1833e1f | j_mayer | case POWERPC_EXCP_RUNM: /* Run mode exception */ |
2376 | e1833e1f | j_mayer | /* XXX: TODO */
|
2377 | e1833e1f | j_mayer | cpu_abort(env, "601 run mode exception is not implemented yet !\n");
|
2378 | e1833e1f | j_mayer | goto store_next;
|
2379 | e1833e1f | j_mayer | case POWERPC_EXCP_EMUL: /* Emulation trap exception */ |
2380 | e1833e1f | j_mayer | /* XXX: TODO */
|
2381 | e1833e1f | j_mayer | cpu_abort(env, "602 emulation trap exception "
|
2382 | e1833e1f | j_mayer | "is not implemented yet !\n");
|
2383 | e1833e1f | j_mayer | goto store_next;
|
2384 | e1833e1f | j_mayer | case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */ |
2385 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
2386 | a4f30719 | j_mayer | if (lpes1 == 0) /* XXX: check this */ |
2387 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2388 | e1833e1f | j_mayer | switch (excp_model) {
|
2389 | a750fc0b | j_mayer | case POWERPC_EXCP_602:
|
2390 | a750fc0b | j_mayer | case POWERPC_EXCP_603:
|
2391 | a750fc0b | j_mayer | case POWERPC_EXCP_603E:
|
2392 | a750fc0b | j_mayer | case POWERPC_EXCP_G2:
|
2393 | e1833e1f | j_mayer | goto tlb_miss_tgpr;
|
2394 | a750fc0b | j_mayer | case POWERPC_EXCP_7x5:
|
2395 | 76a66253 | j_mayer | goto tlb_miss;
|
2396 | 7dbe11ac | j_mayer | case POWERPC_EXCP_74xx:
|
2397 | 7dbe11ac | j_mayer | goto tlb_miss_74xx;
|
2398 | 2be0071f | bellard | default:
|
2399 | e1833e1f | j_mayer | cpu_abort(env, "Invalid instruction TLB miss exception\n");
|
2400 | 2be0071f | bellard | break;
|
2401 | 2be0071f | bellard | } |
2402 | e1833e1f | j_mayer | break;
|
2403 | e1833e1f | j_mayer | case POWERPC_EXCP_DLTLB: /* Data load TLB miss */ |
2404 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
2405 | a4f30719 | j_mayer | if (lpes1 == 0) /* XXX: check this */ |
2406 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2407 | e1833e1f | j_mayer | switch (excp_model) {
|
2408 | a750fc0b | j_mayer | case POWERPC_EXCP_602:
|
2409 | a750fc0b | j_mayer | case POWERPC_EXCP_603:
|
2410 | a750fc0b | j_mayer | case POWERPC_EXCP_603E:
|
2411 | a750fc0b | j_mayer | case POWERPC_EXCP_G2:
|
2412 | e1833e1f | j_mayer | goto tlb_miss_tgpr;
|
2413 | a750fc0b | j_mayer | case POWERPC_EXCP_7x5:
|
2414 | 76a66253 | j_mayer | goto tlb_miss;
|
2415 | 7dbe11ac | j_mayer | case POWERPC_EXCP_74xx:
|
2416 | 7dbe11ac | j_mayer | goto tlb_miss_74xx;
|
2417 | 2be0071f | bellard | default:
|
2418 | e1833e1f | j_mayer | cpu_abort(env, "Invalid data load TLB miss exception\n");
|
2419 | 2be0071f | bellard | break;
|
2420 | 2be0071f | bellard | } |
2421 | e1833e1f | j_mayer | break;
|
2422 | e1833e1f | j_mayer | case POWERPC_EXCP_DSTLB: /* Data store TLB miss */ |
2423 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
2424 | a4f30719 | j_mayer | if (lpes1 == 0) /* XXX: check this */ |
2425 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2426 | e1833e1f | j_mayer | switch (excp_model) {
|
2427 | a750fc0b | j_mayer | case POWERPC_EXCP_602:
|
2428 | a750fc0b | j_mayer | case POWERPC_EXCP_603:
|
2429 | a750fc0b | j_mayer | case POWERPC_EXCP_603E:
|
2430 | a750fc0b | j_mayer | case POWERPC_EXCP_G2:
|
2431 | e1833e1f | j_mayer | tlb_miss_tgpr:
|
2432 | 76a66253 | j_mayer | /* Swap temporary saved registers with GPRs */
|
2433 | 0411a972 | j_mayer | if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) { |
2434 | 0411a972 | j_mayer | new_msr |= (target_ulong)1 << MSR_TGPR;
|
2435 | 0411a972 | j_mayer | hreg_swap_gpr_tgpr(env); |
2436 | 0411a972 | j_mayer | } |
2437 | e1833e1f | j_mayer | goto tlb_miss;
|
2438 | e1833e1f | j_mayer | case POWERPC_EXCP_7x5:
|
2439 | e1833e1f | j_mayer | tlb_miss:
|
2440 | 2be0071f | bellard | #if defined (DEBUG_SOFTWARE_TLB)
|
2441 | 93fcfe39 | aliguori | if (qemu_log_enabled()) {
|
2442 | 76a66253 | j_mayer | const unsigned char *es; |
2443 | 76a66253 | j_mayer | target_ulong *miss, *cmp; |
2444 | 76a66253 | j_mayer | int en;
|
2445 | 1e6784f9 | j_mayer | if (excp == POWERPC_EXCP_IFTLB) {
|
2446 | 76a66253 | j_mayer | es = "I";
|
2447 | 76a66253 | j_mayer | en = 'I';
|
2448 | 76a66253 | j_mayer | miss = &env->spr[SPR_IMISS]; |
2449 | 76a66253 | j_mayer | cmp = &env->spr[SPR_ICMP]; |
2450 | 76a66253 | j_mayer | } else {
|
2451 | 1e6784f9 | j_mayer | if (excp == POWERPC_EXCP_DLTLB)
|
2452 | 76a66253 | j_mayer | es = "DL";
|
2453 | 76a66253 | j_mayer | else
|
2454 | 76a66253 | j_mayer | es = "DS";
|
2455 | 76a66253 | j_mayer | en = 'D';
|
2456 | 76a66253 | j_mayer | miss = &env->spr[SPR_DMISS]; |
2457 | 76a66253 | j_mayer | cmp = &env->spr[SPR_DCMP]; |
2458 | 76a66253 | j_mayer | } |
2459 | 93fcfe39 | aliguori | qemu_log("6xx %sTLB miss: %cM " ADDRX " %cC " ADDRX |
2460 | 4a057712 | j_mayer | " H1 " ADDRX " H2 " ADDRX " %08x\n", |
2461 | 1b9eb036 | j_mayer | es, en, *miss, en, *cmp, |
2462 | 76a66253 | j_mayer | env->spr[SPR_HASH1], env->spr[SPR_HASH2], |
2463 | 2be0071f | bellard | env->error_code); |
2464 | 2be0071f | bellard | } |
2465 | 9a64fbe4 | bellard | #endif
|
2466 | 2be0071f | bellard | msr |= env->crf[0] << 28; |
2467 | 2be0071f | bellard | msr |= env->error_code; /* key, D/I, S/L bits */
|
2468 | 2be0071f | bellard | /* Set way using a LRU mechanism */
|
2469 | 76a66253 | j_mayer | msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17; |
2470 | c62db105 | j_mayer | break;
|
2471 | 7dbe11ac | j_mayer | case POWERPC_EXCP_74xx:
|
2472 | 7dbe11ac | j_mayer | tlb_miss_74xx:
|
2473 | 7dbe11ac | j_mayer | #if defined (DEBUG_SOFTWARE_TLB)
|
2474 | 93fcfe39 | aliguori | if (qemu_log_enabled()) {
|
2475 | 7dbe11ac | j_mayer | const unsigned char *es; |
2476 | 7dbe11ac | j_mayer | target_ulong *miss, *cmp; |
2477 | 7dbe11ac | j_mayer | int en;
|
2478 | 7dbe11ac | j_mayer | if (excp == POWERPC_EXCP_IFTLB) {
|
2479 | 7dbe11ac | j_mayer | es = "I";
|
2480 | 7dbe11ac | j_mayer | en = 'I';
|
2481 | 0411a972 | j_mayer | miss = &env->spr[SPR_TLBMISS]; |
2482 | 0411a972 | j_mayer | cmp = &env->spr[SPR_PTEHI]; |
2483 | 7dbe11ac | j_mayer | } else {
|
2484 | 7dbe11ac | j_mayer | if (excp == POWERPC_EXCP_DLTLB)
|
2485 | 7dbe11ac | j_mayer | es = "DL";
|
2486 | 7dbe11ac | j_mayer | else
|
2487 | 7dbe11ac | j_mayer | es = "DS";
|
2488 | 7dbe11ac | j_mayer | en = 'D';
|
2489 | 7dbe11ac | j_mayer | miss = &env->spr[SPR_TLBMISS]; |
2490 | 7dbe11ac | j_mayer | cmp = &env->spr[SPR_PTEHI]; |
2491 | 7dbe11ac | j_mayer | } |
2492 | 93fcfe39 | aliguori | qemu_log("74xx %sTLB miss: %cM " ADDRX " %cC " ADDRX |
2493 | 7dbe11ac | j_mayer | " %08x\n",
|
2494 | 7dbe11ac | j_mayer | es, en, *miss, en, *cmp, env->error_code); |
2495 | 7dbe11ac | j_mayer | } |
2496 | 7dbe11ac | j_mayer | #endif
|
2497 | 7dbe11ac | j_mayer | msr |= env->error_code; /* key bit */
|
2498 | 7dbe11ac | j_mayer | break;
|
2499 | 2be0071f | bellard | default:
|
2500 | e1833e1f | j_mayer | cpu_abort(env, "Invalid data store TLB miss exception\n");
|
2501 | 2be0071f | bellard | break;
|
2502 | 2be0071f | bellard | } |
2503 | e1833e1f | j_mayer | goto store_next;
|
2504 | e1833e1f | j_mayer | case POWERPC_EXCP_FPA: /* Floating-point assist exception */ |
2505 | e1833e1f | j_mayer | /* XXX: TODO */
|
2506 | e1833e1f | j_mayer | cpu_abort(env, "Floating point assist exception "
|
2507 | e1833e1f | j_mayer | "is not implemented yet !\n");
|
2508 | e1833e1f | j_mayer | goto store_next;
|
2509 | b4095fed | j_mayer | case POWERPC_EXCP_DABR: /* Data address breakpoint */ |
2510 | b4095fed | j_mayer | /* XXX: TODO */
|
2511 | b4095fed | j_mayer | cpu_abort(env, "DABR exception is not implemented yet !\n");
|
2512 | b4095fed | j_mayer | goto store_next;
|
2513 | e1833e1f | j_mayer | case POWERPC_EXCP_IABR: /* Instruction address breakpoint */ |
2514 | e1833e1f | j_mayer | /* XXX: TODO */
|
2515 | e1833e1f | j_mayer | cpu_abort(env, "IABR exception is not implemented yet !\n");
|
2516 | e1833e1f | j_mayer | goto store_next;
|
2517 | e1833e1f | j_mayer | case POWERPC_EXCP_SMI: /* System management interrupt */ |
2518 | e1833e1f | j_mayer | /* XXX: TODO */
|
2519 | e1833e1f | j_mayer | cpu_abort(env, "SMI exception is not implemented yet !\n");
|
2520 | e1833e1f | j_mayer | goto store_next;
|
2521 | e1833e1f | j_mayer | case POWERPC_EXCP_THERM: /* Thermal interrupt */ |
2522 | e1833e1f | j_mayer | /* XXX: TODO */
|
2523 | e1833e1f | j_mayer | cpu_abort(env, "Thermal management exception "
|
2524 | e1833e1f | j_mayer | "is not implemented yet !\n");
|
2525 | e1833e1f | j_mayer | goto store_next;
|
2526 | e1833e1f | j_mayer | case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */ |
2527 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2528 | e1833e1f | j_mayer | if (lpes1 == 0) |
2529 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2530 | e1833e1f | j_mayer | /* XXX: TODO */
|
2531 | e1833e1f | j_mayer | cpu_abort(env, |
2532 | e1833e1f | j_mayer | "Performance counter exception is not implemented yet !\n");
|
2533 | e1833e1f | j_mayer | goto store_next;
|
2534 | e1833e1f | j_mayer | case POWERPC_EXCP_VPUA: /* Vector assist exception */ |
2535 | e1833e1f | j_mayer | /* XXX: TODO */
|
2536 | e1833e1f | j_mayer | cpu_abort(env, "VPU assist exception is not implemented yet !\n");
|
2537 | e1833e1f | j_mayer | goto store_next;
|
2538 | e1833e1f | j_mayer | case POWERPC_EXCP_SOFTP: /* Soft patch exception */ |
2539 | e1833e1f | j_mayer | /* XXX: TODO */
|
2540 | e1833e1f | j_mayer | cpu_abort(env, |
2541 | e1833e1f | j_mayer | "970 soft-patch exception is not implemented yet !\n");
|
2542 | e1833e1f | j_mayer | goto store_next;
|
2543 | e1833e1f | j_mayer | case POWERPC_EXCP_MAINT: /* Maintenance exception */ |
2544 | e1833e1f | j_mayer | /* XXX: TODO */
|
2545 | e1833e1f | j_mayer | cpu_abort(env, |
2546 | e1833e1f | j_mayer | "970 maintenance exception is not implemented yet !\n");
|
2547 | e1833e1f | j_mayer | goto store_next;
|
2548 | b4095fed | j_mayer | case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint */ |
2549 | b4095fed | j_mayer | /* XXX: TODO */
|
2550 | b4095fed | j_mayer | cpu_abort(env, "Maskable external exception "
|
2551 | b4095fed | j_mayer | "is not implemented yet !\n");
|
2552 | b4095fed | j_mayer | goto store_next;
|
2553 | b4095fed | j_mayer | case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint */ |
2554 | b4095fed | j_mayer | /* XXX: TODO */
|
2555 | b4095fed | j_mayer | cpu_abort(env, "Non maskable external exception "
|
2556 | b4095fed | j_mayer | "is not implemented yet !\n");
|
2557 | b4095fed | j_mayer | goto store_next;
|
2558 | 2be0071f | bellard | default:
|
2559 | e1833e1f | j_mayer | excp_invalid:
|
2560 | e1833e1f | j_mayer | cpu_abort(env, "Invalid PowerPC exception %d. Aborting\n", excp);
|
2561 | e1833e1f | j_mayer | break;
|
2562 | 9a64fbe4 | bellard | store_current:
|
2563 | 2be0071f | bellard | /* save current instruction location */
|
2564 | e1833e1f | j_mayer | env->spr[srr0] = env->nip - 4;
|
2565 | 9a64fbe4 | bellard | break;
|
2566 | 9a64fbe4 | bellard | store_next:
|
2567 | 2be0071f | bellard | /* save next instruction location */
|
2568 | e1833e1f | j_mayer | env->spr[srr0] = env->nip; |
2569 | 9a64fbe4 | bellard | break;
|
2570 | 9a64fbe4 | bellard | } |
2571 | e1833e1f | j_mayer | /* Save MSR */
|
2572 | e1833e1f | j_mayer | env->spr[srr1] = msr; |
2573 | e1833e1f | j_mayer | /* If any alternate SRR register are defined, duplicate saved values */
|
2574 | e1833e1f | j_mayer | if (asrr0 != -1) |
2575 | e1833e1f | j_mayer | env->spr[asrr0] = env->spr[srr0]; |
2576 | e1833e1f | j_mayer | if (asrr1 != -1) |
2577 | e1833e1f | j_mayer | env->spr[asrr1] = env->spr[srr1]; |
2578 | 2be0071f | bellard | /* If we disactivated any translation, flush TLBs */
|
2579 | 0411a972 | j_mayer | if (new_msr & ((1 << MSR_IR) | (1 << MSR_DR))) |
2580 | 2be0071f | bellard | tlb_flush(env, 1);
|
2581 | 9a64fbe4 | bellard | /* reload MSR with correct bits */
|
2582 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_EE);
|
2583 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_PR);
|
2584 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_FP);
|
2585 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_FE0);
|
2586 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_SE);
|
2587 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_BE);
|
2588 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_FE1);
|
2589 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_IR);
|
2590 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_DR);
|
2591 | e1833e1f | j_mayer | #if 0 /* Fix this: not on all targets */
|
2592 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_PMM);
|
2593 | e1833e1f | j_mayer | #endif
|
2594 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_LE);
|
2595 | 0411a972 | j_mayer | if (msr_ile)
|
2596 | 0411a972 | j_mayer | new_msr |= (target_ulong)1 << MSR_LE;
|
2597 | 0411a972 | j_mayer | else
|
2598 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_LE);
|
2599 | e1833e1f | j_mayer | /* Jump to handler */
|
2600 | e1833e1f | j_mayer | vector = env->excp_vectors[excp]; |
2601 | 6f2d8978 | j_mayer | if (vector == (target_ulong)-1ULL) { |
2602 | e1833e1f | j_mayer | cpu_abort(env, "Raised an exception without defined vector %d\n",
|
2603 | e1833e1f | j_mayer | excp); |
2604 | e1833e1f | j_mayer | } |
2605 | e1833e1f | j_mayer | vector |= env->excp_prefix; |
2606 | c62db105 | j_mayer | #if defined(TARGET_PPC64)
|
2607 | e1833e1f | j_mayer | if (excp_model == POWERPC_EXCP_BOOKE) {
|
2608 | 0411a972 | j_mayer | if (!msr_icm) {
|
2609 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_CM);
|
2610 | e1833e1f | j_mayer | vector = (uint32_t)vector; |
2611 | 0411a972 | j_mayer | } else {
|
2612 | 0411a972 | j_mayer | new_msr |= (target_ulong)1 << MSR_CM;
|
2613 | 0411a972 | j_mayer | } |
2614 | c62db105 | j_mayer | } else {
|
2615 | 6ce0ca12 | blueswir1 | if (!msr_isf && !(env->mmu_model & POWERPC_MMU_64)) {
|
2616 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_SF);
|
2617 | e1833e1f | j_mayer | vector = (uint32_t)vector; |
2618 | 0411a972 | j_mayer | } else {
|
2619 | 0411a972 | j_mayer | new_msr |= (target_ulong)1 << MSR_SF;
|
2620 | 0411a972 | j_mayer | } |
2621 | c62db105 | j_mayer | } |
2622 | e1833e1f | j_mayer | #endif
|
2623 | 0411a972 | j_mayer | /* XXX: we don't use hreg_store_msr here as already have treated
|
2624 | 0411a972 | j_mayer | * any special case that could occur. Just store MSR and update hflags
|
2625 | 0411a972 | j_mayer | */
|
2626 | a4f30719 | j_mayer | env->msr = new_msr & env->msr_mask; |
2627 | 0411a972 | j_mayer | hreg_compute_hflags(env); |
2628 | e1833e1f | j_mayer | env->nip = vector; |
2629 | e1833e1f | j_mayer | /* Reset exception state */
|
2630 | e1833e1f | j_mayer | env->exception_index = POWERPC_EXCP_NONE; |
2631 | e1833e1f | j_mayer | env->error_code = 0;
|
2632 | fb0eaffc | bellard | } |
2633 | 47103572 | j_mayer | |
2634 | e1833e1f | j_mayer | void do_interrupt (CPUState *env)
|
2635 | 47103572 | j_mayer | { |
2636 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, env->exception_index); |
2637 | e1833e1f | j_mayer | } |
2638 | 47103572 | j_mayer | |
2639 | e1833e1f | j_mayer | void ppc_hw_interrupt (CPUPPCState *env)
|
2640 | e1833e1f | j_mayer | { |
2641 | f9fdea6b | j_mayer | int hdice;
|
2642 | f9fdea6b | j_mayer | |
2643 | 0411a972 | j_mayer | #if 0
|
2644 | 93fcfe39 | aliguori | qemu_log_mask(CPU_LOG_INT, "%s: %p pending %08x req %08x me %d ee %d\n",
|
2645 | a496775f | j_mayer | __func__, env, env->pending_interrupts,
|
2646 | 0411a972 | j_mayer | env->interrupt_request, (int)msr_me, (int)msr_ee);
|
2647 | 47103572 | j_mayer | #endif
|
2648 | e1833e1f | j_mayer | /* External reset */
|
2649 | 47103572 | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_RESET)) { |
2650 | 47103572 | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_RESET);
|
2651 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_RESET); |
2652 | e1833e1f | j_mayer | return;
|
2653 | e1833e1f | j_mayer | } |
2654 | e1833e1f | j_mayer | /* Machine check exception */
|
2655 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_MCK)) { |
2656 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_MCK);
|
2657 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_MCHECK); |
2658 | e1833e1f | j_mayer | return;
|
2659 | 47103572 | j_mayer | } |
2660 | e1833e1f | j_mayer | #if 0 /* TODO */
|
2661 | e1833e1f | j_mayer | /* External debug exception */
|
2662 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_DEBUG)) {
|
2663 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DEBUG);
|
2664 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_DEBUG);
|
2665 | e1833e1f | j_mayer | return;
|
2666 | e1833e1f | j_mayer | }
|
2667 | e1833e1f | j_mayer | #endif
|
2668 | b172c56a | j_mayer | if (0) { |
2669 | b172c56a | j_mayer | /* XXX: find a suitable condition to enable the hypervisor mode */
|
2670 | b172c56a | j_mayer | hdice = env->spr[SPR_LPCR] & 1;
|
2671 | b172c56a | j_mayer | } else {
|
2672 | b172c56a | j_mayer | hdice = 0;
|
2673 | b172c56a | j_mayer | } |
2674 | f9fdea6b | j_mayer | if ((msr_ee != 0 || msr_hv == 0 || msr_pr != 0) && hdice != 0) { |
2675 | 47103572 | j_mayer | /* Hypervisor decrementer exception */
|
2676 | 47103572 | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) { |
2677 | 47103572 | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR);
|
2678 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_HDECR); |
2679 | e1833e1f | j_mayer | return;
|
2680 | e1833e1f | j_mayer | } |
2681 | e1833e1f | j_mayer | } |
2682 | e1833e1f | j_mayer | if (msr_ce != 0) { |
2683 | e1833e1f | j_mayer | /* External critical interrupt */
|
2684 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_CEXT)) { |
2685 | e1833e1f | j_mayer | /* Taking a critical external interrupt does not clear the external
|
2686 | e1833e1f | j_mayer | * critical interrupt status
|
2687 | e1833e1f | j_mayer | */
|
2688 | e1833e1f | j_mayer | #if 0
|
2689 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CEXT);
|
2690 | 47103572 | j_mayer | #endif
|
2691 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_CRITICAL); |
2692 | e1833e1f | j_mayer | return;
|
2693 | e1833e1f | j_mayer | } |
2694 | e1833e1f | j_mayer | } |
2695 | e1833e1f | j_mayer | if (msr_ee != 0) { |
2696 | e1833e1f | j_mayer | /* Watchdog timer on embedded PowerPC */
|
2697 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_WDT)) { |
2698 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_WDT);
|
2699 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_WDT); |
2700 | e1833e1f | j_mayer | return;
|
2701 | e1833e1f | j_mayer | } |
2702 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_CDOORBELL)) { |
2703 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CDOORBELL);
|
2704 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_DOORCI); |
2705 | e1833e1f | j_mayer | return;
|
2706 | e1833e1f | j_mayer | } |
2707 | e1833e1f | j_mayer | /* Fixed interval timer on embedded PowerPC */
|
2708 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_FIT)) { |
2709 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_FIT);
|
2710 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_FIT); |
2711 | e1833e1f | j_mayer | return;
|
2712 | e1833e1f | j_mayer | } |
2713 | e1833e1f | j_mayer | /* Programmable interval timer on embedded PowerPC */
|
2714 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_PIT)) { |
2715 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PIT);
|
2716 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_PIT); |
2717 | e1833e1f | j_mayer | return;
|
2718 | e1833e1f | j_mayer | } |
2719 | 47103572 | j_mayer | /* Decrementer exception */
|
2720 | 47103572 | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_DECR)) { |
2721 | 47103572 | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DECR);
|
2722 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_DECR); |
2723 | e1833e1f | j_mayer | return;
|
2724 | e1833e1f | j_mayer | } |
2725 | 47103572 | j_mayer | /* External interrupt */
|
2726 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) { |
2727 | e9df014c | j_mayer | /* Taking an external interrupt does not clear the external
|
2728 | e9df014c | j_mayer | * interrupt status
|
2729 | e9df014c | j_mayer | */
|
2730 | e9df014c | j_mayer | #if 0
|
2731 | 47103572 | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EXT);
|
2732 | e9df014c | j_mayer | #endif
|
2733 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_EXTERNAL); |
2734 | e1833e1f | j_mayer | return;
|
2735 | e1833e1f | j_mayer | } |
2736 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_DOORBELL)) { |
2737 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DOORBELL);
|
2738 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_DOORI); |
2739 | e1833e1f | j_mayer | return;
|
2740 | 47103572 | j_mayer | } |
2741 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_PERFM)) { |
2742 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PERFM);
|
2743 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_PERFM); |
2744 | e1833e1f | j_mayer | return;
|
2745 | e1833e1f | j_mayer | } |
2746 | e1833e1f | j_mayer | /* Thermal interrupt */
|
2747 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_THERM)) { |
2748 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_THERM);
|
2749 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_THERM); |
2750 | e1833e1f | j_mayer | return;
|
2751 | e1833e1f | j_mayer | } |
2752 | 47103572 | j_mayer | } |
2753 | 47103572 | j_mayer | } |
2754 | 18fba28c | bellard | #endif /* !CONFIG_USER_ONLY */ |
2755 | a496775f | j_mayer | |
2756 | 4a057712 | j_mayer | void cpu_dump_rfi (target_ulong RA, target_ulong msr)
|
2757 | 4a057712 | j_mayer | { |
2758 | 93fcfe39 | aliguori | qemu_log("Return from exception at " ADDRX " with flags " ADDRX "\n", |
2759 | 93fcfe39 | aliguori | RA, msr); |
2760 | a496775f | j_mayer | } |
2761 | a496775f | j_mayer | |
2762 | 0a032cbe | j_mayer | void cpu_ppc_reset (void *opaque) |
2763 | 0a032cbe | j_mayer | { |
2764 | eca1bdf4 | aliguori | CPUPPCState *env = opaque; |
2765 | 0411a972 | j_mayer | target_ulong msr; |
2766 | 0a032cbe | j_mayer | |
2767 | eca1bdf4 | aliguori | if (qemu_loglevel_mask(CPU_LOG_RESET)) {
|
2768 | eca1bdf4 | aliguori | qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
|
2769 | eca1bdf4 | aliguori | log_cpu_state(env, 0);
|
2770 | eca1bdf4 | aliguori | } |
2771 | eca1bdf4 | aliguori | |
2772 | 0411a972 | j_mayer | msr = (target_ulong)0;
|
2773 | a4f30719 | j_mayer | if (0) { |
2774 | a4f30719 | j_mayer | /* XXX: find a suitable condition to enable the hypervisor mode */
|
2775 | a4f30719 | j_mayer | msr |= (target_ulong)MSR_HVB; |
2776 | a4f30719 | j_mayer | } |
2777 | 0411a972 | j_mayer | msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */ |
2778 | 0411a972 | j_mayer | msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */ |
2779 | 0411a972 | j_mayer | msr |= (target_ulong)1 << MSR_EP;
|
2780 | 0a032cbe | j_mayer | #if defined (DO_SINGLE_STEP) && 0 |
2781 | 0a032cbe | j_mayer | /* Single step trace mode */
|
2782 | 0411a972 | j_mayer | msr |= (target_ulong)1 << MSR_SE;
|
2783 | 0411a972 | j_mayer | msr |= (target_ulong)1 << MSR_BE;
|
2784 | 0a032cbe | j_mayer | #endif
|
2785 | 0a032cbe | j_mayer | #if defined(CONFIG_USER_ONLY)
|
2786 | 0411a972 | j_mayer | msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */ |
2787 | 4c2ab988 | aurel32 | msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */ |
2788 | 4c2ab988 | aurel32 | msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */ |
2789 | 0411a972 | j_mayer | msr |= (target_ulong)1 << MSR_PR;
|
2790 | 0a032cbe | j_mayer | #else
|
2791 | 1c27f8fb | j_mayer | env->nip = env->hreset_vector | env->excp_prefix; |
2792 | b4095fed | j_mayer | if (env->mmu_model != POWERPC_MMU_REAL)
|
2793 | 141c8ae2 | j_mayer | ppc_tlb_invalidate_all(env); |
2794 | 0a032cbe | j_mayer | #endif
|
2795 | 07c485ce | blueswir1 | env->msr = msr & env->msr_mask; |
2796 | 6ce0ca12 | blueswir1 | #if defined(TARGET_PPC64)
|
2797 | 6ce0ca12 | blueswir1 | if (env->mmu_model & POWERPC_MMU_64)
|
2798 | 6ce0ca12 | blueswir1 | env->msr |= (1ULL << MSR_SF);
|
2799 | 6ce0ca12 | blueswir1 | #endif
|
2800 | 0411a972 | j_mayer | hreg_compute_hflags(env); |
2801 | 6f2d8978 | j_mayer | env->reserve = (target_ulong)-1ULL;
|
2802 | 5eb7995e | j_mayer | /* Be sure no exception or interrupt is pending */
|
2803 | 5eb7995e | j_mayer | env->pending_interrupts = 0;
|
2804 | e1833e1f | j_mayer | env->exception_index = POWERPC_EXCP_NONE; |
2805 | e1833e1f | j_mayer | env->error_code = 0;
|
2806 | 5eb7995e | j_mayer | /* Flush all TLBs */
|
2807 | 5eb7995e | j_mayer | tlb_flush(env, 1);
|
2808 | 0a032cbe | j_mayer | } |
2809 | 0a032cbe | j_mayer | |
2810 | aaed909a | bellard | CPUPPCState *cpu_ppc_init (const char *cpu_model) |
2811 | 0a032cbe | j_mayer | { |
2812 | 0a032cbe | j_mayer | CPUPPCState *env; |
2813 | aaed909a | bellard | const ppc_def_t *def;
|
2814 | aaed909a | bellard | |
2815 | aaed909a | bellard | def = cpu_ppc_find_by_name(cpu_model); |
2816 | aaed909a | bellard | if (!def)
|
2817 | aaed909a | bellard | return NULL; |
2818 | 0a032cbe | j_mayer | |
2819 | 0a032cbe | j_mayer | env = qemu_mallocz(sizeof(CPUPPCState));
|
2820 | 0a032cbe | j_mayer | cpu_exec_init(env); |
2821 | 2e70f6ef | pbrook | ppc_translate_init(); |
2822 | 01ba9816 | ths | env->cpu_model_str = cpu_model; |
2823 | aaed909a | bellard | cpu_ppc_register_internal(env, def); |
2824 | aaed909a | bellard | cpu_ppc_reset(env); |
2825 | d76d1650 | aurel32 | |
2826 | d76d1650 | aurel32 | if (kvm_enabled())
|
2827 | d76d1650 | aurel32 | kvm_init_vcpu(env); |
2828 | d76d1650 | aurel32 | |
2829 | 0a032cbe | j_mayer | return env;
|
2830 | 0a032cbe | j_mayer | } |
2831 | 0a032cbe | j_mayer | |
2832 | 0a032cbe | j_mayer | void cpu_ppc_close (CPUPPCState *env)
|
2833 | 0a032cbe | j_mayer | { |
2834 | 0a032cbe | j_mayer | /* Should also remove all opcode tables... */
|
2835 | aaed909a | bellard | qemu_free(env); |
2836 | 0a032cbe | j_mayer | } |