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1 | 420557e8 | bellard | /*
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2 | 420557e8 | bellard | * QEMU Sun4m System Emulator
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3 | 420557e8 | bellard | *
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4 | 420557e8 | bellard | * Copyright (c) 2003-2004 Fabrice Bellard
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5 | 420557e8 | bellard | *
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6 | 420557e8 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 420557e8 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 420557e8 | bellard | * in the Software without restriction, including without limitation the rights
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9 | 420557e8 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 420557e8 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 420557e8 | bellard | * furnished to do so, subject to the following conditions:
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12 | 420557e8 | bellard | *
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13 | 420557e8 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 420557e8 | bellard | * all copies or substantial portions of the Software.
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15 | 420557e8 | bellard | *
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16 | 420557e8 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 420557e8 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 420557e8 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 420557e8 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 420557e8 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 420557e8 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 420557e8 | bellard | * THE SOFTWARE.
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23 | 420557e8 | bellard | */
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24 | 420557e8 | bellard | #include "vl.h" |
25 | 420557e8 | bellard | #include "m48t08.h" |
26 | 420557e8 | bellard | |
27 | 420557e8 | bellard | #define KERNEL_LOAD_ADDR 0x00004000 |
28 | b6f479d3 | bellard | #define CMDLINE_ADDR 0x007ff000 |
29 | 713c45fa | bellard | #define INITRD_LOAD_ADDR 0x00800000 |
30 | e80cfcfc | bellard | #define PROM_ADDR 0xffd00000 |
31 | 8d5f07fa | bellard | #define PROM_FILENAMEB "proll.bin" |
32 | 8d5f07fa | bellard | #define PROM_FILENAMEE "proll.elf" |
33 | e80cfcfc | bellard | #define PHYS_JJ_EEPROM 0x71200000 /* m48t08 */ |
34 | 420557e8 | bellard | #define PHYS_JJ_IDPROM_OFF 0x1FD8 |
35 | 420557e8 | bellard | #define PHYS_JJ_EEPROM_SIZE 0x2000 |
36 | e80cfcfc | bellard | // IRQs are not PIL ones, but master interrupt controller register
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37 | e80cfcfc | bellard | // bits
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38 | e80cfcfc | bellard | #define PHYS_JJ_IOMMU 0x10000000 /* I/O MMU */ |
39 | 6f7e9aec | bellard | #define PHYS_JJ_TCX_FB 0x50000000 /* TCX frame buffer */ |
40 | 6f7e9aec | bellard | #define PHYS_JJ_ESPDMA 0x78400000 /* ESP DMA controller */ |
41 | 6f7e9aec | bellard | #define PHYS_JJ_ESP 0x78800000 /* ESP SCSI */ |
42 | 6f7e9aec | bellard | #define PHYS_JJ_ESP_IRQ 18 |
43 | e80cfcfc | bellard | #define PHYS_JJ_LEDMA 0x78400010 /* Lance DMA controller */ |
44 | e80cfcfc | bellard | #define PHYS_JJ_LE 0x78C00000 /* Lance ethernet */ |
45 | e80cfcfc | bellard | #define PHYS_JJ_LE_IRQ 16 |
46 | e80cfcfc | bellard | #define PHYS_JJ_CLOCK 0x71D00000 /* Per-CPU timer/counter, L14 */ |
47 | e80cfcfc | bellard | #define PHYS_JJ_CLOCK_IRQ 7 |
48 | e80cfcfc | bellard | #define PHYS_JJ_CLOCK1 0x71D10000 /* System timer/counter, L10 */ |
49 | e80cfcfc | bellard | #define PHYS_JJ_CLOCK1_IRQ 19 |
50 | e80cfcfc | bellard | #define PHYS_JJ_INTR0 0x71E00000 /* Per-CPU interrupt control registers */ |
51 | 8d5f07fa | bellard | #define PHYS_JJ_INTR_G 0x71E10000 /* Master interrupt control registers */ |
52 | e80cfcfc | bellard | #define PHYS_JJ_MS_KBD 0x71000000 /* Mouse and keyboard */ |
53 | e80cfcfc | bellard | #define PHYS_JJ_MS_KBD_IRQ 14 |
54 | e80cfcfc | bellard | #define PHYS_JJ_SER 0x71100000 /* Serial */ |
55 | e80cfcfc | bellard | #define PHYS_JJ_SER_IRQ 15 |
56 | e80cfcfc | bellard | #define PHYS_JJ_FDC 0x71400000 /* Floppy */ |
57 | e80cfcfc | bellard | #define PHYS_JJ_FLOPPY_IRQ 22 |
58 | 420557e8 | bellard | |
59 | 420557e8 | bellard | /* TSC handling */
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60 | 420557e8 | bellard | |
61 | 420557e8 | bellard | uint64_t cpu_get_tsc() |
62 | 420557e8 | bellard | { |
63 | 420557e8 | bellard | return qemu_get_clock(vm_clock);
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64 | 420557e8 | bellard | } |
65 | 420557e8 | bellard | |
66 | 6f7e9aec | bellard | int DMA_get_channel_mode (int nchan) |
67 | 6f7e9aec | bellard | { |
68 | 6f7e9aec | bellard | return 0; |
69 | 6f7e9aec | bellard | } |
70 | 6f7e9aec | bellard | int DMA_read_memory (int nchan, void *buf, int pos, int size) |
71 | 6f7e9aec | bellard | { |
72 | 6f7e9aec | bellard | return 0; |
73 | 6f7e9aec | bellard | } |
74 | 6f7e9aec | bellard | int DMA_write_memory (int nchan, void *buf, int pos, int size) |
75 | 6f7e9aec | bellard | { |
76 | 6f7e9aec | bellard | return 0; |
77 | 6f7e9aec | bellard | } |
78 | 6f7e9aec | bellard | void DMA_hold_DREQ (int nchan) {} |
79 | 6f7e9aec | bellard | void DMA_release_DREQ (int nchan) {} |
80 | 6f7e9aec | bellard | void DMA_schedule(int nchan) {} |
81 | 6f7e9aec | bellard | void DMA_run (void) {} |
82 | 6f7e9aec | bellard | void DMA_init (int high_page_enable) {} |
83 | 6f7e9aec | bellard | void DMA_register_channel (int nchan, |
84 | 6f7e9aec | bellard | DMA_transfer_handler transfer_handler, |
85 | 6f7e9aec | bellard | void *opaque)
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86 | 6f7e9aec | bellard | { |
87 | 6f7e9aec | bellard | } |
88 | 6f7e9aec | bellard | |
89 | 6f7e9aec | bellard | static void nvram_set_word (m48t08_t *nvram, uint32_t addr, uint16_t value) |
90 | 6f7e9aec | bellard | { |
91 | 6f7e9aec | bellard | m48t08_write(nvram, addr++, (value >> 8) & 0xff); |
92 | 6f7e9aec | bellard | m48t08_write(nvram, addr++, value & 0xff);
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93 | 6f7e9aec | bellard | } |
94 | 6f7e9aec | bellard | |
95 | 6f7e9aec | bellard | static void nvram_set_lword (m48t08_t *nvram, uint32_t addr, uint32_t value) |
96 | 6f7e9aec | bellard | { |
97 | 6f7e9aec | bellard | m48t08_write(nvram, addr++, value >> 24);
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98 | 6f7e9aec | bellard | m48t08_write(nvram, addr++, (value >> 16) & 0xff); |
99 | 6f7e9aec | bellard | m48t08_write(nvram, addr++, (value >> 8) & 0xff); |
100 | 6f7e9aec | bellard | m48t08_write(nvram, addr++, value & 0xff);
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101 | 6f7e9aec | bellard | } |
102 | 6f7e9aec | bellard | |
103 | 6f7e9aec | bellard | static void nvram_set_string (m48t08_t *nvram, uint32_t addr, |
104 | 6f7e9aec | bellard | const unsigned char *str, uint32_t max) |
105 | 6f7e9aec | bellard | { |
106 | 6f7e9aec | bellard | unsigned int i; |
107 | 6f7e9aec | bellard | |
108 | 6f7e9aec | bellard | for (i = 0; i < max && str[i] != '\0'; i++) { |
109 | 6f7e9aec | bellard | m48t08_write(nvram, addr + i, str[i]); |
110 | 6f7e9aec | bellard | } |
111 | 6f7e9aec | bellard | m48t08_write(nvram, addr + max - 1, '\0'); |
112 | 6f7e9aec | bellard | } |
113 | 420557e8 | bellard | |
114 | 420557e8 | bellard | static m48t08_t *nvram;
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115 | 420557e8 | bellard | |
116 | 6f7e9aec | bellard | extern int nographic; |
117 | 6f7e9aec | bellard | |
118 | 6f7e9aec | bellard | static void nvram_init(m48t08_t *nvram, uint8_t *macaddr, const char *cmdline, |
119 | 6f7e9aec | bellard | int boot_device, uint32_t RAM_size,
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120 | 6f7e9aec | bellard | uint32_t kernel_size, |
121 | 6f7e9aec | bellard | int width, int height, int depth) |
122 | e80cfcfc | bellard | { |
123 | e80cfcfc | bellard | unsigned char tmp = 0; |
124 | e80cfcfc | bellard | int i, j;
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125 | e80cfcfc | bellard | |
126 | 6f7e9aec | bellard | // Try to match PPC NVRAM
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127 | 6f7e9aec | bellard | nvram_set_string(nvram, 0x00, "QEMU_BIOS", 16); |
128 | 6f7e9aec | bellard | nvram_set_lword(nvram, 0x10, 0x00000001); /* structure v1 */ |
129 | 6f7e9aec | bellard | // NVRAM_size, arch not applicable
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130 | 6f7e9aec | bellard | m48t08_write(nvram, 0x2F, nographic & 0xff); |
131 | 6f7e9aec | bellard | nvram_set_lword(nvram, 0x30, RAM_size);
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132 | 6f7e9aec | bellard | m48t08_write(nvram, 0x34, boot_device & 0xff); |
133 | 6f7e9aec | bellard | nvram_set_lword(nvram, 0x38, KERNEL_LOAD_ADDR);
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134 | 6f7e9aec | bellard | nvram_set_lword(nvram, 0x3C, kernel_size);
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135 | b6f479d3 | bellard | if (cmdline) {
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136 | b6f479d3 | bellard | strcpy(phys_ram_base + CMDLINE_ADDR, cmdline); |
137 | 6f7e9aec | bellard | nvram_set_lword(nvram, 0x40, CMDLINE_ADDR);
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138 | 6f7e9aec | bellard | nvram_set_lword(nvram, 0x44, strlen(cmdline));
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139 | b6f479d3 | bellard | } |
140 | 6f7e9aec | bellard | // initrd_image, initrd_size passed differently
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141 | 6f7e9aec | bellard | nvram_set_word(nvram, 0x54, width);
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142 | 6f7e9aec | bellard | nvram_set_word(nvram, 0x56, height);
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143 | 6f7e9aec | bellard | nvram_set_word(nvram, 0x58, depth);
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144 | b6f479d3 | bellard | |
145 | 6f7e9aec | bellard | // Sun4m specific use
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146 | e80cfcfc | bellard | i = 0x1fd8;
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147 | e80cfcfc | bellard | m48t08_write(nvram, i++, 0x01);
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148 | e80cfcfc | bellard | m48t08_write(nvram, i++, 0x80); /* Sun4m OBP */ |
149 | e80cfcfc | bellard | j = 0;
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150 | e80cfcfc | bellard | m48t08_write(nvram, i++, macaddr[j++]); |
151 | e80cfcfc | bellard | m48t08_write(nvram, i++, macaddr[j++]); |
152 | e80cfcfc | bellard | m48t08_write(nvram, i++, macaddr[j++]); |
153 | e80cfcfc | bellard | m48t08_write(nvram, i++, macaddr[j++]); |
154 | e80cfcfc | bellard | m48t08_write(nvram, i++, macaddr[j++]); |
155 | e80cfcfc | bellard | m48t08_write(nvram, i, macaddr[j]); |
156 | e80cfcfc | bellard | |
157 | e80cfcfc | bellard | /* Calculate checksum */
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158 | e80cfcfc | bellard | for (i = 0x1fd8; i < 0x1fe7; i++) { |
159 | e80cfcfc | bellard | tmp ^= m48t08_read(nvram, i); |
160 | e80cfcfc | bellard | } |
161 | e80cfcfc | bellard | m48t08_write(nvram, 0x1fe7, tmp);
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162 | e80cfcfc | bellard | } |
163 | e80cfcfc | bellard | |
164 | e80cfcfc | bellard | static void *slavio_intctl; |
165 | e80cfcfc | bellard | |
166 | e80cfcfc | bellard | void pic_info()
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167 | e80cfcfc | bellard | { |
168 | e80cfcfc | bellard | slavio_pic_info(slavio_intctl); |
169 | e80cfcfc | bellard | } |
170 | e80cfcfc | bellard | |
171 | e80cfcfc | bellard | void irq_info()
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172 | e80cfcfc | bellard | { |
173 | e80cfcfc | bellard | slavio_irq_info(slavio_intctl); |
174 | e80cfcfc | bellard | } |
175 | e80cfcfc | bellard | |
176 | e80cfcfc | bellard | void pic_set_irq(int irq, int level) |
177 | e80cfcfc | bellard | { |
178 | e80cfcfc | bellard | slavio_pic_set_irq(slavio_intctl, irq, level); |
179 | e80cfcfc | bellard | } |
180 | e80cfcfc | bellard | |
181 | e80cfcfc | bellard | static void *tcx; |
182 | e80cfcfc | bellard | |
183 | e80cfcfc | bellard | void vga_update_display()
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184 | e80cfcfc | bellard | { |
185 | e80cfcfc | bellard | tcx_update_display(tcx); |
186 | e80cfcfc | bellard | } |
187 | e80cfcfc | bellard | |
188 | e80cfcfc | bellard | void vga_invalidate_display()
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189 | e80cfcfc | bellard | { |
190 | e80cfcfc | bellard | tcx_invalidate_display(tcx); |
191 | e80cfcfc | bellard | } |
192 | e80cfcfc | bellard | |
193 | e80cfcfc | bellard | void vga_screen_dump(const char *filename) |
194 | e80cfcfc | bellard | { |
195 | e80cfcfc | bellard | tcx_screen_dump(tcx, filename); |
196 | e80cfcfc | bellard | } |
197 | e80cfcfc | bellard | |
198 | e80cfcfc | bellard | static void *iommu; |
199 | e80cfcfc | bellard | |
200 | e80cfcfc | bellard | uint32_t iommu_translate(uint32_t addr) |
201 | e80cfcfc | bellard | { |
202 | e80cfcfc | bellard | return iommu_translate_local(iommu, addr);
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203 | e80cfcfc | bellard | } |
204 | e80cfcfc | bellard | |
205 | 420557e8 | bellard | /* Sun4m hardware initialisation */
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206 | 420557e8 | bellard | void sun4m_init(int ram_size, int vga_ram_size, int boot_device, |
207 | 420557e8 | bellard | DisplayState *ds, const char **fd_filename, int snapshot, |
208 | 420557e8 | bellard | const char *kernel_filename, const char *kernel_cmdline, |
209 | 420557e8 | bellard | const char *initrd_filename) |
210 | 420557e8 | bellard | { |
211 | 420557e8 | bellard | char buf[1024]; |
212 | 8d5f07fa | bellard | int ret, linux_boot;
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213 | 713c45fa | bellard | unsigned int i; |
214 | 6f7e9aec | bellard | long vram_size = 0x100000, prom_offset, initrd_size, kernel_size; |
215 | 420557e8 | bellard | |
216 | 420557e8 | bellard | linux_boot = (kernel_filename != NULL);
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217 | 420557e8 | bellard | |
218 | 420557e8 | bellard | /* allocate RAM */
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219 | 420557e8 | bellard | cpu_register_physical_memory(0, ram_size, 0); |
220 | 420557e8 | bellard | |
221 | e80cfcfc | bellard | iommu = iommu_init(PHYS_JJ_IOMMU); |
222 | e80cfcfc | bellard | slavio_intctl = slavio_intctl_init(PHYS_JJ_INTR0, PHYS_JJ_INTR_G); |
223 | 6f7e9aec | bellard | tcx = tcx_init(ds, PHYS_JJ_TCX_FB, phys_ram_base + ram_size, ram_size, vram_size, graphic_width, graphic_height); |
224 | 8d5f07fa | bellard | lance_init(&nd_table[0], PHYS_JJ_LE_IRQ, PHYS_JJ_LE, PHYS_JJ_LEDMA);
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225 | e80cfcfc | bellard | nvram = m48t08_init(PHYS_JJ_EEPROM, PHYS_JJ_EEPROM_SIZE); |
226 | e80cfcfc | bellard | slavio_timer_init(PHYS_JJ_CLOCK, PHYS_JJ_CLOCK_IRQ, PHYS_JJ_CLOCK1, PHYS_JJ_CLOCK1_IRQ); |
227 | e80cfcfc | bellard | slavio_serial_ms_kbd_init(PHYS_JJ_MS_KBD, PHYS_JJ_MS_KBD_IRQ); |
228 | e80cfcfc | bellard | slavio_serial_init(PHYS_JJ_SER, PHYS_JJ_SER_IRQ, serial_hds[0], serial_hds[1]); |
229 | e80cfcfc | bellard | fdctrl_init(PHYS_JJ_FLOPPY_IRQ, 0, 1, PHYS_JJ_FDC, fd_table); |
230 | 6f7e9aec | bellard | esp_init(bs_table, PHYS_JJ_ESP_IRQ, PHYS_JJ_ESP, PHYS_JJ_ESPDMA); |
231 | 420557e8 | bellard | |
232 | e80cfcfc | bellard | prom_offset = ram_size + vram_size; |
233 | e80cfcfc | bellard | |
234 | e80cfcfc | bellard | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAMEE); |
235 | e80cfcfc | bellard | ret = load_elf(buf, phys_ram_base + prom_offset); |
236 | e80cfcfc | bellard | if (ret < 0) { |
237 | 8d5f07fa | bellard | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAMEB); |
238 | e80cfcfc | bellard | ret = load_image(buf, phys_ram_base + prom_offset); |
239 | e80cfcfc | bellard | } |
240 | e80cfcfc | bellard | if (ret < 0) { |
241 | e80cfcfc | bellard | fprintf(stderr, "qemu: could not load prom '%s'\n",
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242 | e80cfcfc | bellard | buf); |
243 | e80cfcfc | bellard | exit(1);
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244 | e80cfcfc | bellard | } |
245 | e80cfcfc | bellard | cpu_register_physical_memory(PROM_ADDR, (ret + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK, |
246 | e80cfcfc | bellard | prom_offset | IO_MEM_ROM); |
247 | e80cfcfc | bellard | |
248 | 6f7e9aec | bellard | kernel_size = 0;
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249 | e80cfcfc | bellard | if (linux_boot) {
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250 | 6f7e9aec | bellard | kernel_size = load_elf(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); |
251 | 6f7e9aec | bellard | if (kernel_size < 0) |
252 | 6f7e9aec | bellard | kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); |
253 | 6f7e9aec | bellard | if (kernel_size < 0) |
254 | 6f7e9aec | bellard | kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); |
255 | 6f7e9aec | bellard | if (kernel_size < 0) { |
256 | 420557e8 | bellard | fprintf(stderr, "qemu: could not load kernel '%s'\n",
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257 | e80cfcfc | bellard | kernel_filename); |
258 | e80cfcfc | bellard | exit(1);
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259 | 420557e8 | bellard | } |
260 | 713c45fa | bellard | |
261 | 713c45fa | bellard | /* load initrd */
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262 | 713c45fa | bellard | initrd_size = 0;
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263 | 713c45fa | bellard | if (initrd_filename) {
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264 | 713c45fa | bellard | initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR); |
265 | 713c45fa | bellard | if (initrd_size < 0) { |
266 | 713c45fa | bellard | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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267 | 713c45fa | bellard | initrd_filename); |
268 | 713c45fa | bellard | exit(1);
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269 | 713c45fa | bellard | } |
270 | 713c45fa | bellard | } |
271 | 713c45fa | bellard | if (initrd_size > 0) { |
272 | 713c45fa | bellard | for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { |
273 | 713c45fa | bellard | if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i)
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274 | 713c45fa | bellard | == 0x48647253) { // HdrS |
275 | 713c45fa | bellard | stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
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276 | 713c45fa | bellard | stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size);
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277 | 713c45fa | bellard | break;
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278 | 713c45fa | bellard | } |
279 | 713c45fa | bellard | } |
280 | 713c45fa | bellard | } |
281 | 420557e8 | bellard | } |
282 | 6f7e9aec | bellard | nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline, boot_device, ram_size, kernel_size, graphic_width, graphic_height, graphic_depth);
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283 | 420557e8 | bellard | } |