Statistics
| Branch: | Revision:

root / hw / xtensa_sample.c @ 71cf9e62

History | View | Annotate | Download (3.8 kB)

# Date Author Comment
f3df4c04 09/10/2011 07:57 pm Max Filippov

target-xtensa: implement CPENABLE and PRID SRs

Signed-off-by: Max Filippov <>
Signed-off-by: Blue Swirl <>
7b039f74 09/10/2011 07:57 pm Max Filippov

target-xtensa: add sample board

Sample board and sample CPU core are used for debug and may be used for
development of custom SoC emulators.

This board has two fixed size memory regions for DTCM and ITCM and
variable length SRAM region.

Signed-off-by: Max Filippov <>...