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1 | 2c0262af | bellard | /*
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2 | 2c0262af | bellard | * i386 virtual CPU header
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3 | 5fafdf24 | ths | *
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4 | 2c0262af | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | 2c0262af | bellard | *
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6 | 2c0262af | bellard | * This library is free software; you can redistribute it and/or
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7 | 2c0262af | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 2c0262af | bellard | * License as published by the Free Software Foundation; either
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9 | 2c0262af | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 2c0262af | bellard | *
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11 | 2c0262af | bellard | * This library is distributed in the hope that it will be useful,
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12 | 2c0262af | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 2c0262af | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 2c0262af | bellard | * Lesser General Public License for more details.
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15 | 2c0262af | bellard | *
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16 | 2c0262af | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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18 | 2c0262af | bellard | */
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19 | 2c0262af | bellard | #ifndef CPU_I386_H
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20 | 2c0262af | bellard | #define CPU_I386_H
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21 | 2c0262af | bellard | |
22 | 14ce26e7 | bellard | #include "config.h" |
23 | 9a78eead | Stefan Weil | #include "qemu-common.h" |
24 | 14ce26e7 | bellard | |
25 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
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26 | 14ce26e7 | bellard | #define TARGET_LONG_BITS 64 |
27 | 14ce26e7 | bellard | #else
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28 | 3cf1e035 | bellard | #define TARGET_LONG_BITS 32 |
29 | 14ce26e7 | bellard | #endif
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30 | 3cf1e035 | bellard | |
31 | d720b93d | bellard | /* target supports implicit self modifying code */
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32 | d720b93d | bellard | #define TARGET_HAS_SMC
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33 | d720b93d | bellard | /* support for self modifying code even if the modified instruction is
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34 | d720b93d | bellard | close to the modifying instruction */
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35 | d720b93d | bellard | #define TARGET_HAS_PRECISE_SMC
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36 | d720b93d | bellard | |
37 | 1fddef4b | bellard | #define TARGET_HAS_ICE 1 |
38 | 1fddef4b | bellard | |
39 | 9042c0e2 | ths | #ifdef TARGET_X86_64
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40 | 9042c0e2 | ths | #define ELF_MACHINE EM_X86_64
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41 | 9042c0e2 | ths | #else
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42 | 9042c0e2 | ths | #define ELF_MACHINE EM_386
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43 | 9042c0e2 | ths | #endif
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44 | 9042c0e2 | ths | |
45 | c2764719 | pbrook | #define CPUState struct CPUX86State |
46 | c2764719 | pbrook | |
47 | 2c0262af | bellard | #include "cpu-defs.h" |
48 | 2c0262af | bellard | |
49 | 7a0e1f41 | bellard | #include "softfloat.h" |
50 | 7a0e1f41 | bellard | |
51 | 2c0262af | bellard | #define R_EAX 0 |
52 | 2c0262af | bellard | #define R_ECX 1 |
53 | 2c0262af | bellard | #define R_EDX 2 |
54 | 2c0262af | bellard | #define R_EBX 3 |
55 | 2c0262af | bellard | #define R_ESP 4 |
56 | 2c0262af | bellard | #define R_EBP 5 |
57 | 2c0262af | bellard | #define R_ESI 6 |
58 | 2c0262af | bellard | #define R_EDI 7 |
59 | 2c0262af | bellard | |
60 | 2c0262af | bellard | #define R_AL 0 |
61 | 2c0262af | bellard | #define R_CL 1 |
62 | 2c0262af | bellard | #define R_DL 2 |
63 | 2c0262af | bellard | #define R_BL 3 |
64 | 2c0262af | bellard | #define R_AH 4 |
65 | 2c0262af | bellard | #define R_CH 5 |
66 | 2c0262af | bellard | #define R_DH 6 |
67 | 2c0262af | bellard | #define R_BH 7 |
68 | 2c0262af | bellard | |
69 | 2c0262af | bellard | #define R_ES 0 |
70 | 2c0262af | bellard | #define R_CS 1 |
71 | 2c0262af | bellard | #define R_SS 2 |
72 | 2c0262af | bellard | #define R_DS 3 |
73 | 2c0262af | bellard | #define R_FS 4 |
74 | 2c0262af | bellard | #define R_GS 5 |
75 | 2c0262af | bellard | |
76 | 2c0262af | bellard | /* segment descriptor fields */
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77 | 2c0262af | bellard | #define DESC_G_MASK (1 << 23) |
78 | 2c0262af | bellard | #define DESC_B_SHIFT 22 |
79 | 2c0262af | bellard | #define DESC_B_MASK (1 << DESC_B_SHIFT) |
80 | 14ce26e7 | bellard | #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */ |
81 | 14ce26e7 | bellard | #define DESC_L_MASK (1 << DESC_L_SHIFT) |
82 | 2c0262af | bellard | #define DESC_AVL_MASK (1 << 20) |
83 | 2c0262af | bellard | #define DESC_P_MASK (1 << 15) |
84 | 2c0262af | bellard | #define DESC_DPL_SHIFT 13 |
85 | a3867ed2 | aliguori | #define DESC_DPL_MASK (3 << DESC_DPL_SHIFT) |
86 | 2c0262af | bellard | #define DESC_S_MASK (1 << 12) |
87 | 2c0262af | bellard | #define DESC_TYPE_SHIFT 8 |
88 | a3867ed2 | aliguori | #define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT) |
89 | 2c0262af | bellard | #define DESC_A_MASK (1 << 8) |
90 | 2c0262af | bellard | |
91 | e670b89e | bellard | #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */ |
92 | e670b89e | bellard | #define DESC_C_MASK (1 << 10) /* code: conforming */ |
93 | e670b89e | bellard | #define DESC_R_MASK (1 << 9) /* code: readable */ |
94 | 2c0262af | bellard | |
95 | e670b89e | bellard | #define DESC_E_MASK (1 << 10) /* data: expansion direction */ |
96 | e670b89e | bellard | #define DESC_W_MASK (1 << 9) /* data: writable */ |
97 | e670b89e | bellard | |
98 | e670b89e | bellard | #define DESC_TSS_BUSY_MASK (1 << 9) |
99 | 2c0262af | bellard | |
100 | 2c0262af | bellard | /* eflags masks */
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101 | 2c0262af | bellard | #define CC_C 0x0001 |
102 | 2c0262af | bellard | #define CC_P 0x0004 |
103 | 2c0262af | bellard | #define CC_A 0x0010 |
104 | 2c0262af | bellard | #define CC_Z 0x0040 |
105 | 2c0262af | bellard | #define CC_S 0x0080 |
106 | 2c0262af | bellard | #define CC_O 0x0800 |
107 | 2c0262af | bellard | |
108 | 2c0262af | bellard | #define TF_SHIFT 8 |
109 | 2c0262af | bellard | #define IOPL_SHIFT 12 |
110 | 2c0262af | bellard | #define VM_SHIFT 17 |
111 | 2c0262af | bellard | |
112 | 2c0262af | bellard | #define TF_MASK 0x00000100 |
113 | 2c0262af | bellard | #define IF_MASK 0x00000200 |
114 | 2c0262af | bellard | #define DF_MASK 0x00000400 |
115 | 2c0262af | bellard | #define IOPL_MASK 0x00003000 |
116 | 2c0262af | bellard | #define NT_MASK 0x00004000 |
117 | 2c0262af | bellard | #define RF_MASK 0x00010000 |
118 | 2c0262af | bellard | #define VM_MASK 0x00020000 |
119 | 5fafdf24 | ths | #define AC_MASK 0x00040000 |
120 | 2c0262af | bellard | #define VIF_MASK 0x00080000 |
121 | 2c0262af | bellard | #define VIP_MASK 0x00100000 |
122 | 2c0262af | bellard | #define ID_MASK 0x00200000 |
123 | 2c0262af | bellard | |
124 | aa1f17c1 | ths | /* hidden flags - used internally by qemu to represent additional cpu
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125 | 33c263df | bellard | states. Only the CPL, INHIBIT_IRQ, SMM and SVMI are not
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126 | 33c263df | bellard | redundant. We avoid using the IOPL_MASK, TF_MASK and VM_MASK bit
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127 | 33c263df | bellard | position to ease oring with eflags. */
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128 | 2c0262af | bellard | /* current cpl */
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129 | 2c0262af | bellard | #define HF_CPL_SHIFT 0 |
130 | 2c0262af | bellard | /* true if soft mmu is being used */
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131 | 2c0262af | bellard | #define HF_SOFTMMU_SHIFT 2 |
132 | 2c0262af | bellard | /* true if hardware interrupts must be disabled for next instruction */
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133 | 2c0262af | bellard | #define HF_INHIBIT_IRQ_SHIFT 3 |
134 | 2c0262af | bellard | /* 16 or 32 segments */
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135 | 2c0262af | bellard | #define HF_CS32_SHIFT 4 |
136 | 2c0262af | bellard | #define HF_SS32_SHIFT 5 |
137 | dc196a57 | bellard | /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
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138 | 2c0262af | bellard | #define HF_ADDSEG_SHIFT 6 |
139 | 65262d57 | bellard | /* copy of CR0.PE (protected mode) */
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140 | 65262d57 | bellard | #define HF_PE_SHIFT 7 |
141 | 65262d57 | bellard | #define HF_TF_SHIFT 8 /* must be same as eflags */ |
142 | 7eee2a50 | bellard | #define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */ |
143 | 7eee2a50 | bellard | #define HF_EM_SHIFT 10 |
144 | 7eee2a50 | bellard | #define HF_TS_SHIFT 11 |
145 | 65262d57 | bellard | #define HF_IOPL_SHIFT 12 /* must be same as eflags */ |
146 | 14ce26e7 | bellard | #define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */ |
147 | 14ce26e7 | bellard | #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */ |
148 | a2397807 | Jan Kiszka | #define HF_RF_SHIFT 16 /* must be same as eflags */ |
149 | 65262d57 | bellard | #define HF_VM_SHIFT 17 /* must be same as eflags */ |
150 | 3b21e03e | bellard | #define HF_SMM_SHIFT 19 /* CPU in SMM mode */ |
151 | db620f46 | bellard | #define HF_SVME_SHIFT 20 /* SVME enabled (copy of EFER.SVME) */ |
152 | db620f46 | bellard | #define HF_SVMI_SHIFT 21 /* SVM intercepts are active */ |
153 | a2397807 | Jan Kiszka | #define HF_OSFXSR_SHIFT 22 /* CR4.OSFXSR */ |
154 | 2c0262af | bellard | |
155 | 2c0262af | bellard | #define HF_CPL_MASK (3 << HF_CPL_SHIFT) |
156 | 2c0262af | bellard | #define HF_SOFTMMU_MASK (1 << HF_SOFTMMU_SHIFT) |
157 | 2c0262af | bellard | #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT) |
158 | 2c0262af | bellard | #define HF_CS32_MASK (1 << HF_CS32_SHIFT) |
159 | 2c0262af | bellard | #define HF_SS32_MASK (1 << HF_SS32_SHIFT) |
160 | 2c0262af | bellard | #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT) |
161 | 65262d57 | bellard | #define HF_PE_MASK (1 << HF_PE_SHIFT) |
162 | 58fe2f10 | bellard | #define HF_TF_MASK (1 << HF_TF_SHIFT) |
163 | 7eee2a50 | bellard | #define HF_MP_MASK (1 << HF_MP_SHIFT) |
164 | 7eee2a50 | bellard | #define HF_EM_MASK (1 << HF_EM_SHIFT) |
165 | 7eee2a50 | bellard | #define HF_TS_MASK (1 << HF_TS_SHIFT) |
166 | 0650f1ab | aliguori | #define HF_IOPL_MASK (3 << HF_IOPL_SHIFT) |
167 | 14ce26e7 | bellard | #define HF_LMA_MASK (1 << HF_LMA_SHIFT) |
168 | 14ce26e7 | bellard | #define HF_CS64_MASK (1 << HF_CS64_SHIFT) |
169 | a2397807 | Jan Kiszka | #define HF_RF_MASK (1 << HF_RF_SHIFT) |
170 | 0650f1ab | aliguori | #define HF_VM_MASK (1 << HF_VM_SHIFT) |
171 | 3b21e03e | bellard | #define HF_SMM_MASK (1 << HF_SMM_SHIFT) |
172 | 872929aa | bellard | #define HF_SVME_MASK (1 << HF_SVME_SHIFT) |
173 | 872929aa | bellard | #define HF_SVMI_MASK (1 << HF_SVMI_SHIFT) |
174 | a2397807 | Jan Kiszka | #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT) |
175 | 2c0262af | bellard | |
176 | db620f46 | bellard | /* hflags2 */
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177 | db620f46 | bellard | |
178 | db620f46 | bellard | #define HF2_GIF_SHIFT 0 /* if set CPU takes interrupts */ |
179 | db620f46 | bellard | #define HF2_HIF_SHIFT 1 /* value of IF_MASK when entering SVM */ |
180 | db620f46 | bellard | #define HF2_NMI_SHIFT 2 /* CPU serving NMI */ |
181 | db620f46 | bellard | #define HF2_VINTR_SHIFT 3 /* value of V_INTR_MASKING bit */ |
182 | db620f46 | bellard | |
183 | db620f46 | bellard | #define HF2_GIF_MASK (1 << HF2_GIF_SHIFT) |
184 | db620f46 | bellard | #define HF2_HIF_MASK (1 << HF2_HIF_SHIFT) |
185 | db620f46 | bellard | #define HF2_NMI_MASK (1 << HF2_NMI_SHIFT) |
186 | db620f46 | bellard | #define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT) |
187 | db620f46 | bellard | |
188 | 0650f1ab | aliguori | #define CR0_PE_SHIFT 0 |
189 | 0650f1ab | aliguori | #define CR0_MP_SHIFT 1 |
190 | 0650f1ab | aliguori | |
191 | 2c0262af | bellard | #define CR0_PE_MASK (1 << 0) |
192 | 7eee2a50 | bellard | #define CR0_MP_MASK (1 << 1) |
193 | 7eee2a50 | bellard | #define CR0_EM_MASK (1 << 2) |
194 | 2c0262af | bellard | #define CR0_TS_MASK (1 << 3) |
195 | 2ee73ac3 | bellard | #define CR0_ET_MASK (1 << 4) |
196 | 7eee2a50 | bellard | #define CR0_NE_MASK (1 << 5) |
197 | 2c0262af | bellard | #define CR0_WP_MASK (1 << 16) |
198 | 2c0262af | bellard | #define CR0_AM_MASK (1 << 18) |
199 | 2c0262af | bellard | #define CR0_PG_MASK (1 << 31) |
200 | 2c0262af | bellard | |
201 | 2c0262af | bellard | #define CR4_VME_MASK (1 << 0) |
202 | 2c0262af | bellard | #define CR4_PVI_MASK (1 << 1) |
203 | 2c0262af | bellard | #define CR4_TSD_MASK (1 << 2) |
204 | 2c0262af | bellard | #define CR4_DE_MASK (1 << 3) |
205 | 2c0262af | bellard | #define CR4_PSE_MASK (1 << 4) |
206 | 64a595f2 | bellard | #define CR4_PAE_MASK (1 << 5) |
207 | 79c4f6b0 | Huang Ying | #define CR4_MCE_MASK (1 << 6) |
208 | 64a595f2 | bellard | #define CR4_PGE_MASK (1 << 7) |
209 | 14ce26e7 | bellard | #define CR4_PCE_MASK (1 << 8) |
210 | 0650f1ab | aliguori | #define CR4_OSFXSR_SHIFT 9 |
211 | 0650f1ab | aliguori | #define CR4_OSFXSR_MASK (1 << CR4_OSFXSR_SHIFT) |
212 | 14ce26e7 | bellard | #define CR4_OSXMMEXCPT_MASK (1 << 10) |
213 | 2c0262af | bellard | |
214 | 01df040b | aliguori | #define DR6_BD (1 << 13) |
215 | 01df040b | aliguori | #define DR6_BS (1 << 14) |
216 | 01df040b | aliguori | #define DR6_BT (1 << 15) |
217 | 01df040b | aliguori | #define DR6_FIXED_1 0xffff0ff0 |
218 | 01df040b | aliguori | |
219 | 01df040b | aliguori | #define DR7_GD (1 << 13) |
220 | 01df040b | aliguori | #define DR7_TYPE_SHIFT 16 |
221 | 01df040b | aliguori | #define DR7_LEN_SHIFT 18 |
222 | 01df040b | aliguori | #define DR7_FIXED_1 0x00000400 |
223 | 01df040b | aliguori | |
224 | 2c0262af | bellard | #define PG_PRESENT_BIT 0 |
225 | 2c0262af | bellard | #define PG_RW_BIT 1 |
226 | 2c0262af | bellard | #define PG_USER_BIT 2 |
227 | 2c0262af | bellard | #define PG_PWT_BIT 3 |
228 | 2c0262af | bellard | #define PG_PCD_BIT 4 |
229 | 2c0262af | bellard | #define PG_ACCESSED_BIT 5 |
230 | 2c0262af | bellard | #define PG_DIRTY_BIT 6 |
231 | 2c0262af | bellard | #define PG_PSE_BIT 7 |
232 | 2c0262af | bellard | #define PG_GLOBAL_BIT 8 |
233 | 5cf38396 | bellard | #define PG_NX_BIT 63 |
234 | 2c0262af | bellard | |
235 | 2c0262af | bellard | #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT) |
236 | 2c0262af | bellard | #define PG_RW_MASK (1 << PG_RW_BIT) |
237 | 2c0262af | bellard | #define PG_USER_MASK (1 << PG_USER_BIT) |
238 | 2c0262af | bellard | #define PG_PWT_MASK (1 << PG_PWT_BIT) |
239 | 2c0262af | bellard | #define PG_PCD_MASK (1 << PG_PCD_BIT) |
240 | 2c0262af | bellard | #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) |
241 | 2c0262af | bellard | #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT) |
242 | 2c0262af | bellard | #define PG_PSE_MASK (1 << PG_PSE_BIT) |
243 | 2c0262af | bellard | #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT) |
244 | 5cf38396 | bellard | #define PG_NX_MASK (1LL << PG_NX_BIT) |
245 | 2c0262af | bellard | |
246 | 2c0262af | bellard | #define PG_ERROR_W_BIT 1 |
247 | 2c0262af | bellard | |
248 | 2c0262af | bellard | #define PG_ERROR_P_MASK 0x01 |
249 | 2c0262af | bellard | #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT) |
250 | 2c0262af | bellard | #define PG_ERROR_U_MASK 0x04 |
251 | 2c0262af | bellard | #define PG_ERROR_RSVD_MASK 0x08 |
252 | 5cf38396 | bellard | #define PG_ERROR_I_D_MASK 0x10 |
253 | 2c0262af | bellard | |
254 | c0532a76 | Marcelo Tosatti | #define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */ |
255 | c0532a76 | Marcelo Tosatti | #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */ |
256 | 79c4f6b0 | Huang Ying | |
257 | c0532a76 | Marcelo Tosatti | #define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P)
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258 | 79c4f6b0 | Huang Ying | #define MCE_BANKS_DEF 10 |
259 | 79c4f6b0 | Huang Ying | |
260 | c0532a76 | Marcelo Tosatti | #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */ |
261 | c0532a76 | Marcelo Tosatti | #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */ |
262 | e6a0575e | Anthony Liguori | #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */ |
263 | 79c4f6b0 | Huang Ying | |
264 | e6a0575e | Anthony Liguori | #define MCI_STATUS_VAL (1ULL<<63) /* valid error */ |
265 | e6a0575e | Anthony Liguori | #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */ |
266 | e6a0575e | Anthony Liguori | #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */ |
267 | c0532a76 | Marcelo Tosatti | #define MCI_STATUS_EN (1ULL<<60) /* error enabled */ |
268 | c0532a76 | Marcelo Tosatti | #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */ |
269 | c0532a76 | Marcelo Tosatti | #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */ |
270 | c0532a76 | Marcelo Tosatti | #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */ |
271 | c0532a76 | Marcelo Tosatti | #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */ |
272 | c0532a76 | Marcelo Tosatti | #define MCI_STATUS_AR (1ULL<<55) /* Action required */ |
273 | c0532a76 | Marcelo Tosatti | |
274 | c0532a76 | Marcelo Tosatti | /* MISC register defines */
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275 | c0532a76 | Marcelo Tosatti | #define MCM_ADDR_SEGOFF 0 /* segment offset */ |
276 | c0532a76 | Marcelo Tosatti | #define MCM_ADDR_LINEAR 1 /* linear address */ |
277 | c0532a76 | Marcelo Tosatti | #define MCM_ADDR_PHYS 2 /* physical address */ |
278 | c0532a76 | Marcelo Tosatti | #define MCM_ADDR_MEM 3 /* memory address */ |
279 | c0532a76 | Marcelo Tosatti | #define MCM_ADDR_GENERIC 7 /* generic */ |
280 | 79c4f6b0 | Huang Ying | |
281 | 0650f1ab | aliguori | #define MSR_IA32_TSC 0x10 |
282 | 2c0262af | bellard | #define MSR_IA32_APICBASE 0x1b |
283 | 2c0262af | bellard | #define MSR_IA32_APICBASE_BSP (1<<8) |
284 | 2c0262af | bellard | #define MSR_IA32_APICBASE_ENABLE (1<<11) |
285 | 2c0262af | bellard | #define MSR_IA32_APICBASE_BASE (0xfffff<<12) |
286 | aa82ba54 | Liu, Jinsong | #define MSR_IA32_TSCDEADLINE 0x6e0 |
287 | 2c0262af | bellard | |
288 | dd5e3b17 | aliguori | #define MSR_MTRRcap 0xfe |
289 | dd5e3b17 | aliguori | #define MSR_MTRRcap_VCNT 8 |
290 | dd5e3b17 | aliguori | #define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8) |
291 | dd5e3b17 | aliguori | #define MSR_MTRRcap_WC_SUPPORTED (1 << 10) |
292 | dd5e3b17 | aliguori | |
293 | 2c0262af | bellard | #define MSR_IA32_SYSENTER_CS 0x174 |
294 | 2c0262af | bellard | #define MSR_IA32_SYSENTER_ESP 0x175 |
295 | 2c0262af | bellard | #define MSR_IA32_SYSENTER_EIP 0x176 |
296 | 2c0262af | bellard | |
297 | 8f091a59 | bellard | #define MSR_MCG_CAP 0x179 |
298 | 8f091a59 | bellard | #define MSR_MCG_STATUS 0x17a |
299 | 8f091a59 | bellard | #define MSR_MCG_CTL 0x17b |
300 | 8f091a59 | bellard | |
301 | e737b32a | balrog | #define MSR_IA32_PERF_STATUS 0x198 |
302 | e737b32a | balrog | |
303 | 21e87c46 | Avi Kivity | #define MSR_IA32_MISC_ENABLE 0x1a0 |
304 | 21e87c46 | Avi Kivity | /* Indicates good rep/movs microcode on some processors: */
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305 | 21e87c46 | Avi Kivity | #define MSR_IA32_MISC_ENABLE_DEFAULT 1 |
306 | 21e87c46 | Avi Kivity | |
307 | 165d9b82 | aliguori | #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg)) |
308 | 165d9b82 | aliguori | #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1) |
309 | 165d9b82 | aliguori | |
310 | 165d9b82 | aliguori | #define MSR_MTRRfix64K_00000 0x250 |
311 | 165d9b82 | aliguori | #define MSR_MTRRfix16K_80000 0x258 |
312 | 165d9b82 | aliguori | #define MSR_MTRRfix16K_A0000 0x259 |
313 | 165d9b82 | aliguori | #define MSR_MTRRfix4K_C0000 0x268 |
314 | 165d9b82 | aliguori | #define MSR_MTRRfix4K_C8000 0x269 |
315 | 165d9b82 | aliguori | #define MSR_MTRRfix4K_D0000 0x26a |
316 | 165d9b82 | aliguori | #define MSR_MTRRfix4K_D8000 0x26b |
317 | 165d9b82 | aliguori | #define MSR_MTRRfix4K_E0000 0x26c |
318 | 165d9b82 | aliguori | #define MSR_MTRRfix4K_E8000 0x26d |
319 | 165d9b82 | aliguori | #define MSR_MTRRfix4K_F0000 0x26e |
320 | 165d9b82 | aliguori | #define MSR_MTRRfix4K_F8000 0x26f |
321 | 165d9b82 | aliguori | |
322 | 8f091a59 | bellard | #define MSR_PAT 0x277 |
323 | 8f091a59 | bellard | |
324 | 165d9b82 | aliguori | #define MSR_MTRRdefType 0x2ff |
325 | 165d9b82 | aliguori | |
326 | 79c4f6b0 | Huang Ying | #define MSR_MC0_CTL 0x400 |
327 | 79c4f6b0 | Huang Ying | #define MSR_MC0_STATUS 0x401 |
328 | 79c4f6b0 | Huang Ying | #define MSR_MC0_ADDR 0x402 |
329 | 79c4f6b0 | Huang Ying | #define MSR_MC0_MISC 0x403 |
330 | 79c4f6b0 | Huang Ying | |
331 | 14ce26e7 | bellard | #define MSR_EFER 0xc0000080 |
332 | 14ce26e7 | bellard | |
333 | 14ce26e7 | bellard | #define MSR_EFER_SCE (1 << 0) |
334 | 14ce26e7 | bellard | #define MSR_EFER_LME (1 << 8) |
335 | 14ce26e7 | bellard | #define MSR_EFER_LMA (1 << 10) |
336 | 14ce26e7 | bellard | #define MSR_EFER_NXE (1 << 11) |
337 | 872929aa | bellard | #define MSR_EFER_SVME (1 << 12) |
338 | 14ce26e7 | bellard | #define MSR_EFER_FFXSR (1 << 14) |
339 | 14ce26e7 | bellard | |
340 | 14ce26e7 | bellard | #define MSR_STAR 0xc0000081 |
341 | 14ce26e7 | bellard | #define MSR_LSTAR 0xc0000082 |
342 | 14ce26e7 | bellard | #define MSR_CSTAR 0xc0000083 |
343 | 14ce26e7 | bellard | #define MSR_FMASK 0xc0000084 |
344 | 14ce26e7 | bellard | #define MSR_FSBASE 0xc0000100 |
345 | 14ce26e7 | bellard | #define MSR_GSBASE 0xc0000101 |
346 | 14ce26e7 | bellard | #define MSR_KERNELGSBASE 0xc0000102 |
347 | 1b050077 | Andre Przywara | #define MSR_TSC_AUX 0xc0000103 |
348 | 14ce26e7 | bellard | |
349 | 0573fbfc | ths | #define MSR_VM_HSAVE_PA 0xc0010117 |
350 | 0573fbfc | ths | |
351 | 14ce26e7 | bellard | /* cpuid_features bits */
|
352 | 14ce26e7 | bellard | #define CPUID_FP87 (1 << 0) |
353 | 14ce26e7 | bellard | #define CPUID_VME (1 << 1) |
354 | 14ce26e7 | bellard | #define CPUID_DE (1 << 2) |
355 | 14ce26e7 | bellard | #define CPUID_PSE (1 << 3) |
356 | 14ce26e7 | bellard | #define CPUID_TSC (1 << 4) |
357 | 14ce26e7 | bellard | #define CPUID_MSR (1 << 5) |
358 | 14ce26e7 | bellard | #define CPUID_PAE (1 << 6) |
359 | 14ce26e7 | bellard | #define CPUID_MCE (1 << 7) |
360 | 14ce26e7 | bellard | #define CPUID_CX8 (1 << 8) |
361 | 14ce26e7 | bellard | #define CPUID_APIC (1 << 9) |
362 | 14ce26e7 | bellard | #define CPUID_SEP (1 << 11) /* sysenter/sysexit */ |
363 | 14ce26e7 | bellard | #define CPUID_MTRR (1 << 12) |
364 | 14ce26e7 | bellard | #define CPUID_PGE (1 << 13) |
365 | 14ce26e7 | bellard | #define CPUID_MCA (1 << 14) |
366 | 14ce26e7 | bellard | #define CPUID_CMOV (1 << 15) |
367 | 8f091a59 | bellard | #define CPUID_PAT (1 << 16) |
368 | 8988ae89 | bellard | #define CPUID_PSE36 (1 << 17) |
369 | a049de61 | bellard | #define CPUID_PN (1 << 18) |
370 | 8f091a59 | bellard | #define CPUID_CLFLUSH (1 << 19) |
371 | a049de61 | bellard | #define CPUID_DTS (1 << 21) |
372 | a049de61 | bellard | #define CPUID_ACPI (1 << 22) |
373 | 14ce26e7 | bellard | #define CPUID_MMX (1 << 23) |
374 | 14ce26e7 | bellard | #define CPUID_FXSR (1 << 24) |
375 | 14ce26e7 | bellard | #define CPUID_SSE (1 << 25) |
376 | 14ce26e7 | bellard | #define CPUID_SSE2 (1 << 26) |
377 | a049de61 | bellard | #define CPUID_SS (1 << 27) |
378 | a049de61 | bellard | #define CPUID_HT (1 << 28) |
379 | a049de61 | bellard | #define CPUID_TM (1 << 29) |
380 | a049de61 | bellard | #define CPUID_IA64 (1 << 30) |
381 | a049de61 | bellard | #define CPUID_PBE (1 << 31) |
382 | 14ce26e7 | bellard | |
383 | 465e9838 | bellard | #define CPUID_EXT_SSE3 (1 << 0) |
384 | 558fa836 | pbrook | #define CPUID_EXT_DTES64 (1 << 2) |
385 | 9df217a3 | bellard | #define CPUID_EXT_MONITOR (1 << 3) |
386 | a049de61 | bellard | #define CPUID_EXT_DSCPL (1 << 4) |
387 | a049de61 | bellard | #define CPUID_EXT_VMX (1 << 5) |
388 | a049de61 | bellard | #define CPUID_EXT_SMX (1 << 6) |
389 | a049de61 | bellard | #define CPUID_EXT_EST (1 << 7) |
390 | a049de61 | bellard | #define CPUID_EXT_TM2 (1 << 8) |
391 | a049de61 | bellard | #define CPUID_EXT_SSSE3 (1 << 9) |
392 | a049de61 | bellard | #define CPUID_EXT_CID (1 << 10) |
393 | 9df217a3 | bellard | #define CPUID_EXT_CX16 (1 << 13) |
394 | a049de61 | bellard | #define CPUID_EXT_XTPR (1 << 14) |
395 | 558fa836 | pbrook | #define CPUID_EXT_PDCM (1 << 15) |
396 | 558fa836 | pbrook | #define CPUID_EXT_DCA (1 << 18) |
397 | 558fa836 | pbrook | #define CPUID_EXT_SSE41 (1 << 19) |
398 | 558fa836 | pbrook | #define CPUID_EXT_SSE42 (1 << 20) |
399 | 558fa836 | pbrook | #define CPUID_EXT_X2APIC (1 << 21) |
400 | 558fa836 | pbrook | #define CPUID_EXT_MOVBE (1 << 22) |
401 | 558fa836 | pbrook | #define CPUID_EXT_POPCNT (1 << 23) |
402 | 558fa836 | pbrook | #define CPUID_EXT_XSAVE (1 << 26) |
403 | 558fa836 | pbrook | #define CPUID_EXT_OSXSAVE (1 << 27) |
404 | 6c0d7ee8 | Andre Przywara | #define CPUID_EXT_HYPERVISOR (1 << 31) |
405 | 9df217a3 | bellard | |
406 | 9df217a3 | bellard | #define CPUID_EXT2_SYSCALL (1 << 11) |
407 | a049de61 | bellard | #define CPUID_EXT2_MP (1 << 19) |
408 | 9df217a3 | bellard | #define CPUID_EXT2_NX (1 << 20) |
409 | a049de61 | bellard | #define CPUID_EXT2_MMXEXT (1 << 22) |
410 | 8d9bfc2b | bellard | #define CPUID_EXT2_FFXSR (1 << 25) |
411 | a049de61 | bellard | #define CPUID_EXT2_PDPE1GB (1 << 26) |
412 | a049de61 | bellard | #define CPUID_EXT2_RDTSCP (1 << 27) |
413 | 9df217a3 | bellard | #define CPUID_EXT2_LM (1 << 29) |
414 | a049de61 | bellard | #define CPUID_EXT2_3DNOWEXT (1 << 30) |
415 | a049de61 | bellard | #define CPUID_EXT2_3DNOW (1 << 31) |
416 | 9df217a3 | bellard | |
417 | a049de61 | bellard | #define CPUID_EXT3_LAHF_LM (1 << 0) |
418 | a049de61 | bellard | #define CPUID_EXT3_CMP_LEG (1 << 1) |
419 | 0573fbfc | ths | #define CPUID_EXT3_SVM (1 << 2) |
420 | a049de61 | bellard | #define CPUID_EXT3_EXTAPIC (1 << 3) |
421 | a049de61 | bellard | #define CPUID_EXT3_CR8LEG (1 << 4) |
422 | a049de61 | bellard | #define CPUID_EXT3_ABM (1 << 5) |
423 | a049de61 | bellard | #define CPUID_EXT3_SSE4A (1 << 6) |
424 | a049de61 | bellard | #define CPUID_EXT3_MISALIGNSSE (1 << 7) |
425 | a049de61 | bellard | #define CPUID_EXT3_3DNOWPREFETCH (1 << 8) |
426 | a049de61 | bellard | #define CPUID_EXT3_OSVW (1 << 9) |
427 | a049de61 | bellard | #define CPUID_EXT3_IBS (1 << 10) |
428 | 872929aa | bellard | #define CPUID_EXT3_SKINIT (1 << 12) |
429 | 0573fbfc | ths | |
430 | 296acb64 | Joerg Roedel | #define CPUID_SVM_NPT (1 << 0) |
431 | 296acb64 | Joerg Roedel | #define CPUID_SVM_LBRV (1 << 1) |
432 | 296acb64 | Joerg Roedel | #define CPUID_SVM_SVMLOCK (1 << 2) |
433 | 296acb64 | Joerg Roedel | #define CPUID_SVM_NRIPSAVE (1 << 3) |
434 | 296acb64 | Joerg Roedel | #define CPUID_SVM_TSCSCALE (1 << 4) |
435 | 296acb64 | Joerg Roedel | #define CPUID_SVM_VMCBCLEAN (1 << 5) |
436 | 296acb64 | Joerg Roedel | #define CPUID_SVM_FLUSHASID (1 << 6) |
437 | 296acb64 | Joerg Roedel | #define CPUID_SVM_DECODEASSIST (1 << 7) |
438 | 296acb64 | Joerg Roedel | #define CPUID_SVM_PAUSEFILTER (1 << 10) |
439 | 296acb64 | Joerg Roedel | #define CPUID_SVM_PFTHRESHOLD (1 << 12) |
440 | 296acb64 | Joerg Roedel | |
441 | c5096daf | balrog | #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */ |
442 | c5096daf | balrog | #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */ |
443 | c5096daf | balrog | #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */ |
444 | c5096daf | balrog | |
445 | c5096daf | balrog | #define CPUID_VENDOR_AMD_1 0x68747541 /* "Auth" */ |
446 | b3baa152 | brillywu@viatech.com.cn | #define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */ |
447 | c5096daf | balrog | #define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */ |
448 | c5096daf | balrog | |
449 | b3baa152 | brillywu@viatech.com.cn | #define CPUID_VENDOR_VIA_1 0x746e6543 /* "Cent" */ |
450 | b3baa152 | brillywu@viatech.com.cn | #define CPUID_VENDOR_VIA_2 0x48727561 /* "aurH" */ |
451 | b3baa152 | brillywu@viatech.com.cn | #define CPUID_VENDOR_VIA_3 0x736c7561 /* "auls" */ |
452 | b3baa152 | brillywu@viatech.com.cn | |
453 | e737b32a | balrog | #define CPUID_MWAIT_IBE (1 << 1) /* Interrupts can exit capability */ |
454 | a876e289 | balrog | #define CPUID_MWAIT_EMX (1 << 0) /* enumeration supported */ |
455 | e737b32a | balrog | |
456 | 2c0262af | bellard | #define EXCP00_DIVZ 0 |
457 | 01df040b | aliguori | #define EXCP01_DB 1 |
458 | 2c0262af | bellard | #define EXCP02_NMI 2 |
459 | 2c0262af | bellard | #define EXCP03_INT3 3 |
460 | 2c0262af | bellard | #define EXCP04_INTO 4 |
461 | 2c0262af | bellard | #define EXCP05_BOUND 5 |
462 | 2c0262af | bellard | #define EXCP06_ILLOP 6 |
463 | 2c0262af | bellard | #define EXCP07_PREX 7 |
464 | 2c0262af | bellard | #define EXCP08_DBLE 8 |
465 | 2c0262af | bellard | #define EXCP09_XERR 9 |
466 | 2c0262af | bellard | #define EXCP0A_TSS 10 |
467 | 2c0262af | bellard | #define EXCP0B_NOSEG 11 |
468 | 2c0262af | bellard | #define EXCP0C_STACK 12 |
469 | 2c0262af | bellard | #define EXCP0D_GPF 13 |
470 | 2c0262af | bellard | #define EXCP0E_PAGE 14 |
471 | 2c0262af | bellard | #define EXCP10_COPR 16 |
472 | 2c0262af | bellard | #define EXCP11_ALGN 17 |
473 | 2c0262af | bellard | #define EXCP12_MCHK 18 |
474 | 2c0262af | bellard | |
475 | d2fd1af7 | bellard | #define EXCP_SYSCALL 0x100 /* only happens in user only emulation |
476 | d2fd1af7 | bellard | for syscall instruction */
|
477 | d2fd1af7 | bellard | |
478 | 00a152b4 | Richard Henderson | /* i386-specific interrupt pending bits. */
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479 | 00a152b4 | Richard Henderson | #define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2
|
480 | 85097db6 | Richard Henderson | #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
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481 | 00a152b4 | Richard Henderson | #define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4
|
482 | 00a152b4 | Richard Henderson | #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0
|
483 | 00a152b4 | Richard Henderson | #define CPU_INTERRUPT_INIT CPU_INTERRUPT_TGT_INT_1
|
484 | 00a152b4 | Richard Henderson | #define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_2
|
485 | 00a152b4 | Richard Henderson | |
486 | 00a152b4 | Richard Henderson | |
487 | 2c0262af | bellard | enum {
|
488 | 2c0262af | bellard | CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
|
489 | 1235fc06 | ths | CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */
|
490 | d36cd60e | bellard | |
491 | d36cd60e | bellard | CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
|
492 | d36cd60e | bellard | CC_OP_MULW, |
493 | d36cd60e | bellard | CC_OP_MULL, |
494 | 14ce26e7 | bellard | CC_OP_MULQ, |
495 | 2c0262af | bellard | |
496 | 2c0262af | bellard | CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
|
497 | 2c0262af | bellard | CC_OP_ADDW, |
498 | 2c0262af | bellard | CC_OP_ADDL, |
499 | 14ce26e7 | bellard | CC_OP_ADDQ, |
500 | 2c0262af | bellard | |
501 | 2c0262af | bellard | CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
|
502 | 2c0262af | bellard | CC_OP_ADCW, |
503 | 2c0262af | bellard | CC_OP_ADCL, |
504 | 14ce26e7 | bellard | CC_OP_ADCQ, |
505 | 2c0262af | bellard | |
506 | 2c0262af | bellard | CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
|
507 | 2c0262af | bellard | CC_OP_SUBW, |
508 | 2c0262af | bellard | CC_OP_SUBL, |
509 | 14ce26e7 | bellard | CC_OP_SUBQ, |
510 | 2c0262af | bellard | |
511 | 2c0262af | bellard | CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
|
512 | 2c0262af | bellard | CC_OP_SBBW, |
513 | 2c0262af | bellard | CC_OP_SBBL, |
514 | 14ce26e7 | bellard | CC_OP_SBBQ, |
515 | 2c0262af | bellard | |
516 | 2c0262af | bellard | CC_OP_LOGICB, /* modify all flags, CC_DST = res */
|
517 | 2c0262af | bellard | CC_OP_LOGICW, |
518 | 2c0262af | bellard | CC_OP_LOGICL, |
519 | 14ce26e7 | bellard | CC_OP_LOGICQ, |
520 | 2c0262af | bellard | |
521 | 2c0262af | bellard | CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
|
522 | 2c0262af | bellard | CC_OP_INCW, |
523 | 2c0262af | bellard | CC_OP_INCL, |
524 | 14ce26e7 | bellard | CC_OP_INCQ, |
525 | 2c0262af | bellard | |
526 | 2c0262af | bellard | CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */
|
527 | 2c0262af | bellard | CC_OP_DECW, |
528 | 2c0262af | bellard | CC_OP_DECL, |
529 | 14ce26e7 | bellard | CC_OP_DECQ, |
530 | 2c0262af | bellard | |
531 | 6b652794 | bellard | CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
|
532 | 2c0262af | bellard | CC_OP_SHLW, |
533 | 2c0262af | bellard | CC_OP_SHLL, |
534 | 14ce26e7 | bellard | CC_OP_SHLQ, |
535 | 2c0262af | bellard | |
536 | 2c0262af | bellard | CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
|
537 | 2c0262af | bellard | CC_OP_SARW, |
538 | 2c0262af | bellard | CC_OP_SARL, |
539 | 14ce26e7 | bellard | CC_OP_SARQ, |
540 | 2c0262af | bellard | |
541 | 2c0262af | bellard | CC_OP_NB, |
542 | 2c0262af | bellard | }; |
543 | 2c0262af | bellard | |
544 | 2c0262af | bellard | typedef struct SegmentCache { |
545 | 2c0262af | bellard | uint32_t selector; |
546 | 14ce26e7 | bellard | target_ulong base; |
547 | 2c0262af | bellard | uint32_t limit; |
548 | 2c0262af | bellard | uint32_t flags; |
549 | 2c0262af | bellard | } SegmentCache; |
550 | 2c0262af | bellard | |
551 | 826461bb | bellard | typedef union { |
552 | 664e0f19 | bellard | uint8_t _b[16];
|
553 | 664e0f19 | bellard | uint16_t _w[8];
|
554 | 664e0f19 | bellard | uint32_t _l[4];
|
555 | 664e0f19 | bellard | uint64_t _q[2];
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556 | 7a0e1f41 | bellard | float32 _s[4];
|
557 | 7a0e1f41 | bellard | float64 _d[2];
|
558 | 14ce26e7 | bellard | } XMMReg; |
559 | 14ce26e7 | bellard | |
560 | 826461bb | bellard | typedef union { |
561 | 826461bb | bellard | uint8_t _b[8];
|
562 | a35f3ec7 | aurel32 | uint16_t _w[4];
|
563 | a35f3ec7 | aurel32 | uint32_t _l[2];
|
564 | a35f3ec7 | aurel32 | float32 _s[2];
|
565 | 826461bb | bellard | uint64_t q; |
566 | 826461bb | bellard | } MMXReg; |
567 | 826461bb | bellard | |
568 | e2542fe2 | Juan Quintela | #ifdef HOST_WORDS_BIGENDIAN
|
569 | 826461bb | bellard | #define XMM_B(n) _b[15 - (n)] |
570 | 826461bb | bellard | #define XMM_W(n) _w[7 - (n)] |
571 | 826461bb | bellard | #define XMM_L(n) _l[3 - (n)] |
572 | 664e0f19 | bellard | #define XMM_S(n) _s[3 - (n)] |
573 | 826461bb | bellard | #define XMM_Q(n) _q[1 - (n)] |
574 | 664e0f19 | bellard | #define XMM_D(n) _d[1 - (n)] |
575 | 826461bb | bellard | |
576 | 826461bb | bellard | #define MMX_B(n) _b[7 - (n)] |
577 | 826461bb | bellard | #define MMX_W(n) _w[3 - (n)] |
578 | 826461bb | bellard | #define MMX_L(n) _l[1 - (n)] |
579 | a35f3ec7 | aurel32 | #define MMX_S(n) _s[1 - (n)] |
580 | 826461bb | bellard | #else
|
581 | 826461bb | bellard | #define XMM_B(n) _b[n]
|
582 | 826461bb | bellard | #define XMM_W(n) _w[n]
|
583 | 826461bb | bellard | #define XMM_L(n) _l[n]
|
584 | 664e0f19 | bellard | #define XMM_S(n) _s[n]
|
585 | 826461bb | bellard | #define XMM_Q(n) _q[n]
|
586 | 664e0f19 | bellard | #define XMM_D(n) _d[n]
|
587 | 826461bb | bellard | |
588 | 826461bb | bellard | #define MMX_B(n) _b[n]
|
589 | 826461bb | bellard | #define MMX_W(n) _w[n]
|
590 | 826461bb | bellard | #define MMX_L(n) _l[n]
|
591 | a35f3ec7 | aurel32 | #define MMX_S(n) _s[n]
|
592 | 826461bb | bellard | #endif
|
593 | 664e0f19 | bellard | #define MMX_Q(n) q
|
594 | 826461bb | bellard | |
595 | acc68836 | Juan Quintela | typedef union { |
596 | c31da136 | Aurelien Jarno | floatx80 d __attribute__((aligned(16)));
|
597 | acc68836 | Juan Quintela | MMXReg mmx; |
598 | acc68836 | Juan Quintela | } FPReg; |
599 | acc68836 | Juan Quintela | |
600 | c1a54d57 | Juan Quintela | typedef struct { |
601 | c1a54d57 | Juan Quintela | uint64_t base; |
602 | c1a54d57 | Juan Quintela | uint64_t mask; |
603 | c1a54d57 | Juan Quintela | } MTRRVar; |
604 | c1a54d57 | Juan Quintela | |
605 | 5f30fa18 | Jan Kiszka | #define CPU_NB_REGS64 16 |
606 | 5f30fa18 | Jan Kiszka | #define CPU_NB_REGS32 8 |
607 | 5f30fa18 | Jan Kiszka | |
608 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
609 | 5f30fa18 | Jan Kiszka | #define CPU_NB_REGS CPU_NB_REGS64
|
610 | 14ce26e7 | bellard | #else
|
611 | 5f30fa18 | Jan Kiszka | #define CPU_NB_REGS CPU_NB_REGS32
|
612 | 14ce26e7 | bellard | #endif
|
613 | 14ce26e7 | bellard | |
614 | 6ebbf390 | j_mayer | #define NB_MMU_MODES 2 |
615 | 6ebbf390 | j_mayer | |
616 | 2c0262af | bellard | typedef struct CPUX86State { |
617 | 2c0262af | bellard | /* standard registers */
|
618 | 14ce26e7 | bellard | target_ulong regs[CPU_NB_REGS]; |
619 | 14ce26e7 | bellard | target_ulong eip; |
620 | 14ce26e7 | bellard | target_ulong eflags; /* eflags register. During CPU emulation, CC
|
621 | 2c0262af | bellard | flags and DF are set to zero because they are
|
622 | 2c0262af | bellard | stored elsewhere */
|
623 | 2c0262af | bellard | |
624 | 2c0262af | bellard | /* emulator internal eflags handling */
|
625 | 14ce26e7 | bellard | target_ulong cc_src; |
626 | 14ce26e7 | bellard | target_ulong cc_dst; |
627 | 2c0262af | bellard | uint32_t cc_op; |
628 | 2c0262af | bellard | int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
|
629 | db620f46 | bellard | uint32_t hflags; /* TB flags, see HF_xxx constants. These flags
|
630 | db620f46 | bellard | are known at translation time. */
|
631 | db620f46 | bellard | uint32_t hflags2; /* various other flags, see HF2_xxx constants. */
|
632 | 2c0262af | bellard | |
633 | 9df217a3 | bellard | /* segments */
|
634 | 9df217a3 | bellard | SegmentCache segs[6]; /* selector values */ |
635 | 9df217a3 | bellard | SegmentCache ldt; |
636 | 9df217a3 | bellard | SegmentCache tr; |
637 | 9df217a3 | bellard | SegmentCache gdt; /* only base and limit are used */
|
638 | 9df217a3 | bellard | SegmentCache idt; /* only base and limit are used */
|
639 | 9df217a3 | bellard | |
640 | db620f46 | bellard | target_ulong cr[5]; /* NOTE: cr1 is unused */ |
641 | 5ee0ffaa | Juan Quintela | int32_t a20_mask; |
642 | 9df217a3 | bellard | |
643 | 2c0262af | bellard | /* FPU state */
|
644 | 2c0262af | bellard | unsigned int fpstt; /* top of stack index */ |
645 | 67b8f419 | Juan Quintela | uint16_t fpus; |
646 | eb831623 | Juan Quintela | uint16_t fpuc; |
647 | 2c0262af | bellard | uint8_t fptags[8]; /* 0 = valid, 1 = empty */ |
648 | acc68836 | Juan Quintela | FPReg fpregs[8];
|
649 | 42cc8fa6 | Jan Kiszka | /* KVM-only so far */
|
650 | 42cc8fa6 | Jan Kiszka | uint16_t fpop; |
651 | 42cc8fa6 | Jan Kiszka | uint64_t fpip; |
652 | 42cc8fa6 | Jan Kiszka | uint64_t fpdp; |
653 | 2c0262af | bellard | |
654 | 2c0262af | bellard | /* emulator internal variables */
|
655 | 7a0e1f41 | bellard | float_status fp_status; |
656 | c31da136 | Aurelien Jarno | floatx80 ft0; |
657 | 3b46e624 | ths | |
658 | a35f3ec7 | aurel32 | float_status mmx_status; /* for 3DNow! float ops */
|
659 | 7a0e1f41 | bellard | float_status sse_status; |
660 | 664e0f19 | bellard | uint32_t mxcsr; |
661 | 14ce26e7 | bellard | XMMReg xmm_regs[CPU_NB_REGS]; |
662 | 14ce26e7 | bellard | XMMReg xmm_t0; |
663 | 664e0f19 | bellard | MMXReg mmx_t0; |
664 | 1e4840bf | bellard | target_ulong cc_tmp; /* temporary for rcr/rcl */
|
665 | 14ce26e7 | bellard | |
666 | 2c0262af | bellard | /* sysenter registers */
|
667 | 2c0262af | bellard | uint32_t sysenter_cs; |
668 | 2436b61a | balrog | target_ulong sysenter_esp; |
669 | 2436b61a | balrog | target_ulong sysenter_eip; |
670 | 8d9bfc2b | bellard | uint64_t efer; |
671 | 8d9bfc2b | bellard | uint64_t star; |
672 | 0573fbfc | ths | |
673 | 5cc1d1e6 | bellard | uint64_t vm_hsave; |
674 | 5cc1d1e6 | bellard | uint64_t vm_vmcb; |
675 | 33c263df | bellard | uint64_t tsc_offset; |
676 | 0573fbfc | ths | uint64_t intercept; |
677 | 0573fbfc | ths | uint16_t intercept_cr_read; |
678 | 0573fbfc | ths | uint16_t intercept_cr_write; |
679 | 0573fbfc | ths | uint16_t intercept_dr_read; |
680 | 0573fbfc | ths | uint16_t intercept_dr_write; |
681 | 0573fbfc | ths | uint32_t intercept_exceptions; |
682 | db620f46 | bellard | uint8_t v_tpr; |
683 | 0573fbfc | ths | |
684 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
685 | 14ce26e7 | bellard | target_ulong lstar; |
686 | 14ce26e7 | bellard | target_ulong cstar; |
687 | 14ce26e7 | bellard | target_ulong fmask; |
688 | 14ce26e7 | bellard | target_ulong kernelgsbase; |
689 | 14ce26e7 | bellard | #endif
|
690 | 1a03675d | Glauber Costa | uint64_t system_time_msr; |
691 | 1a03675d | Glauber Costa | uint64_t wall_clock_msr; |
692 | f6584ee2 | Gleb Natapov | uint64_t async_pf_en_msr; |
693 | 58fe2f10 | bellard | |
694 | 7ba1e619 | aliguori | uint64_t tsc; |
695 | aa82ba54 | Liu, Jinsong | uint64_t tsc_deadline; |
696 | 7ba1e619 | aliguori | |
697 | 18559232 | Jan Kiszka | uint64_t mcg_status; |
698 | 21e87c46 | Avi Kivity | uint64_t msr_ia32_misc_enable; |
699 | 18559232 | Jan Kiszka | |
700 | 2c0262af | bellard | /* exception/interrupt handling */
|
701 | 2c0262af | bellard | int error_code;
|
702 | 2c0262af | bellard | int exception_is_int;
|
703 | 826461bb | bellard | target_ulong exception_next_eip; |
704 | 14ce26e7 | bellard | target_ulong dr[8]; /* debug registers */ |
705 | 01df040b | aliguori | union {
|
706 | 01df040b | aliguori | CPUBreakpoint *cpu_breakpoint[4];
|
707 | 01df040b | aliguori | CPUWatchpoint *cpu_watchpoint[4];
|
708 | 01df040b | aliguori | }; /* break/watchpoints for dr[0..3] */
|
709 | 3b21e03e | bellard | uint32_t smbase; |
710 | 678dde13 | ths | int old_exception; /* exception in flight */ |
711 | 2c0262af | bellard | |
712 | d8f771d9 | Jan Kiszka | /* KVM states, automatically cleared on reset */
|
713 | d8f771d9 | Jan Kiszka | uint8_t nmi_injected; |
714 | d8f771d9 | Jan Kiszka | uint8_t nmi_pending; |
715 | d8f771d9 | Jan Kiszka | |
716 | a316d335 | bellard | CPU_COMMON |
717 | 2c0262af | bellard | |
718 | ebda377f | Jan Kiszka | uint64_t pat; |
719 | ebda377f | Jan Kiszka | |
720 | 14ce26e7 | bellard | /* processor features (e.g. for CPUID insn) */
|
721 | 8d9bfc2b | bellard | uint32_t cpuid_level; |
722 | 14ce26e7 | bellard | uint32_t cpuid_vendor1; |
723 | 14ce26e7 | bellard | uint32_t cpuid_vendor2; |
724 | 14ce26e7 | bellard | uint32_t cpuid_vendor3; |
725 | 14ce26e7 | bellard | uint32_t cpuid_version; |
726 | 14ce26e7 | bellard | uint32_t cpuid_features; |
727 | 9df217a3 | bellard | uint32_t cpuid_ext_features; |
728 | 8d9bfc2b | bellard | uint32_t cpuid_xlevel; |
729 | 8d9bfc2b | bellard | uint32_t cpuid_model[12];
|
730 | 8d9bfc2b | bellard | uint32_t cpuid_ext2_features; |
731 | 0573fbfc | ths | uint32_t cpuid_ext3_features; |
732 | eae7629b | ths | uint32_t cpuid_apic_id; |
733 | ef768138 | Andre Przywara | int cpuid_vendor_override;
|
734 | b3baa152 | brillywu@viatech.com.cn | /* Store the results of Centaur's CPUID instructions */
|
735 | b3baa152 | brillywu@viatech.com.cn | uint32_t cpuid_xlevel2; |
736 | b3baa152 | brillywu@viatech.com.cn | uint32_t cpuid_ext4_features; |
737 | 3b46e624 | ths | |
738 | 165d9b82 | aliguori | /* MTRRs */
|
739 | 165d9b82 | aliguori | uint64_t mtrr_fixed[11];
|
740 | 165d9b82 | aliguori | uint64_t mtrr_deftype; |
741 | c1a54d57 | Juan Quintela | MTRRVar mtrr_var[8];
|
742 | 165d9b82 | aliguori | |
743 | 7ba1e619 | aliguori | /* For KVM */
|
744 | f8d926e9 | Jan Kiszka | uint32_t mp_state; |
745 | 31827373 | Jan Kiszka | int32_t exception_injected; |
746 | 0e607a80 | Jan Kiszka | int32_t interrupt_injected; |
747 | a0fb002c | Jan Kiszka | uint8_t soft_interrupt; |
748 | a0fb002c | Jan Kiszka | uint8_t has_error_code; |
749 | a0fb002c | Jan Kiszka | uint32_t sipi_vector; |
750 | bb0300dc | Gleb Natapov | uint32_t cpuid_kvm_features; |
751 | 296acb64 | Joerg Roedel | uint32_t cpuid_svm_features; |
752 | b8cc45d6 | Glauber Costa | bool tsc_valid;
|
753 | b862d1fe | Joerg Roedel | int tsc_khz;
|
754 | bb0300dc | Gleb Natapov | |
755 | 14ce26e7 | bellard | /* in order to simplify APIC support, we leave this pointer to the
|
756 | 14ce26e7 | bellard | user */
|
757 | 92a16d7a | Blue Swirl | struct DeviceState *apic_state;
|
758 | 79c4f6b0 | Huang Ying | |
759 | ac6c4120 | Andreas Fรคrber | uint64_t mcg_cap; |
760 | ac6c4120 | Andreas Fรคrber | uint64_t mcg_ctl; |
761 | ac6c4120 | Andreas Fรคrber | uint64_t mce_banks[MCE_BANKS_DEF*4];
|
762 | 1b050077 | Andre Przywara | |
763 | 1b050077 | Andre Przywara | uint64_t tsc_aux; |
764 | 5a2d0e57 | Aurelien Jarno | |
765 | 5a2d0e57 | Aurelien Jarno | /* vmstate */
|
766 | 5a2d0e57 | Aurelien Jarno | uint16_t fpus_vmstate; |
767 | 5a2d0e57 | Aurelien Jarno | uint16_t fptag_vmstate; |
768 | 5a2d0e57 | Aurelien Jarno | uint16_t fpregs_format_vmstate; |
769 | f1665b21 | Sheng Yang | |
770 | f1665b21 | Sheng Yang | uint64_t xstate_bv; |
771 | f1665b21 | Sheng Yang | XMMReg ymmh_regs[CPU_NB_REGS]; |
772 | f1665b21 | Sheng Yang | |
773 | f1665b21 | Sheng Yang | uint64_t xcr0; |
774 | 2c0262af | bellard | } CPUX86State; |
775 | 2c0262af | bellard | |
776 | aaed909a | bellard | CPUX86State *cpu_x86_init(const char *cpu_model); |
777 | 2c0262af | bellard | int cpu_x86_exec(CPUX86State *s);
|
778 | 2c0262af | bellard | void cpu_x86_close(CPUX86State *s);
|
779 | 9a78eead | Stefan Weil | void x86_cpu_list (FILE *f, fprintf_function cpu_fprintf, const char *optarg); |
780 | b5ec5ce0 | john cooper | void x86_cpudef_setup(void); |
781 | 2bd3e04c | Jin Dongming | int cpu_x86_support_mca_broadcast(CPUState *env);
|
782 | b5ec5ce0 | john cooper | |
783 | d720b93d | bellard | int cpu_get_pic_interrupt(CPUX86State *s);
|
784 | 2ee73ac3 | bellard | /* MSDOS compatibility mode FPU exception support */
|
785 | 2ee73ac3 | bellard | void cpu_set_ferr(CPUX86State *s);
|
786 | 2c0262af | bellard | |
787 | 2c0262af | bellard | /* this function must always be used to load data in the segment
|
788 | 2c0262af | bellard | cache: it synchronizes the hflags with the segment cache values */
|
789 | 5fafdf24 | ths | static inline void cpu_x86_load_seg_cache(CPUX86State *env, |
790 | 2c0262af | bellard | int seg_reg, unsigned int selector, |
791 | 8988ae89 | bellard | target_ulong base, |
792 | 5fafdf24 | ths | unsigned int limit, |
793 | 2c0262af | bellard | unsigned int flags) |
794 | 2c0262af | bellard | { |
795 | 2c0262af | bellard | SegmentCache *sc; |
796 | 2c0262af | bellard | unsigned int new_hflags; |
797 | 3b46e624 | ths | |
798 | 2c0262af | bellard | sc = &env->segs[seg_reg]; |
799 | 2c0262af | bellard | sc->selector = selector; |
800 | 2c0262af | bellard | sc->base = base; |
801 | 2c0262af | bellard | sc->limit = limit; |
802 | 2c0262af | bellard | sc->flags = flags; |
803 | 2c0262af | bellard | |
804 | 2c0262af | bellard | /* update the hidden flags */
|
805 | 14ce26e7 | bellard | { |
806 | 14ce26e7 | bellard | if (seg_reg == R_CS) {
|
807 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
808 | 14ce26e7 | bellard | if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
|
809 | 14ce26e7 | bellard | /* long mode */
|
810 | 14ce26e7 | bellard | env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; |
811 | 14ce26e7 | bellard | env->hflags &= ~(HF_ADDSEG_MASK); |
812 | 5fafdf24 | ths | } else
|
813 | 14ce26e7 | bellard | #endif
|
814 | 14ce26e7 | bellard | { |
815 | 14ce26e7 | bellard | /* legacy / compatibility case */
|
816 | 14ce26e7 | bellard | new_hflags = (env->segs[R_CS].flags & DESC_B_MASK) |
817 | 14ce26e7 | bellard | >> (DESC_B_SHIFT - HF_CS32_SHIFT); |
818 | 14ce26e7 | bellard | env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) | |
819 | 14ce26e7 | bellard | new_hflags; |
820 | 14ce26e7 | bellard | } |
821 | 14ce26e7 | bellard | } |
822 | 14ce26e7 | bellard | new_hflags = (env->segs[R_SS].flags & DESC_B_MASK) |
823 | 14ce26e7 | bellard | >> (DESC_B_SHIFT - HF_SS32_SHIFT); |
824 | 14ce26e7 | bellard | if (env->hflags & HF_CS64_MASK) {
|
825 | 14ce26e7 | bellard | /* zero base assumed for DS, ES and SS in long mode */
|
826 | 5fafdf24 | ths | } else if (!(env->cr[0] & CR0_PE_MASK) || |
827 | 735a8fd3 | bellard | (env->eflags & VM_MASK) || |
828 | 735a8fd3 | bellard | !(env->hflags & HF_CS32_MASK)) { |
829 | 14ce26e7 | bellard | /* XXX: try to avoid this test. The problem comes from the
|
830 | 14ce26e7 | bellard | fact that is real mode or vm86 mode we only modify the
|
831 | 14ce26e7 | bellard | 'base' and 'selector' fields of the segment cache to go
|
832 | 14ce26e7 | bellard | faster. A solution may be to force addseg to one in
|
833 | 14ce26e7 | bellard | translate-i386.c. */
|
834 | 14ce26e7 | bellard | new_hflags |= HF_ADDSEG_MASK; |
835 | 14ce26e7 | bellard | } else {
|
836 | 5fafdf24 | ths | new_hflags |= ((env->segs[R_DS].base | |
837 | 735a8fd3 | bellard | env->segs[R_ES].base | |
838 | 5fafdf24 | ths | env->segs[R_SS].base) != 0) <<
|
839 | 14ce26e7 | bellard | HF_ADDSEG_SHIFT; |
840 | 14ce26e7 | bellard | } |
841 | 5fafdf24 | ths | env->hflags = (env->hflags & |
842 | 14ce26e7 | bellard | ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags; |
843 | 2c0262af | bellard | } |
844 | 2c0262af | bellard | } |
845 | 2c0262af | bellard | |
846 | 0e26b7b8 | Blue Swirl | static inline void cpu_x86_load_seg_cache_sipi(CPUX86State *env, |
847 | 0e26b7b8 | Blue Swirl | int sipi_vector)
|
848 | 0e26b7b8 | Blue Swirl | { |
849 | 0e26b7b8 | Blue Swirl | env->eip = 0;
|
850 | 0e26b7b8 | Blue Swirl | cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8,
|
851 | 0e26b7b8 | Blue Swirl | sipi_vector << 12,
|
852 | 0e26b7b8 | Blue Swirl | env->segs[R_CS].limit, |
853 | 0e26b7b8 | Blue Swirl | env->segs[R_CS].flags); |
854 | 0e26b7b8 | Blue Swirl | env->halted = 0;
|
855 | 0e26b7b8 | Blue Swirl | } |
856 | 0e26b7b8 | Blue Swirl | |
857 | 84273177 | Jan Kiszka | int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector, |
858 | 84273177 | Jan Kiszka | target_ulong *base, unsigned int *limit, |
859 | 84273177 | Jan Kiszka | unsigned int *flags); |
860 | 84273177 | Jan Kiszka | |
861 | 2c0262af | bellard | /* wrapper, just in case memory mappings must be changed */
|
862 | 2c0262af | bellard | static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl) |
863 | 2c0262af | bellard | { |
864 | 2c0262af | bellard | #if HF_CPL_MASK == 3 |
865 | 2c0262af | bellard | s->hflags = (s->hflags & ~HF_CPL_MASK) | cpl; |
866 | 2c0262af | bellard | #else
|
867 | 2c0262af | bellard | #error HF_CPL_MASK is hardcoded
|
868 | 2c0262af | bellard | #endif
|
869 | 2c0262af | bellard | } |
870 | 2c0262af | bellard | |
871 | d9957a8b | blueswir1 | /* op_helper.c */
|
872 | 1f1af9fd | bellard | /* used for debug or cpu save/restore */
|
873 | c31da136 | Aurelien Jarno | void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, floatx80 f);
|
874 | c31da136 | Aurelien Jarno | floatx80 cpu_set_fp80(uint64_t mant, uint16_t upper); |
875 | 1f1af9fd | bellard | |
876 | d9957a8b | blueswir1 | /* cpu-exec.c */
|
877 | 2c0262af | bellard | /* the following helpers are only usable in user mode simulation as
|
878 | 2c0262af | bellard | they can trigger unexpected exceptions */
|
879 | 2c0262af | bellard | void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector); |
880 | 6f12a2a6 | bellard | void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32); |
881 | 6f12a2a6 | bellard | void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32); |
882 | 2c0262af | bellard | |
883 | 2c0262af | bellard | /* you can call this signal handler from your SIGBUS and SIGSEGV
|
884 | 2c0262af | bellard | signal handlers to inform the virtual CPU of exceptions. non zero
|
885 | 2c0262af | bellard | is returned if the signal was handled by the virtual CPU. */
|
886 | 5fafdf24 | ths | int cpu_x86_signal_handler(int host_signum, void *pinfo, |
887 | 2c0262af | bellard | void *puc);
|
888 | d9957a8b | blueswir1 | |
889 | c6dc6f63 | Andre Przywara | /* cpuid.c */
|
890 | c6dc6f63 | Andre Przywara | void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
|
891 | c6dc6f63 | Andre Przywara | uint32_t *eax, uint32_t *ebx, |
892 | c6dc6f63 | Andre Przywara | uint32_t *ecx, uint32_t *edx); |
893 | c6dc6f63 | Andre Przywara | int cpu_x86_register (CPUX86State *env, const char *cpu_model); |
894 | 0e26b7b8 | Blue Swirl | void cpu_clear_apic_feature(CPUX86State *env);
|
895 | bb44e0d1 | Jan Kiszka | void host_cpuid(uint32_t function, uint32_t count,
|
896 | bb44e0d1 | Jan Kiszka | uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx); |
897 | c6dc6f63 | Andre Przywara | |
898 | d9957a8b | blueswir1 | /* helper.c */
|
899 | d9957a8b | blueswir1 | int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
|
900 | 97b348e7 | Blue Swirl | int is_write, int mmu_idx); |
901 | 0b5c1ce8 | Nathan Froyd | #define cpu_handle_mmu_fault cpu_x86_handle_mmu_fault
|
902 | 461c0471 | bellard | void cpu_x86_set_a20(CPUX86State *env, int a20_state); |
903 | 2c0262af | bellard | |
904 | d9957a8b | blueswir1 | static inline int hw_breakpoint_enabled(unsigned long dr7, int index) |
905 | d9957a8b | blueswir1 | { |
906 | d9957a8b | blueswir1 | return (dr7 >> (index * 2)) & 3; |
907 | d9957a8b | blueswir1 | } |
908 | 28ab0e2e | bellard | |
909 | d9957a8b | blueswir1 | static inline int hw_breakpoint_type(unsigned long dr7, int index) |
910 | d9957a8b | blueswir1 | { |
911 | d46272c7 | Jan Kiszka | return (dr7 >> (DR7_TYPE_SHIFT + (index * 4))) & 3; |
912 | d9957a8b | blueswir1 | } |
913 | d9957a8b | blueswir1 | |
914 | d9957a8b | blueswir1 | static inline int hw_breakpoint_len(unsigned long dr7, int index) |
915 | d9957a8b | blueswir1 | { |
916 | d46272c7 | Jan Kiszka | int len = ((dr7 >> (DR7_LEN_SHIFT + (index * 4))) & 3); |
917 | d9957a8b | blueswir1 | return (len == 2) ? 8 : len + 1; |
918 | d9957a8b | blueswir1 | } |
919 | d9957a8b | blueswir1 | |
920 | d9957a8b | blueswir1 | void hw_breakpoint_insert(CPUX86State *env, int index); |
921 | d9957a8b | blueswir1 | void hw_breakpoint_remove(CPUX86State *env, int index); |
922 | d9957a8b | blueswir1 | int check_hw_breakpoints(CPUX86State *env, int force_dr6_update); |
923 | d9957a8b | blueswir1 | |
924 | d9957a8b | blueswir1 | /* will be suppressed */
|
925 | d9957a8b | blueswir1 | void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
|
926 | d9957a8b | blueswir1 | void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
|
927 | d9957a8b | blueswir1 | void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
|
928 | d9957a8b | blueswir1 | |
929 | d9957a8b | blueswir1 | /* hw/pc.c */
|
930 | d9957a8b | blueswir1 | void cpu_smm_update(CPUX86State *env);
|
931 | d9957a8b | blueswir1 | uint64_t cpu_get_tsc(CPUX86State *env); |
932 | 6fd805e1 | aliguori | |
933 | 2c0262af | bellard | /* used to debug */
|
934 | 2c0262af | bellard | #define X86_DUMP_FPU 0x0001 /* dump FPU state too */ |
935 | 2c0262af | bellard | #define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */ |
936 | 2c0262af | bellard | |
937 | 2c0262af | bellard | #define TARGET_PAGE_BITS 12 |
938 | 9467d44c | ths | |
939 | 52705890 | Richard Henderson | #ifdef TARGET_X86_64
|
940 | 52705890 | Richard Henderson | #define TARGET_PHYS_ADDR_SPACE_BITS 52 |
941 | 52705890 | Richard Henderson | /* ??? This is really 48 bits, sign-extended, but the only thing
|
942 | 52705890 | Richard Henderson | accessible to userland with bit 48 set is the VSYSCALL, and that
|
943 | 52705890 | Richard Henderson | is handled via other mechanisms. */
|
944 | 52705890 | Richard Henderson | #define TARGET_VIRT_ADDR_SPACE_BITS 47 |
945 | 52705890 | Richard Henderson | #else
|
946 | 52705890 | Richard Henderson | #define TARGET_PHYS_ADDR_SPACE_BITS 36 |
947 | 52705890 | Richard Henderson | #define TARGET_VIRT_ADDR_SPACE_BITS 32 |
948 | 52705890 | Richard Henderson | #endif
|
949 | 52705890 | Richard Henderson | |
950 | 9467d44c | ths | #define cpu_init cpu_x86_init
|
951 | 9467d44c | ths | #define cpu_exec cpu_x86_exec
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952 | 9467d44c | ths | #define cpu_gen_code cpu_x86_gen_code
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953 | 9467d44c | ths | #define cpu_signal_handler cpu_x86_signal_handler
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954 | b5ec5ce0 | john cooper | #define cpu_list_id x86_cpu_list
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955 | b5ec5ce0 | john cooper | #define cpudef_setup x86_cpudef_setup
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956 | 9467d44c | ths | |
957 | 38d2c27e | Marcelo Tosatti | #define CPU_SAVE_VERSION 12 |
958 | b3c7724c | pbrook | |
959 | 6ebbf390 | j_mayer | /* MMU modes definitions */
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960 | 6ebbf390 | j_mayer | #define MMU_MODE0_SUFFIX _kernel
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961 | 6ebbf390 | j_mayer | #define MMU_MODE1_SUFFIX _user
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962 | 6ebbf390 | j_mayer | #define MMU_USER_IDX 1 |
963 | 6ebbf390 | j_mayer | static inline int cpu_mmu_index (CPUState *env) |
964 | 6ebbf390 | j_mayer | { |
965 | 6ebbf390 | j_mayer | return (env->hflags & HF_CPL_MASK) == 3 ? 1 : 0; |
966 | 6ebbf390 | j_mayer | } |
967 | 6ebbf390 | j_mayer | |
968 | f081c76c | Blue Swirl | #undef EAX
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969 | f081c76c | Blue Swirl | #define EAX (env->regs[R_EAX])
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970 | f081c76c | Blue Swirl | #undef ECX
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971 | f081c76c | Blue Swirl | #define ECX (env->regs[R_ECX])
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972 | f081c76c | Blue Swirl | #undef EDX
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973 | f081c76c | Blue Swirl | #define EDX (env->regs[R_EDX])
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974 | f081c76c | Blue Swirl | #undef EBX
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975 | f081c76c | Blue Swirl | #define EBX (env->regs[R_EBX])
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976 | f081c76c | Blue Swirl | #undef ESP
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977 | f081c76c | Blue Swirl | #define ESP (env->regs[R_ESP])
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978 | f081c76c | Blue Swirl | #undef EBP
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979 | f081c76c | Blue Swirl | #define EBP (env->regs[R_EBP])
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980 | f081c76c | Blue Swirl | #undef ESI
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981 | f081c76c | Blue Swirl | #define ESI (env->regs[R_ESI])
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982 | f081c76c | Blue Swirl | #undef EDI
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983 | f081c76c | Blue Swirl | #define EDI (env->regs[R_EDI])
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984 | f081c76c | Blue Swirl | #undef EIP
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985 | f081c76c | Blue Swirl | #define EIP (env->eip)
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986 | f081c76c | Blue Swirl | #define DF (env->df)
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987 | f081c76c | Blue Swirl | |
988 | f081c76c | Blue Swirl | #define CC_SRC (env->cc_src)
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989 | f081c76c | Blue Swirl | #define CC_DST (env->cc_dst)
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990 | f081c76c | Blue Swirl | #define CC_OP (env->cc_op)
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991 | f081c76c | Blue Swirl | |
992 | f081c76c | Blue Swirl | /* float macros */
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993 | f081c76c | Blue Swirl | #define FT0 (env->ft0)
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994 | f081c76c | Blue Swirl | #define ST0 (env->fpregs[env->fpstt].d)
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995 | f081c76c | Blue Swirl | #define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d) |
996 | f081c76c | Blue Swirl | #define ST1 ST(1) |
997 | f081c76c | Blue Swirl | |
998 | d9957a8b | blueswir1 | /* translate.c */
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999 | 26a5f13b | bellard | void optimize_flags_init(void); |
1000 | 26a5f13b | bellard | |
1001 | 6e68e076 | pbrook | #if defined(CONFIG_USER_ONLY)
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1002 | 6e68e076 | pbrook | static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) |
1003 | 6e68e076 | pbrook | { |
1004 | f8ed7070 | pbrook | if (newsp)
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1005 | 6e68e076 | pbrook | env->regs[R_ESP] = newsp; |
1006 | 6e68e076 | pbrook | env->regs[R_EAX] = 0;
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1007 | 6e68e076 | pbrook | } |
1008 | 6e68e076 | pbrook | #endif
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1009 | 6e68e076 | pbrook | |
1010 | 2c0262af | bellard | #include "cpu-all.h" |
1011 | 0573fbfc | ths | #include "svm.h" |
1012 | 0573fbfc | ths | |
1013 | 0e26b7b8 | Blue Swirl | #if !defined(CONFIG_USER_ONLY)
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1014 | 0e26b7b8 | Blue Swirl | #include "hw/apic.h" |
1015 | 0e26b7b8 | Blue Swirl | #endif
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1016 | 0e26b7b8 | Blue Swirl | |
1017 | f081c76c | Blue Swirl | static inline bool cpu_has_work(CPUState *env) |
1018 | f081c76c | Blue Swirl | { |
1019 | f081c76c | Blue Swirl | return ((env->interrupt_request & CPU_INTERRUPT_HARD) &&
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1020 | f081c76c | Blue Swirl | (env->eflags & IF_MASK)) || |
1021 | f081c76c | Blue Swirl | (env->interrupt_request & (CPU_INTERRUPT_NMI | |
1022 | f081c76c | Blue Swirl | CPU_INTERRUPT_INIT | |
1023 | f081c76c | Blue Swirl | CPU_INTERRUPT_SIPI | |
1024 | f081c76c | Blue Swirl | CPU_INTERRUPT_MCE)); |
1025 | f081c76c | Blue Swirl | } |
1026 | f081c76c | Blue Swirl | |
1027 | f081c76c | Blue Swirl | #include "exec-all.h" |
1028 | f081c76c | Blue Swirl | |
1029 | f081c76c | Blue Swirl | static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb) |
1030 | f081c76c | Blue Swirl | { |
1031 | f081c76c | Blue Swirl | env->eip = tb->pc - tb->cs_base; |
1032 | f081c76c | Blue Swirl | } |
1033 | f081c76c | Blue Swirl | |
1034 | 6b917547 | aliguori | static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, |
1035 | 6b917547 | aliguori | target_ulong *cs_base, int *flags)
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1036 | 6b917547 | aliguori | { |
1037 | 6b917547 | aliguori | *cs_base = env->segs[R_CS].base; |
1038 | 6b917547 | aliguori | *pc = *cs_base + env->eip; |
1039 | a2397807 | Jan Kiszka | *flags = env->hflags | |
1040 | a2397807 | Jan Kiszka | (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK)); |
1041 | 6b917547 | aliguori | } |
1042 | 6b917547 | aliguori | |
1043 | b09ea7d5 | Gleb Natapov | void do_cpu_init(CPUState *env);
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1044 | b09ea7d5 | Gleb Natapov | void do_cpu_sipi(CPUState *env);
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1045 | 2fa11da0 | Jan Kiszka | |
1046 | 747461c7 | Jan Kiszka | #define MCE_INJECT_BROADCAST 1 |
1047 | 747461c7 | Jan Kiszka | #define MCE_INJECT_UNCOND_AO 2 |
1048 | 747461c7 | Jan Kiszka | |
1049 | 316378e4 | Jan Kiszka | void cpu_x86_inject_mce(Monitor *mon, CPUState *cenv, int bank, |
1050 | 316378e4 | Jan Kiszka | uint64_t status, uint64_t mcg_status, uint64_t addr, |
1051 | 747461c7 | Jan Kiszka | uint64_t misc, int flags);
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1052 | 2fa11da0 | Jan Kiszka | |
1053 | e694d4e2 | Blue Swirl | /* op_helper.c */
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1054 | e694d4e2 | Blue Swirl | void do_interrupt(CPUState *env);
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1055 | e694d4e2 | Blue Swirl | void do_interrupt_x86_hardirq(CPUState *env, int intno, int is_hw); |
1056 | 3e457172 | Blue Swirl | void QEMU_NORETURN raise_exception_env(int exception_index, CPUState *nenv); |
1057 | 3e457172 | Blue Swirl | void QEMU_NORETURN raise_exception_err_env(CPUState *nenv, int exception_index, |
1058 | 3e457172 | Blue Swirl | int error_code);
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1059 | e694d4e2 | Blue Swirl | |
1060 | e694d4e2 | Blue Swirl | void do_smm_enter(CPUState *env1);
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1061 | e694d4e2 | Blue Swirl | |
1062 | e694d4e2 | Blue Swirl | void svm_check_intercept(CPUState *env1, uint32_t type);
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1063 | e694d4e2 | Blue Swirl | |
1064 | e694d4e2 | Blue Swirl | uint32_t cpu_cc_compute_all(CPUState *env1, int op);
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1065 | e694d4e2 | Blue Swirl | |
1066 | 2c0262af | bellard | #endif /* CPU_I386_H */ |