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i386: wire up MSR_IA32_MISC_ENABLE
It's needed for its default value - bit 0 specifies that "rep movs" isgood enough for memcpy, and Linux may use a slower memcpu if it is not set,depending on cpu family/model.
Signed-off-by: Avi Kivity <avi@redhat.com>...
kvm: support TSC deadline MSR with subsection
KVM add emulation of lapic tsc deadline timer for guest.This patch is co-operation work at qemu side.
Use subsections to save/restore the field (mtosatti).
Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>...
Revert "kvm: support TSC deadline MSR"
This reverts commit bfc2455ddbb41148494a084d15777e6bed7533c3.New patch with subsections will follow.
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
kvm: support TSC deadline MSR
Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
target-i386: Remove data type CCTable
Remove also two assert statements which were the last remaining users.
Signed-off-by: Stefan Weil <weil@mail.berlios.de>Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
Merge remote-tracking branch 'qemu-kvm/uq/master' into staging
Remove unused is_softmmu parameter from cpu_handle_mmu_fault
Parameter is_softmmu (and its evil mutant twin brother is_softmuu)is not used in cpu_*_handle_mmu_fault() functions, remove themand adjust callers.
Acked-by: Richard Henderson <rth@twiddle.net>...
qemu-x86: Add tsc_freq option to -cpu
To let the user configure the desired tsc frequency for theguest if running in KVM.
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
exec.h cleanup
Move softmmu_exec.h include directives from target-*/exec.h totarget-*/op_helper.c. Move also various other stuff only used inop_helper.c there.
Define global env in dyngen-exec.h.
For i386, move wrappers for segment and FPU helpers from user-exec.c...
Move cpu_has_work and cpu_pc_from_tb to cpu.h
Move functions cpu_has_work() and cpu_pc_from_tb() from exec.h to cpu.h. This isneeded by later patches.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
x86: use caller supplied CPUState for interrupt related stuff
Several x86 specific functions are called from cpu-exec.c with theassumption that global env register is valid. This will be changedlater, so make the functions use caller supplied CPUState parameter....
kvm: x86: Save/restore FPU OP, IP and DP
These FPU states are properly maintained by KVM but not yet by TCG. Sofar we unconditionally set them to 0 in the guest which may causestate corruptions, though not with modern guests.
To avoid breaking backward migration, use a conditional subsection that...
kvm: Add CPUID support for VIA CPU
When KVM is running on VIA CPU with host cpu's model, thefeautures of VIA CPU will be passed into kvm guest by callingthe CPUID instruction for Centaur.
Signed-off-by: BrillyWu<brillywu@viatech.com.cn>Signed-off-by: KaryJin<karyjin@viatech.com.cn>...
target-i386: remove old code handling float64
Now that target-i386 uses softfloat, floatx80 is always available andthere is no need anymore to have code handling both float64 and floax80.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
irq: Privatize CPU_INTERRUPT_NMI.
This interrupt name is used by i386, CRIS, and MicroBlaze.Copy the name into each target.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-i386: Privatize some i386-specific interrupt names.
SMI, VIRQ, INIT, SIPI, and MCE are all only used by the i386 port.
x86: Properly reset PAT MSR
Conforming to the Intel spec, set the power-on value of PAT also onreset, but save it across INIT.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
x86: Perform implicit mcg_status reset
Reorder mcg_status in CPUState to achieve automatic clearing on reset.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>CC: Huang Ying <ying.huang@intel.com>CC: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>CC: Jin Dongming <jin.dongming@np.css.fujitsu.com>...
x86: Small cleanups of MCE helpers
Fix some code style issues, use proper headers, and align to cpu_x86naming scheme. No functional changes.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>CC: Huang Ying <ying.huang@intel.com>CC: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>...
x86: Refine error reporting of MCE injection services
As this service is used by the human monitor, make sure that errors getreported to the right channel, and also raise the verbosity.
This requires to move Monitor typedef in qemu-common.h to resolve the...
x86: Optionally avoid injecting AO MCEs while others are pending
Allow to tell cpu_x86_inject_mce that it should ignore Action OptionalMCE events when the target VCPU is still processing another one. Thiswill be used by KVM soon.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>...
kvm: make tsc stable over migration and machine start
If the machine is stopped, we should not record two different tsc valuesupon a save operation. The same problem happens with kvmclock.
But kvmclock is taking a different diretion, being now seen as a separate...
kvm: x86: Implicitly clear nmi_injected/pending on reset
All CPUX86State variables before CPU_COMMON are automatically cleared onreset. Reorder nmi_injected and nmi_pending to avoid having to touchthem explicitly.
kvm: Improve reporting of fatal errors
Report KVM_EXIT_UNKNOWN, KVM_EXIT_FAIL_ENTRY, and KVM_EXIT_EXCEPTIONwith more details to stderr. The latter two are so far x86-only, so movethem into the arch-specific handler. Integrate the Intel real modewarning on KVM_EXIT_FAIL_ENTRY that qemu-kvm carries, but actually...
Add function for checking mca broadcast of CPU
Add function for checking whether current CPU support mca broadcast.
Signed-off-by: Jin Dongming <jin.dongming@np.css.fujitsu.com>Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
target-i386: Fix accidental use of SoftFloat uint64 type
softfloat.h's uint64 type has least-width semantics.Use uint64_t instead since that is used in helpers.
Signed-off-by: Andreas Färber <andreas.faerber@web.de>...
Add support for async page fault to qemu
Add save/restore of MSR for migration and cpuid bit.
Signed-off-by: Gleb Natapov <gleb@redhat.com>Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
target-xxx: Use fprintf_function (format checking)
fprintf_function uses format checking with GCC_FMT_ATTR.
Cc: Blue Swirl <blauwirbel@gmail.com>Signed-off-by: Stefan Weil <weil@mail.berlios.de>...
Add svm cpuid features
This patch adds the svm cpuid feature flags to the qemuintialization path. It also adds the svm features availableon phenom to its cpu-definition and extends the host cputype to support all svm features KVM can provide.
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>...
MCE: Relay UCR MCE to guest
Port qemu-kvm's
commit 4b62fff1101a7ad77553147717a8bd3bf79df7efAuthor: Huang Ying <ying.huang@intel.com>Date: Mon Sep 21 10:43:25 2009 +0800
UCR (uncorrected recovery) MCE is supported in recent Intel CPUs,...
remove exec-all.h inclusion from cpu.h
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
move cpu_pc_from_tb to target-*/exec.h
kvm: Enable XSAVE live migration support
Signed-off-by: Sheng Yang <sheng@linux.intel.com>Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
apic: qdev conversion cleanup
Make APICState completely private to apic.c by using DeviceStatein external APIs.
Move apic_init() to pc.c.
apic: avoid using CPUState internals
Move the actual CPUState contents handling to cpu.h and cpuid.c.
Handle CPU reset and set env->halted in pc.c.
Add a function to get the local APIC state of the currentCPU for the MMIO.
apic: avoid passing CPUState from CPU code
Pass only APICState when accessing APIC from CPU code.
x86/cpuid: move CPUID functions into separate file
about half of target-i386/helper.c consist of CPUID related functions.Only one of them is a real TCG helper function. So move the wholeCPUID stuff out of this into a separate file to get bettermaintainable parts....
Move TARGET_PHYS_ADDR_SPACE_BITS to target-*/cpu.h.
Removes a set of ifdefs from exec.c.
Introduce TARGET_VIRT_ADDR_SPACE_BITS for all targets otherthan Alpha. This will be used for page_find_alloc, which issupposed to be using virtual addresses in the first place....
Add cpu model configuration support..
This is a reimplementation of prior versions which addsthe ability to define cpu models for contemporary processors.The added models are likewise selected via -cpu <name>,and are intended to displace the existing convention...
Add KVM paravirt cpuid leaf
Initialize KVM paravirt cpuid leaf and allow user to control guestvisible PV features through -cpu flag.
Signed-off-by: Gleb Natapov <gleb@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
kvm: x86: Use separate exception_injected CPUState field
Marcelo correctly remarked that there are usage conflicts between QEMUcore code and KVM /wrt exception_index. So spend a separate field andalso save/restore it properly.
target-i386: Fix evaluation of DR7 register
hw_breakpoint_type and hw_breakpoint_len used the wrong index multiplierto extract type and len.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
v2: properly save kvm system time msr registers
Currently, the msrs involved in setting up pvclock are not saved overmigration and/or save/restore. This patch puts their value in specialfields in our CPUState, and deal with them using vmstate.
kvm also has to account for it, by including them in the msr list...
kvm: x86: Add support for VCPU event states
This patch extends the qemu-kvm state sync logic with support forKVM_GET/SET_VCPU_EVENTS, giving access to yet missing exception,interrupt and NMI states.
kvm: x86: Refactor use of interrupt_bitmap
Drop interrupt_bitmap from the cpustate and solely rely on the integerinterupt_injected. This prepares us for the new injected-interruptinterface, which will deprecate the bitmap, while preservingcompatibility....
target-i386: move recently added vmstate fields at the end of the structure
This reduce the impact on hosts that have addressing modes with limitedoffsets. Suggested by Laurent Desnogues.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
gdbstub: x86: Switch 64/32 bit registers dynamically
Commit 56aebc891674cd2d07b3f64183415697be200084 changed gdbstub in waythat debugging 32 or 16-bit guest code is no longer possible with qemufor x86_64 guest CPUs. Since that commit, qemu only provides registers...
x86: split FPReg union
Signed-off-by: Juan Quintela <quintela@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
x86: split MTRRVar union
x86: add fpregs_format_vmstate
Don't even ask, being able to load/save between 64<->80bit floats should be forbidden
x86: mce_banks always have the same size
mce_banks is always MCE_BANKS_DEF * 4 in size, value never change
CC: Huang Ying <ying.huang@intel.com>Signed-off-by: Juan Quintela <quintela@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
x86: fpuc is uint16_t not unsigned int
x86: fpus is uint16_t not unsigned int
We save more that fpus on that 16 bits (fpstt), we need an additional field
x86: add fptag_vmstate to the state
It is needed to store fptags
x86: add pending_irq_vmstate to the state
It is needed to save the interrupt_bitmap
x86: make a20_mask int32_t
This makes the savevm code correct, and sign extensins gives us exactlywhat we need (namely, sign extend to 64 bits when used with 64bit addresess.
Once there, change 0x100000 for 1 << 20, that maks all a20 use the same syntax....
target-i386: add RDTSCP support
RDTSCP reads the time stamp counter and atomically also the contentof a 32-bit MSR, which can be freely set by the OS. This allows CPUlocal data to be queried by userspace.Linux uses this to allow a fast implementation of the getcpu()...
cleanup cpu-exec.c, part 0/N: consolidate handle_cpu_signal
handle_cpu_signal is very nearly copy-paste code for each target, with afew minor variations. This patch sets up appropriate defaults for ageneric handle_cpu_signal and provides overrides for particular targets...
Unbreak large mem support by removing kqemu
kqemu introduces a number of restrictions on the i386 target. The worst is thatit prevents large memory from working in the default build.
Furthermore, kqemu is fundamentally flawed in a number of ways. It relies on...
rename WORDS_BIGENDIAN to HOST_WORDS_BIGENDIAN
Update to a hopefully more future proof FSF address
gdbstub: x86: Support for setting segment registers
This allows to set segment registers via gdb also in system emulationmode. Basic sanity checks are applied and nothing is changed if theyfail. But screwing up the target via this interface will never be...
Make sure to mark MCE defines as ULL
Fixes build on 32-bit
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
QEMU: MCE: Add MCE simulation to qemu/tcg
- MCE features are initialized when VCPU is intialized according to CPUID.- A monitor command "mce" is added to inject a MCE.- A new interrupt mask: CPU_INTERRUPT_MCE is added to inject the MCE.
aliguori: fix build for linux-user...
preserve the hypervisor bit while KVM trims the CPUID bits
The KVM kernel will disable all bits in CPUID which are not present inthe host. As this is mostly true for the hypervisor bit (1.ecx),preserve its value before the trim and restore it afterwards....
Handle init/sipi in a main cpu exec loop. (v2)
This should fix compilation problem in case of CONFIG_USER_ONLY.
Currently INIT/SIPI is handled in the context of CPU that sends IPI.This patch changes this to handle them like all other events in a maincpu exec loop. When KVM will gain thread per vcpu capability it will...
allow CPUID vendor override
KVM-enabled QEMU will always report the vendor ID of the physical CPU it isrunning on. Allow to override this if explicitly requested on thecommand line. It will not suffice to name a CPU type (like -cpu phenom),but you have to explicitly set the vendor: -cpu phenom,vendor=AuthenticAMD...
x86: Add support for resume flag
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
kvm: x86: Save/restore KVM-specific CPU states
Save and restore all so far neglected KVM-specific CPU states. Handlingthe TSC stabilizes migration in KVM mode. The interrupt_bitmap andmp_state are currently unused, but will become relevant for in-kernel...
kqemu: merge CONFIG_KQEMU and USE_KQEMU
Basically a recursive ":%s/USE_KQEMU/CONFIG_KQEMU/g".
Signed-off-by: Paul Bolle <pebolle@tiscali.nl>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7189 c046a42c-6fe2-441c-8c8c-71466251a162
x86: Enhanced dump of segment registers (Jan Kiszka)
Parse the descriptor flags that segment registers refer to and show theresult in a more human-friendly format. The output of info registers eg.then looks like this:
[...]ES =007b 00000000 ffffffff 00cff300 DPL=3 DS [-WA]...
The _exit syscall is used for both thread termination in NPTL applications,and process termination in legacy applications. Try to guess which we wantbased on the presence of multiple threads.
Also implement locking when modifying the CPU list.
Signed-off-by: Paul Brook <paul@codesourcery.com>...
KVM: CPUID takes ecx as input value for some functions (Amit Shah)
The CPUID instruction takes the value of ECX as an input parameterin addition to the value of EAX as the count for functions 4, 0xband 0xd. Make sure we pass the value to the instruction....
MTRR support on x86, part 2 (Carl-Daniel Hailfinger)
Load and save MTRR state together with machine state.
Add support for the MTRRcap MSR which is used by the latest Bochs BIOSand some operating systems.
Fix a typo in ext2_feature_name.
With this patch, MTRR emulation should be good enough to not trigger any...
MTRR support on x86 (Carl-Daniel Hailfinger)
The current codebase ignores MTRR (Memory Type Range Register)configuration writes and reads because Qemu does not implement caching.All BIOS/firmware in know of for x86 do implement a mode calledCache-as-RAM (CAR) which locks down the CPU cache lines and uses the CPU...
Update FSF address in GPL/LGPL boilerplate
The attached patch updates the FSF address in the GPL/LGPL boilerplatein most GPL/LGPLed files, and also in COPYING.LIB.
Signed-off-by: Stuart Brady <stuart.brady@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>...
x86 cleanup
Remove some unnecessary includes, add needed includes, move prototypes tocpu.h to suppress missing prototype warnings.
Remove unused functions and prototypes (cpu_x86_flush_tlb, cpu_lock,cpu_unlock, restore_native_fp_state, save_native_fp_state)....
x86: Debug register emulation (Jan Kiszka)
Built on top of previously enhanced breakpoint/watchpoint support, thispatch adds full debug register emulation for the x86 architecture.
Many corner cases were considered, and the result was successfullytested inside a Linux guest with gdb, but I won't be surprised if one...
Refactor translation block CPU state handling (Jan Kiszka)
This patch refactors the way the CPU state is handled that is associatedwith a TB. The basic motivation is to move more arch specific code outof generic files. Specifically the long #ifdef clutter in tb_find_fast()...
Convert CPU_PC_FROM_TB to static inline (Jan Kiszka)
as macros should be avoided when possible.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5735 c046a42c-6fe2-441c-8c8c-71466251a162
TCG variable type checking.
Signed-off-by: Paul Brook <paul@codesourcery.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
Add KVM support to QEMU
This patch adds very basic KVM support. KVM is a kernel module for Linux thatallows userspace programs to make use of hardware virtualization support. Itcurrent supports x86 hardware virtualization using Intel VT-x or AMD-V. It...
Split CPUID from op_helper
KVM needs to call CPUID from outside of the TCG code. This patchsplits out the CPUID logic into a separate helper that both the ophelper and KVM can call.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5626 c046a42c-6fe2-441c-8c8c-71466251a162
Add additional CPU flag definitions
Some x86 CPU definitions that KVM needs
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5625 c046a42c-6fe2-441c-8c8c-71466251a162
My core2duo patch introduced a vague statement of "missing features" inthe CPUID specification. This patch addresses this by specifying exactlywhat is missing.While going along the missing CPUID entries I also stumbled acrossinvalid and missing CPUID #defines while comparing them to the Intel...
Fix definition of EMX bit in cpuid (Jens Axboe).
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5330 c046a42c-6fe2-441c-8c8c-71466251a162
SYSENTER/SYSEXIT IA-32e implementation (Alexander Graf).
On Intel CPUs, sysenter and sysexit are valid in 64-bit mode. This patchmakes both 64-bit aware and enables them for Intel CPUs.Add cpu save/load for 64-bit wide sysenter variables.
Signed-off-by: Alexander Graf <agraf@suse.de>...
Core 2 Duo specification (Alexander Graf).
This patch adds a Core 2 Duo CPU to the available CPU types. The CPUdefinition tries to resemble a real CPU as good as possible, whilst notexposing features qemu does not implement.The patch also includes some minor additions that Core 2 Duo CPUs have:...
Clean up vendor identification (Alexander Graf).
Right now CPU vendor identification contains a lot of magic numbers. Thepatch cleans them up to defines, so we can identify the CPU later onwithout copying magic numbers.
Move interrupt_request and user_mode_only to common cpu state.Save and restore env->interrupt_request and env->halted.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4817 c046a42c-6fe2-441c-8c8c-71466251a162
Move CPU save/load registration to common code.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4808 c046a42c-6fe2-441c-8c8c-71466251a162
Add instruction counter.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4799 c046a42c-6fe2-441c-8c8c-71466251a162
save more CPU state
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4669 c046a42c-6fe2-441c-8c8c-71466251a162
SVM: added tsc_offset
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4668 c046a42c-6fe2-441c-8c8c-71466251a162
reworked SVM interrupt handling logic - fixed vmrun EIP saved value - reworked cr8 handling - added CPUState.hflags2
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4662 c046a42c-6fe2-441c-8c8c-71466251a162
EFER loading fixes, including SVME bit
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4659 c046a42c-6fe2-441c-8c8c-71466251a162
Spelling fixes, by Stefan Weil.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4655 c046a42c-6fe2-441c-8c8c-71466251a162
Fix typo.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4624 c046a42c-6fe2-441c-8c8c-71466251a162
Move clone() register setup to target specific code. Handle fork-like clone.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4623 c046a42c-6fe2-441c-8c8c-71466251a162
Push common interrupt variables to cpu-defs.h (Glauber Costa)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4612 c046a42c-6fe2-441c-8c8c-71466251a162