Statistics
| Branch: | Revision:

root / target-arm @ 750813cf

Name Size
Makefile.objs 465 Bytes
arm-semi.c 17.2 kB
cpu-qom.h 5.9 kB
cpu.c 32.5 kB
cpu.h 38.4 kB
cpu64.c 3.5 kB
crypto_helper.c 13 kB
gdbstub.c 2.8 kB
gdbstub64.c 1.9 kB
helper-a64.c 1.9 kB
helper-a64.h 1.1 kB
helper.c 139.4 kB
helper.h 17.4 kB
iwmmxt_helper.c 24.8 kB
kvm-consts.h 3.8 kB
kvm-stub.c 437 Bytes
kvm.c 9.4 kB
kvm32.c 15.7 kB
kvm64.c 5.2 kB
kvm_arm.h 3.8 kB
machine.c 7.9 kB
neon_helper.c 52.8 kB
op_addsub.h 1.8 kB
op_helper.c 8.9 kB
translate-a64.c 98.2 kB
translate.c 365.8 kB
translate.h 1.9 kB

Latest revisions

# Date Author Comment
643dbb07 01/08/2014 09:07 pm Claudio Fontana

target-arm: A64: add support for add/sub with carry

This patch adds support for C3.5.3 Add/subtract (with carry):
instructions ADC, ADCS, SBC, SBCS.

Signed-off-by: Claudio Fontana <>
Signed-off-by: Peter Maydell <>...
750813cf 01/08/2014 09:07 pm Claudio Fontana

target-arm: A64: add support for conditional compare insns

this patch adds support for C3.5.4 - C3.5.5
Conditional compare (both immediate and register)

Signed-off-by: Claudio Fontana <>
Signed-off-by: Peter Maydell <>...
b0d2b7d0 01/07/2014 09:17 pm Peter Maydell

target-arm: A64: Implement minimal set of EL0-visible sysregs

Implement an initial minimal set of EL0-visible system registers: * NZCV * FPCR * FPSR * CTR_EL0 * DCZID_EL0

Signed-off-by: Peter Maydell <>
Reviewed-by: Richard Henderson <>...
e4fe830b 01/07/2014 09:17 pm Peter Maydell

target-arm: Widen thread-local register state fields to 64 bits

The common pattern for system registers in a 64-bit capable ARM
CPU is that when in AArch32 the cp15 register is a view of the
bottom 32 bits of the 64-bit AArch64 system register; writes in...
60322b39 01/07/2014 09:17 pm Peter Maydell

target-arm: Remove ARMCPU/CPUARMState from cpregs APIs used by decoder

The cpregs APIs used by the decoder (get_arm_cp_reginfo() and
cp_access_ok()) currently take either a CPUARMState* or an ARMCPU*.
This is problematic for the A64 decoder, which doesn't pass the...
fea50522 01/07/2014 09:17 pm Peter Maydell

target-arm: A64: Implement MRS/MSR/SYS/SYSL

The AArch64 equivalent of the traditional AArch32
cp15 coprocessor registers is the set of instructions
MRS/MSR/SYS/SYSL, which cover between them both true
system registers and the "operations with side effects"...
6e6efd61 01/05/2014 12:15 am Peter Maydell

target-arm: Pull "add one cpreg to hashtable" into its own function

define_one_arm_cp_reg_with_opaque() has a set of nested loops which
insert a cpreg entry into the hashtable for each of the possible
opc/crn/crm values allowed by wildcard specifications. We're about...
f5a0a5a5 01/05/2014 12:15 am Peter Maydell

target-arm: Update generic cpreg code for AArch64

Update the generic cpreg support code to also handle AArch64:
AArch64-visible registers coexist in the same hash table with
AArch32-visible ones, with a bit in the hash key distinguishing
them.

Signed-off-by: Peter Maydell <>...
ce5458e8 12/24/2013 01:27 am Peter Maydell

target-arm: A64: implement FMOV

Implement FMOV, ie non-converting moves between general purpose
registers and floating point registers. This is a subtype of
the floating point <-> integer instruction class.

Signed-off-by: Peter Maydell <>...
faa0ba46 12/24/2013 01:27 am Peter Maydell

target-arm: A64: Add decoder skeleton for FP instructions

Add a top level decoder skeleton for FP instructions.

Signed-off-by: Peter Maydell <>
Reviewed-by: Richard Henderson <>

View revisions

Also available in: Atom