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Name Size
  core-dc232b
  core-dc233c
  core-fsf
Makefile.objs 172 Bytes
core-dc232b.c 2.1 kB
core-dc233c.c 2.1 kB
core-fsf.c 2 kB
cpu-qom.h 2.6 kB
cpu.c 3 kB
cpu.h 13.2 kB
helper.c 19.3 kB
helper.h 1.5 kB
machine.c 1.7 kB
op_helper.c 22.3 kB
overlay_tool.h 16.8 kB
translate.c 84.3 kB
xtensa-semi.c 6.7 kB

Latest revisions

# Date Author Comment
7ff7563f 07/28/2012 12:06 pm Max Filippov

target-xtensa: fix big-endian BBS/BBC implementation

Quote from ISA, 2.1:

For most Xtensa instructions, bit numbering is irrelevant; only the BBC
and BBS instructions assign bit numbers to values on which the processor
operates. The BBC/BBS instructions use big-endian bit ordering (0 is the...
f492b82d 06/10/2012 11:09 pm Max Filippov

target-xtensa: switch to AREG0-free mode

Add env parameter to every helper function that needs it, update
'configure' script.

Signed-off-by: Max Filippov <>
Signed-off-by: Blue Swirl <>
e8de1ea8 06/10/2012 11:09 pm Max Filippov

target-xtensa: add attributes to helper functions

Mark exception generating functions 'noreturn' and pure constant
functions as such.

Signed-off-by: Max Filippov <>
Signed-off-by: Blue Swirl <>
9ed3a188 06/10/2012 11:09 pm Peter Portante

target-xtensa: remove unnecessary include of dyngen-exec.h

Signed-off-by: Peter Portante <>
Signed-off-by: Max Filippov <>
Signed-off-by: Blue Swirl <>
d865f307 06/09/2012 01:49 pm Max Filippov

target-xtensa: fix CCOUNT for conditional branches

Taken conditional branches fail to update CCOUNT register because
accumulated ccount_delta is reset during translation of non-taken
branch. To fix it only update CCOUNT once per conditional branch
instruction translation....
e323bdef 06/09/2012 01:45 pm Max Filippov

target-xtensa: flush TLB page for new MMU mapping

Both old and new mappings need flushing because their VPN may be
different in MMU case.

Signed-off-by: Max Filippov <>
Signed-off-by: Blue Swirl <>
39e7d37f 06/09/2012 01:45 pm Max Filippov

target-xtensa: update EXCVADDR in case of page table lookup

According to ISA, 4.4.2.6, EXCVADDR may be changed by any TLB miss, even
if the miss is handled entirely by processor hardware.

Signed-off-by: Max Filippov <>
Signed-off-by: Blue Swirl <>
16bde77a 06/09/2012 01:45 pm Max Filippov

target-xtensa: extract TLB entry setting method

Signed-off-by: Max Filippov <>
Signed-off-by: Blue Swirl <>
ae4e7982 06/09/2012 01:45 pm Max Filippov

target-xtensa: update autorefill TLB entries conditionally

This is to avoid interference of internal QEMU helpers
(cpu_get_phys_page_debug, tb_invalidate_virtual_addr) with guest-visible
TLB state.

Signed-off-by: Max Filippov <>
Signed-off-by: Blue Swirl <>
57705a67 06/09/2012 01:45 pm Max Filippov

target-xtensa: control page table lookup explicitly

Hardware pagetable walking may not be nested. Stop guessing and pass
explicit flag to the get_physical_addr_mmu function that controls page
table lookup.

Signed-off-by: Max Filippov <>...

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