root / tcg / sparc / tcg-target.c @ 79383c9c
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1 | 8289b279 | blueswir1 | /*
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2 | 8289b279 | blueswir1 | * Tiny Code Generator for QEMU
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3 | 8289b279 | blueswir1 | *
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4 | 8289b279 | blueswir1 | * Copyright (c) 2008 Fabrice Bellard
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5 | 8289b279 | blueswir1 | *
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6 | 8289b279 | blueswir1 | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 8289b279 | blueswir1 | * of this software and associated documentation files (the "Software"), to deal
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8 | 8289b279 | blueswir1 | * in the Software without restriction, including without limitation the rights
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9 | 8289b279 | blueswir1 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 8289b279 | blueswir1 | * copies of the Software, and to permit persons to whom the Software is
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11 | 8289b279 | blueswir1 | * furnished to do so, subject to the following conditions:
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12 | 8289b279 | blueswir1 | *
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13 | 8289b279 | blueswir1 | * The above copyright notice and this permission notice shall be included in
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14 | 8289b279 | blueswir1 | * all copies or substantial portions of the Software.
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15 | 8289b279 | blueswir1 | *
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16 | 8289b279 | blueswir1 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 8289b279 | blueswir1 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 8289b279 | blueswir1 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 8289b279 | blueswir1 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 8289b279 | blueswir1 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 8289b279 | blueswir1 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 8289b279 | blueswir1 | * THE SOFTWARE.
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23 | 8289b279 | blueswir1 | */
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24 | 8289b279 | blueswir1 | |
25 | 8289b279 | blueswir1 | static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { |
26 | 8289b279 | blueswir1 | "%g0",
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27 | 8289b279 | blueswir1 | "%g1",
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28 | 8289b279 | blueswir1 | "%g2",
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29 | 8289b279 | blueswir1 | "%g3",
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30 | 8289b279 | blueswir1 | "%g4",
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31 | 8289b279 | blueswir1 | "%g5",
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32 | 8289b279 | blueswir1 | "%g6",
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33 | 8289b279 | blueswir1 | "%g7",
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34 | 8289b279 | blueswir1 | "%o0",
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35 | 8289b279 | blueswir1 | "%o1",
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36 | 8289b279 | blueswir1 | "%o2",
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37 | 8289b279 | blueswir1 | "%o3",
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38 | 8289b279 | blueswir1 | "%o4",
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39 | 8289b279 | blueswir1 | "%o5",
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40 | 8289b279 | blueswir1 | "%o6",
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41 | 8289b279 | blueswir1 | "%o7",
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42 | 8289b279 | blueswir1 | "%l0",
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43 | 8289b279 | blueswir1 | "%l1",
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44 | 8289b279 | blueswir1 | "%l2",
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45 | 8289b279 | blueswir1 | "%l3",
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46 | 8289b279 | blueswir1 | "%l4",
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47 | 8289b279 | blueswir1 | "%l5",
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48 | 8289b279 | blueswir1 | "%l6",
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49 | 8289b279 | blueswir1 | "%l7",
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50 | 8289b279 | blueswir1 | "%i0",
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51 | 8289b279 | blueswir1 | "%i1",
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52 | 8289b279 | blueswir1 | "%i2",
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53 | 8289b279 | blueswir1 | "%i3",
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54 | 8289b279 | blueswir1 | "%i4",
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55 | 8289b279 | blueswir1 | "%i5",
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56 | 8289b279 | blueswir1 | "%i6",
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57 | 8289b279 | blueswir1 | "%i7",
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58 | 8289b279 | blueswir1 | }; |
59 | 8289b279 | blueswir1 | |
60 | 0954d0d9 | blueswir1 | static const int tcg_target_reg_alloc_order[] = { |
61 | 8289b279 | blueswir1 | TCG_REG_L0, |
62 | 8289b279 | blueswir1 | TCG_REG_L1, |
63 | 8289b279 | blueswir1 | TCG_REG_L2, |
64 | 8289b279 | blueswir1 | TCG_REG_L3, |
65 | 8289b279 | blueswir1 | TCG_REG_L4, |
66 | 8289b279 | blueswir1 | TCG_REG_L5, |
67 | 8289b279 | blueswir1 | TCG_REG_L6, |
68 | 8289b279 | blueswir1 | TCG_REG_L7, |
69 | 8289b279 | blueswir1 | TCG_REG_I0, |
70 | 8289b279 | blueswir1 | TCG_REG_I1, |
71 | 8289b279 | blueswir1 | TCG_REG_I2, |
72 | 8289b279 | blueswir1 | TCG_REG_I3, |
73 | 8289b279 | blueswir1 | TCG_REG_I4, |
74 | 8289b279 | blueswir1 | }; |
75 | 8289b279 | blueswir1 | |
76 | 8289b279 | blueswir1 | static const int tcg_target_call_iarg_regs[6] = { |
77 | 8289b279 | blueswir1 | TCG_REG_O0, |
78 | 8289b279 | blueswir1 | TCG_REG_O1, |
79 | 8289b279 | blueswir1 | TCG_REG_O2, |
80 | 8289b279 | blueswir1 | TCG_REG_O3, |
81 | 8289b279 | blueswir1 | TCG_REG_O4, |
82 | 8289b279 | blueswir1 | TCG_REG_O5, |
83 | 8289b279 | blueswir1 | }; |
84 | 8289b279 | blueswir1 | |
85 | 8289b279 | blueswir1 | static const int tcg_target_call_oarg_regs[2] = { |
86 | 8289b279 | blueswir1 | TCG_REG_O0, |
87 | 8289b279 | blueswir1 | TCG_REG_O1, |
88 | 8289b279 | blueswir1 | }; |
89 | 8289b279 | blueswir1 | |
90 | 57e49b40 | blueswir1 | static inline int check_fit_tl(tcg_target_long val, unsigned int bits) |
91 | f5ef6aac | blueswir1 | { |
92 | 57e49b40 | blueswir1 | return (val << ((sizeof(tcg_target_long) * 8 - bits)) |
93 | 57e49b40 | blueswir1 | >> (sizeof(tcg_target_long) * 8 - bits)) == val; |
94 | 57e49b40 | blueswir1 | } |
95 | 57e49b40 | blueswir1 | |
96 | 57e49b40 | blueswir1 | static inline int check_fit_i32(uint32_t val, unsigned int bits) |
97 | 57e49b40 | blueswir1 | { |
98 | 57e49b40 | blueswir1 | return ((val << (32 - bits)) >> (32 - bits)) == val; |
99 | f5ef6aac | blueswir1 | } |
100 | f5ef6aac | blueswir1 | |
101 | 8289b279 | blueswir1 | static void patch_reloc(uint8_t *code_ptr, int type, |
102 | f54b3f92 | aurel32 | tcg_target_long value, tcg_target_long addend) |
103 | 8289b279 | blueswir1 | { |
104 | f54b3f92 | aurel32 | value += addend; |
105 | 8289b279 | blueswir1 | switch (type) {
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106 | 8289b279 | blueswir1 | case R_SPARC_32:
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107 | 8289b279 | blueswir1 | if (value != (uint32_t)value)
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108 | 8289b279 | blueswir1 | tcg_abort(); |
109 | 8289b279 | blueswir1 | *(uint32_t *)code_ptr = value; |
110 | 8289b279 | blueswir1 | break;
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111 | f5ef6aac | blueswir1 | case R_SPARC_WDISP22:
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112 | f5ef6aac | blueswir1 | value -= (long)code_ptr;
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113 | f5ef6aac | blueswir1 | value >>= 2;
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114 | 57e49b40 | blueswir1 | if (!check_fit_tl(value, 22)) |
115 | f5ef6aac | blueswir1 | tcg_abort(); |
116 | f5ef6aac | blueswir1 | *(uint32_t *)code_ptr = ((*(uint32_t *)code_ptr) & ~0x3fffff) | value;
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117 | f5ef6aac | blueswir1 | break;
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118 | 8289b279 | blueswir1 | default:
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119 | 8289b279 | blueswir1 | tcg_abort(); |
120 | 8289b279 | blueswir1 | } |
121 | 8289b279 | blueswir1 | } |
122 | 8289b279 | blueswir1 | |
123 | 8289b279 | blueswir1 | /* maximum number of register used for input function arguments */
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124 | 8289b279 | blueswir1 | static inline int tcg_target_get_call_iarg_regs_count(int flags) |
125 | 8289b279 | blueswir1 | { |
126 | 8289b279 | blueswir1 | return 6; |
127 | 8289b279 | blueswir1 | } |
128 | 8289b279 | blueswir1 | |
129 | 8289b279 | blueswir1 | /* parse target specific constraints */
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130 | 8289b279 | blueswir1 | static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str) |
131 | 8289b279 | blueswir1 | { |
132 | 8289b279 | blueswir1 | const char *ct_str; |
133 | 8289b279 | blueswir1 | |
134 | 8289b279 | blueswir1 | ct_str = *pct_str; |
135 | 8289b279 | blueswir1 | switch (ct_str[0]) { |
136 | 8289b279 | blueswir1 | case 'r': |
137 | 8289b279 | blueswir1 | case 'L': /* qemu_ld/st constraint */ |
138 | 8289b279 | blueswir1 | ct->ct |= TCG_CT_REG; |
139 | 8289b279 | blueswir1 | tcg_regset_set32(ct->u.regs, 0, 0xffffffff); |
140 | 53c37487 | blueswir1 | // Helper args
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141 | 53c37487 | blueswir1 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_O0); |
142 | 53c37487 | blueswir1 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_O1); |
143 | 53c37487 | blueswir1 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_O2); |
144 | 8289b279 | blueswir1 | break;
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145 | 8289b279 | blueswir1 | case 'I': |
146 | 8289b279 | blueswir1 | ct->ct |= TCG_CT_CONST_S11; |
147 | 8289b279 | blueswir1 | break;
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148 | 8289b279 | blueswir1 | case 'J': |
149 | 8289b279 | blueswir1 | ct->ct |= TCG_CT_CONST_S13; |
150 | 8289b279 | blueswir1 | break;
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151 | 8289b279 | blueswir1 | default:
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152 | 8289b279 | blueswir1 | return -1; |
153 | 8289b279 | blueswir1 | } |
154 | 8289b279 | blueswir1 | ct_str++; |
155 | 8289b279 | blueswir1 | *pct_str = ct_str; |
156 | 8289b279 | blueswir1 | return 0; |
157 | 8289b279 | blueswir1 | } |
158 | 8289b279 | blueswir1 | |
159 | 8289b279 | blueswir1 | /* test if a constant matches the constraint */
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160 | 8289b279 | blueswir1 | static inline int tcg_target_const_match(tcg_target_long val, |
161 | 8289b279 | blueswir1 | const TCGArgConstraint *arg_ct)
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162 | 8289b279 | blueswir1 | { |
163 | 8289b279 | blueswir1 | int ct;
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164 | 8289b279 | blueswir1 | |
165 | 8289b279 | blueswir1 | ct = arg_ct->ct; |
166 | 8289b279 | blueswir1 | if (ct & TCG_CT_CONST)
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167 | 8289b279 | blueswir1 | return 1; |
168 | 57e49b40 | blueswir1 | else if ((ct & TCG_CT_CONST_S11) && check_fit_tl(val, 11)) |
169 | 8289b279 | blueswir1 | return 1; |
170 | 57e49b40 | blueswir1 | else if ((ct & TCG_CT_CONST_S13) && check_fit_tl(val, 13)) |
171 | 8289b279 | blueswir1 | return 1; |
172 | 8289b279 | blueswir1 | else
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173 | 8289b279 | blueswir1 | return 0; |
174 | 8289b279 | blueswir1 | } |
175 | 8289b279 | blueswir1 | |
176 | 8289b279 | blueswir1 | #define INSN_OP(x) ((x) << 30) |
177 | 8289b279 | blueswir1 | #define INSN_OP2(x) ((x) << 22) |
178 | 8289b279 | blueswir1 | #define INSN_OP3(x) ((x) << 19) |
179 | 8289b279 | blueswir1 | #define INSN_OPF(x) ((x) << 5) |
180 | 8289b279 | blueswir1 | #define INSN_RD(x) ((x) << 25) |
181 | 8289b279 | blueswir1 | #define INSN_RS1(x) ((x) << 14) |
182 | 8289b279 | blueswir1 | #define INSN_RS2(x) (x)
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183 | 8384dd67 | blueswir1 | #define INSN_ASI(x) ((x) << 5) |
184 | 8289b279 | blueswir1 | |
185 | 8289b279 | blueswir1 | #define INSN_IMM13(x) ((1 << 13) | ((x) & 0x1fff)) |
186 | b3db8758 | blueswir1 | #define INSN_OFF22(x) (((x) >> 2) & 0x3fffff) |
187 | 8289b279 | blueswir1 | |
188 | b3db8758 | blueswir1 | #define INSN_COND(x, a) (((x) << 25) | ((a) << 29)) |
189 | cf7c2ca5 | blueswir1 | #define COND_N 0x0 |
190 | cf7c2ca5 | blueswir1 | #define COND_E 0x1 |
191 | cf7c2ca5 | blueswir1 | #define COND_LE 0x2 |
192 | cf7c2ca5 | blueswir1 | #define COND_L 0x3 |
193 | cf7c2ca5 | blueswir1 | #define COND_LEU 0x4 |
194 | cf7c2ca5 | blueswir1 | #define COND_CS 0x5 |
195 | cf7c2ca5 | blueswir1 | #define COND_NEG 0x6 |
196 | cf7c2ca5 | blueswir1 | #define COND_VS 0x7 |
197 | b3db8758 | blueswir1 | #define COND_A 0x8 |
198 | cf7c2ca5 | blueswir1 | #define COND_NE 0x9 |
199 | cf7c2ca5 | blueswir1 | #define COND_G 0xa |
200 | cf7c2ca5 | blueswir1 | #define COND_GE 0xb |
201 | cf7c2ca5 | blueswir1 | #define COND_GU 0xc |
202 | cf7c2ca5 | blueswir1 | #define COND_CC 0xd |
203 | cf7c2ca5 | blueswir1 | #define COND_POS 0xe |
204 | cf7c2ca5 | blueswir1 | #define COND_VC 0xf |
205 | b3db8758 | blueswir1 | #define BA (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2)) |
206 | 8289b279 | blueswir1 | |
207 | 8289b279 | blueswir1 | #define ARITH_ADD (INSN_OP(2) | INSN_OP3(0x00)) |
208 | 8289b279 | blueswir1 | #define ARITH_AND (INSN_OP(2) | INSN_OP3(0x01)) |
209 | 8289b279 | blueswir1 | #define ARITH_OR (INSN_OP(2) | INSN_OP3(0x02)) |
210 | 9a7f3228 | blueswir1 | #define ARITH_ORCC (INSN_OP(2) | INSN_OP3(0x12)) |
211 | 8289b279 | blueswir1 | #define ARITH_XOR (INSN_OP(2) | INSN_OP3(0x03)) |
212 | f5ef6aac | blueswir1 | #define ARITH_SUB (INSN_OP(2) | INSN_OP3(0x04)) |
213 | f5ef6aac | blueswir1 | #define ARITH_SUBCC (INSN_OP(2) | INSN_OP3(0x14)) |
214 | 8289b279 | blueswir1 | #define ARITH_ADDX (INSN_OP(2) | INSN_OP3(0x10)) |
215 | 8289b279 | blueswir1 | #define ARITH_SUBX (INSN_OP(2) | INSN_OP3(0x0c)) |
216 | 8289b279 | blueswir1 | #define ARITH_UMUL (INSN_OP(2) | INSN_OP3(0x0a)) |
217 | 8289b279 | blueswir1 | #define ARITH_UDIV (INSN_OP(2) | INSN_OP3(0x0e)) |
218 | 8289b279 | blueswir1 | #define ARITH_SDIV (INSN_OP(2) | INSN_OP3(0x0f)) |
219 | 8289b279 | blueswir1 | #define ARITH_MULX (INSN_OP(2) | INSN_OP3(0x09)) |
220 | 8289b279 | blueswir1 | #define ARITH_UDIVX (INSN_OP(2) | INSN_OP3(0x0d)) |
221 | 8289b279 | blueswir1 | #define ARITH_SDIVX (INSN_OP(2) | INSN_OP3(0x2d)) |
222 | 8289b279 | blueswir1 | |
223 | 8289b279 | blueswir1 | #define SHIFT_SLL (INSN_OP(2) | INSN_OP3(0x25)) |
224 | 8289b279 | blueswir1 | #define SHIFT_SRL (INSN_OP(2) | INSN_OP3(0x26)) |
225 | 8289b279 | blueswir1 | #define SHIFT_SRA (INSN_OP(2) | INSN_OP3(0x27)) |
226 | 8289b279 | blueswir1 | |
227 | 8289b279 | blueswir1 | #define SHIFT_SLLX (INSN_OP(2) | INSN_OP3(0x25) | (1 << 12)) |
228 | 8289b279 | blueswir1 | #define SHIFT_SRLX (INSN_OP(2) | INSN_OP3(0x26) | (1 << 12)) |
229 | 8289b279 | blueswir1 | #define SHIFT_SRAX (INSN_OP(2) | INSN_OP3(0x27) | (1 << 12)) |
230 | 8289b279 | blueswir1 | |
231 | 8289b279 | blueswir1 | #define WRY (INSN_OP(2) | INSN_OP3(0x30)) |
232 | 8289b279 | blueswir1 | #define JMPL (INSN_OP(2) | INSN_OP3(0x38)) |
233 | 8289b279 | blueswir1 | #define SAVE (INSN_OP(2) | INSN_OP3(0x3c)) |
234 | 8289b279 | blueswir1 | #define RESTORE (INSN_OP(2) | INSN_OP3(0x3d)) |
235 | 8289b279 | blueswir1 | #define SETHI (INSN_OP(0) | INSN_OP2(0x4)) |
236 | 8289b279 | blueswir1 | #define CALL INSN_OP(1) |
237 | 8289b279 | blueswir1 | #define LDUB (INSN_OP(3) | INSN_OP3(0x01)) |
238 | 8289b279 | blueswir1 | #define LDSB (INSN_OP(3) | INSN_OP3(0x09)) |
239 | 8289b279 | blueswir1 | #define LDUH (INSN_OP(3) | INSN_OP3(0x02)) |
240 | 8289b279 | blueswir1 | #define LDSH (INSN_OP(3) | INSN_OP3(0x0a)) |
241 | 8289b279 | blueswir1 | #define LDUW (INSN_OP(3) | INSN_OP3(0x00)) |
242 | 8289b279 | blueswir1 | #define LDSW (INSN_OP(3) | INSN_OP3(0x08)) |
243 | 8289b279 | blueswir1 | #define LDX (INSN_OP(3) | INSN_OP3(0x0b)) |
244 | 8289b279 | blueswir1 | #define STB (INSN_OP(3) | INSN_OP3(0x05)) |
245 | 8289b279 | blueswir1 | #define STH (INSN_OP(3) | INSN_OP3(0x06)) |
246 | 8289b279 | blueswir1 | #define STW (INSN_OP(3) | INSN_OP3(0x04)) |
247 | 8289b279 | blueswir1 | #define STX (INSN_OP(3) | INSN_OP3(0x0e)) |
248 | 8384dd67 | blueswir1 | #define LDUBA (INSN_OP(3) | INSN_OP3(0x11)) |
249 | 8384dd67 | blueswir1 | #define LDSBA (INSN_OP(3) | INSN_OP3(0x19)) |
250 | 8384dd67 | blueswir1 | #define LDUHA (INSN_OP(3) | INSN_OP3(0x12)) |
251 | 8384dd67 | blueswir1 | #define LDSHA (INSN_OP(3) | INSN_OP3(0x1a)) |
252 | 8384dd67 | blueswir1 | #define LDUWA (INSN_OP(3) | INSN_OP3(0x10)) |
253 | 8384dd67 | blueswir1 | #define LDSWA (INSN_OP(3) | INSN_OP3(0x18)) |
254 | 8384dd67 | blueswir1 | #define LDXA (INSN_OP(3) | INSN_OP3(0x1b)) |
255 | 8384dd67 | blueswir1 | #define STBA (INSN_OP(3) | INSN_OP3(0x15)) |
256 | 8384dd67 | blueswir1 | #define STHA (INSN_OP(3) | INSN_OP3(0x16)) |
257 | 8384dd67 | blueswir1 | #define STWA (INSN_OP(3) | INSN_OP3(0x14)) |
258 | 8384dd67 | blueswir1 | #define STXA (INSN_OP(3) | INSN_OP3(0x1e)) |
259 | 8384dd67 | blueswir1 | |
260 | 8384dd67 | blueswir1 | #ifndef ASI_PRIMARY_LITTLE
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261 | 8384dd67 | blueswir1 | #define ASI_PRIMARY_LITTLE 0x88 |
262 | 8384dd67 | blueswir1 | #endif
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263 | 8289b279 | blueswir1 | |
264 | 26cc915c | blueswir1 | static inline void tcg_out_arith(TCGContext *s, int rd, int rs1, int rs2, |
265 | 26cc915c | blueswir1 | int op)
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266 | 26cc915c | blueswir1 | { |
267 | 26cc915c | blueswir1 | tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | |
268 | 26cc915c | blueswir1 | INSN_RS2(rs2)); |
269 | 26cc915c | blueswir1 | } |
270 | 26cc915c | blueswir1 | |
271 | 6f41b777 | blueswir1 | static inline void tcg_out_arithi(TCGContext *s, int rd, int rs1, |
272 | 6f41b777 | blueswir1 | uint32_t offset, int op)
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273 | 26cc915c | blueswir1 | { |
274 | 26cc915c | blueswir1 | tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | |
275 | 26cc915c | blueswir1 | INSN_IMM13(offset)); |
276 | 26cc915c | blueswir1 | } |
277 | 26cc915c | blueswir1 | |
278 | 8289b279 | blueswir1 | static inline void tcg_out_mov(TCGContext *s, int ret, int arg) |
279 | 8289b279 | blueswir1 | { |
280 | 26cc915c | blueswir1 | tcg_out_arith(s, ret, arg, TCG_REG_G0, ARITH_OR); |
281 | 26cc915c | blueswir1 | } |
282 | 26cc915c | blueswir1 | |
283 | 26cc915c | blueswir1 | static inline void tcg_out_sethi(TCGContext *s, int ret, uint32_t arg) |
284 | 26cc915c | blueswir1 | { |
285 | 26cc915c | blueswir1 | tcg_out32(s, SETHI | INSN_RD(ret) | ((arg & 0xfffffc00) >> 10)); |
286 | 8289b279 | blueswir1 | } |
287 | 8289b279 | blueswir1 | |
288 | b101234a | blueswir1 | static inline void tcg_out_movi_imm13(TCGContext *s, int ret, uint32_t arg) |
289 | b101234a | blueswir1 | { |
290 | b101234a | blueswir1 | tcg_out_arithi(s, ret, TCG_REG_G0, arg, ARITH_OR); |
291 | b101234a | blueswir1 | } |
292 | b101234a | blueswir1 | |
293 | b101234a | blueswir1 | static inline void tcg_out_movi_imm32(TCGContext *s, int ret, uint32_t arg) |
294 | 8289b279 | blueswir1 | { |
295 | 6f41b777 | blueswir1 | if (check_fit_tl(arg, 12)) |
296 | b101234a | blueswir1 | tcg_out_movi_imm13(s, ret, arg); |
297 | 8289b279 | blueswir1 | else {
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298 | 26cc915c | blueswir1 | tcg_out_sethi(s, ret, arg); |
299 | 8289b279 | blueswir1 | if (arg & 0x3ff) |
300 | b101234a | blueswir1 | tcg_out_arithi(s, ret, ret, arg & 0x3ff, ARITH_OR);
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301 | 8289b279 | blueswir1 | } |
302 | 8289b279 | blueswir1 | } |
303 | 8289b279 | blueswir1 | |
304 | b101234a | blueswir1 | static inline void tcg_out_movi(TCGContext *s, TCGType type, |
305 | b101234a | blueswir1 | int ret, tcg_target_long arg)
|
306 | b101234a | blueswir1 | { |
307 | b101234a | blueswir1 | #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
|
308 | b101234a | blueswir1 | if (!check_fit_tl(arg, 32) && (arg & ~0xffffffffULL) != 0) { |
309 | d795eb86 | blueswir1 | tcg_out_movi_imm32(s, TCG_REG_I4, arg >> 32);
|
310 | d795eb86 | blueswir1 | tcg_out_arithi(s, TCG_REG_I4, TCG_REG_I4, 32, SHIFT_SLLX);
|
311 | b101234a | blueswir1 | tcg_out_movi_imm32(s, ret, arg); |
312 | d795eb86 | blueswir1 | tcg_out_arith(s, ret, ret, TCG_REG_I4, ARITH_OR); |
313 | 6f41b777 | blueswir1 | } else if (check_fit_tl(arg, 12)) |
314 | 6f41b777 | blueswir1 | tcg_out_movi_imm13(s, ret, arg); |
315 | 6f41b777 | blueswir1 | else {
|
316 | 6f41b777 | blueswir1 | tcg_out_sethi(s, ret, arg); |
317 | 6f41b777 | blueswir1 | if (arg & 0x3ff) |
318 | 6f41b777 | blueswir1 | tcg_out_arithi(s, ret, ret, arg & 0x3ff, ARITH_OR);
|
319 | 6f41b777 | blueswir1 | } |
320 | 6f41b777 | blueswir1 | #else
|
321 | 6f41b777 | blueswir1 | tcg_out_movi_imm32(s, ret, arg); |
322 | b101234a | blueswir1 | #endif
|
323 | b101234a | blueswir1 | } |
324 | b101234a | blueswir1 | |
325 | 8289b279 | blueswir1 | static inline void tcg_out_ld_raw(TCGContext *s, int ret, |
326 | 8289b279 | blueswir1 | tcg_target_long arg) |
327 | 8289b279 | blueswir1 | { |
328 | 26cc915c | blueswir1 | tcg_out_sethi(s, ret, arg); |
329 | 8289b279 | blueswir1 | tcg_out32(s, LDUW | INSN_RD(ret) | INSN_RS1(ret) | |
330 | 8289b279 | blueswir1 | INSN_IMM13(arg & 0x3ff));
|
331 | 8289b279 | blueswir1 | } |
332 | 8289b279 | blueswir1 | |
333 | b3db8758 | blueswir1 | static inline void tcg_out_ld_ptr(TCGContext *s, int ret, |
334 | b3db8758 | blueswir1 | tcg_target_long arg) |
335 | b3db8758 | blueswir1 | { |
336 | b101234a | blueswir1 | if (!check_fit_tl(arg, 10)) |
337 | b101234a | blueswir1 | tcg_out_movi(s, TCG_TYPE_PTR, ret, arg & ~0x3ffULL);
|
338 | b3db8758 | blueswir1 | #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
|
339 | b3db8758 | blueswir1 | tcg_out32(s, LDX | INSN_RD(ret) | INSN_RS1(ret) | |
340 | b3db8758 | blueswir1 | INSN_IMM13(arg & 0x3ff));
|
341 | b3db8758 | blueswir1 | #else
|
342 | b101234a | blueswir1 | tcg_out32(s, LDUW | INSN_RD(ret) | INSN_RS1(ret) | |
343 | b101234a | blueswir1 | INSN_IMM13(arg & 0x3ff));
|
344 | b3db8758 | blueswir1 | #endif
|
345 | b3db8758 | blueswir1 | } |
346 | b3db8758 | blueswir1 | |
347 | 8289b279 | blueswir1 | static inline void tcg_out_ldst(TCGContext *s, int ret, int addr, int offset, int op) |
348 | 8289b279 | blueswir1 | { |
349 | 57e49b40 | blueswir1 | if (check_fit_tl(offset, 13)) |
350 | 8289b279 | blueswir1 | tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(addr) | |
351 | 8289b279 | blueswir1 | INSN_IMM13(offset)); |
352 | cf7c2ca5 | blueswir1 | else {
|
353 | cf7c2ca5 | blueswir1 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, offset); |
354 | cf7c2ca5 | blueswir1 | tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(TCG_REG_I5) | |
355 | cf7c2ca5 | blueswir1 | INSN_RS2(addr)); |
356 | cf7c2ca5 | blueswir1 | } |
357 | 8289b279 | blueswir1 | } |
358 | 8289b279 | blueswir1 | |
359 | 8384dd67 | blueswir1 | static inline void tcg_out_ldst_asi(TCGContext *s, int ret, int addr, |
360 | 8384dd67 | blueswir1 | int offset, int op, int asi) |
361 | 8384dd67 | blueswir1 | { |
362 | 8384dd67 | blueswir1 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, offset); |
363 | 8384dd67 | blueswir1 | tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(TCG_REG_I5) | |
364 | 8384dd67 | blueswir1 | INSN_ASI(asi) | INSN_RS2(addr)); |
365 | 8384dd67 | blueswir1 | } |
366 | 8384dd67 | blueswir1 | |
367 | e4d5434c | blueswir1 | static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret, |
368 | 8289b279 | blueswir1 | int arg1, tcg_target_long arg2)
|
369 | 8289b279 | blueswir1 | { |
370 | 7d551702 | blueswir1 | if (type == TCG_TYPE_I32)
|
371 | 7d551702 | blueswir1 | tcg_out_ldst(s, ret, arg1, arg2, LDUW); |
372 | 7d551702 | blueswir1 | else
|
373 | 7d551702 | blueswir1 | tcg_out_ldst(s, ret, arg1, arg2, LDX); |
374 | 8289b279 | blueswir1 | } |
375 | 8289b279 | blueswir1 | |
376 | e4d5434c | blueswir1 | static inline void tcg_out_st(TCGContext *s, TCGType type, int arg, |
377 | 8289b279 | blueswir1 | int arg1, tcg_target_long arg2)
|
378 | 8289b279 | blueswir1 | { |
379 | 7d551702 | blueswir1 | if (type == TCG_TYPE_I32)
|
380 | 7d551702 | blueswir1 | tcg_out_ldst(s, arg, arg1, arg2, STW); |
381 | 7d551702 | blueswir1 | else
|
382 | 7d551702 | blueswir1 | tcg_out_ldst(s, arg, arg1, arg2, STX); |
383 | 8289b279 | blueswir1 | } |
384 | 8289b279 | blueswir1 | |
385 | 8289b279 | blueswir1 | static inline void tcg_out_sety(TCGContext *s, tcg_target_long val) |
386 | 8289b279 | blueswir1 | { |
387 | 8289b279 | blueswir1 | if (val == 0 || val == -1) |
388 | 8289b279 | blueswir1 | tcg_out32(s, WRY | INSN_IMM13(val)); |
389 | 8289b279 | blueswir1 | else
|
390 | 8289b279 | blueswir1 | fprintf(stderr, "unimplemented sety %ld\n", (long)val); |
391 | 8289b279 | blueswir1 | } |
392 | 8289b279 | blueswir1 | |
393 | 8289b279 | blueswir1 | static inline void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val) |
394 | 8289b279 | blueswir1 | { |
395 | 8289b279 | blueswir1 | if (val != 0) { |
396 | 57e49b40 | blueswir1 | if (check_fit_tl(val, 13)) |
397 | 8289b279 | blueswir1 | tcg_out_arithi(s, reg, reg, val, ARITH_ADD); |
398 | f5ef6aac | blueswir1 | else {
|
399 | f5ef6aac | blueswir1 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, val); |
400 | f5ef6aac | blueswir1 | tcg_out_arith(s, reg, reg, TCG_REG_I5, ARITH_ADD); |
401 | f5ef6aac | blueswir1 | } |
402 | 8289b279 | blueswir1 | } |
403 | 8289b279 | blueswir1 | } |
404 | 8289b279 | blueswir1 | |
405 | 53c37487 | blueswir1 | static inline void tcg_out_andi(TCGContext *s, int reg, tcg_target_long val) |
406 | 53c37487 | blueswir1 | { |
407 | 53c37487 | blueswir1 | if (val != 0) { |
408 | 53c37487 | blueswir1 | if (check_fit_tl(val, 13)) |
409 | 53c37487 | blueswir1 | tcg_out_arithi(s, reg, reg, val, ARITH_AND); |
410 | 53c37487 | blueswir1 | else {
|
411 | 53c37487 | blueswir1 | tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_I5, val); |
412 | 53c37487 | blueswir1 | tcg_out_arith(s, reg, reg, TCG_REG_I5, ARITH_AND); |
413 | 53c37487 | blueswir1 | } |
414 | 53c37487 | blueswir1 | } |
415 | 53c37487 | blueswir1 | } |
416 | 53c37487 | blueswir1 | |
417 | 8289b279 | blueswir1 | static inline void tcg_out_nop(TCGContext *s) |
418 | 8289b279 | blueswir1 | { |
419 | 26cc915c | blueswir1 | tcg_out_sethi(s, TCG_REG_G0, 0);
|
420 | 8289b279 | blueswir1 | } |
421 | 8289b279 | blueswir1 | |
422 | cf7c2ca5 | blueswir1 | static void tcg_out_branch(TCGContext *s, int opc, int label_index) |
423 | cf7c2ca5 | blueswir1 | { |
424 | cf7c2ca5 | blueswir1 | int32_t val; |
425 | cf7c2ca5 | blueswir1 | TCGLabel *l = &s->labels[label_index]; |
426 | cf7c2ca5 | blueswir1 | |
427 | cf7c2ca5 | blueswir1 | if (l->has_value) {
|
428 | cf7c2ca5 | blueswir1 | val = l->u.value - (tcg_target_long)s->code_ptr; |
429 | f5ef6aac | blueswir1 | tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x2) |
430 | cf7c2ca5 | blueswir1 | | INSN_OFF22(l->u.value - (unsigned long)s->code_ptr))); |
431 | f5ef6aac | blueswir1 | } else {
|
432 | f5ef6aac | blueswir1 | tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP22, label_index, 0);
|
433 | f5ef6aac | blueswir1 | tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x2) | 0)); |
434 | f5ef6aac | blueswir1 | } |
435 | cf7c2ca5 | blueswir1 | } |
436 | cf7c2ca5 | blueswir1 | |
437 | cf7c2ca5 | blueswir1 | static const uint8_t tcg_cond_to_bcond[10] = { |
438 | cf7c2ca5 | blueswir1 | [TCG_COND_EQ] = COND_E, |
439 | cf7c2ca5 | blueswir1 | [TCG_COND_NE] = COND_NE, |
440 | cf7c2ca5 | blueswir1 | [TCG_COND_LT] = COND_L, |
441 | cf7c2ca5 | blueswir1 | [TCG_COND_GE] = COND_GE, |
442 | cf7c2ca5 | blueswir1 | [TCG_COND_LE] = COND_LE, |
443 | cf7c2ca5 | blueswir1 | [TCG_COND_GT] = COND_G, |
444 | cf7c2ca5 | blueswir1 | [TCG_COND_LTU] = COND_CS, |
445 | cf7c2ca5 | blueswir1 | [TCG_COND_GEU] = COND_CC, |
446 | cf7c2ca5 | blueswir1 | [TCG_COND_LEU] = COND_LEU, |
447 | cf7c2ca5 | blueswir1 | [TCG_COND_GTU] = COND_GU, |
448 | cf7c2ca5 | blueswir1 | }; |
449 | cf7c2ca5 | blueswir1 | |
450 | cf7c2ca5 | blueswir1 | static void tcg_out_brcond(TCGContext *s, int cond, |
451 | cf7c2ca5 | blueswir1 | TCGArg arg1, TCGArg arg2, int const_arg2,
|
452 | cf7c2ca5 | blueswir1 | int label_index)
|
453 | cf7c2ca5 | blueswir1 | { |
454 | cf7c2ca5 | blueswir1 | if (const_arg2 && arg2 == 0) |
455 | 26cc915c | blueswir1 | /* orcc %g0, r, %g0 */
|
456 | 9a7f3228 | blueswir1 | tcg_out_arith(s, TCG_REG_G0, TCG_REG_G0, arg1, ARITH_ORCC); |
457 | cf7c2ca5 | blueswir1 | else
|
458 | cf7c2ca5 | blueswir1 | /* subcc r1, r2, %g0 */
|
459 | cf7c2ca5 | blueswir1 | tcg_out_arith(s, TCG_REG_G0, arg1, arg2, ARITH_SUBCC); |
460 | cf7c2ca5 | blueswir1 | tcg_out_branch(s, tcg_cond_to_bcond[cond], label_index); |
461 | cf7c2ca5 | blueswir1 | tcg_out_nop(s); |
462 | cf7c2ca5 | blueswir1 | } |
463 | cf7c2ca5 | blueswir1 | |
464 | 7d551702 | blueswir1 | /* Generate global QEMU prologue and epilogue code */
|
465 | 7d551702 | blueswir1 | void tcg_target_qemu_prologue(TCGContext *s)
|
466 | b3db8758 | blueswir1 | { |
467 | b3db8758 | blueswir1 | tcg_out32(s, SAVE | INSN_RD(TCG_REG_O6) | INSN_RS1(TCG_REG_O6) | |
468 | b3db8758 | blueswir1 | INSN_IMM13(-TCG_TARGET_STACK_MINFRAME)); |
469 | cf7c2ca5 | blueswir1 | tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I0) | |
470 | 7d551702 | blueswir1 | INSN_RS2(TCG_REG_G0)); |
471 | 7d551702 | blueswir1 | tcg_out_nop(s); |
472 | b3db8758 | blueswir1 | } |
473 | b3db8758 | blueswir1 | |
474 | f5ef6aac | blueswir1 | #if defined(CONFIG_SOFTMMU)
|
475 | f5ef6aac | blueswir1 | |
476 | 79383c9c | blueswir1 | #include "../../softmmu_defs.h" |
477 | f5ef6aac | blueswir1 | |
478 | 9a7f3228 | blueswir1 | static const void * const qemu_ld_helpers[4] = { |
479 | f5ef6aac | blueswir1 | __ldb_mmu, |
480 | f5ef6aac | blueswir1 | __ldw_mmu, |
481 | f5ef6aac | blueswir1 | __ldl_mmu, |
482 | f5ef6aac | blueswir1 | __ldq_mmu, |
483 | f5ef6aac | blueswir1 | }; |
484 | f5ef6aac | blueswir1 | |
485 | 9a7f3228 | blueswir1 | static const void * const qemu_st_helpers[4] = { |
486 | f5ef6aac | blueswir1 | __stb_mmu, |
487 | f5ef6aac | blueswir1 | __stw_mmu, |
488 | f5ef6aac | blueswir1 | __stl_mmu, |
489 | f5ef6aac | blueswir1 | __stq_mmu, |
490 | f5ef6aac | blueswir1 | }; |
491 | f5ef6aac | blueswir1 | #endif
|
492 | f5ef6aac | blueswir1 | |
493 | bffe1431 | blueswir1 | #if TARGET_LONG_BITS == 32 |
494 | bffe1431 | blueswir1 | #define TARGET_LD_OP LDUW
|
495 | bffe1431 | blueswir1 | #else
|
496 | bffe1431 | blueswir1 | #define TARGET_LD_OP LDX
|
497 | bffe1431 | blueswir1 | #endif
|
498 | bffe1431 | blueswir1 | |
499 | bffe1431 | blueswir1 | #ifdef __arch64__
|
500 | bffe1431 | blueswir1 | #define HOST_LD_OP LDX
|
501 | bffe1431 | blueswir1 | #define HOST_ST_OP STX
|
502 | bffe1431 | blueswir1 | #define HOST_SLL_OP SHIFT_SLLX
|
503 | bffe1431 | blueswir1 | #define HOST_SRA_OP SHIFT_SRAX
|
504 | bffe1431 | blueswir1 | #else
|
505 | bffe1431 | blueswir1 | #define HOST_LD_OP LDUW
|
506 | bffe1431 | blueswir1 | #define HOST_ST_OP STW
|
507 | bffe1431 | blueswir1 | #define HOST_SLL_OP SHIFT_SLL
|
508 | bffe1431 | blueswir1 | #define HOST_SRA_OP SHIFT_SRA
|
509 | bffe1431 | blueswir1 | #endif
|
510 | bffe1431 | blueswir1 | |
511 | f5ef6aac | blueswir1 | static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, |
512 | f5ef6aac | blueswir1 | int opc)
|
513 | f5ef6aac | blueswir1 | { |
514 | 56fc64df | blueswir1 | int addr_reg, data_reg, arg0, arg1, arg2, mem_index, s_bits;
|
515 | f5ef6aac | blueswir1 | #if defined(CONFIG_SOFTMMU)
|
516 | 53c37487 | blueswir1 | uint32_t *label1_ptr, *label2_ptr; |
517 | f5ef6aac | blueswir1 | #endif
|
518 | f5ef6aac | blueswir1 | |
519 | f5ef6aac | blueswir1 | data_reg = *args++; |
520 | f5ef6aac | blueswir1 | addr_reg = *args++; |
521 | f5ef6aac | blueswir1 | mem_index = *args; |
522 | f5ef6aac | blueswir1 | s_bits = opc & 3;
|
523 | f5ef6aac | blueswir1 | |
524 | 53c37487 | blueswir1 | arg0 = TCG_REG_O0; |
525 | 53c37487 | blueswir1 | arg1 = TCG_REG_O1; |
526 | 56fc64df | blueswir1 | arg2 = TCG_REG_O2; |
527 | f5ef6aac | blueswir1 | |
528 | f5ef6aac | blueswir1 | #if defined(CONFIG_SOFTMMU)
|
529 | 56fc64df | blueswir1 | /* srl addr_reg, x, arg1 */
|
530 | 56fc64df | blueswir1 | tcg_out_arithi(s, arg1, addr_reg, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS, |
531 | f5ef6aac | blueswir1 | SHIFT_SRL); |
532 | 56fc64df | blueswir1 | /* and addr_reg, x, arg0 */
|
533 | 56fc64df | blueswir1 | tcg_out_arithi(s, arg0, addr_reg, TARGET_PAGE_MASK | ((1 << s_bits) - 1), |
534 | f5ef6aac | blueswir1 | ARITH_AND); |
535 | f5ef6aac | blueswir1 | |
536 | 56fc64df | blueswir1 | /* and arg1, x, arg1 */
|
537 | 56fc64df | blueswir1 | tcg_out_andi(s, arg1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
|
538 | f5ef6aac | blueswir1 | |
539 | 56fc64df | blueswir1 | /* add arg1, x, arg1 */
|
540 | 56fc64df | blueswir1 | tcg_out_addi(s, arg1, offsetof(CPUState, |
541 | 56fc64df | blueswir1 | tlb_table[mem_index][0].addr_read));
|
542 | 53c37487 | blueswir1 | |
543 | 56fc64df | blueswir1 | /* add env, arg1, arg1 */
|
544 | 56fc64df | blueswir1 | tcg_out_arith(s, arg1, TCG_AREG0, arg1, ARITH_ADD); |
545 | f5ef6aac | blueswir1 | |
546 | 56fc64df | blueswir1 | /* ld [arg1], arg2 */
|
547 | bffe1431 | blueswir1 | tcg_out32(s, TARGET_LD_OP | INSN_RD(arg2) | INSN_RS1(arg1) | |
548 | 56fc64df | blueswir1 | INSN_RS2(TCG_REG_G0)); |
549 | f5ef6aac | blueswir1 | |
550 | 56fc64df | blueswir1 | /* subcc arg0, arg2, %g0 */
|
551 | 56fc64df | blueswir1 | tcg_out_arith(s, TCG_REG_G0, arg0, arg2, ARITH_SUBCC); |
552 | f5ef6aac | blueswir1 | |
553 | f5ef6aac | blueswir1 | /* will become:
|
554 | f5ef6aac | blueswir1 | be label1 */
|
555 | 53c37487 | blueswir1 | label1_ptr = (uint32_t *)s->code_ptr; |
556 | f5ef6aac | blueswir1 | tcg_out32(s, 0);
|
557 | f5ef6aac | blueswir1 | |
558 | 53c37487 | blueswir1 | /* mov (delay slot) */
|
559 | 53c37487 | blueswir1 | tcg_out_mov(s, arg0, addr_reg); |
560 | f5ef6aac | blueswir1 | |
561 | bffe1431 | blueswir1 | /* mov */
|
562 | bffe1431 | blueswir1 | tcg_out_movi(s, TCG_TYPE_I32, arg1, mem_index); |
563 | bffe1431 | blueswir1 | |
564 | f5ef6aac | blueswir1 | /* XXX: move that code at the end of the TB */
|
565 | 53c37487 | blueswir1 | /* qemu_ld_helper[s_bits](arg0, arg1) */
|
566 | f5ef6aac | blueswir1 | tcg_out32(s, CALL | ((((tcg_target_ulong)qemu_ld_helpers[s_bits] |
567 | f5ef6aac | blueswir1 | - (tcg_target_ulong)s->code_ptr) >> 2)
|
568 | f5ef6aac | blueswir1 | & 0x3fffffff));
|
569 | bffe1431 | blueswir1 | /* Store AREG0 in stack to avoid ugly glibc bugs that mangle
|
570 | bffe1431 | blueswir1 | global registers */
|
571 | bffe1431 | blueswir1 | // delay slot
|
572 | bffe1431 | blueswir1 | tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK, |
573 | bffe1431 | blueswir1 | TCG_TARGET_CALL_STACK_OFFSET - sizeof(long), HOST_ST_OP); |
574 | bffe1431 | blueswir1 | tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK, |
575 | bffe1431 | blueswir1 | TCG_TARGET_CALL_STACK_OFFSET - sizeof(long), HOST_LD_OP); |
576 | f5ef6aac | blueswir1 | |
577 | 53c37487 | blueswir1 | /* data_reg = sign_extend(arg0) */
|
578 | f5ef6aac | blueswir1 | switch(opc) {
|
579 | f5ef6aac | blueswir1 | case 0 | 4: |
580 | 53c37487 | blueswir1 | /* sll arg0, 24/56, data_reg */
|
581 | 56fc64df | blueswir1 | tcg_out_arithi(s, data_reg, arg0, (int)sizeof(tcg_target_long) * 8 - 8, |
582 | bffe1431 | blueswir1 | HOST_SLL_OP); |
583 | 53c37487 | blueswir1 | /* sra data_reg, 24/56, data_reg */
|
584 | 56fc64df | blueswir1 | tcg_out_arithi(s, data_reg, data_reg, |
585 | bffe1431 | blueswir1 | (int)sizeof(tcg_target_long) * 8 - 8, HOST_SRA_OP); |
586 | f5ef6aac | blueswir1 | break;
|
587 | f5ef6aac | blueswir1 | case 1 | 4: |
588 | 53c37487 | blueswir1 | /* sll arg0, 16/48, data_reg */
|
589 | 56fc64df | blueswir1 | tcg_out_arithi(s, data_reg, arg0, |
590 | bffe1431 | blueswir1 | (int)sizeof(tcg_target_long) * 8 - 16, HOST_SLL_OP); |
591 | 53c37487 | blueswir1 | /* sra data_reg, 16/48, data_reg */
|
592 | 56fc64df | blueswir1 | tcg_out_arithi(s, data_reg, data_reg, |
593 | bffe1431 | blueswir1 | (int)sizeof(tcg_target_long) * 8 - 16, HOST_SRA_OP); |
594 | f5ef6aac | blueswir1 | break;
|
595 | f5ef6aac | blueswir1 | case 2 | 4: |
596 | 53c37487 | blueswir1 | /* sll arg0, 32, data_reg */
|
597 | bffe1431 | blueswir1 | tcg_out_arithi(s, data_reg, arg0, 32, HOST_SLL_OP);
|
598 | 53c37487 | blueswir1 | /* sra data_reg, 32, data_reg */
|
599 | bffe1431 | blueswir1 | tcg_out_arithi(s, data_reg, data_reg, 32, HOST_SRA_OP);
|
600 | f5ef6aac | blueswir1 | break;
|
601 | f5ef6aac | blueswir1 | case 0: |
602 | f5ef6aac | blueswir1 | case 1: |
603 | f5ef6aac | blueswir1 | case 2: |
604 | f5ef6aac | blueswir1 | case 3: |
605 | f5ef6aac | blueswir1 | default:
|
606 | f5ef6aac | blueswir1 | /* mov */
|
607 | 53c37487 | blueswir1 | tcg_out_mov(s, data_reg, arg0); |
608 | f5ef6aac | blueswir1 | break;
|
609 | f5ef6aac | blueswir1 | } |
610 | f5ef6aac | blueswir1 | |
611 | f5ef6aac | blueswir1 | /* will become:
|
612 | f5ef6aac | blueswir1 | ba label2 */
|
613 | 53c37487 | blueswir1 | label2_ptr = (uint32_t *)s->code_ptr; |
614 | f5ef6aac | blueswir1 | tcg_out32(s, 0);
|
615 | f5ef6aac | blueswir1 | |
616 | 53c37487 | blueswir1 | /* nop (delay slot */
|
617 | 53c37487 | blueswir1 | tcg_out_nop(s); |
618 | 53c37487 | blueswir1 | |
619 | f5ef6aac | blueswir1 | /* label1: */
|
620 | 53c37487 | blueswir1 | *label1_ptr = (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x2) | |
621 | 53c37487 | blueswir1 | INSN_OFF22((unsigned long)s->code_ptr - |
622 | 53c37487 | blueswir1 | (unsigned long)label1_ptr)); |
623 | f5ef6aac | blueswir1 | |
624 | 56fc64df | blueswir1 | /* ld [arg1 + x], arg1 */
|
625 | 56fc64df | blueswir1 | tcg_out_ldst(s, arg1, arg1, offsetof(CPUTLBEntry, addend) - |
626 | bffe1431 | blueswir1 | offsetof(CPUTLBEntry, addr_read), HOST_LD_OP); |
627 | 90cbed46 | blueswir1 | |
628 | 90cbed46 | blueswir1 | #if TARGET_LONG_BITS == 32 |
629 | 90cbed46 | blueswir1 | /* and addr_reg, x, arg0 */
|
630 | 90cbed46 | blueswir1 | tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_I5, 0xffffffff);
|
631 | 90cbed46 | blueswir1 | tcg_out_arith(s, arg0, addr_reg, TCG_REG_I5, ARITH_AND); |
632 | 90cbed46 | blueswir1 | /* add arg0, arg1, arg0 */
|
633 | 90cbed46 | blueswir1 | tcg_out_arith(s, arg0, arg0, arg1, ARITH_ADD); |
634 | 90cbed46 | blueswir1 | #else
|
635 | 56fc64df | blueswir1 | /* add addr_reg, arg1, arg0 */
|
636 | 56fc64df | blueswir1 | tcg_out_arith(s, arg0, addr_reg, arg1, ARITH_ADD); |
637 | 90cbed46 | blueswir1 | #endif
|
638 | 90cbed46 | blueswir1 | |
639 | f5ef6aac | blueswir1 | #else
|
640 | 56fc64df | blueswir1 | arg0 = addr_reg; |
641 | f5ef6aac | blueswir1 | #endif
|
642 | f5ef6aac | blueswir1 | |
643 | f5ef6aac | blueswir1 | switch(opc) {
|
644 | f5ef6aac | blueswir1 | case 0: |
645 | 56fc64df | blueswir1 | /* ldub [arg0], data_reg */
|
646 | 56fc64df | blueswir1 | tcg_out_ldst(s, data_reg, arg0, 0, LDUB);
|
647 | f5ef6aac | blueswir1 | break;
|
648 | f5ef6aac | blueswir1 | case 0 | 4: |
649 | 56fc64df | blueswir1 | /* ldsb [arg0], data_reg */
|
650 | 56fc64df | blueswir1 | tcg_out_ldst(s, data_reg, arg0, 0, LDSB);
|
651 | f5ef6aac | blueswir1 | break;
|
652 | f5ef6aac | blueswir1 | case 1: |
653 | 8384dd67 | blueswir1 | #ifdef TARGET_WORDS_BIGENDIAN
|
654 | 56fc64df | blueswir1 | /* lduh [arg0], data_reg */
|
655 | 56fc64df | blueswir1 | tcg_out_ldst(s, data_reg, arg0, 0, LDUH);
|
656 | 8384dd67 | blueswir1 | #else
|
657 | 56fc64df | blueswir1 | /* lduha [arg0] ASI_PRIMARY_LITTLE, data_reg */
|
658 | 56fc64df | blueswir1 | tcg_out_ldst_asi(s, data_reg, arg0, 0, LDUHA, ASI_PRIMARY_LITTLE);
|
659 | 8384dd67 | blueswir1 | #endif
|
660 | f5ef6aac | blueswir1 | break;
|
661 | f5ef6aac | blueswir1 | case 1 | 4: |
662 | 8384dd67 | blueswir1 | #ifdef TARGET_WORDS_BIGENDIAN
|
663 | 56fc64df | blueswir1 | /* ldsh [arg0], data_reg */
|
664 | 56fc64df | blueswir1 | tcg_out_ldst(s, data_reg, arg0, 0, LDSH);
|
665 | 8384dd67 | blueswir1 | #else
|
666 | 56fc64df | blueswir1 | /* ldsha [arg0] ASI_PRIMARY_LITTLE, data_reg */
|
667 | 56fc64df | blueswir1 | tcg_out_ldst_asi(s, data_reg, arg0, 0, LDSHA, ASI_PRIMARY_LITTLE);
|
668 | 8384dd67 | blueswir1 | #endif
|
669 | f5ef6aac | blueswir1 | break;
|
670 | f5ef6aac | blueswir1 | case 2: |
671 | 8384dd67 | blueswir1 | #ifdef TARGET_WORDS_BIGENDIAN
|
672 | 56fc64df | blueswir1 | /* lduw [arg0], data_reg */
|
673 | 56fc64df | blueswir1 | tcg_out_ldst(s, data_reg, arg0, 0, LDUW);
|
674 | 8384dd67 | blueswir1 | #else
|
675 | 56fc64df | blueswir1 | /* lduwa [arg0] ASI_PRIMARY_LITTLE, data_reg */
|
676 | 56fc64df | blueswir1 | tcg_out_ldst_asi(s, data_reg, arg0, 0, LDUWA, ASI_PRIMARY_LITTLE);
|
677 | 8384dd67 | blueswir1 | #endif
|
678 | f5ef6aac | blueswir1 | break;
|
679 | f5ef6aac | blueswir1 | case 2 | 4: |
680 | 8384dd67 | blueswir1 | #ifdef TARGET_WORDS_BIGENDIAN
|
681 | 56fc64df | blueswir1 | /* ldsw [arg0], data_reg */
|
682 | 56fc64df | blueswir1 | tcg_out_ldst(s, data_reg, arg0, 0, LDSW);
|
683 | 8384dd67 | blueswir1 | #else
|
684 | 56fc64df | blueswir1 | /* ldswa [arg0] ASI_PRIMARY_LITTLE, data_reg */
|
685 | 56fc64df | blueswir1 | tcg_out_ldst_asi(s, data_reg, arg0, 0, LDSWA, ASI_PRIMARY_LITTLE);
|
686 | 8384dd67 | blueswir1 | #endif
|
687 | f5ef6aac | blueswir1 | break;
|
688 | f5ef6aac | blueswir1 | case 3: |
689 | 8384dd67 | blueswir1 | #ifdef TARGET_WORDS_BIGENDIAN
|
690 | 56fc64df | blueswir1 | /* ldx [arg0], data_reg */
|
691 | 56fc64df | blueswir1 | tcg_out_ldst(s, data_reg, arg0, 0, LDX);
|
692 | 8384dd67 | blueswir1 | #else
|
693 | 56fc64df | blueswir1 | /* ldxa [arg0] ASI_PRIMARY_LITTLE, data_reg */
|
694 | 56fc64df | blueswir1 | tcg_out_ldst_asi(s, data_reg, arg0, 0, LDXA, ASI_PRIMARY_LITTLE);
|
695 | 8384dd67 | blueswir1 | #endif
|
696 | f5ef6aac | blueswir1 | break;
|
697 | f5ef6aac | blueswir1 | default:
|
698 | f5ef6aac | blueswir1 | tcg_abort(); |
699 | f5ef6aac | blueswir1 | } |
700 | f5ef6aac | blueswir1 | |
701 | f5ef6aac | blueswir1 | #if defined(CONFIG_SOFTMMU)
|
702 | f5ef6aac | blueswir1 | /* label2: */
|
703 | 9a7f3228 | blueswir1 | *label2_ptr = (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2) | |
704 | 53c37487 | blueswir1 | INSN_OFF22((unsigned long)s->code_ptr - |
705 | 53c37487 | blueswir1 | (unsigned long)label2_ptr)); |
706 | f5ef6aac | blueswir1 | #endif
|
707 | f5ef6aac | blueswir1 | } |
708 | f5ef6aac | blueswir1 | |
709 | f5ef6aac | blueswir1 | static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, |
710 | f5ef6aac | blueswir1 | int opc)
|
711 | f5ef6aac | blueswir1 | { |
712 | 56fc64df | blueswir1 | int addr_reg, data_reg, arg0, arg1, arg2, mem_index, s_bits;
|
713 | f5ef6aac | blueswir1 | #if defined(CONFIG_SOFTMMU)
|
714 | 53c37487 | blueswir1 | uint32_t *label1_ptr, *label2_ptr; |
715 | f5ef6aac | blueswir1 | #endif
|
716 | f5ef6aac | blueswir1 | |
717 | f5ef6aac | blueswir1 | data_reg = *args++; |
718 | f5ef6aac | blueswir1 | addr_reg = *args++; |
719 | f5ef6aac | blueswir1 | mem_index = *args; |
720 | f5ef6aac | blueswir1 | |
721 | f5ef6aac | blueswir1 | s_bits = opc; |
722 | f5ef6aac | blueswir1 | |
723 | 53c37487 | blueswir1 | arg0 = TCG_REG_O0; |
724 | 53c37487 | blueswir1 | arg1 = TCG_REG_O1; |
725 | 53c37487 | blueswir1 | arg2 = TCG_REG_O2; |
726 | f5ef6aac | blueswir1 | |
727 | f5ef6aac | blueswir1 | #if defined(CONFIG_SOFTMMU)
|
728 | 56fc64df | blueswir1 | /* srl addr_reg, x, arg1 */
|
729 | 56fc64df | blueswir1 | tcg_out_arithi(s, arg1, addr_reg, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS, |
730 | f5ef6aac | blueswir1 | SHIFT_SRL); |
731 | 53c37487 | blueswir1 | |
732 | 56fc64df | blueswir1 | /* and addr_reg, x, arg0 */
|
733 | 56fc64df | blueswir1 | tcg_out_arithi(s, arg0, addr_reg, TARGET_PAGE_MASK | ((1 << s_bits) - 1), |
734 | f5ef6aac | blueswir1 | ARITH_AND); |
735 | f5ef6aac | blueswir1 | |
736 | 56fc64df | blueswir1 | /* and arg1, x, arg1 */
|
737 | 56fc64df | blueswir1 | tcg_out_andi(s, arg1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
|
738 | f5ef6aac | blueswir1 | |
739 | 56fc64df | blueswir1 | /* add arg1, x, arg1 */
|
740 | 56fc64df | blueswir1 | tcg_out_addi(s, arg1, offsetof(CPUState, |
741 | 56fc64df | blueswir1 | tlb_table[mem_index][0].addr_write));
|
742 | f5ef6aac | blueswir1 | |
743 | 56fc64df | blueswir1 | /* add env, arg1, arg1 */
|
744 | 56fc64df | blueswir1 | tcg_out_arith(s, arg1, TCG_AREG0, arg1, ARITH_ADD); |
745 | f5ef6aac | blueswir1 | |
746 | 56fc64df | blueswir1 | /* ld [arg1], arg2 */
|
747 | bffe1431 | blueswir1 | tcg_out32(s, TARGET_LD_OP | INSN_RD(arg2) | INSN_RS1(arg1) | |
748 | 56fc64df | blueswir1 | INSN_RS2(TCG_REG_G0)); |
749 | 53c37487 | blueswir1 | |
750 | 56fc64df | blueswir1 | /* subcc arg0, arg2, %g0 */
|
751 | 56fc64df | blueswir1 | tcg_out_arith(s, TCG_REG_G0, arg0, arg2, ARITH_SUBCC); |
752 | f5ef6aac | blueswir1 | |
753 | f5ef6aac | blueswir1 | /* will become:
|
754 | f5ef6aac | blueswir1 | be label1 */
|
755 | 53c37487 | blueswir1 | label1_ptr = (uint32_t *)s->code_ptr; |
756 | f5ef6aac | blueswir1 | tcg_out32(s, 0);
|
757 | f5ef6aac | blueswir1 | |
758 | 53c37487 | blueswir1 | /* mov (delay slot) */
|
759 | 53c37487 | blueswir1 | tcg_out_mov(s, arg0, addr_reg); |
760 | 53c37487 | blueswir1 | |
761 | 53c37487 | blueswir1 | /* mov */
|
762 | 56fc64df | blueswir1 | tcg_out_mov(s, arg1, data_reg); |
763 | 53c37487 | blueswir1 | |
764 | bffe1431 | blueswir1 | /* mov */
|
765 | bffe1431 | blueswir1 | tcg_out_movi(s, TCG_TYPE_I32, arg2, mem_index); |
766 | bffe1431 | blueswir1 | |
767 | 53c37487 | blueswir1 | /* XXX: move that code at the end of the TB */
|
768 | 53c37487 | blueswir1 | /* qemu_st_helper[s_bits](arg0, arg1, arg2) */
|
769 | f5ef6aac | blueswir1 | tcg_out32(s, CALL | ((((tcg_target_ulong)qemu_st_helpers[s_bits] |
770 | f5ef6aac | blueswir1 | - (tcg_target_ulong)s->code_ptr) >> 2)
|
771 | f5ef6aac | blueswir1 | & 0x3fffffff));
|
772 | bffe1431 | blueswir1 | /* Store AREG0 in stack to avoid ugly glibc bugs that mangle
|
773 | bffe1431 | blueswir1 | global registers */
|
774 | bffe1431 | blueswir1 | // delay slot
|
775 | bffe1431 | blueswir1 | tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK, |
776 | bffe1431 | blueswir1 | TCG_TARGET_CALL_STACK_OFFSET - sizeof(long), HOST_ST_OP); |
777 | bffe1431 | blueswir1 | tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK, |
778 | bffe1431 | blueswir1 | TCG_TARGET_CALL_STACK_OFFSET - sizeof(long), HOST_LD_OP); |
779 | f5ef6aac | blueswir1 | |
780 | f5ef6aac | blueswir1 | /* will become:
|
781 | f5ef6aac | blueswir1 | ba label2 */
|
782 | 53c37487 | blueswir1 | label2_ptr = (uint32_t *)s->code_ptr; |
783 | f5ef6aac | blueswir1 | tcg_out32(s, 0);
|
784 | f5ef6aac | blueswir1 | |
785 | 53c37487 | blueswir1 | /* nop (delay slot) */
|
786 | 53c37487 | blueswir1 | tcg_out_nop(s); |
787 | 53c37487 | blueswir1 | |
788 | f5ef6aac | blueswir1 | /* label1: */
|
789 | 53c37487 | blueswir1 | *label1_ptr = (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x2) | |
790 | 53c37487 | blueswir1 | INSN_OFF22((unsigned long)s->code_ptr - |
791 | 53c37487 | blueswir1 | (unsigned long)label1_ptr)); |
792 | f5ef6aac | blueswir1 | |
793 | 56fc64df | blueswir1 | /* ld [arg1 + x], arg1 */
|
794 | 56fc64df | blueswir1 | tcg_out_ldst(s, arg1, arg1, offsetof(CPUTLBEntry, addend) - |
795 | bffe1431 | blueswir1 | offsetof(CPUTLBEntry, addr_write), HOST_LD_OP); |
796 | 53c37487 | blueswir1 | |
797 | 90cbed46 | blueswir1 | #if TARGET_LONG_BITS == 32 |
798 | 90cbed46 | blueswir1 | /* and addr_reg, x, arg0 */
|
799 | 90cbed46 | blueswir1 | tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_I5, 0xffffffff);
|
800 | 90cbed46 | blueswir1 | tcg_out_arith(s, arg0, addr_reg, TCG_REG_I5, ARITH_AND); |
801 | 90cbed46 | blueswir1 | /* add arg0, arg1, arg0 */
|
802 | 90cbed46 | blueswir1 | tcg_out_arith(s, arg0, arg0, arg1, ARITH_ADD); |
803 | 90cbed46 | blueswir1 | #else
|
804 | 56fc64df | blueswir1 | /* add addr_reg, arg1, arg0 */
|
805 | 56fc64df | blueswir1 | tcg_out_arith(s, arg0, addr_reg, arg1, ARITH_ADD); |
806 | 90cbed46 | blueswir1 | #endif
|
807 | 90cbed46 | blueswir1 | |
808 | f5ef6aac | blueswir1 | #else
|
809 | 56fc64df | blueswir1 | arg0 = addr_reg; |
810 | f5ef6aac | blueswir1 | #endif
|
811 | f5ef6aac | blueswir1 | |
812 | f5ef6aac | blueswir1 | switch(opc) {
|
813 | f5ef6aac | blueswir1 | case 0: |
814 | 56fc64df | blueswir1 | /* stb data_reg, [arg0] */
|
815 | 56fc64df | blueswir1 | tcg_out_ldst(s, data_reg, arg0, 0, STB);
|
816 | f5ef6aac | blueswir1 | break;
|
817 | f5ef6aac | blueswir1 | case 1: |
818 | 8384dd67 | blueswir1 | #ifdef TARGET_WORDS_BIGENDIAN
|
819 | 56fc64df | blueswir1 | /* sth data_reg, [arg0] */
|
820 | 56fc64df | blueswir1 | tcg_out_ldst(s, data_reg, arg0, 0, STH);
|
821 | 8384dd67 | blueswir1 | #else
|
822 | 56fc64df | blueswir1 | /* stha data_reg, [arg0] ASI_PRIMARY_LITTLE */
|
823 | 56fc64df | blueswir1 | tcg_out_ldst_asi(s, data_reg, arg0, 0, STHA, ASI_PRIMARY_LITTLE);
|
824 | 8384dd67 | blueswir1 | #endif
|
825 | f5ef6aac | blueswir1 | break;
|
826 | f5ef6aac | blueswir1 | case 2: |
827 | 8384dd67 | blueswir1 | #ifdef TARGET_WORDS_BIGENDIAN
|
828 | 56fc64df | blueswir1 | /* stw data_reg, [arg0] */
|
829 | 56fc64df | blueswir1 | tcg_out_ldst(s, data_reg, arg0, 0, STW);
|
830 | 8384dd67 | blueswir1 | #else
|
831 | 56fc64df | blueswir1 | /* stwa data_reg, [arg0] ASI_PRIMARY_LITTLE */
|
832 | 56fc64df | blueswir1 | tcg_out_ldst_asi(s, data_reg, arg0, 0, STWA, ASI_PRIMARY_LITTLE);
|
833 | 8384dd67 | blueswir1 | #endif
|
834 | f5ef6aac | blueswir1 | break;
|
835 | f5ef6aac | blueswir1 | case 3: |
836 | 8384dd67 | blueswir1 | #ifdef TARGET_WORDS_BIGENDIAN
|
837 | 56fc64df | blueswir1 | /* stx data_reg, [arg0] */
|
838 | 56fc64df | blueswir1 | tcg_out_ldst(s, data_reg, arg0, 0, STX);
|
839 | 8384dd67 | blueswir1 | #else
|
840 | 56fc64df | blueswir1 | /* stxa data_reg, [arg0] ASI_PRIMARY_LITTLE */
|
841 | 56fc64df | blueswir1 | tcg_out_ldst_asi(s, data_reg, arg0, 0, STXA, ASI_PRIMARY_LITTLE);
|
842 | 8384dd67 | blueswir1 | #endif
|
843 | f5ef6aac | blueswir1 | break;
|
844 | f5ef6aac | blueswir1 | default:
|
845 | f5ef6aac | blueswir1 | tcg_abort(); |
846 | f5ef6aac | blueswir1 | } |
847 | f5ef6aac | blueswir1 | |
848 | f5ef6aac | blueswir1 | #if defined(CONFIG_SOFTMMU)
|
849 | f5ef6aac | blueswir1 | /* label2: */
|
850 | 9a7f3228 | blueswir1 | *label2_ptr = (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2) | |
851 | 53c37487 | blueswir1 | INSN_OFF22((unsigned long)s->code_ptr - |
852 | 53c37487 | blueswir1 | (unsigned long)label2_ptr)); |
853 | f5ef6aac | blueswir1 | #endif
|
854 | f5ef6aac | blueswir1 | } |
855 | f5ef6aac | blueswir1 | |
856 | 8289b279 | blueswir1 | static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args, |
857 | 8289b279 | blueswir1 | const int *const_args) |
858 | 8289b279 | blueswir1 | { |
859 | 8289b279 | blueswir1 | int c;
|
860 | 8289b279 | blueswir1 | |
861 | 8289b279 | blueswir1 | switch (opc) {
|
862 | 8289b279 | blueswir1 | case INDEX_op_exit_tb:
|
863 | b3db8758 | blueswir1 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I0, args[0]);
|
864 | b3db8758 | blueswir1 | tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I7) | |
865 | 8289b279 | blueswir1 | INSN_IMM13(8));
|
866 | b3db8758 | blueswir1 | tcg_out32(s, RESTORE | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_G0) | |
867 | b3db8758 | blueswir1 | INSN_RS2(TCG_REG_G0)); |
868 | 8289b279 | blueswir1 | break;
|
869 | 8289b279 | blueswir1 | case INDEX_op_goto_tb:
|
870 | 8289b279 | blueswir1 | if (s->tb_jmp_offset) {
|
871 | 8289b279 | blueswir1 | /* direct jump method */
|
872 | 26cc915c | blueswir1 | tcg_out_sethi(s, TCG_REG_I5, args[0] & 0xffffe000); |
873 | cf7c2ca5 | blueswir1 | tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I5) | |
874 | cf7c2ca5 | blueswir1 | INSN_IMM13((args[0] & 0x1fff))); |
875 | 8289b279 | blueswir1 | s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
|
876 | 8289b279 | blueswir1 | } else {
|
877 | 8289b279 | blueswir1 | /* indirect jump method */
|
878 | b3db8758 | blueswir1 | tcg_out_ld_ptr(s, TCG_REG_I5, (tcg_target_long)(s->tb_next + args[0]));
|
879 | b3db8758 | blueswir1 | tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I5) | |
880 | b3db8758 | blueswir1 | INSN_RS2(TCG_REG_G0)); |
881 | 8289b279 | blueswir1 | } |
882 | 53cd9273 | blueswir1 | tcg_out_nop(s); |
883 | 8289b279 | blueswir1 | s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
|
884 | 8289b279 | blueswir1 | break;
|
885 | 8289b279 | blueswir1 | case INDEX_op_call:
|
886 | bffe1431 | blueswir1 | if (const_args[0]) |
887 | bffe1431 | blueswir1 | tcg_out32(s, CALL | ((((tcg_target_ulong)args[0]
|
888 | bffe1431 | blueswir1 | - (tcg_target_ulong)s->code_ptr) >> 2)
|
889 | bffe1431 | blueswir1 | & 0x3fffffff));
|
890 | bffe1431 | blueswir1 | else {
|
891 | bffe1431 | blueswir1 | tcg_out_ld_ptr(s, TCG_REG_I5, |
892 | bffe1431 | blueswir1 | (tcg_target_long)(s->tb_next + args[0]));
|
893 | bffe1431 | blueswir1 | tcg_out32(s, JMPL | INSN_RD(TCG_REG_O7) | INSN_RS1(TCG_REG_I5) | |
894 | bffe1431 | blueswir1 | INSN_RS2(TCG_REG_G0)); |
895 | 8289b279 | blueswir1 | } |
896 | bffe1431 | blueswir1 | /* Store AREG0 in stack to avoid ugly glibc bugs that mangle
|
897 | bffe1431 | blueswir1 | global registers */
|
898 | bffe1431 | blueswir1 | // delay slot
|
899 | bffe1431 | blueswir1 | tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK, |
900 | bffe1431 | blueswir1 | TCG_TARGET_CALL_STACK_OFFSET - sizeof(long), HOST_ST_OP); |
901 | bffe1431 | blueswir1 | tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK, |
902 | bffe1431 | blueswir1 | TCG_TARGET_CALL_STACK_OFFSET - sizeof(long), HOST_LD_OP); |
903 | 8289b279 | blueswir1 | break;
|
904 | 8289b279 | blueswir1 | case INDEX_op_jmp:
|
905 | 8289b279 | blueswir1 | case INDEX_op_br:
|
906 | f5ef6aac | blueswir1 | tcg_out_branch(s, COND_A, args[0]);
|
907 | f5ef6aac | blueswir1 | tcg_out_nop(s); |
908 | 8289b279 | blueswir1 | break;
|
909 | 8289b279 | blueswir1 | case INDEX_op_movi_i32:
|
910 | 8289b279 | blueswir1 | tcg_out_movi(s, TCG_TYPE_I32, args[0], (uint32_t)args[1]); |
911 | 8289b279 | blueswir1 | break;
|
912 | 8289b279 | blueswir1 | |
913 | 8289b279 | blueswir1 | #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
|
914 | 8289b279 | blueswir1 | #define OP_32_64(x) \
|
915 | 8289b279 | blueswir1 | glue(glue(case INDEX_op_, x), _i32:) \
|
916 | 8289b279 | blueswir1 | glue(glue(case INDEX_op_, x), _i64:)
|
917 | 8289b279 | blueswir1 | #else
|
918 | 8289b279 | blueswir1 | #define OP_32_64(x) \
|
919 | 8289b279 | blueswir1 | glue(glue(case INDEX_op_, x), _i32:)
|
920 | 8289b279 | blueswir1 | #endif
|
921 | 8289b279 | blueswir1 | OP_32_64(ld8u); |
922 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], LDUB); |
923 | 8289b279 | blueswir1 | break;
|
924 | 8289b279 | blueswir1 | OP_32_64(ld8s); |
925 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], LDSB); |
926 | 8289b279 | blueswir1 | break;
|
927 | 8289b279 | blueswir1 | OP_32_64(ld16u); |
928 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], LDUH); |
929 | 8289b279 | blueswir1 | break;
|
930 | 8289b279 | blueswir1 | OP_32_64(ld16s); |
931 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], LDSH); |
932 | 8289b279 | blueswir1 | break;
|
933 | 8289b279 | blueswir1 | case INDEX_op_ld_i32:
|
934 | 8289b279 | blueswir1 | #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
|
935 | 53cd9273 | blueswir1 | case INDEX_op_ld32u_i64:
|
936 | 8289b279 | blueswir1 | #endif
|
937 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], LDUW); |
938 | 8289b279 | blueswir1 | break;
|
939 | 8289b279 | blueswir1 | OP_32_64(st8); |
940 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], STB); |
941 | 8289b279 | blueswir1 | break;
|
942 | 8289b279 | blueswir1 | OP_32_64(st16); |
943 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], STH); |
944 | 8289b279 | blueswir1 | break;
|
945 | 8289b279 | blueswir1 | case INDEX_op_st_i32:
|
946 | 8289b279 | blueswir1 | #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
|
947 | 53cd9273 | blueswir1 | case INDEX_op_st32_i64:
|
948 | 8289b279 | blueswir1 | #endif
|
949 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], STW); |
950 | 8289b279 | blueswir1 | break;
|
951 | 53cd9273 | blueswir1 | OP_32_64(add); |
952 | 53cd9273 | blueswir1 | c = ARITH_ADD; |
953 | 53cd9273 | blueswir1 | goto gen_arith32;
|
954 | 8289b279 | blueswir1 | OP_32_64(sub); |
955 | 8289b279 | blueswir1 | c = ARITH_SUB; |
956 | 8289b279 | blueswir1 | goto gen_arith32;
|
957 | 8289b279 | blueswir1 | OP_32_64(and); |
958 | 8289b279 | blueswir1 | c = ARITH_AND; |
959 | 8289b279 | blueswir1 | goto gen_arith32;
|
960 | 8289b279 | blueswir1 | OP_32_64(or); |
961 | 8289b279 | blueswir1 | c = ARITH_OR; |
962 | 8289b279 | blueswir1 | goto gen_arith32;
|
963 | 8289b279 | blueswir1 | OP_32_64(xor); |
964 | 8289b279 | blueswir1 | c = ARITH_XOR; |
965 | 8289b279 | blueswir1 | goto gen_arith32;
|
966 | 8289b279 | blueswir1 | case INDEX_op_shl_i32:
|
967 | 8289b279 | blueswir1 | c = SHIFT_SLL; |
968 | 8289b279 | blueswir1 | goto gen_arith32;
|
969 | 8289b279 | blueswir1 | case INDEX_op_shr_i32:
|
970 | 8289b279 | blueswir1 | c = SHIFT_SRL; |
971 | 8289b279 | blueswir1 | goto gen_arith32;
|
972 | 8289b279 | blueswir1 | case INDEX_op_sar_i32:
|
973 | 8289b279 | blueswir1 | c = SHIFT_SRA; |
974 | 8289b279 | blueswir1 | goto gen_arith32;
|
975 | 8289b279 | blueswir1 | case INDEX_op_mul_i32:
|
976 | 8289b279 | blueswir1 | c = ARITH_UMUL; |
977 | 8289b279 | blueswir1 | goto gen_arith32;
|
978 | 8289b279 | blueswir1 | case INDEX_op_div2_i32:
|
979 | 8289b279 | blueswir1 | #if defined(__sparc_v9__) || defined(__sparc_v8plus__)
|
980 | 8289b279 | blueswir1 | c = ARITH_SDIVX; |
981 | 8289b279 | blueswir1 | goto gen_arith32;
|
982 | 8289b279 | blueswir1 | #else
|
983 | 8289b279 | blueswir1 | tcg_out_sety(s, 0);
|
984 | 8289b279 | blueswir1 | c = ARITH_SDIV; |
985 | 8289b279 | blueswir1 | goto gen_arith32;
|
986 | 8289b279 | blueswir1 | #endif
|
987 | 8289b279 | blueswir1 | case INDEX_op_divu2_i32:
|
988 | 8289b279 | blueswir1 | #if defined(__sparc_v9__) || defined(__sparc_v8plus__)
|
989 | 8289b279 | blueswir1 | c = ARITH_UDIVX; |
990 | 8289b279 | blueswir1 | goto gen_arith32;
|
991 | 8289b279 | blueswir1 | #else
|
992 | 8289b279 | blueswir1 | tcg_out_sety(s, 0);
|
993 | 8289b279 | blueswir1 | c = ARITH_UDIV; |
994 | 8289b279 | blueswir1 | goto gen_arith32;
|
995 | 8289b279 | blueswir1 | #endif
|
996 | 8289b279 | blueswir1 | |
997 | 8289b279 | blueswir1 | case INDEX_op_brcond_i32:
|
998 | cf7c2ca5 | blueswir1 | tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], |
999 | cf7c2ca5 | blueswir1 | args[3]);
|
1000 | 8289b279 | blueswir1 | break;
|
1001 | 8289b279 | blueswir1 | |
1002 | 8289b279 | blueswir1 | case INDEX_op_qemu_ld8u:
|
1003 | f5ef6aac | blueswir1 | tcg_out_qemu_ld(s, args, 0);
|
1004 | 8289b279 | blueswir1 | break;
|
1005 | 8289b279 | blueswir1 | case INDEX_op_qemu_ld8s:
|
1006 | f5ef6aac | blueswir1 | tcg_out_qemu_ld(s, args, 0 | 4); |
1007 | 8289b279 | blueswir1 | break;
|
1008 | 8289b279 | blueswir1 | case INDEX_op_qemu_ld16u:
|
1009 | f5ef6aac | blueswir1 | tcg_out_qemu_ld(s, args, 1);
|
1010 | 8289b279 | blueswir1 | break;
|
1011 | 8289b279 | blueswir1 | case INDEX_op_qemu_ld16s:
|
1012 | f5ef6aac | blueswir1 | tcg_out_qemu_ld(s, args, 1 | 4); |
1013 | 8289b279 | blueswir1 | break;
|
1014 | 8289b279 | blueswir1 | case INDEX_op_qemu_ld32u:
|
1015 | f5ef6aac | blueswir1 | tcg_out_qemu_ld(s, args, 2);
|
1016 | 8289b279 | blueswir1 | break;
|
1017 | 8289b279 | blueswir1 | case INDEX_op_qemu_ld32s:
|
1018 | f5ef6aac | blueswir1 | tcg_out_qemu_ld(s, args, 2 | 4); |
1019 | 8289b279 | blueswir1 | break;
|
1020 | 8289b279 | blueswir1 | case INDEX_op_qemu_st8:
|
1021 | f5ef6aac | blueswir1 | tcg_out_qemu_st(s, args, 0);
|
1022 | 8289b279 | blueswir1 | break;
|
1023 | 8289b279 | blueswir1 | case INDEX_op_qemu_st16:
|
1024 | f5ef6aac | blueswir1 | tcg_out_qemu_st(s, args, 1);
|
1025 | 8289b279 | blueswir1 | break;
|
1026 | 8289b279 | blueswir1 | case INDEX_op_qemu_st32:
|
1027 | f5ef6aac | blueswir1 | tcg_out_qemu_st(s, args, 2);
|
1028 | 8289b279 | blueswir1 | break;
|
1029 | 8289b279 | blueswir1 | |
1030 | 8289b279 | blueswir1 | #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
|
1031 | 8289b279 | blueswir1 | case INDEX_op_movi_i64:
|
1032 | 8289b279 | blueswir1 | tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]); |
1033 | 8289b279 | blueswir1 | break;
|
1034 | 53cd9273 | blueswir1 | case INDEX_op_ld32s_i64:
|
1035 | 53cd9273 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], LDSW); |
1036 | 53cd9273 | blueswir1 | break;
|
1037 | 8289b279 | blueswir1 | case INDEX_op_ld_i64:
|
1038 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], LDX); |
1039 | 8289b279 | blueswir1 | break;
|
1040 | 8289b279 | blueswir1 | case INDEX_op_st_i64:
|
1041 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], STX); |
1042 | 8289b279 | blueswir1 | break;
|
1043 | 8289b279 | blueswir1 | case INDEX_op_shl_i64:
|
1044 | 8289b279 | blueswir1 | c = SHIFT_SLLX; |
1045 | 8289b279 | blueswir1 | goto gen_arith32;
|
1046 | 8289b279 | blueswir1 | case INDEX_op_shr_i64:
|
1047 | 8289b279 | blueswir1 | c = SHIFT_SRLX; |
1048 | 8289b279 | blueswir1 | goto gen_arith32;
|
1049 | 8289b279 | blueswir1 | case INDEX_op_sar_i64:
|
1050 | 8289b279 | blueswir1 | c = SHIFT_SRAX; |
1051 | 8289b279 | blueswir1 | goto gen_arith32;
|
1052 | 8289b279 | blueswir1 | case INDEX_op_mul_i64:
|
1053 | 8289b279 | blueswir1 | c = ARITH_MULX; |
1054 | 8289b279 | blueswir1 | goto gen_arith32;
|
1055 | 8289b279 | blueswir1 | case INDEX_op_div2_i64:
|
1056 | 53cd9273 | blueswir1 | c = ARITH_SDIVX; |
1057 | 8289b279 | blueswir1 | goto gen_arith32;
|
1058 | 8289b279 | blueswir1 | case INDEX_op_divu2_i64:
|
1059 | 8289b279 | blueswir1 | c = ARITH_UDIVX; |
1060 | 8289b279 | blueswir1 | goto gen_arith32;
|
1061 | 8289b279 | blueswir1 | |
1062 | 8289b279 | blueswir1 | case INDEX_op_brcond_i64:
|
1063 | f5ef6aac | blueswir1 | tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], |
1064 | f5ef6aac | blueswir1 | args[3]);
|
1065 | 8289b279 | blueswir1 | break;
|
1066 | 8289b279 | blueswir1 | case INDEX_op_qemu_ld64:
|
1067 | f5ef6aac | blueswir1 | tcg_out_qemu_ld(s, args, 3);
|
1068 | 8289b279 | blueswir1 | break;
|
1069 | 8289b279 | blueswir1 | case INDEX_op_qemu_st64:
|
1070 | f5ef6aac | blueswir1 | tcg_out_qemu_st(s, args, 3);
|
1071 | 8289b279 | blueswir1 | break;
|
1072 | 8289b279 | blueswir1 | |
1073 | 8289b279 | blueswir1 | #endif
|
1074 | 53cd9273 | blueswir1 | gen_arith32:
|
1075 | 53cd9273 | blueswir1 | if (const_args[2]) { |
1076 | 53cd9273 | blueswir1 | tcg_out_arithi(s, args[0], args[1], args[2], c); |
1077 | 53cd9273 | blueswir1 | } else {
|
1078 | 53cd9273 | blueswir1 | tcg_out_arith(s, args[0], args[1], args[2], c); |
1079 | 53cd9273 | blueswir1 | } |
1080 | 53cd9273 | blueswir1 | break;
|
1081 | 53cd9273 | blueswir1 | |
1082 | 8289b279 | blueswir1 | default:
|
1083 | 8289b279 | blueswir1 | fprintf(stderr, "unknown opcode 0x%x\n", opc);
|
1084 | 8289b279 | blueswir1 | tcg_abort(); |
1085 | 8289b279 | blueswir1 | } |
1086 | 8289b279 | blueswir1 | } |
1087 | 8289b279 | blueswir1 | |
1088 | 8289b279 | blueswir1 | static const TCGTargetOpDef sparc_op_defs[] = { |
1089 | 8289b279 | blueswir1 | { INDEX_op_exit_tb, { } }, |
1090 | b3db8758 | blueswir1 | { INDEX_op_goto_tb, { } }, |
1091 | 8289b279 | blueswir1 | { INDEX_op_call, { "ri" } },
|
1092 | 8289b279 | blueswir1 | { INDEX_op_jmp, { "ri" } },
|
1093 | 8289b279 | blueswir1 | { INDEX_op_br, { } }, |
1094 | 8289b279 | blueswir1 | |
1095 | 8289b279 | blueswir1 | { INDEX_op_mov_i32, { "r", "r" } }, |
1096 | 8289b279 | blueswir1 | { INDEX_op_movi_i32, { "r" } },
|
1097 | 8289b279 | blueswir1 | { INDEX_op_ld8u_i32, { "r", "r" } }, |
1098 | 8289b279 | blueswir1 | { INDEX_op_ld8s_i32, { "r", "r" } }, |
1099 | 8289b279 | blueswir1 | { INDEX_op_ld16u_i32, { "r", "r" } }, |
1100 | 8289b279 | blueswir1 | { INDEX_op_ld16s_i32, { "r", "r" } }, |
1101 | 8289b279 | blueswir1 | { INDEX_op_ld_i32, { "r", "r" } }, |
1102 | 8289b279 | blueswir1 | { INDEX_op_st8_i32, { "r", "r" } }, |
1103 | 8289b279 | blueswir1 | { INDEX_op_st16_i32, { "r", "r" } }, |
1104 | 8289b279 | blueswir1 | { INDEX_op_st_i32, { "r", "r" } }, |
1105 | 8289b279 | blueswir1 | |
1106 | 53cd9273 | blueswir1 | { INDEX_op_add_i32, { "r", "r", "rJ" } }, |
1107 | 53cd9273 | blueswir1 | { INDEX_op_mul_i32, { "r", "r", "rJ" } }, |
1108 | 8289b279 | blueswir1 | { INDEX_op_div2_i32, { "r", "r", "0", "1", "r" } }, |
1109 | 8289b279 | blueswir1 | { INDEX_op_divu2_i32, { "r", "r", "0", "1", "r" } }, |
1110 | 53cd9273 | blueswir1 | { INDEX_op_sub_i32, { "r", "r", "rJ" } }, |
1111 | 53cd9273 | blueswir1 | { INDEX_op_and_i32, { "r", "r", "rJ" } }, |
1112 | 53cd9273 | blueswir1 | { INDEX_op_or_i32, { "r", "r", "rJ" } }, |
1113 | 53cd9273 | blueswir1 | { INDEX_op_xor_i32, { "r", "r", "rJ" } }, |
1114 | 8289b279 | blueswir1 | |
1115 | 53cd9273 | blueswir1 | { INDEX_op_shl_i32, { "r", "r", "rJ" } }, |
1116 | 53cd9273 | blueswir1 | { INDEX_op_shr_i32, { "r", "r", "rJ" } }, |
1117 | 53cd9273 | blueswir1 | { INDEX_op_sar_i32, { "r", "r", "rJ" } }, |
1118 | 8289b279 | blueswir1 | |
1119 | 8289b279 | blueswir1 | { INDEX_op_brcond_i32, { "r", "ri" } }, |
1120 | 8289b279 | blueswir1 | |
1121 | 8289b279 | blueswir1 | { INDEX_op_qemu_ld8u, { "r", "L" } }, |
1122 | 8289b279 | blueswir1 | { INDEX_op_qemu_ld8s, { "r", "L" } }, |
1123 | 8289b279 | blueswir1 | { INDEX_op_qemu_ld16u, { "r", "L" } }, |
1124 | 8289b279 | blueswir1 | { INDEX_op_qemu_ld16s, { "r", "L" } }, |
1125 | 8289b279 | blueswir1 | { INDEX_op_qemu_ld32u, { "r", "L" } }, |
1126 | 8289b279 | blueswir1 | { INDEX_op_qemu_ld32s, { "r", "L" } }, |
1127 | 8289b279 | blueswir1 | |
1128 | 8289b279 | blueswir1 | { INDEX_op_qemu_st8, { "L", "L" } }, |
1129 | 8289b279 | blueswir1 | { INDEX_op_qemu_st16, { "L", "L" } }, |
1130 | 8289b279 | blueswir1 | { INDEX_op_qemu_st32, { "L", "L" } }, |
1131 | 8289b279 | blueswir1 | |
1132 | 8289b279 | blueswir1 | #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
|
1133 | 8289b279 | blueswir1 | { INDEX_op_mov_i64, { "r", "r" } }, |
1134 | 8289b279 | blueswir1 | { INDEX_op_movi_i64, { "r" } },
|
1135 | 8289b279 | blueswir1 | { INDEX_op_ld8u_i64, { "r", "r" } }, |
1136 | 8289b279 | blueswir1 | { INDEX_op_ld8s_i64, { "r", "r" } }, |
1137 | 8289b279 | blueswir1 | { INDEX_op_ld16u_i64, { "r", "r" } }, |
1138 | 8289b279 | blueswir1 | { INDEX_op_ld16s_i64, { "r", "r" } }, |
1139 | 8289b279 | blueswir1 | { INDEX_op_ld32u_i64, { "r", "r" } }, |
1140 | 8289b279 | blueswir1 | { INDEX_op_ld32s_i64, { "r", "r" } }, |
1141 | 8289b279 | blueswir1 | { INDEX_op_ld_i64, { "r", "r" } }, |
1142 | 8289b279 | blueswir1 | { INDEX_op_st8_i64, { "r", "r" } }, |
1143 | 8289b279 | blueswir1 | { INDEX_op_st16_i64, { "r", "r" } }, |
1144 | 8289b279 | blueswir1 | { INDEX_op_st32_i64, { "r", "r" } }, |
1145 | 8289b279 | blueswir1 | { INDEX_op_st_i64, { "r", "r" } }, |
1146 | 56fc64df | blueswir1 | { INDEX_op_qemu_ld64, { "L", "L" } }, |
1147 | 56fc64df | blueswir1 | { INDEX_op_qemu_st64, { "L", "L" } }, |
1148 | 8289b279 | blueswir1 | |
1149 | 53cd9273 | blueswir1 | { INDEX_op_add_i64, { "r", "r", "rJ" } }, |
1150 | 53cd9273 | blueswir1 | { INDEX_op_mul_i64, { "r", "r", "rJ" } }, |
1151 | 8289b279 | blueswir1 | { INDEX_op_div2_i64, { "r", "r", "0", "1", "r" } }, |
1152 | 8289b279 | blueswir1 | { INDEX_op_divu2_i64, { "r", "r", "0", "1", "r" } }, |
1153 | 53cd9273 | blueswir1 | { INDEX_op_sub_i64, { "r", "r", "rJ" } }, |
1154 | 53cd9273 | blueswir1 | { INDEX_op_and_i64, { "r", "r", "rJ" } }, |
1155 | 53cd9273 | blueswir1 | { INDEX_op_or_i64, { "r", "r", "rJ" } }, |
1156 | 53cd9273 | blueswir1 | { INDEX_op_xor_i64, { "r", "r", "rJ" } }, |
1157 | 8289b279 | blueswir1 | |
1158 | 53cd9273 | blueswir1 | { INDEX_op_shl_i64, { "r", "r", "rJ" } }, |
1159 | 53cd9273 | blueswir1 | { INDEX_op_shr_i64, { "r", "r", "rJ" } }, |
1160 | 53cd9273 | blueswir1 | { INDEX_op_sar_i64, { "r", "r", "rJ" } }, |
1161 | 8289b279 | blueswir1 | |
1162 | 8289b279 | blueswir1 | { INDEX_op_brcond_i64, { "r", "ri" } }, |
1163 | 8289b279 | blueswir1 | #endif
|
1164 | 8289b279 | blueswir1 | { -1 },
|
1165 | 8289b279 | blueswir1 | }; |
1166 | 8289b279 | blueswir1 | |
1167 | 8289b279 | blueswir1 | void tcg_target_init(TCGContext *s)
|
1168 | 8289b279 | blueswir1 | { |
1169 | 8289b279 | blueswir1 | tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff); |
1170 | 8289b279 | blueswir1 | #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
|
1171 | 8289b279 | blueswir1 | tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff); |
1172 | 8289b279 | blueswir1 | #endif
|
1173 | 8289b279 | blueswir1 | tcg_regset_set32(tcg_target_call_clobber_regs, 0,
|
1174 | b3db8758 | blueswir1 | (1 << TCG_REG_G1) |
|
1175 | b3db8758 | blueswir1 | (1 << TCG_REG_G2) |
|
1176 | b3db8758 | blueswir1 | (1 << TCG_REG_G3) |
|
1177 | b3db8758 | blueswir1 | (1 << TCG_REG_G4) |
|
1178 | b3db8758 | blueswir1 | (1 << TCG_REG_G5) |
|
1179 | b3db8758 | blueswir1 | (1 << TCG_REG_G6) |
|
1180 | b3db8758 | blueswir1 | (1 << TCG_REG_G7) |
|
1181 | 8289b279 | blueswir1 | (1 << TCG_REG_O0) |
|
1182 | 8289b279 | blueswir1 | (1 << TCG_REG_O1) |
|
1183 | 8289b279 | blueswir1 | (1 << TCG_REG_O2) |
|
1184 | 8289b279 | blueswir1 | (1 << TCG_REG_O3) |
|
1185 | 8289b279 | blueswir1 | (1 << TCG_REG_O4) |
|
1186 | 8289b279 | blueswir1 | (1 << TCG_REG_O5) |
|
1187 | 8289b279 | blueswir1 | (1 << TCG_REG_O7));
|
1188 | 8289b279 | blueswir1 | |
1189 | 8289b279 | blueswir1 | tcg_regset_clear(s->reserved_regs); |
1190 | 8289b279 | blueswir1 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0); |
1191 | d795eb86 | blueswir1 | #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
|
1192 | d795eb86 | blueswir1 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_I4); // for internal use
|
1193 | d795eb86 | blueswir1 | #endif
|
1194 | 53cd9273 | blueswir1 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_I5); // for internal use
|
1195 | 8289b279 | blueswir1 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_I6); |
1196 | 8289b279 | blueswir1 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_I7); |
1197 | 8289b279 | blueswir1 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_O6); |
1198 | 8289b279 | blueswir1 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_O7); |
1199 | 8289b279 | blueswir1 | tcg_add_target_add_op_defs(sparc_op_defs); |
1200 | 8289b279 | blueswir1 | } |