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pci_host: convert conf index and data ports to memory API
Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Avi Kivity <avi@redhat.com>
Revert "Merge remote-tracking branch 'qemu-kvm/memory/batch' into staging"
This reverts commit 8ef9ea85a2cc1007eaefa53e6871f1f83bcef22d, reversingchanges made to 444dc48298c480e42e15a8fe676be737d8a6b2a1.
From Avi:
Please revert the entire pull (git revert 8ef9ea85a2cc1) while I work this...
Use glib memory allocation and free functions
qemu_malloc/qemu_free no longer exist after this commit.
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
pci: pass I/O address space to new PCI bus
This lets us register BARs in the I/O address space.
Reviewed-by: Richard Henderson <rth@twiddle.net>Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>Signed-off-by: Avi Kivity <avi@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
pci: pass address space to pci bus when created
This is now done sloppily, via get_system_memory(). Eventually callerswill be converted to stop using that.
Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>Signed-off-by: Avi Kivity <avi@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
vmstate: port ppc4xx_pci
Signed-off-by: Juan Quintela <quintela@redhat.com>
ppc4xx_pci: Declare as little endian
This patch replaces explicit bswaps with endianness hints to themmio layer.
Signed-off-by: Alexander Graf <agraf@suse.de>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Add endianness as io mem parameter
As stated before, devices can be little, big or native endian. Thetarget endianness is not of their concern, so we need to push thingsdown a level.
This patch adds a parameter to cpu_register_io_memory that allows adevice to choose its endianness. For now, all devices simply choose...
savevm: Add DeviceState param
When available, we'd like to be able to access the DeviceStatewhen registering a savevm. For buses with a get_dev_path()function, this will allow us to create more unique savevmid strings.
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>...
Compile pci_host only once
Convert pci_host_conf_register_mmio_noswap(x) topci_host_conf_register_mmio(x, 0).
Convert pci_host_conf_register_mmio(x) topci_host_conf_register_mmio(x, 1) for big endian hosts, all caseshappen to be BE.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
pci: shorten pci_host_{conf, data}_register_xxx function a bit.
pci_host_data_register_io_memory and its variants are too long a bit.So shorten them. Now they arepci_host_{conf, data}_register_{mmio, mmio_noswap, ioport}()
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>...
pci_host.h: move functions in pci_host.h into .c file.
split static functions in pci_host.h into pci_host.c andpci_host_template.h.Later a structures declared in pci_host.h, PCIHostState, will be used.However pci_host.h doesn't allow to include itself easily. This patches...
Revert "Get rid of _t suffix"
In the very least, a change like this requires discussion on the list.
The naming convention is goofy and it causes a massive merge problem. Somethinglike this must be presented on the list first so people can provide input...
Get rid of _t suffix
Some not so obvious bits, slirp and Xen were left alone for the timebeing.
Signed-off-by: malc <av1474@comtv.ru>
We want the argument pass to set_irq to be opaque
piix_pci want to pass more things that the pic
Signed-off-by: Juan Quintela <quintela@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Make CPURead/WriteFunc structure 'const'
Update to a hopefully more future proof FSF address
Revert "Introduce reset notifier order"
This reverts commit 8217606e6edb49591b4a6fd5a0d1229cebe470a9 (andupdates later added users of qemu_register_reset), we solved theproblem it originally addressed less invasively.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>...
Remove io_index argument from cpu_register_io_memory()
The parameter is always zero except when registering the three internalio regions (ROM, unassigned, notdirty). Remove the parameter to reducethe API's power, thus facilitating future change.
Signed-off-by: Avi Kivity <avi@redhat.com>...
Add common BusState
Implement and use a common device bus state. The main side-effect isthat creating a bus and attaching it to a parent device are no longerseparate operations. For legacy code we allow a NULL parent, but thatshould go away eventually....
Introduce reset notifier order
Add the parameter 'order' to qemu_register_reset and sort callbacks onregistration. On system reset, callbacks with lower order will beinvoked before those with higher order. Update all existing users to thestandard order 0....
Replace gcc variadic macro extension with C99 version
Add and use remaining #defines for PCI device IDs (Stuart Brady)
This patch adds and uses #defines for the remaining hardcoded PCIdevice IDs. It also moves definitions taken from linux/pci_ids.hinto a separate header (hw/pci_ids.h), removes the 'RTL' from...
hw: remove error handling from qemu_malloc() callers (Avi Kivity)
Signed-off-by: Avi Kivity <avi@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6529 c046a42c-6fe2-441c-8c8c-71466251a162
Add and use #defines for PCI device classes
This patch adds and uses #defines for PCI device classes and subclases,using a new pci_config_set_class() function, similar to the recentlyadded pci_config_set_vendor_id() and pci_config_set_device_id().
Change since v1: fixed compilation of hw/sun4u.c...
Define PCI vendor and device IDs in pci.h (Stuart Brady)
This patch defines PCI vendor and device IDs in pci.h (matching thosefrom Linux's pci_ids.h), and uses those definitions where appropriate.
Change from v1: Introduces pci_config_set_vendor_id() / pci_config_set_device_id()...
target-ppc: kill a few warnings
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5941 c046a42c-6fe2-441c-8c8c-71466251a162
hw/ppc4xx_pci.c: kill two warnings
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5883 c046a42c-6fe2-441c-8c8c-71466251a162
IBM PowerPC 4xx 32-bit PCI controller emulation
This PCI controller can be found on a number of 4xx SoCs, including the 440EP.
Signed-off-by: Hollis Blanchard <hollisb@us.ibm.com>Acked-by: Anthony Liguori <aliguori@us.ibm.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>...