qxl: clear irq on reset
Without this we occasionally trigger an assert athw/pci/pci.c:pcibus_reset that asserts the irq_count is zero on reset.
This has become a problem with the new drm driver for linux, since doinga reboot from console causes a race between console updates that set the...
hw/display/qxl: fix signed to unsigned comparison
Several small signedness / overflow corrections to qxl_create_guest_primary:1. use 64 bit unsigned for size to avoid overflow possible from two 32bit multiplicants.2. correct sign for requested_height3. add a more verbose error message when setting guest bug state (which...
Add the ability to vary Spice playback and record rates, to facilitate Opus support.
Signed-off-by: Jeremy White <jwhite@codeweavers.com>Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Merge remote-tracking branch 'qmp-unstable/queue/qmp' into staging
Merge remote-tracking branch 'pmaydell/tags/pull-target-arm-20140131' into staging
target-arm queue: * implementation of first part of the A64 Neon instruction set * v8 AArch32 rounding and 16<->64 fp conversion instructions * fix MIDR value on Zynq boards...
Merge remote-tracking branch 'remotes/awilliam/tags/vfio-pci-for-qemu-20140128.0' into staging
vfio-pci updates include: - Destroy MemoryRegions on device teardown - Print warnings around PCI option ROM failures - Skip bogus mappings from 64bit BAR sizing...
Merge remote-tracking branch 'remotes/sstabellini/xen-140130' into staging
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
arm_gic: Introduce define for GIC_NR_SGIS
Instead of hardcoding 16 various places in the code, use a define tomake it more clear what is going on.
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>...
arm_gic: Fix GICD_ICPENDR and GICD_ISPENDR writes
Fix two bugs that would allow changing the state of SGIs through theICPENDR and ISPENDRs.
target-arm: A64: Add top level decode for SIMD 3-same group
Add top level decode for the A64 SIMD three regs same group(C3.6.16), splitting it into the pairwise, logical, float andinteger subgroups.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
target-arm: A64: Add logic ops from SIMD 3 same group
Add support for the logical operations (ORR, AND, BIC, ORN, EOR, BSL,BIT and BIF) from the SIMD 3 register same group (C3.6.16).
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
target-arm: A64: Add integer ops from SIMD 3-same group
Add some of the integer operations in the SIMD 3-same group:specifically, the comparisons, addition and subtraction.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Richard Henderson <rth@twiddle.net>
target-arm: A64: Add simple SIMD 3-same floating point ops
Implement a simple subset of the SIMD 3-same floating pointoperations. This includes a common helper function used for bothscalar and vector ops; FABD is the only currently implementedshared op....
target-arm: A64: Add SIMD shift by immediate
This implements a subset of the AdvSIMD shift operations (namely all thenone saturating or narrowing ones). The actual shift generation codeitself is common for both the scalar and vector cases but wrapped with...
target-arm: A64: Add SIMD three-different multiply accumulate insns
Add support for the multiply-accumulate instructions from theSIMD three-different instructions group (C3.6.15): * skeleton decode of unallocated encodings and split of the group into its three sub-parts...
target-arm: A64: Add SIMD three-different ABDL instructions
Implement the absolute-difference instructions in the SIMDthree-different group: SABAL, SABAL2, UABAL, UABAL2, SABDL,SABDL2, UABDL, UABDL2.
target-arm: A64: Add SIMD scalar 3 same add, sub and compare ops
Implement the add, sub and compare ops from the SIMD "scalar three same" group.
target-arm: Add set_neon_rmode helper
This helper sets the rounding mode in the standard_fp_status word toallow NEON instructions to modify the rounding mode whilst using thestandard FPSCR values for everything else.
Signed-off-by: Will Newton <will.newton@linaro.org>...
target-arm: Add AArch32 SIMD VRINTA, VRINTN, VRINTP, VRINTM, VRINTZ
Add support for the AArch32 Advanced SIMD VRINTA, VRINTN, VRINTPVRINTM and VRINTZ instructions.
Signed-off-by: Will Newton <will.newton@linaro.org>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Add AArch32 FP VCVTA, VCVTN, VCVTP and VCVTM
Add support for the AArch32 floating-point VCVTA, VCVTN, VCVTPand VCVTM instructions.
target-arm: Add AArch32 SIMD VCVTA, VCVTN, VCVTP and VCVTM
Add support for the AArch32 Advanced SIMD VCVTA, VCVTN, VCVTPand VCVTM instructions.
target-arm: Add support for AArch32 FP VRINTR
Add support for the AArch32 floating-point VRINTR instruction.
target-arm: Add support for AArch32 FP VRINTZ
Add support for the AArch32 floating-point VRINTZ instruction.
target-arm: Add support for AArch32 FP VRINTX
Add support for the AArch32 floating-point VRINTX instruction.
target-arm: Add support for AArch32 SIMD VRINTX
Add support for the AArch32 Advanced SIMD VRINTX instruction.
Signed-off-by: Will Newton <will.newton@linaro.org>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
ZYNQ: Implement board MIDR control for Zynq
This patch uses the fact that the midr variable is now a propertyThis patch sets the midr variable to the boards custom midr
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>Message-id: a3754b10d150af72e4688a993e484fa2b9b8fa21.1390176489.git.alistair.francis@xilinx.com...
display: avoid multi-statement macro
For blizzard, pl110 and tc6393xb this is harmless, but for pxa2xxCoverity noticed that it is used inside an "if" statement.Fix it because it's the file with the highest number of defectsin the whole QEMU tree! Use "do...while (0)", or just remove the...
target-arm: Move arm_rmode_to_sf to a shared location.
This function will be needed for AArch32 ARMv8 support, so move it tohelper.c where it can be used by both targets. Also moves the code outof line, but as it is quite a large function I don't believe this...
target-arm: Add AArch32 FP VRINTA, VRINTN, VRINTP and VRINTM
Add support for AArch32 ARMv8 FP VRINTA, VRINTN, VRINTP and VRINTMinstructions.
target-arm: A64: Add SIMD modified immediate group
This patch adds support for the AdvSIMD modified immediate group(C3.6.6) with all its suboperations (movi, orr, fmov, mvni, bic).
Signed-off-by: Alexander Graf <agraf@suse.de>[AJB: new decode struct, minor bug fixes, optimisation]...
target-arm: A64: Add SIMD scalar copy instructions
Add support for the SIMD scalar copy instruction group (C3.6.7),which consists of the single instruction DUP (element, scalar).
hw/arm/boot: Don't set up ATAGS for autogenerated dtb booting
The code which decides whether to set up the ATAGS data structure onreset was using the wrong conditional, which meant we were creatingan ATAGS structure when doing a device-tree boot if the dtb was...
ARM: Convert MIDR to a property
Convert the MIDR register to a property. This allows boards to later seta custom MIDR value. This has been done in such a way to maintaincompatibility with all existing CPUs and boards
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>...
target-arm: A64: Add SIMD TBL/TBLX
Add support for the SIMD TBL/TBLX instructions (group C3.6.2).
Signed-off-by: Michael Matz <matz@suse.de>[PMM: rewritten to do more of the decode in translate-a64.c, and to do only one 64 bit pass at a time in the helper]...
target-arm: A64: Add SIMD ZIP/UZP/TRN
Add support for the SIMD ZIP/UZIP/TRN instruction group(C3.6.3).
Signed-off-by: Michael Matz <matz@suse.de>[PMM: use new do_vec_get/set etc functions and generally update to new codebase standards; refactor to pull per-element loop outside switch]...
target-arm: A64: Add SIMD across-lanes instructions
Add support for the SIMD "across lanes" instruction group (C3.6.4).
Signed-off-by: Michael Matz <matz@suse.de>[PMM: Updated to current codebase, added fp min/max ops, added unallocated encoding checks]...
target-arm: A64: Add SIMD copy operations
This adds support for the all the AdvSIMD vector copy operations(ARM ARM 3.6.5).
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Richard Henderson <rth@twiddle.net>
target-arm: A64: Add SIMD ld/st multiple
This adds support support for the SIMD load/storemultiple category of instructions.
This also brings in a couple of helper functions for manipulatingsections of the SIMD registers:
target-arm: A64: Add SIMD ld/st single
Implement the SIMD ld/st single structure instructions.
target-arm: A64: Add decode skeleton for SIMD data processing insns
Add decode skeleton and function placeholders for all the SIMD dataprocessing instructions. Due to the complexity of this part of thetable the normal extract and switch approach gets very messy very...
target-arm: A64: Add SIMD EXT
Add support for the SIMD EXT instruction (the only one in itsgroup, C3.6.1).
Merge remote-tracking branch 'stefanha/tags/tracing-pull-request' into staging
Tracing pull request
Merge remote-tracking branch 'mst/tags/for_anthony' into staging
acpi,pci,pc,virtio fixes and enhancements
This includes new unit-tests for acpi by Marcel,hotplug for pci bridges by myself (piix only so far)and cpu hotplug for q35.And a bunch of fixes all over the place as usual....
Merge remote-tracking branch 'sstabellini/xen-170114' into staging
Message-id: alpine.DEB.2.02.1401171537140.21510@kaball.uk.xensource.com...
Merge remote-tracking branch 'stefanha/tags/net-pull-request' into staging
Net patches
Merge remote-tracking branch 'rth/tcg-movbe' into staging
address_space_translate: do not cross page boundaries
The following commit:
commit 149f54b53b7666a3facd45e86eece60ce7d3b114Author: Paolo Bonzini <pbonzini@redhat.com>Date: Fri May 24 12:59:37 2013 +0200
memory: add address_space_translate
breaks Xen support in QEMU, in particular the Xen mapcache. The effect...
Merge remote-tracking branch 'mjt/tags/trivial-patches-2014-01-16' into staging
trivial-patches for 2014-01-16
TCG: Fix I64-on-32bit-host temporaries
We have cache pools of temporaries that we can reuse later when they'vealready been allocated before.
These cache pools differenciate between the target TCG variable type theycontain. So we have one pool for I32 and one pool for I64 variables....
monitor: Cleanup mon->outbuf on write error
In case monitor_flush() fails to write the contents of mon->outbuf tothe output device, mon->outbuf is not cleaned up properly. Check thereturn code of the qemu_chr_fe_write() function and cleanup the outbufif it fails....
virtio_rng: replace custom backend API with UserCreatable.complete() callback
in addition fix default backend leak by releasing it if itsinitialization failed.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>...
add optional 2nd stage initialization to -object/object-add commands
Introduces USER_CREATABLE interface that must be implemented byobjects which are designed to created with -object CLI option orobject-add QMP command.
Interface provides an ability to do an optional second stage...
object_add: consolidate error handling
Signed-off-by: Igor Mammedov <imammedo@redhat.com>Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>Signed-off-by: Luiz Capitulino <lcapitulino@redhat.com>
vl.c: -object: don't ignore duplicate 'id'
object_property_add_child() may fail if 'id' matchesan already existing object. Which means an incorrectcommand line.So instead of silently ignoring error, report it andterminate QEMU.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>...
vfio: correct debug macro typo
Change to DEBUG_VFIO in vfio_msi_interrupt() for debugmessages to get printed
Signed-off-by: Bandan Das <bsd@redhat.com>Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
tracing: start trace processing thread in final child process
When running with trace backend e.g. "simple" the writer thread needs to beimplemented in the same process context as the trace points that will beprocessed. Under libvirtd control, qemu gets first started in daemonized...
trace: [simple] Do not include "trace/simple.h" in generated tracer headers
The header is not necessary, given that the simple backend does not define anyinlined tracing routines.
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
trace: add glib 2.32+ static GMutex support
The GStaticMutex API was deprecated in glib 2.32. We cannot switch overto GMutex unconditionally since we would drop support for older glibversions. But the deprecated API warnings during build are annoying so...
trace: fix simple trace "disable" keyword
The trace-events "disable" keyword turns an event into a nop atcompile-time. This is important for high-frequency events that canimpact performance.
The "disable" keyword is currently broken in the simple trace backend....
net: Use g_strdup_printf instead of snprintf.
assign_name() in net/net.c is using snprintf + g_strdup to get the sameresult as g_strdup_printf.
Signed-off-by: Hani Benhabiles <kroosec@gmail.com>Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Fix lan9118 TX "CMD A" handling
The 9118 ethernet controller supports transmission of multi-buffer packetswith arbitrary byte alignment of the start and end bytes. All writes tothe packet fifo are 32 bits, so the controller discards bytes at the beginning...
Fix lan9118 buffer length handling
tap-linux: Get features once and use it many times
Signed-off-by: Kusanagi Kouichi <slash@ac.auone-net.jp>Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
acpi-test: update expected AML since recent changes
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
hw/pci: fix error flow in pci multifunction init
Scenario: - There is a non multifunction pci device A on 00:0X.0. - Hot-plug another multifunction pci device B at 00:0X.1. - The operation will fail of course. - Try to hot-plug the B device 2-3 more times, qemu will crash....
pc: Save size of RAM below 4GB
The ram_below_4g value will be useful in other places, such as the ACPItable code, and other code that currently requires passingbelow_4g_mem_size around in function arguments.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>...
acpi: Fix PCI hole handling on build_srat()
The original SeaBIOS code used the RamSize variable, that was used bySeaBIOS for the size of RAM below 4GB, not for all RAM. When copied toQEMU, the code was changed to use the full RAM size, and this broke the...
q35: gigabyte alignment for ram
Map 2G (q35) of memory below 4G, so the RAM piecesare nicely aligned to gigabyte borders.
Keep old memory layout for (a) old machine types and (b) in case allmemory fits below 4G and thus we don't have to split RAM into pieces...
q35: document gigabyte_align
Document the logic behind the below/above 4G split.
MAINTAINERS: add self as virtio co-maintainer
This will help make sure I get Cc'd on patches.
piix4: add acpi pci hotplug support
Add support for acpi pci hotplug using thenew infrastructure.PIIX4 legacy interface is maintained as is formachine types 1.7 and older.
acpi-build: enable hotplug for PCI bridges
This enables support for device hotplug behindpci bridges. Bridge devices themselves needto be pre-configured on qemu command line.
Design: - at machine init time, assign "bsel" property to bridges with hotplug support...
acpi: factor out common cpu hotplug code for PIIX4/Q35
.. so it could be used for adding CPU hotplug to Q35 machine
Add an additional header with that will be shared betweenC and ASL code: include/hw/acpi/cpu_hotplug_defs.h
acpi: ich9: add CPU hotplug handling to Q35 machine
.. use IO port 0cd8-0xcf7 range for CPU present bitmap
Signed-off-by: Igor Mammedov <imammedo@redhat.com>Reviewed-by: Michael S. Tsirkin <mst@redhat.com>Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
pc: set PRST base in DSDT depending on chipset
pc: PIIX DSDT: exclude CPU/PCI hotplug & GPE0 IO range from PCI bus resources
.. so that they might not be used by PCI devices.
Note:Resort to concatenating templates with preprocessor help,because 1.0b spec isn't supporting ConcatenateResTemplate,as result Windows XP fails to execute PCI0._CRS method if...
pc: Q35 DSDT: exclude CPU hotplug IO range from PCI bus resources
... for range defined at hw/acpi/ich9.c:ICH9_PROC_BASE
pc: ACPI: expose PRST IO range via _CRS
.. so OSPM could notice resource conflict if there is any.
pc: ACPI: unify source of CPU hotplug IO base/len
use C headers defines as source of IO base/len for respectivevalues in ASL code.
pc: ACPI: update acpi-dsdt.hex.generated q35-acpi-dsdt.hex.generated
acpi unit-test: add test files
Added unit-test's expected aml files to be comparedwith the actual ACPI tables.
Signed-off-by: Marcel Apfelbaum <marcel.a@redhat.com>Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
configure: added acpi unit-test files
Ensure configure will set-up links for the filesif the build is created in other directory.
acpi unit-test: compare DSDT and SSDT tables against expected values
This test will run only if iasl is installed on the host machine.The test plan: 1. Dumps the ACPI tables as AML on the disk. 2. Runs iasl to disassembly the tables into ASL files. 3. Runs iasl to disassembly the offline AML files into ASL files....
configure: add CONFIG_IASL to config-host.h
Acpi unit-tests will extract iasl executablefrom CONFIG_IASL define.
acpi unit-test: extract iasl executable from configuration
The test checked if iasl is installed by running "iasl" and checking the error output.It is better to use the iasl executable as appearsin configuration.
Signed-off-by: Marcel Apfelbaum <marcel.a@redhat.com>...
acpi unit-test: added script to rebuild the expected aml files
Acpi unit-test will fail every time the acpi tables change.This script rebuild the expected aml files, so the testwill pass. It also validates the modifications.
acpi unit-test: hook to rebuild expected aml files
When running the test with TEST_ACPI_REBUILD_AML=y environmentvariable, the test will rebuild and validate the expected amlfiles.
tests: fix acpi to work on bigendian host
Double endianness convertion make this test failing on POWERPC machinerunning in big-endian.
This fixes the test to success on big-endian host.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
acpi unit-test: renamed ssdt_tables to tables
Just a refactoring, ssdt_tables name was confusing asit included other tables as well.
Signed-off-by: Marcel Apfelbaum <marcel.a@redhat.com>Reviewed-by: Michael S. Tsirkin <mst@redhat.com>Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
acpi unit-test: resolved iasl crash
It seems that iasl has an issue when disassemblessome ACPI tables using the command line:iasl -e DSDT -e SSDT -d HPET
Modified the iasl command line to "iasl -d HPET" until the problem is solved. The command lineremained the same for DSDT and SSDT tables....
acpi unit-test: do not fail on asl mismatch
The asl comparison will break every time the ACPItables are updated. This may break the git bisect.Instead of failing print a warning on stderrincluding the retained asl files, so they can becompared offline....
pc: make: fix dependencies: rebuild when included file is changed
some *.dsl files include another *.dsl files but there weren'tany dependicies and when included file changed target table wasn'trebuild. Fix this by using the same auto dependency generation...
pci: add pci_for_each_bus_depth_first
Useful for ACPI hotplug.
pcihp: generalization of piix4 acpi
Add ACPI based PCI hotplug library with bridge hotplugsupport.Design - each bus gets assigned "bsel" property. - ACPI code writes this number to a new BNUM register, then uses existing UP/DOWN registers to probe slot status;...
Python-lang gdb script to extract x86_64 guest vmcore from qemu coredump
When qemu dies unexpectedly, for example in response to an explicitabort() call, or (more importantly) when an external signal is deliveredto it that results in a coredump, sometimes it is useful to extract the...
Add DSDT node for AppleSMC
AppleSMC (-device isa-applesmc) is required to boot OS X guests.OS X expects a SMC node to be present in the ACPI DSDT. This patchadds a SMC node to the DSDT, and dynamically patches the return valueof SMC._STA to either 0x0B if the chip is present, or otherwise to 0x00,...
ACPI: Fix AppleSMC _STA size
Minimize the storage used for AppleSMC's _STA (8bit), relying on ASLto implicitly convert it to the officially specified 32bit value.
Signed-off-by: Gabriel Somlo <somlo@cmu.edu>Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
virtio: Fix return value for dummy function vhost_net_virtqueue_pending
cgcc complains that -ENOSYS is not a good value for 'bool'.
A dummy virtio will never have pending queue entries, so let us returnfalse.
Signed-off-by: Stefan Weil <sw@weilnetz.de>...
tcg/i386: cleanup useless #ifdef
TCG_TARGET_HAS_movcond_i32 is always defined to 1 in tcg-target.h, soremove the corresponding #ifdef #endif sequence, left from a previousrefactoring.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg/i386: use movbe instruction in qemu_ldst routines
The movbe instruction has been added on some Intel Atom CPUs and onrecent Intel Haswell CPUs. It allows to load/store a value and at thesame time bswap it.
This patch detects the avaibility of this instruction and when available...