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tcg-arm: The shift count of op_rotl_i32 is in args2 not args1.
It's this that should be subtracted from 0x20 when converting to a right rotate.
Cc: qemu-stable@nongnu.orgSigned-off-by: Huw Davies <huw@codeweavers.com>Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-arm: Use qemu_getauxval
Allow host detection on linux systems without glibc 2.16 or later.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-arm: Tidy variable naming convention in qemu_ld/st
s/addr_reg2/addrhi/s/addr_reg/addrlo/s/data_reg2/datahi/s/data_reg/datalo/
Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-arm: Convert to new ldst opcodes
tcg-arm: Improve GUEST_BASE qemu_ld/st
If we pull the code to emit the actual load/store into a subroutine,we can share the reg+reg addressing mode code between softmmu andusermode. This lets us load GUEST_BASE into a temporary registerrather than attempting to add it piece-wise to the address....
tcg-arm: Use TCGMemOp within qemu_ldst routines
tcg-arm: Convert to le/be ldst helpers
tcg: Add tcg-be-ldst.h
Move TCGLabelQemuLdst and related stuff out of tcg.h.
tcg-arm: Use ldrd/strd for appropriate qemu_ld/st64
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-arm: Rearrange slow-path qemu_ld/st
Use the new helper_ret_*_mmu routines. Use a conditional callto arrange for a tail-call from the store path, and to load thereturn address for the helper for the load path.
tcg-arm: Use strd for tcg_out_arg_reg64
tcg-arm: Use QEMU_BUILD_BUG_ON to verify constraints on tlb
One of the two constraints we already checked via #if, butthe tlb offset distance was only checked at runtime.
tcg-arm: Move load of tlb addend into tcg_out_tlb_read
This allows us to make more intelligent decisions about the relativeoffsets of the tlb comparator and the addend, avoiding any need ofwriteback addressing.
tcg-arm: Return register containing tlb addend
Preparatory to rescheduling the tlb load, and changing said register.Continues to use R1 for now.
tcg-arm: Remove restriction on qemu_ld output register
The main intent of the patch is to allow the tlb addend registerto be changed, without tying that change to the constraint. Butthe most common side-effect seems to be to enable usage of ldrdwith the r0,r1 pair....
tcg-arm: Move the tlb addend load earlier
There are free scheduling slots between the sequence ofcomparison instructions. This requires changing theregister in use to avoid conflict with those compares.
tcg: Change tcg_out_ld/st offset to intptr_t
exec: Split softmmu_defs.h
The _cmmu helpers can be moved to exec-all.h. The helpers that areused from TCG will shortly need access to tcg_target_long so movetheir declarations into tcg.h.
This requires minor include adjustments to all TCG backends....
tcg: Change relocation offsets to intptr_t
tcg-arm: Implement tcg_register_jit
Allows unwinding past the code_gen_buffer.
tcg-arm: Use AT_PLATFORM to detect the host ISA
With this we can generate armv7 insns even when the OS compiles for alower common denominator. The macros are arranged so that when we docompile for a given ISA, all of the runtime checks for that ISA are...
tcg-arm: Simplify logic in detecting the ARM ISA in use
GCC 4.8 defines a handy __ARM_ARCH symbol that we can use, whichwill make us nicely forward compatible with ARMv8 AArch32.
tcg-arm: Rename use_armv5_instructions to use_armvt5_instructions
As it really controls the availability of a thumb interworkinginstruction on armv5t.
tcg-arm: Make use of conditional availability of opcodes for divide
We can now detect and use divide instructions at runtime, rather thanhaving to restrict their availability to compile-time.
tcg-arm: Don't implement rem
tcg: Remove redundant tcg_target_init checks
We've got a compile-time check for the condition in exec/cpu-defs.h.
Reviewed-by: Andreas Färber <afaerber@suse.de>Reviewed-by: liguang <lig.fnst@cn.fujitsu.com>Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-arm: Use movi32 in exit_tb
Avoid the mini constant pool for armv7, and avoid replicatingthe test for pre-v7.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg-arm: Fix 64-bit tlb load for pre-v6
Found by inspection, since the effect of the bug was simply tosend all memory ops through the slow path.
tcg-arm: Split out tcg_out_tlb_read
Share code between qemu_ld and qemu_st to process the tlb.
tcg-arm: Improve scheduling of tcg_out_tlb_read
The schedule was fully serial, with no possibility for dual issue.The old schedule had a minimal issue of 7 cycles; the new schedulehas a minimal issue of 5 cycles.
tcg-arm: Delete the 'S' constraint
After the previous patch, 's' and 'S' are the same.
tcg-arm: Use movi32 + blx for calls on v7
Work better with branch predition when we have movw+movt,as the size of the code is the same. Perhaps re-evaluatewhen we have a proper constant pool.
tcg-arm: Convert to CONFIG_QEMU_LDST_OPTIMIZATION
Move the slow path out of line, as the TODO's mention.This allows the fast path to be unconditional, which canspeed up the fast path as well, depending on the core.
tcg-arm: Remove long jump from tcg_out_goto_label
Branches within a TB will always be within 16MB.
tcg-arm: Implement deposit for armv7
We have BFI and BFC available for implementing it.
tcg-arm: Implement division instructions
An armv7 extension implements division, present on Cortex A15.
tcg-arm: Use TCG_REG_TMP name for the tcg temporary
Don't hard-code R8.
tcg-arm: Use R12 for the tcg temporary
R12 is call clobbered, while R8 is call saved. This changegives tcg one more call saved register for real data.
tcg-arm: Cleanup multiply subroutines
Make the code more readable by only having one copy of the magicnumbers, swapping registers as needed prior to that. Speed thecompiler by not applying the rd == rn avoidance for v6 or later.
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>...
tcg-arm: Cleanup most primitive load store subroutines
Use even more primitive helper functions to avoid lots of duplicated code.
tcg-arm: Handle negated constant arguments to and/sub
This greatly improves code generation for addition of smallnegative constants.
tcg-arm: Allow constant first argument to sub
This allows the generation of RSB instructions.
tcg-arm: Use tcg_out_dat_rIN for compares
This allows us to emit CMN instructions.
tcg-arm: Handle constant arguments to add2/sub2
We get to re-use the _rIN and _rIK subroutines to handle the variouscombinations of add vs sub. Fold the << 21 into the opcode enum valuesso that we can explicitly add TO_CPSR as desired.
tcg-arm: Improve constant generation
Try fully rotated arguments to mov and mvn before trying movtor full decomposition. Begin decomposition with mvn when itlooks like it'll help. Examples include
: mov r9, #0x00000fa0: orr r9, r9, #0x000ee000...
tcg-arm: Use bic to implement and with constant
This greatly improves the code we can produce for depositwithout armv7 support.
tcg-arm: Fix local stack frame
We were not allocating TCG_STATIC_CALL_ARGS_SIZE, so this meant thatany helper with more than 4 arguments would clobber the saved regs.Realizing that we're supposed to have this memory pre-allocated meanswe can clean up the tcg_out_arg functions, which were trying to do...
tcg-arm: Implement muls2_i32
We even had the encoding of smull already handy...
Cc: Andrzej Zaborowski <balrogg@gmail.com>Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
tcg/target-arm: Add missing parens to assertions
Silence a (legitimate) complaint about missing parentheses:
tcg/arm/tcg-target.c: In function ‘tcg_out_qemu_ld’:tcg/arm/tcg-target.c:1148:5: error: suggest parentheses aroundcomparison in operand of ‘&’ [-Werror=parentheses]...
exec: move include files to include/exec/
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
tcg/arm: fix TLB access in qemu-ld/st ops
The TCG arm backend considers likely that the offset to the TLBentries does not exceed 12 bits for mem_index = 0. In practice this isnot true for at least the MIPS target.
The current patch fixes that by loading the bits 23-12 with a separate...
tcg/arm: fix cross-endian qemu_st16
The bswap16 TCG opcode assumes that the high bytes of the temp equalto 0 before calling it. The ARM backend implementation takes thisassumption to slightly optimize the generated code.
The same implementation is called for implementing the cross-endian...
tcg/arm: Implement movcond_i32
Implement movcond_i32 for ARM, as the sequence mov dst, v2 (implicitly done by the tcg common code) cmp c1, c2 movCC dst, v1
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg/arm: Factor out code to emit immediate or reg-reg op
The code to emit either an immediate cmp or a register cmp insn isduplicated in several places; factor it out into its own function.
Merge branch 'trivial-patches' of git://github.com/stefanha/qemu
tcg: Add TCG_COND_NEVER, TCG_COND_ALWAYS
There are several cases that can be handled easier inside bothtranslators and code generators if we have out-of-band valuesfor conditions. It's easy enough to handle ALWAYS and NEVER inthe natural way inside the tcg middle-end....
tcg: remove obsolete jmp op
The TCG jmp operation doesn't really make sense in the QEMU context, itis unused, it is not implemented by some targets, and it is wronglyimplemented by some others.
This patch simply removes it.
Reviewed-by: Richard Henderson <rth@twiddle.net>...
tcg/arm: Use tcg_out_mov_reg rather than inline equivalent code
Use the recently introduced tcg_out_mov_reg() function rather thanthe equivalent inline code.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>...
tcg: Remove tcg_target_get_call_iarg_regs_count
The TCG targets no longer need individual implementations.
Since commit 6a18ae2d2947532d5c26439548afa0481c4529f9,'flags' is no longer used in tcg_target_get_call_iarg_regs_count.
The remaining tcg_target_get_call_iarg_regs_count is trivial and only...
Remove unused CONFIG_TCG_PASS_AREG0 and dead code
Now that CONFIG_TCG_PASS_AREG0 is enabled for all targets,remove dead code and support for !CONFIG_TCG_PASS_AREG0 case.
Remove dyngen-exec.h and all references to it. Although included byhw/spapr_hcall.c, it does not seem to use it....
tcg/arm: Fix broken CONFIG_TCG_PASS_AREG0 code
The CONFIG_TCG_PASS_AREG0 code for calling ld/st helpers wasbroken in that it did not respect the ABI requirement that 64bit values were passed in even-odd register pairs. The simplestway to fix this is to implement some new utility functions...
softmmu templates: optionally pass CPUState to memory access functions
Optionally, make memory access helpers take a parameter for CPUStateinstead of relying on global env.
On most targets, perform simple moves to reorder registers. On i386,switch from regparm(3) calling convention to standard stack-based...
Rename CPUState -> CPUArchState
Scripted conversion: for file in .[hc] hw/.[hc] hw/kvm/*.[hc] linux-user/*.[hc] linux-user/m68k/*.[hc] bsd-user/*.[hc] darwin-user/*.[hc] tcg/*/*.[hc] target-*/cpu.h; do sed -i "s/CPUState/CPUArchState/g" $file done...
tcg-arm: fix a typo in comments
ARM still doesn't support 16GB buffers in 32-bit modes, replace the16GB by 16MB in the comment.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
tcg/arm: remove fixed map code buffer restriction
On ARM, don't map the code buffer at a fixed location, and fix up thecall/goto tcg routines to let it do long jumps.
Mapping the code buffer at a fixed address could sometimes result in it beingmapped over the top of the heap with pretty random results....
tcg: Use TCGReg for standard tcg-target entry points.
Including tcg_out_ld, tcg_out_st, tcg_out_mov, tcg_out_movi.
Signed-off-by: Richard Henderson <rth@twiddle.net>Reviewed-by: Andreas Färber <afaerber@suse.de>Reviewed-by: Stefan Weil <sw@weilnetz.de>...
tcg/arm: Remove unused tcg_out_addi()
Remove the unused function tcg_out_addi() from the ARM TCG backend;this fixes a compilation failure on ARM hosts with newer gcc.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Richard Henderson <rth@twiddle.net>...
Delegate setup of TCG temporaries to targets
Delegate TCG temp_buf setup to targets, so that they can use a stackframe later instead.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
cpu-exec.c: avoid AREG0 use
Make functions take a parameter for CPUState instead of relyingon global env. Pass CPUState pointer to TCG prologue, which movesit to AREG0.
Thanks to Peter Maydell and Laurent Desnogues for the ARM prologuechange.
Revert the hacks to avoid AREG0 use on Sparc hosts....
tcg/arm: Support host code being compiled for Thumb
Although the TCG generated code is always in ARM mode, it is possiblethat the host code was compiled by gcc in Thumb mode (this is often thedefault for Linux distributions targeting ARM v7 only). Handle this...
tcg arm/mips/ia64: add a comment about retranslation and caches
Add a comment about cache coherency and retranslation, so that peopledevelopping new targets based on existing ones are warned of the issue.
Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>...
tcg/arm: improve constant loading
Improve constant loading in two ways:- On all ARM versions, it's possible to load 0xffffff00 = 0x100 using the mvn rd, #0. Fix the conditions. On <= ARMv6 versions, where movw and movt are not available, load the constants using mov and orr with rotations depending on the constant...
tcg/arm: fix qemu_st64 for big endian targets
Due to a typo, qemu_st64 doesn't properly byteswap the 32-bit low word ofa 64 bit word before saving it. This patch fixes that.
Acked-by: Andrzej Zaborowski <balrogg@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg/arm: fix branch target change during code retranslation
QEMU uses code retranslation to restore the CPU state when an exceptionhappens. For it to work the retranslation must not modify the generatedcode. This is what is currently implemented in ARM TCG....
tcg: Make some tcg-target.c routines static.
Both tcg_target_init and tcg_target_qemu_prologueare unused outside of tcg.c.
tcg: Add TYPE parameter to tcg_out_mov.
Mirror tcg_out_movi in having a TYPE parameter. This allows x86_64to perform the move at the proper width, which may elide a REX prefix.
Introduce a TCG_TYPE_REG enumerator to represent the "native width" of the host register, and to distinguish the usage from "pointer data"...
tcg/arm: fix condition in zero/sign extension functions
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg/arm: remove conditional argument for qemu_ld/st
While it make sense to pass a conditional argument to tcg_out_*()functions as the ARM architecture allows that, it doesn't make sensefor qemu_ld/st functions. These functions use comparison instructions...
tcg/arm: use ext* ops in qemu_ld
tcg/arm: bswap arguments in qemu_ld/st if needed
On big endian targets, data arguments of qemu_ld/st ops have to bebyte swapped. Two temporary registers are needed for qemu_st to dothe bswap. r0 and r1 are used in system mode, do the same in usermode, which implies reworking the constraints....
tcg/arm: remove useless register tests in qemu_ld/st
addr_reg, data_reg and data_reg2 can't be register r0 or r1 du to theconstraints. Don't check if they equals these registers.
tcg/arm: fix argument alignment in qemu_st64
64-bit arguments should be aligned on an even register as specifiedby the "Procedure Call Standard for the ARM Architecture".
tcg/arm: optimize register allocation order
The beginning of the register allocation order list on the TCG armtarget matches the list of clobbered registers. This means that when anhelper is called, there is almost always clobbered registers that haveto be spilled....
tcg/arm: don't try to load constants using pc
There is statistically almost 0 chances to use this code, soremove it.
tcg/arm: sxtb and sxth are available starting with ARMv6
tcg/arm: use the blx instruction when possible
tcg/arm: add rotation ops
tcg/arm: add ext16u op
Add an ext16u op, either using the uxth instruction on ARMv6+ or twoshifts on previous ARM versions. In both cases the result use the samenumber or less instructions than the pure TCG version.
Also move all sign extension code to separate functions, so that they...
tcg/arm: add bswap ops
Add an bswap16 and bswap32 ops, either using the rev and rev16instructions on ARMv6+ or shifts and logical operations on previousARM versions. In both cases the result use less instructions thanthe pure TCG version.
These ops are also needed by the qemu_ld/st functions....
tcg/arm: remove SAVE_LR code
There is no need to save the LR register (r14) before a call to asubroutine. According to the "Procedure Call Standard for the ARMArchitecture", it is the job of the callee to save this register.Moreover, this register is already saved in the prologue/epilogue....
tcg/arm: explicitely list clobbered/reserved regs
Instead of writing very compact code, declare all registers that areclobbered or reserved one by one. This makes the code easier to read.
Also declare all the 16 registers to TCG, and mark pc as reserved....
tcg/arm: remove store signed functions
Store signed functions doesn't make sense, and are not used. Removethem.
tcg/arm: replace integer values by registers enum
The TCG ARM backends uses integer values to refer to both immediatevalues and register number. This makes the code difficult to read.
The patch below replaces all (if I haven't miss any ;-) integer values...
tcg/arm: add variables to define the allowed instructions set
Use a set of variables to define the allowed ARM instructions, dependingon the ARM_ARCH_* GCC defines.
tcg/arm: Replace qemu_ld32u (left over from previous commit)
Commit 86feb1c860dc38e9c89e787c5210e8191800385edid not change all occurrences of INDEX_op_qemu_ld32ufor tcg/arm.
Please note that I could not test this patch(I have currently no arm system available)....
tcg: Disambiguate qemu_ld32u with 32-bit and 64-bit outputs.
Some targets (e.g. Alpha and MIPS64) need to keep 32-bit operandssign-extended in 64-bit registers (regardless of the "real" signof the operand). For that, we need to be able to distinguishbetween a 32-bit load with a 32-bit result and a 32-bit load with...
tcg: Name the opcode enumeration.
Give the enumeration formed from tcg-opc.h a name: TCGOpcode.Use that enumeration type instead of "int" whereever appropriate.
tcg/arm: don't save/restore r7 in prologue/epilogue
There is no need to save r7, it is used to store the addressof the env structure and is not modified by GCC.
tcg/arm: fix load/store definitions for 32-bit targets
tcg/arm: use helpers for divu/remu