root / target-sparc / op_helper.c @ 7a5e4488
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#include "cpu.h" |
---|---|
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#include "dyngen-exec.h" |
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#include "helper.h" |
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|
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#if !defined(CONFIG_USER_ONLY)
|
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#include "softmmu_exec.h" |
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#endif
|
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|
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//#define DEBUG_MMU
|
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//#define DEBUG_MXCC
|
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//#define DEBUG_UNALIGNED
|
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//#define DEBUG_UNASSIGNED
|
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//#define DEBUG_ASI
|
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//#define DEBUG_CACHE_CONTROL
|
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|
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#ifdef DEBUG_MMU
|
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#define DPRINTF_MMU(fmt, ...) \
|
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do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0) |
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#else
|
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#define DPRINTF_MMU(fmt, ...) do {} while (0) |
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#endif
|
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|
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#ifdef DEBUG_MXCC
|
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#define DPRINTF_MXCC(fmt, ...) \
|
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do { printf("MXCC: " fmt , ## __VA_ARGS__); } while (0) |
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#else
|
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#define DPRINTF_MXCC(fmt, ...) do {} while (0) |
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#endif
|
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|
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#ifdef DEBUG_ASI
|
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#define DPRINTF_ASI(fmt, ...) \
|
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do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0) |
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#endif
|
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|
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#ifdef DEBUG_CACHE_CONTROL
|
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#define DPRINTF_CACHE_CONTROL(fmt, ...) \
|
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do { printf("CACHE_CONTROL: " fmt , ## __VA_ARGS__); } while (0) |
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#else
|
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#define DPRINTF_CACHE_CONTROL(fmt, ...) do {} while (0) |
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#endif
|
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|
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#ifdef TARGET_SPARC64
|
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#ifndef TARGET_ABI32
|
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#define AM_CHECK(env1) ((env1)->pstate & PS_AM)
|
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#else
|
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#define AM_CHECK(env1) (1) |
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#endif
|
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#endif
|
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|
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#define DT0 (env->dt0)
|
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#define DT1 (env->dt1)
|
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#define QT0 (env->qt0)
|
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#define QT1 (env->qt1)
|
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|
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#if !defined(CONFIG_USER_ONLY)
|
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static void do_unassigned_access(target_phys_addr_t addr, int is_write, |
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int is_exec, int is_asi, int size); |
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#else
|
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#ifdef TARGET_SPARC64
|
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static void do_unassigned_access(target_ulong addr, int is_write, int is_exec, |
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int is_asi, int size); |
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#endif
|
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#endif
|
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|
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#if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
|
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/* Calculates TSB pointer value for fault page size 8k or 64k */
|
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static uint64_t ultrasparc_tsb_pointer(uint64_t tsb_register,
|
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uint64_t tag_access_register, |
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int page_size)
|
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{ |
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uint64_t tsb_base = tsb_register & ~0x1fffULL;
|
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int tsb_split = (tsb_register & 0x1000ULL) ? 1 : 0; |
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int tsb_size = tsb_register & 0xf; |
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|
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/* discard lower 13 bits which hold tag access context */
|
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uint64_t tag_access_va = tag_access_register & ~0x1fffULL;
|
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|
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/* now reorder bits */
|
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uint64_t tsb_base_mask = ~0x1fffULL;
|
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uint64_t va = tag_access_va; |
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|
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/* move va bits to correct position */
|
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if (page_size == 8*1024) { |
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va >>= 9;
|
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} else if (page_size == 64*1024) { |
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va >>= 12;
|
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} |
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|
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if (tsb_size) {
|
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tsb_base_mask <<= tsb_size; |
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} |
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|
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/* calculate tsb_base mask and adjust va if split is in use */
|
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if (tsb_split) {
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if (page_size == 8*1024) { |
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va &= ~(1ULL << (13 + tsb_size)); |
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} else if (page_size == 64*1024) { |
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va |= (1ULL << (13 + tsb_size)); |
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} |
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tsb_base_mask <<= 1;
|
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} |
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|
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return ((tsb_base & tsb_base_mask) | (va & ~tsb_base_mask)) & ~0xfULL; |
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} |
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|
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/* Calculates tag target register value by reordering bits
|
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in tag access register */
|
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static uint64_t ultrasparc_tag_target(uint64_t tag_access_register)
|
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{ |
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return ((tag_access_register & 0x1fff) << 48) | (tag_access_register >> 22); |
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} |
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|
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static void replace_tlb_entry(SparcTLBEntry *tlb, |
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uint64_t tlb_tag, uint64_t tlb_tte, |
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CPUState *env1) |
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{ |
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target_ulong mask, size, va, offset; |
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|
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/* flush page range if translation is valid */
|
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if (TTE_IS_VALID(tlb->tte)) {
|
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|
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mask = 0xffffffffffffe000ULL;
|
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mask <<= 3 * ((tlb->tte >> 61) & 3); |
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size = ~mask + 1;
|
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|
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va = tlb->tag & mask; |
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|
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for (offset = 0; offset < size; offset += TARGET_PAGE_SIZE) { |
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tlb_flush_page(env1, va + offset); |
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} |
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} |
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|
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tlb->tag = tlb_tag; |
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tlb->tte = tlb_tte; |
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} |
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|
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static void demap_tlb(SparcTLBEntry *tlb, target_ulong demap_addr, |
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const char *strmmu, CPUState *env1) |
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{ |
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unsigned int i; |
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target_ulong mask; |
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uint64_t context; |
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|
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int is_demap_context = (demap_addr >> 6) & 1; |
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|
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/* demap context */
|
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switch ((demap_addr >> 4) & 3) { |
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case 0: /* primary */ |
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context = env1->dmmu.mmu_primary_context; |
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break;
|
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case 1: /* secondary */ |
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context = env1->dmmu.mmu_secondary_context; |
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break;
|
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case 2: /* nucleus */ |
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context = 0;
|
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break;
|
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case 3: /* reserved */ |
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default:
|
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return;
|
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} |
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|
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for (i = 0; i < 64; i++) { |
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if (TTE_IS_VALID(tlb[i].tte)) {
|
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|
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if (is_demap_context) {
|
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/* will remove non-global entries matching context value */
|
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if (TTE_IS_GLOBAL(tlb[i].tte) ||
|
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!tlb_compare_context(&tlb[i], context)) { |
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continue;
|
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} |
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} else {
|
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/* demap page
|
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will remove any entry matching VA */
|
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mask = 0xffffffffffffe000ULL;
|
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mask <<= 3 * ((tlb[i].tte >> 61) & 3); |
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|
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if (!compare_masked(demap_addr, tlb[i].tag, mask)) {
|
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continue;
|
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} |
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|
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/* entry should be global or matching context value */
|
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if (!TTE_IS_GLOBAL(tlb[i].tte) &&
|
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!tlb_compare_context(&tlb[i], context)) { |
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continue;
|
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} |
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} |
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|
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replace_tlb_entry(&tlb[i], 0, 0, env1); |
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#ifdef DEBUG_MMU
|
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DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu, i);
|
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dump_mmu(stdout, fprintf, env1); |
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#endif
|
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} |
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} |
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} |
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|
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static void replace_tlb_1bit_lru(SparcTLBEntry *tlb, |
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uint64_t tlb_tag, uint64_t tlb_tte, |
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const char *strmmu, CPUState *env1) |
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{ |
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unsigned int i, replace_used; |
202 |
|
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/* Try replacing invalid entry */
|
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for (i = 0; i < 64; i++) { |
205 |
if (!TTE_IS_VALID(tlb[i].tte)) {
|
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replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1); |
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#ifdef DEBUG_MMU
|
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DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu, i);
|
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dump_mmu(stdout, fprintf, env1); |
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#endif
|
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return;
|
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} |
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} |
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|
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/* All entries are valid, try replacing unlocked entry */
|
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|
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for (replace_used = 0; replace_used < 2; ++replace_used) { |
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|
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/* Used entries are not replaced on first pass */
|
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|
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for (i = 0; i < 64; i++) { |
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if (!TTE_IS_LOCKED(tlb[i].tte) && !TTE_IS_USED(tlb[i].tte)) {
|
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|
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replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1); |
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#ifdef DEBUG_MMU
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DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n",
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strmmu, (replace_used ? "used" : "unused"), i); |
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dump_mmu(stdout, fprintf, env1); |
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#endif
|
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return;
|
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} |
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} |
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|
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/* Now reset used bit and search for unused entries again */
|
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|
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for (i = 0; i < 64; i++) { |
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TTE_SET_UNUSED(tlb[i].tte); |
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} |
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} |
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|
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#ifdef DEBUG_MMU
|
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DPRINTF_MMU("%s lru replacement failed: no entries available\n", strmmu);
|
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#endif
|
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/* error state? */
|
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} |
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|
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#endif
|
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|
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static inline target_ulong address_mask(CPUState *env1, target_ulong addr) |
250 |
{ |
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#ifdef TARGET_SPARC64
|
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if (AM_CHECK(env1)) {
|
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addr &= 0xffffffffULL;
|
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} |
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#endif
|
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return addr;
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} |
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|
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/* returns true if access using this ASI is to have address translated by MMU
|
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otherwise access is to raw physical address */
|
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static inline int is_translating_asi(int asi) |
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{ |
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#ifdef TARGET_SPARC64
|
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/* Ultrasparc IIi translating asi
|
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- note this list is defined by cpu implementation
|
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*/
|
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switch (asi) {
|
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case 0x04 ... 0x11: |
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case 0x16 ... 0x19: |
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case 0x1E ... 0x1F: |
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case 0x24 ... 0x2C: |
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case 0x70 ... 0x73: |
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case 0x78 ... 0x79: |
274 |
case 0x80 ... 0xFF: |
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return 1; |
276 |
|
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default:
|
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return 0; |
279 |
} |
280 |
#else
|
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/* TODO: check sparc32 bits */
|
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return 0; |
283 |
#endif
|
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} |
285 |
|
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static inline target_ulong asi_address_mask(CPUState *env1, |
287 |
int asi, target_ulong addr)
|
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{ |
289 |
if (is_translating_asi(asi)) {
|
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return address_mask(env, addr);
|
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} else {
|
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return addr;
|
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} |
294 |
} |
295 |
|
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void helper_check_align(target_ulong addr, uint32_t align)
|
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{ |
298 |
if (addr & align) {
|
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#ifdef DEBUG_UNALIGNED
|
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printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx |
301 |
"\n", addr, env->pc);
|
302 |
#endif
|
303 |
helper_raise_exception(env, TT_UNALIGNED); |
304 |
} |
305 |
} |
306 |
|
307 |
#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
|
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defined(DEBUG_MXCC) |
309 |
static void dump_mxcc(CPUState *env) |
310 |
{ |
311 |
printf("mxccdata: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 |
312 |
"\n",
|
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env->mxccdata[0], env->mxccdata[1], |
314 |
env->mxccdata[2], env->mxccdata[3]); |
315 |
printf("mxccregs: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 |
316 |
"\n"
|
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" %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 |
318 |
"\n",
|
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env->mxccregs[0], env->mxccregs[1], |
320 |
env->mxccregs[2], env->mxccregs[3], |
321 |
env->mxccregs[4], env->mxccregs[5], |
322 |
env->mxccregs[6], env->mxccregs[7]); |
323 |
} |
324 |
#endif
|
325 |
|
326 |
#if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
|
327 |
&& defined(DEBUG_ASI) |
328 |
static void dump_asi(const char *txt, target_ulong addr, int asi, int size, |
329 |
uint64_t r1) |
330 |
{ |
331 |
switch (size) {
|
332 |
case 1: |
333 |
DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %02" PRIx64 "\n", txt, |
334 |
addr, asi, r1 & 0xff);
|
335 |
break;
|
336 |
case 2: |
337 |
DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %04" PRIx64 "\n", txt, |
338 |
addr, asi, r1 & 0xffff);
|
339 |
break;
|
340 |
case 4: |
341 |
DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %08" PRIx64 "\n", txt, |
342 |
addr, asi, r1 & 0xffffffff);
|
343 |
break;
|
344 |
case 8: |
345 |
DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %016" PRIx64 "\n", txt, |
346 |
addr, asi, r1); |
347 |
break;
|
348 |
} |
349 |
} |
350 |
#endif
|
351 |
|
352 |
#ifndef TARGET_SPARC64
|
353 |
#ifndef CONFIG_USER_ONLY
|
354 |
|
355 |
|
356 |
/* Leon3 cache control */
|
357 |
|
358 |
static void leon3_cache_control_st(target_ulong addr, uint64_t val, int size) |
359 |
{ |
360 |
DPRINTF_CACHE_CONTROL("st addr:%08x, val:%" PRIx64 ", size:%d\n", |
361 |
addr, val, size); |
362 |
|
363 |
if (size != 4) { |
364 |
DPRINTF_CACHE_CONTROL("32bits only\n");
|
365 |
return;
|
366 |
} |
367 |
|
368 |
switch (addr) {
|
369 |
case 0x00: /* Cache control */ |
370 |
|
371 |
/* These values must always be read as zeros */
|
372 |
val &= ~CACHE_CTRL_FD; |
373 |
val &= ~CACHE_CTRL_FI; |
374 |
val &= ~CACHE_CTRL_IB; |
375 |
val &= ~CACHE_CTRL_IP; |
376 |
val &= ~CACHE_CTRL_DP; |
377 |
|
378 |
env->cache_control = val; |
379 |
break;
|
380 |
case 0x04: /* Instruction cache configuration */ |
381 |
case 0x08: /* Data cache configuration */ |
382 |
/* Read Only */
|
383 |
break;
|
384 |
default:
|
385 |
DPRINTF_CACHE_CONTROL("write unknown register %08x\n", addr);
|
386 |
break;
|
387 |
}; |
388 |
} |
389 |
|
390 |
static uint64_t leon3_cache_control_ld(target_ulong addr, int size) |
391 |
{ |
392 |
uint64_t ret = 0;
|
393 |
|
394 |
if (size != 4) { |
395 |
DPRINTF_CACHE_CONTROL("32bits only\n");
|
396 |
return 0; |
397 |
} |
398 |
|
399 |
switch (addr) {
|
400 |
case 0x00: /* Cache control */ |
401 |
ret = env->cache_control; |
402 |
break;
|
403 |
|
404 |
/* Configuration registers are read and only always keep those
|
405 |
predefined values */
|
406 |
|
407 |
case 0x04: /* Instruction cache configuration */ |
408 |
ret = 0x10220000;
|
409 |
break;
|
410 |
case 0x08: /* Data cache configuration */ |
411 |
ret = 0x18220000;
|
412 |
break;
|
413 |
default:
|
414 |
DPRINTF_CACHE_CONTROL("read unknown register %08x\n", addr);
|
415 |
break;
|
416 |
}; |
417 |
DPRINTF_CACHE_CONTROL("ld addr:%08x, ret:0x%" PRIx64 ", size:%d\n", |
418 |
addr, ret, size); |
419 |
return ret;
|
420 |
} |
421 |
|
422 |
uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign) |
423 |
{ |
424 |
uint64_t ret = 0;
|
425 |
#if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
|
426 |
uint32_t last_addr = addr; |
427 |
#endif
|
428 |
|
429 |
helper_check_align(addr, size - 1);
|
430 |
switch (asi) {
|
431 |
case 2: /* SuperSparc MXCC registers and Leon3 cache control */ |
432 |
switch (addr) {
|
433 |
case 0x00: /* Leon3 Cache Control */ |
434 |
case 0x08: /* Leon3 Instruction Cache config */ |
435 |
case 0x0C: /* Leon3 Date Cache config */ |
436 |
if (env->def->features & CPU_FEATURE_CACHE_CTRL) {
|
437 |
ret = leon3_cache_control_ld(addr, size); |
438 |
} |
439 |
break;
|
440 |
case 0x01c00a00: /* MXCC control register */ |
441 |
if (size == 8) { |
442 |
ret = env->mxccregs[3];
|
443 |
} else {
|
444 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
445 |
size); |
446 |
} |
447 |
break;
|
448 |
case 0x01c00a04: /* MXCC control register */ |
449 |
if (size == 4) { |
450 |
ret = env->mxccregs[3];
|
451 |
} else {
|
452 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
453 |
size); |
454 |
} |
455 |
break;
|
456 |
case 0x01c00c00: /* Module reset register */ |
457 |
if (size == 8) { |
458 |
ret = env->mxccregs[5];
|
459 |
/* should we do something here? */
|
460 |
} else {
|
461 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
462 |
size); |
463 |
} |
464 |
break;
|
465 |
case 0x01c00f00: /* MBus port address register */ |
466 |
if (size == 8) { |
467 |
ret = env->mxccregs[7];
|
468 |
} else {
|
469 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
470 |
size); |
471 |
} |
472 |
break;
|
473 |
default:
|
474 |
DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr,
|
475 |
size); |
476 |
break;
|
477 |
} |
478 |
DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
|
479 |
"addr = %08x -> ret = %" PRIx64 "," |
480 |
"addr = %08x\n", asi, size, sign, last_addr, ret, addr);
|
481 |
#ifdef DEBUG_MXCC
|
482 |
dump_mxcc(env); |
483 |
#endif
|
484 |
break;
|
485 |
case 3: /* MMU probe */ |
486 |
{ |
487 |
int mmulev;
|
488 |
|
489 |
mmulev = (addr >> 8) & 15; |
490 |
if (mmulev > 4) { |
491 |
ret = 0;
|
492 |
} else {
|
493 |
ret = mmu_probe(env, addr, mmulev); |
494 |
} |
495 |
DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64 "\n", |
496 |
addr, mmulev, ret); |
497 |
} |
498 |
break;
|
499 |
case 4: /* read MMU regs */ |
500 |
{ |
501 |
int reg = (addr >> 8) & 0x1f; |
502 |
|
503 |
ret = env->mmuregs[reg]; |
504 |
if (reg == 3) { /* Fault status cleared on read */ |
505 |
env->mmuregs[3] = 0; |
506 |
} else if (reg == 0x13) { /* Fault status read */ |
507 |
ret = env->mmuregs[3];
|
508 |
} else if (reg == 0x14) { /* Fault address read */ |
509 |
ret = env->mmuregs[4];
|
510 |
} |
511 |
DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64 "\n", reg, ret); |
512 |
} |
513 |
break;
|
514 |
case 5: /* Turbosparc ITLB Diagnostic */ |
515 |
case 6: /* Turbosparc DTLB Diagnostic */ |
516 |
case 7: /* Turbosparc IOTLB Diagnostic */ |
517 |
break;
|
518 |
case 9: /* Supervisor code access */ |
519 |
switch (size) {
|
520 |
case 1: |
521 |
ret = ldub_code(addr); |
522 |
break;
|
523 |
case 2: |
524 |
ret = lduw_code(addr); |
525 |
break;
|
526 |
default:
|
527 |
case 4: |
528 |
ret = ldl_code(addr); |
529 |
break;
|
530 |
case 8: |
531 |
ret = ldq_code(addr); |
532 |
break;
|
533 |
} |
534 |
break;
|
535 |
case 0xa: /* User data access */ |
536 |
switch (size) {
|
537 |
case 1: |
538 |
ret = ldub_user(addr); |
539 |
break;
|
540 |
case 2: |
541 |
ret = lduw_user(addr); |
542 |
break;
|
543 |
default:
|
544 |
case 4: |
545 |
ret = ldl_user(addr); |
546 |
break;
|
547 |
case 8: |
548 |
ret = ldq_user(addr); |
549 |
break;
|
550 |
} |
551 |
break;
|
552 |
case 0xb: /* Supervisor data access */ |
553 |
switch (size) {
|
554 |
case 1: |
555 |
ret = ldub_kernel(addr); |
556 |
break;
|
557 |
case 2: |
558 |
ret = lduw_kernel(addr); |
559 |
break;
|
560 |
default:
|
561 |
case 4: |
562 |
ret = ldl_kernel(addr); |
563 |
break;
|
564 |
case 8: |
565 |
ret = ldq_kernel(addr); |
566 |
break;
|
567 |
} |
568 |
break;
|
569 |
case 0xc: /* I-cache tag */ |
570 |
case 0xd: /* I-cache data */ |
571 |
case 0xe: /* D-cache tag */ |
572 |
case 0xf: /* D-cache data */ |
573 |
break;
|
574 |
case 0x20: /* MMU passthrough */ |
575 |
switch (size) {
|
576 |
case 1: |
577 |
ret = ldub_phys(addr); |
578 |
break;
|
579 |
case 2: |
580 |
ret = lduw_phys(addr); |
581 |
break;
|
582 |
default:
|
583 |
case 4: |
584 |
ret = ldl_phys(addr); |
585 |
break;
|
586 |
case 8: |
587 |
ret = ldq_phys(addr); |
588 |
break;
|
589 |
} |
590 |
break;
|
591 |
case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */ |
592 |
switch (size) {
|
593 |
case 1: |
594 |
ret = ldub_phys((target_phys_addr_t)addr |
595 |
| ((target_phys_addr_t)(asi & 0xf) << 32)); |
596 |
break;
|
597 |
case 2: |
598 |
ret = lduw_phys((target_phys_addr_t)addr |
599 |
| ((target_phys_addr_t)(asi & 0xf) << 32)); |
600 |
break;
|
601 |
default:
|
602 |
case 4: |
603 |
ret = ldl_phys((target_phys_addr_t)addr |
604 |
| ((target_phys_addr_t)(asi & 0xf) << 32)); |
605 |
break;
|
606 |
case 8: |
607 |
ret = ldq_phys((target_phys_addr_t)addr |
608 |
| ((target_phys_addr_t)(asi & 0xf) << 32)); |
609 |
break;
|
610 |
} |
611 |
break;
|
612 |
case 0x30: /* Turbosparc secondary cache diagnostic */ |
613 |
case 0x31: /* Turbosparc RAM snoop */ |
614 |
case 0x32: /* Turbosparc page table descriptor diagnostic */ |
615 |
case 0x39: /* data cache diagnostic register */ |
616 |
ret = 0;
|
617 |
break;
|
618 |
case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */ |
619 |
{ |
620 |
int reg = (addr >> 8) & 3; |
621 |
|
622 |
switch (reg) {
|
623 |
case 0: /* Breakpoint Value (Addr) */ |
624 |
ret = env->mmubpregs[reg]; |
625 |
break;
|
626 |
case 1: /* Breakpoint Mask */ |
627 |
ret = env->mmubpregs[reg]; |
628 |
break;
|
629 |
case 2: /* Breakpoint Control */ |
630 |
ret = env->mmubpregs[reg]; |
631 |
break;
|
632 |
case 3: /* Breakpoint Status */ |
633 |
ret = env->mmubpregs[reg]; |
634 |
env->mmubpregs[reg] = 0ULL;
|
635 |
break;
|
636 |
} |
637 |
DPRINTF_MMU("read breakpoint reg[%d] 0x%016" PRIx64 "\n", reg, |
638 |
ret); |
639 |
} |
640 |
break;
|
641 |
case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */ |
642 |
ret = env->mmubpctrv; |
643 |
break;
|
644 |
case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */ |
645 |
ret = env->mmubpctrc; |
646 |
break;
|
647 |
case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */ |
648 |
ret = env->mmubpctrs; |
649 |
break;
|
650 |
case 0x4c: /* SuperSPARC MMU Breakpoint Action */ |
651 |
ret = env->mmubpaction; |
652 |
break;
|
653 |
case 8: /* User code access, XXX */ |
654 |
default:
|
655 |
do_unassigned_access(addr, 0, 0, asi, size); |
656 |
ret = 0;
|
657 |
break;
|
658 |
} |
659 |
if (sign) {
|
660 |
switch (size) {
|
661 |
case 1: |
662 |
ret = (int8_t) ret; |
663 |
break;
|
664 |
case 2: |
665 |
ret = (int16_t) ret; |
666 |
break;
|
667 |
case 4: |
668 |
ret = (int32_t) ret; |
669 |
break;
|
670 |
default:
|
671 |
break;
|
672 |
} |
673 |
} |
674 |
#ifdef DEBUG_ASI
|
675 |
dump_asi("read ", last_addr, asi, size, ret);
|
676 |
#endif
|
677 |
return ret;
|
678 |
} |
679 |
|
680 |
void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size) |
681 |
{ |
682 |
helper_check_align(addr, size - 1);
|
683 |
switch (asi) {
|
684 |
case 2: /* SuperSparc MXCC registers and Leon3 cache control */ |
685 |
switch (addr) {
|
686 |
case 0x00: /* Leon3 Cache Control */ |
687 |
case 0x08: /* Leon3 Instruction Cache config */ |
688 |
case 0x0C: /* Leon3 Date Cache config */ |
689 |
if (env->def->features & CPU_FEATURE_CACHE_CTRL) {
|
690 |
leon3_cache_control_st(addr, val, size); |
691 |
} |
692 |
break;
|
693 |
|
694 |
case 0x01c00000: /* MXCC stream data register 0 */ |
695 |
if (size == 8) { |
696 |
env->mxccdata[0] = val;
|
697 |
} else {
|
698 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
699 |
size); |
700 |
} |
701 |
break;
|
702 |
case 0x01c00008: /* MXCC stream data register 1 */ |
703 |
if (size == 8) { |
704 |
env->mxccdata[1] = val;
|
705 |
} else {
|
706 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
707 |
size); |
708 |
} |
709 |
break;
|
710 |
case 0x01c00010: /* MXCC stream data register 2 */ |
711 |
if (size == 8) { |
712 |
env->mxccdata[2] = val;
|
713 |
} else {
|
714 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
715 |
size); |
716 |
} |
717 |
break;
|
718 |
case 0x01c00018: /* MXCC stream data register 3 */ |
719 |
if (size == 8) { |
720 |
env->mxccdata[3] = val;
|
721 |
} else {
|
722 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
723 |
size); |
724 |
} |
725 |
break;
|
726 |
case 0x01c00100: /* MXCC stream source */ |
727 |
if (size == 8) { |
728 |
env->mxccregs[0] = val;
|
729 |
} else {
|
730 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
731 |
size); |
732 |
} |
733 |
env->mxccdata[0] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + |
734 |
0);
|
735 |
env->mxccdata[1] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + |
736 |
8);
|
737 |
env->mxccdata[2] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + |
738 |
16);
|
739 |
env->mxccdata[3] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + |
740 |
24);
|
741 |
break;
|
742 |
case 0x01c00200: /* MXCC stream destination */ |
743 |
if (size == 8) { |
744 |
env->mxccregs[1] = val;
|
745 |
} else {
|
746 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
747 |
size); |
748 |
} |
749 |
stq_phys((env->mxccregs[1] & 0xffffffffULL) + 0, |
750 |
env->mxccdata[0]);
|
751 |
stq_phys((env->mxccregs[1] & 0xffffffffULL) + 8, |
752 |
env->mxccdata[1]);
|
753 |
stq_phys((env->mxccregs[1] & 0xffffffffULL) + 16, |
754 |
env->mxccdata[2]);
|
755 |
stq_phys((env->mxccregs[1] & 0xffffffffULL) + 24, |
756 |
env->mxccdata[3]);
|
757 |
break;
|
758 |
case 0x01c00a00: /* MXCC control register */ |
759 |
if (size == 8) { |
760 |
env->mxccregs[3] = val;
|
761 |
} else {
|
762 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
763 |
size); |
764 |
} |
765 |
break;
|
766 |
case 0x01c00a04: /* MXCC control register */ |
767 |
if (size == 4) { |
768 |
env->mxccregs[3] = (env->mxccregs[3] & 0xffffffff00000000ULL) |
769 |
| val; |
770 |
} else {
|
771 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
772 |
size); |
773 |
} |
774 |
break;
|
775 |
case 0x01c00e00: /* MXCC error register */ |
776 |
/* writing a 1 bit clears the error */
|
777 |
if (size == 8) { |
778 |
env->mxccregs[6] &= ~val;
|
779 |
} else {
|
780 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
781 |
size); |
782 |
} |
783 |
break;
|
784 |
case 0x01c00f00: /* MBus port address register */ |
785 |
if (size == 8) { |
786 |
env->mxccregs[7] = val;
|
787 |
} else {
|
788 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
789 |
size); |
790 |
} |
791 |
break;
|
792 |
default:
|
793 |
DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr,
|
794 |
size); |
795 |
break;
|
796 |
} |
797 |
DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64 "\n", |
798 |
asi, size, addr, val); |
799 |
#ifdef DEBUG_MXCC
|
800 |
dump_mxcc(env); |
801 |
#endif
|
802 |
break;
|
803 |
case 3: /* MMU flush */ |
804 |
{ |
805 |
int mmulev;
|
806 |
|
807 |
mmulev = (addr >> 8) & 15; |
808 |
DPRINTF_MMU("mmu flush level %d\n", mmulev);
|
809 |
switch (mmulev) {
|
810 |
case 0: /* flush page */ |
811 |
tlb_flush_page(env, addr & 0xfffff000);
|
812 |
break;
|
813 |
case 1: /* flush segment (256k) */ |
814 |
case 2: /* flush region (16M) */ |
815 |
case 3: /* flush context (4G) */ |
816 |
case 4: /* flush entire */ |
817 |
tlb_flush(env, 1);
|
818 |
break;
|
819 |
default:
|
820 |
break;
|
821 |
} |
822 |
#ifdef DEBUG_MMU
|
823 |
dump_mmu(stdout, fprintf, env); |
824 |
#endif
|
825 |
} |
826 |
break;
|
827 |
case 4: /* write MMU regs */ |
828 |
{ |
829 |
int reg = (addr >> 8) & 0x1f; |
830 |
uint32_t oldreg; |
831 |
|
832 |
oldreg = env->mmuregs[reg]; |
833 |
switch (reg) {
|
834 |
case 0: /* Control Register */ |
835 |
env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) |
|
836 |
(val & 0x00ffffff);
|
837 |
/* Mappings generated during no-fault mode or MMU
|
838 |
disabled mode are invalid in normal mode */
|
839 |
if ((oldreg & (MMU_E | MMU_NF | env->def->mmu_bm)) !=
|
840 |
(env->mmuregs[reg] & (MMU_E | MMU_NF | env->def->mmu_bm))) { |
841 |
tlb_flush(env, 1);
|
842 |
} |
843 |
break;
|
844 |
case 1: /* Context Table Pointer Register */ |
845 |
env->mmuregs[reg] = val & env->def->mmu_ctpr_mask; |
846 |
break;
|
847 |
case 2: /* Context Register */ |
848 |
env->mmuregs[reg] = val & env->def->mmu_cxr_mask; |
849 |
if (oldreg != env->mmuregs[reg]) {
|
850 |
/* we flush when the MMU context changes because
|
851 |
QEMU has no MMU context support */
|
852 |
tlb_flush(env, 1);
|
853 |
} |
854 |
break;
|
855 |
case 3: /* Synchronous Fault Status Register with Clear */ |
856 |
case 4: /* Synchronous Fault Address Register */ |
857 |
break;
|
858 |
case 0x10: /* TLB Replacement Control Register */ |
859 |
env->mmuregs[reg] = val & env->def->mmu_trcr_mask; |
860 |
break;
|
861 |
case 0x13: /* Synchronous Fault Status Register with Read |
862 |
and Clear */
|
863 |
env->mmuregs[3] = val & env->def->mmu_sfsr_mask;
|
864 |
break;
|
865 |
case 0x14: /* Synchronous Fault Address Register */ |
866 |
env->mmuregs[4] = val;
|
867 |
break;
|
868 |
default:
|
869 |
env->mmuregs[reg] = val; |
870 |
break;
|
871 |
} |
872 |
if (oldreg != env->mmuregs[reg]) {
|
873 |
DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n",
|
874 |
reg, oldreg, env->mmuregs[reg]); |
875 |
} |
876 |
#ifdef DEBUG_MMU
|
877 |
dump_mmu(stdout, fprintf, env); |
878 |
#endif
|
879 |
} |
880 |
break;
|
881 |
case 5: /* Turbosparc ITLB Diagnostic */ |
882 |
case 6: /* Turbosparc DTLB Diagnostic */ |
883 |
case 7: /* Turbosparc IOTLB Diagnostic */ |
884 |
break;
|
885 |
case 0xa: /* User data access */ |
886 |
switch (size) {
|
887 |
case 1: |
888 |
stb_user(addr, val); |
889 |
break;
|
890 |
case 2: |
891 |
stw_user(addr, val); |
892 |
break;
|
893 |
default:
|
894 |
case 4: |
895 |
stl_user(addr, val); |
896 |
break;
|
897 |
case 8: |
898 |
stq_user(addr, val); |
899 |
break;
|
900 |
} |
901 |
break;
|
902 |
case 0xb: /* Supervisor data access */ |
903 |
switch (size) {
|
904 |
case 1: |
905 |
stb_kernel(addr, val); |
906 |
break;
|
907 |
case 2: |
908 |
stw_kernel(addr, val); |
909 |
break;
|
910 |
default:
|
911 |
case 4: |
912 |
stl_kernel(addr, val); |
913 |
break;
|
914 |
case 8: |
915 |
stq_kernel(addr, val); |
916 |
break;
|
917 |
} |
918 |
break;
|
919 |
case 0xc: /* I-cache tag */ |
920 |
case 0xd: /* I-cache data */ |
921 |
case 0xe: /* D-cache tag */ |
922 |
case 0xf: /* D-cache data */ |
923 |
case 0x10: /* I/D-cache flush page */ |
924 |
case 0x11: /* I/D-cache flush segment */ |
925 |
case 0x12: /* I/D-cache flush region */ |
926 |
case 0x13: /* I/D-cache flush context */ |
927 |
case 0x14: /* I/D-cache flush user */ |
928 |
break;
|
929 |
case 0x17: /* Block copy, sta access */ |
930 |
{ |
931 |
/* val = src
|
932 |
addr = dst
|
933 |
copy 32 bytes */
|
934 |
unsigned int i; |
935 |
uint32_t src = val & ~3, dst = addr & ~3, temp; |
936 |
|
937 |
for (i = 0; i < 32; i += 4, src += 4, dst += 4) { |
938 |
temp = ldl_kernel(src); |
939 |
stl_kernel(dst, temp); |
940 |
} |
941 |
} |
942 |
break;
|
943 |
case 0x1f: /* Block fill, stda access */ |
944 |
{ |
945 |
/* addr = dst
|
946 |
fill 32 bytes with val */
|
947 |
unsigned int i; |
948 |
uint32_t dst = addr & 7;
|
949 |
|
950 |
for (i = 0; i < 32; i += 8, dst += 8) { |
951 |
stq_kernel(dst, val); |
952 |
} |
953 |
} |
954 |
break;
|
955 |
case 0x20: /* MMU passthrough */ |
956 |
{ |
957 |
switch (size) {
|
958 |
case 1: |
959 |
stb_phys(addr, val); |
960 |
break;
|
961 |
case 2: |
962 |
stw_phys(addr, val); |
963 |
break;
|
964 |
case 4: |
965 |
default:
|
966 |
stl_phys(addr, val); |
967 |
break;
|
968 |
case 8: |
969 |
stq_phys(addr, val); |
970 |
break;
|
971 |
} |
972 |
} |
973 |
break;
|
974 |
case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */ |
975 |
{ |
976 |
switch (size) {
|
977 |
case 1: |
978 |
stb_phys((target_phys_addr_t)addr |
979 |
| ((target_phys_addr_t)(asi & 0xf) << 32), val); |
980 |
break;
|
981 |
case 2: |
982 |
stw_phys((target_phys_addr_t)addr |
983 |
| ((target_phys_addr_t)(asi & 0xf) << 32), val); |
984 |
break;
|
985 |
case 4: |
986 |
default:
|
987 |
stl_phys((target_phys_addr_t)addr |
988 |
| ((target_phys_addr_t)(asi & 0xf) << 32), val); |
989 |
break;
|
990 |
case 8: |
991 |
stq_phys((target_phys_addr_t)addr |
992 |
| ((target_phys_addr_t)(asi & 0xf) << 32), val); |
993 |
break;
|
994 |
} |
995 |
} |
996 |
break;
|
997 |
case 0x30: /* store buffer tags or Turbosparc secondary cache diagnostic */ |
998 |
case 0x31: /* store buffer data, Ross RT620 I-cache flush or |
999 |
Turbosparc snoop RAM */
|
1000 |
case 0x32: /* store buffer control or Turbosparc page table |
1001 |
descriptor diagnostic */
|
1002 |
case 0x36: /* I-cache flash clear */ |
1003 |
case 0x37: /* D-cache flash clear */ |
1004 |
break;
|
1005 |
case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/ |
1006 |
{ |
1007 |
int reg = (addr >> 8) & 3; |
1008 |
|
1009 |
switch (reg) {
|
1010 |
case 0: /* Breakpoint Value (Addr) */ |
1011 |
env->mmubpregs[reg] = (val & 0xfffffffffULL);
|
1012 |
break;
|
1013 |
case 1: /* Breakpoint Mask */ |
1014 |
env->mmubpregs[reg] = (val & 0xfffffffffULL);
|
1015 |
break;
|
1016 |
case 2: /* Breakpoint Control */ |
1017 |
env->mmubpregs[reg] = (val & 0x7fULL);
|
1018 |
break;
|
1019 |
case 3: /* Breakpoint Status */ |
1020 |
env->mmubpregs[reg] = (val & 0xfULL);
|
1021 |
break;
|
1022 |
} |
1023 |
DPRINTF_MMU("write breakpoint reg[%d] 0x%016x\n", reg,
|
1024 |
env->mmuregs[reg]); |
1025 |
} |
1026 |
break;
|
1027 |
case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */ |
1028 |
env->mmubpctrv = val & 0xffffffff;
|
1029 |
break;
|
1030 |
case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */ |
1031 |
env->mmubpctrc = val & 0x3;
|
1032 |
break;
|
1033 |
case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */ |
1034 |
env->mmubpctrs = val & 0x3;
|
1035 |
break;
|
1036 |
case 0x4c: /* SuperSPARC MMU Breakpoint Action */ |
1037 |
env->mmubpaction = val & 0x1fff;
|
1038 |
break;
|
1039 |
case 8: /* User code access, XXX */ |
1040 |
case 9: /* Supervisor code access, XXX */ |
1041 |
default:
|
1042 |
do_unassigned_access(addr, 1, 0, asi, size); |
1043 |
break;
|
1044 |
} |
1045 |
#ifdef DEBUG_ASI
|
1046 |
dump_asi("write", addr, asi, size, val);
|
1047 |
#endif
|
1048 |
} |
1049 |
|
1050 |
#endif /* CONFIG_USER_ONLY */ |
1051 |
#else /* TARGET_SPARC64 */ |
1052 |
|
1053 |
#ifdef CONFIG_USER_ONLY
|
1054 |
uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign) |
1055 |
{ |
1056 |
uint64_t ret = 0;
|
1057 |
#if defined(DEBUG_ASI)
|
1058 |
target_ulong last_addr = addr; |
1059 |
#endif
|
1060 |
|
1061 |
if (asi < 0x80) { |
1062 |
helper_raise_exception(env, TT_PRIV_ACT); |
1063 |
} |
1064 |
|
1065 |
helper_check_align(addr, size - 1);
|
1066 |
addr = asi_address_mask(env, asi, addr); |
1067 |
|
1068 |
switch (asi) {
|
1069 |
case 0x82: /* Primary no-fault */ |
1070 |
case 0x8a: /* Primary no-fault LE */ |
1071 |
if (page_check_range(addr, size, PAGE_READ) == -1) { |
1072 |
#ifdef DEBUG_ASI
|
1073 |
dump_asi("read ", last_addr, asi, size, ret);
|
1074 |
#endif
|
1075 |
return 0; |
1076 |
} |
1077 |
/* Fall through */
|
1078 |
case 0x80: /* Primary */ |
1079 |
case 0x88: /* Primary LE */ |
1080 |
{ |
1081 |
switch (size) {
|
1082 |
case 1: |
1083 |
ret = ldub_raw(addr); |
1084 |
break;
|
1085 |
case 2: |
1086 |
ret = lduw_raw(addr); |
1087 |
break;
|
1088 |
case 4: |
1089 |
ret = ldl_raw(addr); |
1090 |
break;
|
1091 |
default:
|
1092 |
case 8: |
1093 |
ret = ldq_raw(addr); |
1094 |
break;
|
1095 |
} |
1096 |
} |
1097 |
break;
|
1098 |
case 0x83: /* Secondary no-fault */ |
1099 |
case 0x8b: /* Secondary no-fault LE */ |
1100 |
if (page_check_range(addr, size, PAGE_READ) == -1) { |
1101 |
#ifdef DEBUG_ASI
|
1102 |
dump_asi("read ", last_addr, asi, size, ret);
|
1103 |
#endif
|
1104 |
return 0; |
1105 |
} |
1106 |
/* Fall through */
|
1107 |
case 0x81: /* Secondary */ |
1108 |
case 0x89: /* Secondary LE */ |
1109 |
/* XXX */
|
1110 |
break;
|
1111 |
default:
|
1112 |
break;
|
1113 |
} |
1114 |
|
1115 |
/* Convert from little endian */
|
1116 |
switch (asi) {
|
1117 |
case 0x88: /* Primary LE */ |
1118 |
case 0x89: /* Secondary LE */ |
1119 |
case 0x8a: /* Primary no-fault LE */ |
1120 |
case 0x8b: /* Secondary no-fault LE */ |
1121 |
switch (size) {
|
1122 |
case 2: |
1123 |
ret = bswap16(ret); |
1124 |
break;
|
1125 |
case 4: |
1126 |
ret = bswap32(ret); |
1127 |
break;
|
1128 |
case 8: |
1129 |
ret = bswap64(ret); |
1130 |
break;
|
1131 |
default:
|
1132 |
break;
|
1133 |
} |
1134 |
default:
|
1135 |
break;
|
1136 |
} |
1137 |
|
1138 |
/* Convert to signed number */
|
1139 |
if (sign) {
|
1140 |
switch (size) {
|
1141 |
case 1: |
1142 |
ret = (int8_t) ret; |
1143 |
break;
|
1144 |
case 2: |
1145 |
ret = (int16_t) ret; |
1146 |
break;
|
1147 |
case 4: |
1148 |
ret = (int32_t) ret; |
1149 |
break;
|
1150 |
default:
|
1151 |
break;
|
1152 |
} |
1153 |
} |
1154 |
#ifdef DEBUG_ASI
|
1155 |
dump_asi("read ", last_addr, asi, size, ret);
|
1156 |
#endif
|
1157 |
return ret;
|
1158 |
} |
1159 |
|
1160 |
void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size) |
1161 |
{ |
1162 |
#ifdef DEBUG_ASI
|
1163 |
dump_asi("write", addr, asi, size, val);
|
1164 |
#endif
|
1165 |
if (asi < 0x80) { |
1166 |
helper_raise_exception(env, TT_PRIV_ACT); |
1167 |
} |
1168 |
|
1169 |
helper_check_align(addr, size - 1);
|
1170 |
addr = asi_address_mask(env, asi, addr); |
1171 |
|
1172 |
/* Convert to little endian */
|
1173 |
switch (asi) {
|
1174 |
case 0x88: /* Primary LE */ |
1175 |
case 0x89: /* Secondary LE */ |
1176 |
switch (size) {
|
1177 |
case 2: |
1178 |
val = bswap16(val); |
1179 |
break;
|
1180 |
case 4: |
1181 |
val = bswap32(val); |
1182 |
break;
|
1183 |
case 8: |
1184 |
val = bswap64(val); |
1185 |
break;
|
1186 |
default:
|
1187 |
break;
|
1188 |
} |
1189 |
default:
|
1190 |
break;
|
1191 |
} |
1192 |
|
1193 |
switch (asi) {
|
1194 |
case 0x80: /* Primary */ |
1195 |
case 0x88: /* Primary LE */ |
1196 |
{ |
1197 |
switch (size) {
|
1198 |
case 1: |
1199 |
stb_raw(addr, val); |
1200 |
break;
|
1201 |
case 2: |
1202 |
stw_raw(addr, val); |
1203 |
break;
|
1204 |
case 4: |
1205 |
stl_raw(addr, val); |
1206 |
break;
|
1207 |
case 8: |
1208 |
default:
|
1209 |
stq_raw(addr, val); |
1210 |
break;
|
1211 |
} |
1212 |
} |
1213 |
break;
|
1214 |
case 0x81: /* Secondary */ |
1215 |
case 0x89: /* Secondary LE */ |
1216 |
/* XXX */
|
1217 |
return;
|
1218 |
|
1219 |
case 0x82: /* Primary no-fault, RO */ |
1220 |
case 0x83: /* Secondary no-fault, RO */ |
1221 |
case 0x8a: /* Primary no-fault LE, RO */ |
1222 |
case 0x8b: /* Secondary no-fault LE, RO */ |
1223 |
default:
|
1224 |
do_unassigned_access(addr, 1, 0, 1, size); |
1225 |
return;
|
1226 |
} |
1227 |
} |
1228 |
|
1229 |
#else /* CONFIG_USER_ONLY */ |
1230 |
|
1231 |
uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign) |
1232 |
{ |
1233 |
uint64_t ret = 0;
|
1234 |
#if defined(DEBUG_ASI)
|
1235 |
target_ulong last_addr = addr; |
1236 |
#endif
|
1237 |
|
1238 |
asi &= 0xff;
|
1239 |
|
1240 |
if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0) |
1241 |
|| (cpu_has_hypervisor(env) |
1242 |
&& asi >= 0x30 && asi < 0x80 |
1243 |
&& !(env->hpstate & HS_PRIV))) { |
1244 |
helper_raise_exception(env, TT_PRIV_ACT); |
1245 |
} |
1246 |
|
1247 |
helper_check_align(addr, size - 1);
|
1248 |
addr = asi_address_mask(env, asi, addr); |
1249 |
|
1250 |
/* process nonfaulting loads first */
|
1251 |
if ((asi & 0xf6) == 0x82) { |
1252 |
int mmu_idx;
|
1253 |
|
1254 |
/* secondary space access has lowest asi bit equal to 1 */
|
1255 |
if (env->pstate & PS_PRIV) {
|
1256 |
mmu_idx = (asi & 1) ? MMU_KERNEL_SECONDARY_IDX : MMU_KERNEL_IDX;
|
1257 |
} else {
|
1258 |
mmu_idx = (asi & 1) ? MMU_USER_SECONDARY_IDX : MMU_USER_IDX;
|
1259 |
} |
1260 |
|
1261 |
if (cpu_get_phys_page_nofault(env, addr, mmu_idx) == -1ULL) { |
1262 |
#ifdef DEBUG_ASI
|
1263 |
dump_asi("read ", last_addr, asi, size, ret);
|
1264 |
#endif
|
1265 |
/* env->exception_index is set in get_physical_address_data(). */
|
1266 |
helper_raise_exception(env, env->exception_index); |
1267 |
} |
1268 |
|
1269 |
/* convert nonfaulting load ASIs to normal load ASIs */
|
1270 |
asi &= ~0x02;
|
1271 |
} |
1272 |
|
1273 |
switch (asi) {
|
1274 |
case 0x10: /* As if user primary */ |
1275 |
case 0x11: /* As if user secondary */ |
1276 |
case 0x18: /* As if user primary LE */ |
1277 |
case 0x19: /* As if user secondary LE */ |
1278 |
case 0x80: /* Primary */ |
1279 |
case 0x81: /* Secondary */ |
1280 |
case 0x88: /* Primary LE */ |
1281 |
case 0x89: /* Secondary LE */ |
1282 |
case 0xe2: /* UA2007 Primary block init */ |
1283 |
case 0xe3: /* UA2007 Secondary block init */ |
1284 |
if ((asi & 0x80) && (env->pstate & PS_PRIV)) { |
1285 |
if (cpu_hypervisor_mode(env)) {
|
1286 |
switch (size) {
|
1287 |
case 1: |
1288 |
ret = ldub_hypv(addr); |
1289 |
break;
|
1290 |
case 2: |
1291 |
ret = lduw_hypv(addr); |
1292 |
break;
|
1293 |
case 4: |
1294 |
ret = ldl_hypv(addr); |
1295 |
break;
|
1296 |
default:
|
1297 |
case 8: |
1298 |
ret = ldq_hypv(addr); |
1299 |
break;
|
1300 |
} |
1301 |
} else {
|
1302 |
/* secondary space access has lowest asi bit equal to 1 */
|
1303 |
if (asi & 1) { |
1304 |
switch (size) {
|
1305 |
case 1: |
1306 |
ret = ldub_kernel_secondary(addr); |
1307 |
break;
|
1308 |
case 2: |
1309 |
ret = lduw_kernel_secondary(addr); |
1310 |
break;
|
1311 |
case 4: |
1312 |
ret = ldl_kernel_secondary(addr); |
1313 |
break;
|
1314 |
default:
|
1315 |
case 8: |
1316 |
ret = ldq_kernel_secondary(addr); |
1317 |
break;
|
1318 |
} |
1319 |
} else {
|
1320 |
switch (size) {
|
1321 |
case 1: |
1322 |
ret = ldub_kernel(addr); |
1323 |
break;
|
1324 |
case 2: |
1325 |
ret = lduw_kernel(addr); |
1326 |
break;
|
1327 |
case 4: |
1328 |
ret = ldl_kernel(addr); |
1329 |
break;
|
1330 |
default:
|
1331 |
case 8: |
1332 |
ret = ldq_kernel(addr); |
1333 |
break;
|
1334 |
} |
1335 |
} |
1336 |
} |
1337 |
} else {
|
1338 |
/* secondary space access has lowest asi bit equal to 1 */
|
1339 |
if (asi & 1) { |
1340 |
switch (size) {
|
1341 |
case 1: |
1342 |
ret = ldub_user_secondary(addr); |
1343 |
break;
|
1344 |
case 2: |
1345 |
ret = lduw_user_secondary(addr); |
1346 |
break;
|
1347 |
case 4: |
1348 |
ret = ldl_user_secondary(addr); |
1349 |
break;
|
1350 |
default:
|
1351 |
case 8: |
1352 |
ret = ldq_user_secondary(addr); |
1353 |
break;
|
1354 |
} |
1355 |
} else {
|
1356 |
switch (size) {
|
1357 |
case 1: |
1358 |
ret = ldub_user(addr); |
1359 |
break;
|
1360 |
case 2: |
1361 |
ret = lduw_user(addr); |
1362 |
break;
|
1363 |
case 4: |
1364 |
ret = ldl_user(addr); |
1365 |
break;
|
1366 |
default:
|
1367 |
case 8: |
1368 |
ret = ldq_user(addr); |
1369 |
break;
|
1370 |
} |
1371 |
} |
1372 |
} |
1373 |
break;
|
1374 |
case 0x14: /* Bypass */ |
1375 |
case 0x15: /* Bypass, non-cacheable */ |
1376 |
case 0x1c: /* Bypass LE */ |
1377 |
case 0x1d: /* Bypass, non-cacheable LE */ |
1378 |
{ |
1379 |
switch (size) {
|
1380 |
case 1: |
1381 |
ret = ldub_phys(addr); |
1382 |
break;
|
1383 |
case 2: |
1384 |
ret = lduw_phys(addr); |
1385 |
break;
|
1386 |
case 4: |
1387 |
ret = ldl_phys(addr); |
1388 |
break;
|
1389 |
default:
|
1390 |
case 8: |
1391 |
ret = ldq_phys(addr); |
1392 |
break;
|
1393 |
} |
1394 |
break;
|
1395 |
} |
1396 |
case 0x24: /* Nucleus quad LDD 128 bit atomic */ |
1397 |
case 0x2c: /* Nucleus quad LDD 128 bit atomic LE |
1398 |
Only ldda allowed */
|
1399 |
helper_raise_exception(env, TT_ILL_INSN); |
1400 |
return 0; |
1401 |
case 0x04: /* Nucleus */ |
1402 |
case 0x0c: /* Nucleus Little Endian (LE) */ |
1403 |
{ |
1404 |
switch (size) {
|
1405 |
case 1: |
1406 |
ret = ldub_nucleus(addr); |
1407 |
break;
|
1408 |
case 2: |
1409 |
ret = lduw_nucleus(addr); |
1410 |
break;
|
1411 |
case 4: |
1412 |
ret = ldl_nucleus(addr); |
1413 |
break;
|
1414 |
default:
|
1415 |
case 8: |
1416 |
ret = ldq_nucleus(addr); |
1417 |
break;
|
1418 |
} |
1419 |
break;
|
1420 |
} |
1421 |
case 0x4a: /* UPA config */ |
1422 |
/* XXX */
|
1423 |
break;
|
1424 |
case 0x45: /* LSU */ |
1425 |
ret = env->lsu; |
1426 |
break;
|
1427 |
case 0x50: /* I-MMU regs */ |
1428 |
{ |
1429 |
int reg = (addr >> 3) & 0xf; |
1430 |
|
1431 |
if (reg == 0) { |
1432 |
/* I-TSB Tag Target register */
|
1433 |
ret = ultrasparc_tag_target(env->immu.tag_access); |
1434 |
} else {
|
1435 |
ret = env->immuregs[reg]; |
1436 |
} |
1437 |
|
1438 |
break;
|
1439 |
} |
1440 |
case 0x51: /* I-MMU 8k TSB pointer */ |
1441 |
{ |
1442 |
/* env->immuregs[5] holds I-MMU TSB register value
|
1443 |
env->immuregs[6] holds I-MMU Tag Access register value */
|
1444 |
ret = ultrasparc_tsb_pointer(env->immu.tsb, env->immu.tag_access, |
1445 |
8*1024); |
1446 |
break;
|
1447 |
} |
1448 |
case 0x52: /* I-MMU 64k TSB pointer */ |
1449 |
{ |
1450 |
/* env->immuregs[5] holds I-MMU TSB register value
|
1451 |
env->immuregs[6] holds I-MMU Tag Access register value */
|
1452 |
ret = ultrasparc_tsb_pointer(env->immu.tsb, env->immu.tag_access, |
1453 |
64*1024); |
1454 |
break;
|
1455 |
} |
1456 |
case 0x55: /* I-MMU data access */ |
1457 |
{ |
1458 |
int reg = (addr >> 3) & 0x3f; |
1459 |
|
1460 |
ret = env->itlb[reg].tte; |
1461 |
break;
|
1462 |
} |
1463 |
case 0x56: /* I-MMU tag read */ |
1464 |
{ |
1465 |
int reg = (addr >> 3) & 0x3f; |
1466 |
|
1467 |
ret = env->itlb[reg].tag; |
1468 |
break;
|
1469 |
} |
1470 |
case 0x58: /* D-MMU regs */ |
1471 |
{ |
1472 |
int reg = (addr >> 3) & 0xf; |
1473 |
|
1474 |
if (reg == 0) { |
1475 |
/* D-TSB Tag Target register */
|
1476 |
ret = ultrasparc_tag_target(env->dmmu.tag_access); |
1477 |
} else {
|
1478 |
ret = env->dmmuregs[reg]; |
1479 |
} |
1480 |
break;
|
1481 |
} |
1482 |
case 0x59: /* D-MMU 8k TSB pointer */ |
1483 |
{ |
1484 |
/* env->dmmuregs[5] holds D-MMU TSB register value
|
1485 |
env->dmmuregs[6] holds D-MMU Tag Access register value */
|
1486 |
ret = ultrasparc_tsb_pointer(env->dmmu.tsb, env->dmmu.tag_access, |
1487 |
8*1024); |
1488 |
break;
|
1489 |
} |
1490 |
case 0x5a: /* D-MMU 64k TSB pointer */ |
1491 |
{ |
1492 |
/* env->dmmuregs[5] holds D-MMU TSB register value
|
1493 |
env->dmmuregs[6] holds D-MMU Tag Access register value */
|
1494 |
ret = ultrasparc_tsb_pointer(env->dmmu.tsb, env->dmmu.tag_access, |
1495 |
64*1024); |
1496 |
break;
|
1497 |
} |
1498 |
case 0x5d: /* D-MMU data access */ |
1499 |
{ |
1500 |
int reg = (addr >> 3) & 0x3f; |
1501 |
|
1502 |
ret = env->dtlb[reg].tte; |
1503 |
break;
|
1504 |
} |
1505 |
case 0x5e: /* D-MMU tag read */ |
1506 |
{ |
1507 |
int reg = (addr >> 3) & 0x3f; |
1508 |
|
1509 |
ret = env->dtlb[reg].tag; |
1510 |
break;
|
1511 |
} |
1512 |
case 0x46: /* D-cache data */ |
1513 |
case 0x47: /* D-cache tag access */ |
1514 |
case 0x4b: /* E-cache error enable */ |
1515 |
case 0x4c: /* E-cache asynchronous fault status */ |
1516 |
case 0x4d: /* E-cache asynchronous fault address */ |
1517 |
case 0x4e: /* E-cache tag data */ |
1518 |
case 0x66: /* I-cache instruction access */ |
1519 |
case 0x67: /* I-cache tag access */ |
1520 |
case 0x6e: /* I-cache predecode */ |
1521 |
case 0x6f: /* I-cache LRU etc. */ |
1522 |
case 0x76: /* E-cache tag */ |
1523 |
case 0x7e: /* E-cache tag */ |
1524 |
break;
|
1525 |
case 0x5b: /* D-MMU data pointer */ |
1526 |
case 0x48: /* Interrupt dispatch, RO */ |
1527 |
case 0x49: /* Interrupt data receive */ |
1528 |
case 0x7f: /* Incoming interrupt vector, RO */ |
1529 |
/* XXX */
|
1530 |
break;
|
1531 |
case 0x54: /* I-MMU data in, WO */ |
1532 |
case 0x57: /* I-MMU demap, WO */ |
1533 |
case 0x5c: /* D-MMU data in, WO */ |
1534 |
case 0x5f: /* D-MMU demap, WO */ |
1535 |
case 0x77: /* Interrupt vector, WO */ |
1536 |
default:
|
1537 |
do_unassigned_access(addr, 0, 0, 1, size); |
1538 |
ret = 0;
|
1539 |
break;
|
1540 |
} |
1541 |
|
1542 |
/* Convert from little endian */
|
1543 |
switch (asi) {
|
1544 |
case 0x0c: /* Nucleus Little Endian (LE) */ |
1545 |
case 0x18: /* As if user primary LE */ |
1546 |
case 0x19: /* As if user secondary LE */ |
1547 |
case 0x1c: /* Bypass LE */ |
1548 |
case 0x1d: /* Bypass, non-cacheable LE */ |
1549 |
case 0x88: /* Primary LE */ |
1550 |
case 0x89: /* Secondary LE */ |
1551 |
switch(size) {
|
1552 |
case 2: |
1553 |
ret = bswap16(ret); |
1554 |
break;
|
1555 |
case 4: |
1556 |
ret = bswap32(ret); |
1557 |
break;
|
1558 |
case 8: |
1559 |
ret = bswap64(ret); |
1560 |
break;
|
1561 |
default:
|
1562 |
break;
|
1563 |
} |
1564 |
default:
|
1565 |
break;
|
1566 |
} |
1567 |
|
1568 |
/* Convert to signed number */
|
1569 |
if (sign) {
|
1570 |
switch (size) {
|
1571 |
case 1: |
1572 |
ret = (int8_t) ret; |
1573 |
break;
|
1574 |
case 2: |
1575 |
ret = (int16_t) ret; |
1576 |
break;
|
1577 |
case 4: |
1578 |
ret = (int32_t) ret; |
1579 |
break;
|
1580 |
default:
|
1581 |
break;
|
1582 |
} |
1583 |
} |
1584 |
#ifdef DEBUG_ASI
|
1585 |
dump_asi("read ", last_addr, asi, size, ret);
|
1586 |
#endif
|
1587 |
return ret;
|
1588 |
} |
1589 |
|
1590 |
void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size) |
1591 |
{ |
1592 |
#ifdef DEBUG_ASI
|
1593 |
dump_asi("write", addr, asi, size, val);
|
1594 |
#endif
|
1595 |
|
1596 |
asi &= 0xff;
|
1597 |
|
1598 |
if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0) |
1599 |
|| (cpu_has_hypervisor(env) |
1600 |
&& asi >= 0x30 && asi < 0x80 |
1601 |
&& !(env->hpstate & HS_PRIV))) { |
1602 |
helper_raise_exception(env, TT_PRIV_ACT); |
1603 |
} |
1604 |
|
1605 |
helper_check_align(addr, size - 1);
|
1606 |
addr = asi_address_mask(env, asi, addr); |
1607 |
|
1608 |
/* Convert to little endian */
|
1609 |
switch (asi) {
|
1610 |
case 0x0c: /* Nucleus Little Endian (LE) */ |
1611 |
case 0x18: /* As if user primary LE */ |
1612 |
case 0x19: /* As if user secondary LE */ |
1613 |
case 0x1c: /* Bypass LE */ |
1614 |
case 0x1d: /* Bypass, non-cacheable LE */ |
1615 |
case 0x88: /* Primary LE */ |
1616 |
case 0x89: /* Secondary LE */ |
1617 |
switch (size) {
|
1618 |
case 2: |
1619 |
val = bswap16(val); |
1620 |
break;
|
1621 |
case 4: |
1622 |
val = bswap32(val); |
1623 |
break;
|
1624 |
case 8: |
1625 |
val = bswap64(val); |
1626 |
break;
|
1627 |
default:
|
1628 |
break;
|
1629 |
} |
1630 |
default:
|
1631 |
break;
|
1632 |
} |
1633 |
|
1634 |
switch (asi) {
|
1635 |
case 0x10: /* As if user primary */ |
1636 |
case 0x11: /* As if user secondary */ |
1637 |
case 0x18: /* As if user primary LE */ |
1638 |
case 0x19: /* As if user secondary LE */ |
1639 |
case 0x80: /* Primary */ |
1640 |
case 0x81: /* Secondary */ |
1641 |
case 0x88: /* Primary LE */ |
1642 |
case 0x89: /* Secondary LE */ |
1643 |
case 0xe2: /* UA2007 Primary block init */ |
1644 |
case 0xe3: /* UA2007 Secondary block init */ |
1645 |
if ((asi & 0x80) && (env->pstate & PS_PRIV)) { |
1646 |
if (cpu_hypervisor_mode(env)) {
|
1647 |
switch (size) {
|
1648 |
case 1: |
1649 |
stb_hypv(addr, val); |
1650 |
break;
|
1651 |
case 2: |
1652 |
stw_hypv(addr, val); |
1653 |
break;
|
1654 |
case 4: |
1655 |
stl_hypv(addr, val); |
1656 |
break;
|
1657 |
case 8: |
1658 |
default:
|
1659 |
stq_hypv(addr, val); |
1660 |
break;
|
1661 |
} |
1662 |
} else {
|
1663 |
/* secondary space access has lowest asi bit equal to 1 */
|
1664 |
if (asi & 1) { |
1665 |
switch (size) {
|
1666 |
case 1: |
1667 |
stb_kernel_secondary(addr, val); |
1668 |
break;
|
1669 |
case 2: |
1670 |
stw_kernel_secondary(addr, val); |
1671 |
break;
|
1672 |
case 4: |
1673 |
stl_kernel_secondary(addr, val); |
1674 |
break;
|
1675 |
case 8: |
1676 |
default:
|
1677 |
stq_kernel_secondary(addr, val); |
1678 |
break;
|
1679 |
} |
1680 |
} else {
|
1681 |
switch (size) {
|
1682 |
case 1: |
1683 |
stb_kernel(addr, val); |
1684 |
break;
|
1685 |
case 2: |
1686 |
stw_kernel(addr, val); |
1687 |
break;
|
1688 |
case 4: |
1689 |
stl_kernel(addr, val); |
1690 |
break;
|
1691 |
case 8: |
1692 |
default:
|
1693 |
stq_kernel(addr, val); |
1694 |
break;
|
1695 |
} |
1696 |
} |
1697 |
} |
1698 |
} else {
|
1699 |
/* secondary space access has lowest asi bit equal to 1 */
|
1700 |
if (asi & 1) { |
1701 |
switch (size) {
|
1702 |
case 1: |
1703 |
stb_user_secondary(addr, val); |
1704 |
break;
|
1705 |
case 2: |
1706 |
stw_user_secondary(addr, val); |
1707 |
break;
|
1708 |
case 4: |
1709 |
stl_user_secondary(addr, val); |
1710 |
break;
|
1711 |
case 8: |
1712 |
default:
|
1713 |
stq_user_secondary(addr, val); |
1714 |
break;
|
1715 |
} |
1716 |
} else {
|
1717 |
switch (size) {
|
1718 |
case 1: |
1719 |
stb_user(addr, val); |
1720 |
break;
|
1721 |
case 2: |
1722 |
stw_user(addr, val); |
1723 |
break;
|
1724 |
case 4: |
1725 |
stl_user(addr, val); |
1726 |
break;
|
1727 |
case 8: |
1728 |
default:
|
1729 |
stq_user(addr, val); |
1730 |
break;
|
1731 |
} |
1732 |
} |
1733 |
} |
1734 |
break;
|
1735 |
case 0x14: /* Bypass */ |
1736 |
case 0x15: /* Bypass, non-cacheable */ |
1737 |
case 0x1c: /* Bypass LE */ |
1738 |
case 0x1d: /* Bypass, non-cacheable LE */ |
1739 |
{ |
1740 |
switch (size) {
|
1741 |
case 1: |
1742 |
stb_phys(addr, val); |
1743 |
break;
|
1744 |
case 2: |
1745 |
stw_phys(addr, val); |
1746 |
break;
|
1747 |
case 4: |
1748 |
stl_phys(addr, val); |
1749 |
break;
|
1750 |
case 8: |
1751 |
default:
|
1752 |
stq_phys(addr, val); |
1753 |
break;
|
1754 |
} |
1755 |
} |
1756 |
return;
|
1757 |
case 0x24: /* Nucleus quad LDD 128 bit atomic */ |
1758 |
case 0x2c: /* Nucleus quad LDD 128 bit atomic LE |
1759 |
Only ldda allowed */
|
1760 |
helper_raise_exception(env, TT_ILL_INSN); |
1761 |
return;
|
1762 |
case 0x04: /* Nucleus */ |
1763 |
case 0x0c: /* Nucleus Little Endian (LE) */ |
1764 |
{ |
1765 |
switch (size) {
|
1766 |
case 1: |
1767 |
stb_nucleus(addr, val); |
1768 |
break;
|
1769 |
case 2: |
1770 |
stw_nucleus(addr, val); |
1771 |
break;
|
1772 |
case 4: |
1773 |
stl_nucleus(addr, val); |
1774 |
break;
|
1775 |
default:
|
1776 |
case 8: |
1777 |
stq_nucleus(addr, val); |
1778 |
break;
|
1779 |
} |
1780 |
break;
|
1781 |
} |
1782 |
|
1783 |
case 0x4a: /* UPA config */ |
1784 |
/* XXX */
|
1785 |
return;
|
1786 |
case 0x45: /* LSU */ |
1787 |
{ |
1788 |
uint64_t oldreg; |
1789 |
|
1790 |
oldreg = env->lsu; |
1791 |
env->lsu = val & (DMMU_E | IMMU_E); |
1792 |
/* Mappings generated during D/I MMU disabled mode are
|
1793 |
invalid in normal mode */
|
1794 |
if (oldreg != env->lsu) {
|
1795 |
DPRINTF_MMU("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n", |
1796 |
oldreg, env->lsu); |
1797 |
#ifdef DEBUG_MMU
|
1798 |
dump_mmu(stdout, fprintf, env1); |
1799 |
#endif
|
1800 |
tlb_flush(env, 1);
|
1801 |
} |
1802 |
return;
|
1803 |
} |
1804 |
case 0x50: /* I-MMU regs */ |
1805 |
{ |
1806 |
int reg = (addr >> 3) & 0xf; |
1807 |
uint64_t oldreg; |
1808 |
|
1809 |
oldreg = env->immuregs[reg]; |
1810 |
switch (reg) {
|
1811 |
case 0: /* RO */ |
1812 |
return;
|
1813 |
case 1: /* Not in I-MMU */ |
1814 |
case 2: |
1815 |
return;
|
1816 |
case 3: /* SFSR */ |
1817 |
if ((val & 1) == 0) { |
1818 |
val = 0; /* Clear SFSR */ |
1819 |
} |
1820 |
env->immu.sfsr = val; |
1821 |
break;
|
1822 |
case 4: /* RO */ |
1823 |
return;
|
1824 |
case 5: /* TSB access */ |
1825 |
DPRINTF_MMU("immu TSB write: 0x%016" PRIx64 " -> 0x%016" |
1826 |
PRIx64 "\n", env->immu.tsb, val);
|
1827 |
env->immu.tsb = val; |
1828 |
break;
|
1829 |
case 6: /* Tag access */ |
1830 |
env->immu.tag_access = val; |
1831 |
break;
|
1832 |
case 7: |
1833 |
case 8: |
1834 |
return;
|
1835 |
default:
|
1836 |
break;
|
1837 |
} |
1838 |
|
1839 |
if (oldreg != env->immuregs[reg]) {
|
1840 |
DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64 " -> 0x%016" |
1841 |
PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
|
1842 |
} |
1843 |
#ifdef DEBUG_MMU
|
1844 |
dump_mmu(stdout, fprintf, env); |
1845 |
#endif
|
1846 |
return;
|
1847 |
} |
1848 |
case 0x54: /* I-MMU data in */ |
1849 |
replace_tlb_1bit_lru(env->itlb, env->immu.tag_access, val, "immu", env);
|
1850 |
return;
|
1851 |
case 0x55: /* I-MMU data access */ |
1852 |
{ |
1853 |
/* TODO: auto demap */
|
1854 |
|
1855 |
unsigned int i = (addr >> 3) & 0x3f; |
1856 |
|
1857 |
replace_tlb_entry(&env->itlb[i], env->immu.tag_access, val, env); |
1858 |
|
1859 |
#ifdef DEBUG_MMU
|
1860 |
DPRINTF_MMU("immu data access replaced entry [%i]\n", i);
|
1861 |
dump_mmu(stdout, fprintf, env); |
1862 |
#endif
|
1863 |
return;
|
1864 |
} |
1865 |
case 0x57: /* I-MMU demap */ |
1866 |
demap_tlb(env->itlb, addr, "immu", env);
|
1867 |
return;
|
1868 |
case 0x58: /* D-MMU regs */ |
1869 |
{ |
1870 |
int reg = (addr >> 3) & 0xf; |
1871 |
uint64_t oldreg; |
1872 |
|
1873 |
oldreg = env->dmmuregs[reg]; |
1874 |
switch (reg) {
|
1875 |
case 0: /* RO */ |
1876 |
case 4: |
1877 |
return;
|
1878 |
case 3: /* SFSR */ |
1879 |
if ((val & 1) == 0) { |
1880 |
val = 0; /* Clear SFSR, Fault address */ |
1881 |
env->dmmu.sfar = 0;
|
1882 |
} |
1883 |
env->dmmu.sfsr = val; |
1884 |
break;
|
1885 |
case 1: /* Primary context */ |
1886 |
env->dmmu.mmu_primary_context = val; |
1887 |
/* can be optimized to only flush MMU_USER_IDX
|
1888 |
and MMU_KERNEL_IDX entries */
|
1889 |
tlb_flush(env, 1);
|
1890 |
break;
|
1891 |
case 2: /* Secondary context */ |
1892 |
env->dmmu.mmu_secondary_context = val; |
1893 |
/* can be optimized to only flush MMU_USER_SECONDARY_IDX
|
1894 |
and MMU_KERNEL_SECONDARY_IDX entries */
|
1895 |
tlb_flush(env, 1);
|
1896 |
break;
|
1897 |
case 5: /* TSB access */ |
1898 |
DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016" |
1899 |
PRIx64 "\n", env->dmmu.tsb, val);
|
1900 |
env->dmmu.tsb = val; |
1901 |
break;
|
1902 |
case 6: /* Tag access */ |
1903 |
env->dmmu.tag_access = val; |
1904 |
break;
|
1905 |
case 7: /* Virtual Watchpoint */ |
1906 |
case 8: /* Physical Watchpoint */ |
1907 |
default:
|
1908 |
env->dmmuregs[reg] = val; |
1909 |
break;
|
1910 |
} |
1911 |
|
1912 |
if (oldreg != env->dmmuregs[reg]) {
|
1913 |
DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64 " -> 0x%016" |
1914 |
PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
|
1915 |
} |
1916 |
#ifdef DEBUG_MMU
|
1917 |
dump_mmu(stdout, fprintf, env); |
1918 |
#endif
|
1919 |
return;
|
1920 |
} |
1921 |
case 0x5c: /* D-MMU data in */ |
1922 |
replace_tlb_1bit_lru(env->dtlb, env->dmmu.tag_access, val, "dmmu", env);
|
1923 |
return;
|
1924 |
case 0x5d: /* D-MMU data access */ |
1925 |
{ |
1926 |
unsigned int i = (addr >> 3) & 0x3f; |
1927 |
|
1928 |
replace_tlb_entry(&env->dtlb[i], env->dmmu.tag_access, val, env); |
1929 |
|
1930 |
#ifdef DEBUG_MMU
|
1931 |
DPRINTF_MMU("dmmu data access replaced entry [%i]\n", i);
|
1932 |
dump_mmu(stdout, fprintf, env); |
1933 |
#endif
|
1934 |
return;
|
1935 |
} |
1936 |
case 0x5f: /* D-MMU demap */ |
1937 |
demap_tlb(env->dtlb, addr, "dmmu", env);
|
1938 |
return;
|
1939 |
case 0x49: /* Interrupt data receive */ |
1940 |
/* XXX */
|
1941 |
return;
|
1942 |
case 0x46: /* D-cache data */ |
1943 |
case 0x47: /* D-cache tag access */ |
1944 |
case 0x4b: /* E-cache error enable */ |
1945 |
case 0x4c: /* E-cache asynchronous fault status */ |
1946 |
case 0x4d: /* E-cache asynchronous fault address */ |
1947 |
case 0x4e: /* E-cache tag data */ |
1948 |
case 0x66: /* I-cache instruction access */ |
1949 |
case 0x67: /* I-cache tag access */ |
1950 |
case 0x6e: /* I-cache predecode */ |
1951 |
case 0x6f: /* I-cache LRU etc. */ |
1952 |
case 0x76: /* E-cache tag */ |
1953 |
case 0x7e: /* E-cache tag */ |
1954 |
return;
|
1955 |
case 0x51: /* I-MMU 8k TSB pointer, RO */ |
1956 |
case 0x52: /* I-MMU 64k TSB pointer, RO */ |
1957 |
case 0x56: /* I-MMU tag read, RO */ |
1958 |
case 0x59: /* D-MMU 8k TSB pointer, RO */ |
1959 |
case 0x5a: /* D-MMU 64k TSB pointer, RO */ |
1960 |
case 0x5b: /* D-MMU data pointer, RO */ |
1961 |
case 0x5e: /* D-MMU tag read, RO */ |
1962 |
case 0x48: /* Interrupt dispatch, RO */ |
1963 |
case 0x7f: /* Incoming interrupt vector, RO */ |
1964 |
case 0x82: /* Primary no-fault, RO */ |
1965 |
case 0x83: /* Secondary no-fault, RO */ |
1966 |
case 0x8a: /* Primary no-fault LE, RO */ |
1967 |
case 0x8b: /* Secondary no-fault LE, RO */ |
1968 |
default:
|
1969 |
do_unassigned_access(addr, 1, 0, 1, size); |
1970 |
return;
|
1971 |
} |
1972 |
} |
1973 |
#endif /* CONFIG_USER_ONLY */ |
1974 |
|
1975 |
void helper_ldda_asi(target_ulong addr, int asi, int rd) |
1976 |
{ |
1977 |
if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0) |
1978 |
|| (cpu_has_hypervisor(env) |
1979 |
&& asi >= 0x30 && asi < 0x80 |
1980 |
&& !(env->hpstate & HS_PRIV))) { |
1981 |
helper_raise_exception(env, TT_PRIV_ACT); |
1982 |
} |
1983 |
|
1984 |
addr = asi_address_mask(env, asi, addr); |
1985 |
|
1986 |
switch (asi) {
|
1987 |
#if !defined(CONFIG_USER_ONLY)
|
1988 |
case 0x24: /* Nucleus quad LDD 128 bit atomic */ |
1989 |
case 0x2c: /* Nucleus quad LDD 128 bit atomic LE */ |
1990 |
helper_check_align(addr, 0xf);
|
1991 |
if (rd == 0) { |
1992 |
env->gregs[1] = ldq_nucleus(addr + 8); |
1993 |
if (asi == 0x2c) { |
1994 |
bswap64s(&env->gregs[1]);
|
1995 |
} |
1996 |
} else if (rd < 8) { |
1997 |
env->gregs[rd] = ldq_nucleus(addr); |
1998 |
env->gregs[rd + 1] = ldq_nucleus(addr + 8); |
1999 |
if (asi == 0x2c) { |
2000 |
bswap64s(&env->gregs[rd]); |
2001 |
bswap64s(&env->gregs[rd + 1]);
|
2002 |
} |
2003 |
} else {
|
2004 |
env->regwptr[rd] = ldq_nucleus(addr); |
2005 |
env->regwptr[rd + 1] = ldq_nucleus(addr + 8); |
2006 |
if (asi == 0x2c) { |
2007 |
bswap64s(&env->regwptr[rd]); |
2008 |
bswap64s(&env->regwptr[rd + 1]);
|
2009 |
} |
2010 |
} |
2011 |
break;
|
2012 |
#endif
|
2013 |
default:
|
2014 |
helper_check_align(addr, 0x3);
|
2015 |
if (rd == 0) { |
2016 |
env->gregs[1] = helper_ld_asi(addr + 4, asi, 4, 0); |
2017 |
} else if (rd < 8) { |
2018 |
env->gregs[rd] = helper_ld_asi(addr, asi, 4, 0); |
2019 |
env->gregs[rd + 1] = helper_ld_asi(addr + 4, asi, 4, 0); |
2020 |
} else {
|
2021 |
env->regwptr[rd] = helper_ld_asi(addr, asi, 4, 0); |
2022 |
env->regwptr[rd + 1] = helper_ld_asi(addr + 4, asi, 4, 0); |
2023 |
} |
2024 |
break;
|
2025 |
} |
2026 |
} |
2027 |
|
2028 |
void helper_ldf_asi(target_ulong addr, int asi, int size, int rd) |
2029 |
{ |
2030 |
unsigned int i; |
2031 |
CPU_DoubleU u; |
2032 |
|
2033 |
helper_check_align(addr, 3);
|
2034 |
addr = asi_address_mask(env, asi, addr); |
2035 |
|
2036 |
switch (asi) {
|
2037 |
case 0xf0: /* UA2007/JPS1 Block load primary */ |
2038 |
case 0xf1: /* UA2007/JPS1 Block load secondary */ |
2039 |
case 0xf8: /* UA2007/JPS1 Block load primary LE */ |
2040 |
case 0xf9: /* UA2007/JPS1 Block load secondary LE */ |
2041 |
if (rd & 7) { |
2042 |
helper_raise_exception(env, TT_ILL_INSN); |
2043 |
return;
|
2044 |
} |
2045 |
helper_check_align(addr, 0x3f);
|
2046 |
for (i = 0; i < 16; i++) { |
2047 |
*(uint32_t *)&env->fpr[rd++] = helper_ld_asi(addr, asi & 0x8f, 4, |
2048 |
0);
|
2049 |
addr += 4;
|
2050 |
} |
2051 |
|
2052 |
return;
|
2053 |
case 0x16: /* UA2007 Block load primary, user privilege */ |
2054 |
case 0x17: /* UA2007 Block load secondary, user privilege */ |
2055 |
case 0x1e: /* UA2007 Block load primary LE, user privilege */ |
2056 |
case 0x1f: /* UA2007 Block load secondary LE, user privilege */ |
2057 |
case 0x70: /* JPS1 Block load primary, user privilege */ |
2058 |
case 0x71: /* JPS1 Block load secondary, user privilege */ |
2059 |
case 0x78: /* JPS1 Block load primary LE, user privilege */ |
2060 |
case 0x79: /* JPS1 Block load secondary LE, user privilege */ |
2061 |
if (rd & 7) { |
2062 |
helper_raise_exception(env, TT_ILL_INSN); |
2063 |
return;
|
2064 |
} |
2065 |
helper_check_align(addr, 0x3f);
|
2066 |
for (i = 0; i < 16; i++) { |
2067 |
*(uint32_t *)&env->fpr[rd++] = helper_ld_asi(addr, asi & 0x19, 4, |
2068 |
0);
|
2069 |
addr += 4;
|
2070 |
} |
2071 |
|
2072 |
return;
|
2073 |
default:
|
2074 |
break;
|
2075 |
} |
2076 |
|
2077 |
switch (size) {
|
2078 |
default:
|
2079 |
case 4: |
2080 |
*((uint32_t *)&env->fpr[rd]) = helper_ld_asi(addr, asi, size, 0);
|
2081 |
break;
|
2082 |
case 8: |
2083 |
u.ll = helper_ld_asi(addr, asi, size, 0);
|
2084 |
*((uint32_t *)&env->fpr[rd++]) = u.l.upper; |
2085 |
*((uint32_t *)&env->fpr[rd++]) = u.l.lower; |
2086 |
break;
|
2087 |
case 16: |
2088 |
u.ll = helper_ld_asi(addr, asi, 8, 0); |
2089 |
*((uint32_t *)&env->fpr[rd++]) = u.l.upper; |
2090 |
*((uint32_t *)&env->fpr[rd++]) = u.l.lower; |
2091 |
u.ll = helper_ld_asi(addr + 8, asi, 8, 0); |
2092 |
*((uint32_t *)&env->fpr[rd++]) = u.l.upper; |
2093 |
*((uint32_t *)&env->fpr[rd++]) = u.l.lower; |
2094 |
break;
|
2095 |
} |
2096 |
} |
2097 |
|
2098 |
void helper_stf_asi(target_ulong addr, int asi, int size, int rd) |
2099 |
{ |
2100 |
unsigned int i; |
2101 |
target_ulong val = 0;
|
2102 |
CPU_DoubleU u; |
2103 |
|
2104 |
helper_check_align(addr, 3);
|
2105 |
addr = asi_address_mask(env, asi, addr); |
2106 |
|
2107 |
switch (asi) {
|
2108 |
case 0xe0: /* UA2007/JPS1 Block commit store primary (cache flush) */ |
2109 |
case 0xe1: /* UA2007/JPS1 Block commit store secondary (cache flush) */ |
2110 |
case 0xf0: /* UA2007/JPS1 Block store primary */ |
2111 |
case 0xf1: /* UA2007/JPS1 Block store secondary */ |
2112 |
case 0xf8: /* UA2007/JPS1 Block store primary LE */ |
2113 |
case 0xf9: /* UA2007/JPS1 Block store secondary LE */ |
2114 |
if (rd & 7) { |
2115 |
helper_raise_exception(env, TT_ILL_INSN); |
2116 |
return;
|
2117 |
} |
2118 |
helper_check_align(addr, 0x3f);
|
2119 |
for (i = 0; i < 16; i++) { |
2120 |
val = *(uint32_t *)&env->fpr[rd++]; |
2121 |
helper_st_asi(addr, val, asi & 0x8f, 4); |
2122 |
addr += 4;
|
2123 |
} |
2124 |
|
2125 |
return;
|
2126 |
case 0x16: /* UA2007 Block load primary, user privilege */ |
2127 |
case 0x17: /* UA2007 Block load secondary, user privilege */ |
2128 |
case 0x1e: /* UA2007 Block load primary LE, user privilege */ |
2129 |
case 0x1f: /* UA2007 Block load secondary LE, user privilege */ |
2130 |
case 0x70: /* JPS1 Block store primary, user privilege */ |
2131 |
case 0x71: /* JPS1 Block store secondary, user privilege */ |
2132 |
case 0x78: /* JPS1 Block load primary LE, user privilege */ |
2133 |
case 0x79: /* JPS1 Block load secondary LE, user privilege */ |
2134 |
if (rd & 7) { |
2135 |
helper_raise_exception(env, TT_ILL_INSN); |
2136 |
return;
|
2137 |
} |
2138 |
helper_check_align(addr, 0x3f);
|
2139 |
for (i = 0; i < 16; i++) { |
2140 |
val = *(uint32_t *)&env->fpr[rd++]; |
2141 |
helper_st_asi(addr, val, asi & 0x19, 4); |
2142 |
addr += 4;
|
2143 |
} |
2144 |
|
2145 |
return;
|
2146 |
default:
|
2147 |
break;
|
2148 |
} |
2149 |
|
2150 |
switch (size) {
|
2151 |
default:
|
2152 |
case 4: |
2153 |
helper_st_asi(addr, *(uint32_t *)&env->fpr[rd], asi, size); |
2154 |
break;
|
2155 |
case 8: |
2156 |
u.l.upper = *(uint32_t *)&env->fpr[rd++]; |
2157 |
u.l.lower = *(uint32_t *)&env->fpr[rd++]; |
2158 |
helper_st_asi(addr, u.ll, asi, size); |
2159 |
break;
|
2160 |
case 16: |
2161 |
u.l.upper = *(uint32_t *)&env->fpr[rd++]; |
2162 |
u.l.lower = *(uint32_t *)&env->fpr[rd++]; |
2163 |
helper_st_asi(addr, u.ll, asi, 8);
|
2164 |
u.l.upper = *(uint32_t *)&env->fpr[rd++]; |
2165 |
u.l.lower = *(uint32_t *)&env->fpr[rd++]; |
2166 |
helper_st_asi(addr + 8, u.ll, asi, 8); |
2167 |
break;
|
2168 |
} |
2169 |
} |
2170 |
|
2171 |
target_ulong helper_cas_asi(target_ulong addr, target_ulong val1, |
2172 |
target_ulong val2, uint32_t asi) |
2173 |
{ |
2174 |
target_ulong ret; |
2175 |
|
2176 |
val2 &= 0xffffffffUL;
|
2177 |
ret = helper_ld_asi(addr, asi, 4, 0); |
2178 |
ret &= 0xffffffffUL;
|
2179 |
if (val2 == ret) {
|
2180 |
helper_st_asi(addr, val1 & 0xffffffffUL, asi, 4); |
2181 |
} |
2182 |
return ret;
|
2183 |
} |
2184 |
|
2185 |
target_ulong helper_casx_asi(target_ulong addr, target_ulong val1, |
2186 |
target_ulong val2, uint32_t asi) |
2187 |
{ |
2188 |
target_ulong ret; |
2189 |
|
2190 |
ret = helper_ld_asi(addr, asi, 8, 0); |
2191 |
if (val2 == ret) {
|
2192 |
helper_st_asi(addr, val1, asi, 8);
|
2193 |
} |
2194 |
return ret;
|
2195 |
} |
2196 |
#endif /* TARGET_SPARC64 */ |
2197 |
|
2198 |
void helper_stdf(target_ulong addr, int mem_idx) |
2199 |
{ |
2200 |
helper_check_align(addr, 7);
|
2201 |
#if !defined(CONFIG_USER_ONLY)
|
2202 |
switch (mem_idx) {
|
2203 |
case MMU_USER_IDX:
|
2204 |
stfq_user(addr, DT0); |
2205 |
break;
|
2206 |
case MMU_KERNEL_IDX:
|
2207 |
stfq_kernel(addr, DT0); |
2208 |
break;
|
2209 |
#ifdef TARGET_SPARC64
|
2210 |
case MMU_HYPV_IDX:
|
2211 |
stfq_hypv(addr, DT0); |
2212 |
break;
|
2213 |
#endif
|
2214 |
default:
|
2215 |
DPRINTF_MMU("helper_stdf: need to check MMU idx %d\n", mem_idx);
|
2216 |
break;
|
2217 |
} |
2218 |
#else
|
2219 |
stfq_raw(address_mask(env, addr), DT0); |
2220 |
#endif
|
2221 |
} |
2222 |
|
2223 |
void helper_lddf(target_ulong addr, int mem_idx) |
2224 |
{ |
2225 |
helper_check_align(addr, 7);
|
2226 |
#if !defined(CONFIG_USER_ONLY)
|
2227 |
switch (mem_idx) {
|
2228 |
case MMU_USER_IDX:
|
2229 |
DT0 = ldfq_user(addr); |
2230 |
break;
|
2231 |
case MMU_KERNEL_IDX:
|
2232 |
DT0 = ldfq_kernel(addr); |
2233 |
break;
|
2234 |
#ifdef TARGET_SPARC64
|
2235 |
case MMU_HYPV_IDX:
|
2236 |
DT0 = ldfq_hypv(addr); |
2237 |
break;
|
2238 |
#endif
|
2239 |
default:
|
2240 |
DPRINTF_MMU("helper_lddf: need to check MMU idx %d\n", mem_idx);
|
2241 |
break;
|
2242 |
} |
2243 |
#else
|
2244 |
DT0 = ldfq_raw(address_mask(env, addr)); |
2245 |
#endif
|
2246 |
} |
2247 |
|
2248 |
void helper_ldqf(target_ulong addr, int mem_idx) |
2249 |
{ |
2250 |
/* XXX add 128 bit load */
|
2251 |
CPU_QuadU u; |
2252 |
|
2253 |
helper_check_align(addr, 7);
|
2254 |
#if !defined(CONFIG_USER_ONLY)
|
2255 |
switch (mem_idx) {
|
2256 |
case MMU_USER_IDX:
|
2257 |
u.ll.upper = ldq_user(addr); |
2258 |
u.ll.lower = ldq_user(addr + 8);
|
2259 |
QT0 = u.q; |
2260 |
break;
|
2261 |
case MMU_KERNEL_IDX:
|
2262 |
u.ll.upper = ldq_kernel(addr); |
2263 |
u.ll.lower = ldq_kernel(addr + 8);
|
2264 |
QT0 = u.q; |
2265 |
break;
|
2266 |
#ifdef TARGET_SPARC64
|
2267 |
case MMU_HYPV_IDX:
|
2268 |
u.ll.upper = ldq_hypv(addr); |
2269 |
u.ll.lower = ldq_hypv(addr + 8);
|
2270 |
QT0 = u.q; |
2271 |
break;
|
2272 |
#endif
|
2273 |
default:
|
2274 |
DPRINTF_MMU("helper_ldqf: need to check MMU idx %d\n", mem_idx);
|
2275 |
break;
|
2276 |
} |
2277 |
#else
|
2278 |
u.ll.upper = ldq_raw(address_mask(env, addr)); |
2279 |
u.ll.lower = ldq_raw(address_mask(env, addr + 8));
|
2280 |
QT0 = u.q; |
2281 |
#endif
|
2282 |
} |
2283 |
|
2284 |
void helper_stqf(target_ulong addr, int mem_idx) |
2285 |
{ |
2286 |
/* XXX add 128 bit store */
|
2287 |
CPU_QuadU u; |
2288 |
|
2289 |
helper_check_align(addr, 7);
|
2290 |
#if !defined(CONFIG_USER_ONLY)
|
2291 |
switch (mem_idx) {
|
2292 |
case MMU_USER_IDX:
|
2293 |
u.q = QT0; |
2294 |
stq_user(addr, u.ll.upper); |
2295 |
stq_user(addr + 8, u.ll.lower);
|
2296 |
break;
|
2297 |
case MMU_KERNEL_IDX:
|
2298 |
u.q = QT0; |
2299 |
stq_kernel(addr, u.ll.upper); |
2300 |
stq_kernel(addr + 8, u.ll.lower);
|
2301 |
break;
|
2302 |
#ifdef TARGET_SPARC64
|
2303 |
case MMU_HYPV_IDX:
|
2304 |
u.q = QT0; |
2305 |
stq_hypv(addr, u.ll.upper); |
2306 |
stq_hypv(addr + 8, u.ll.lower);
|
2307 |
break;
|
2308 |
#endif
|
2309 |
default:
|
2310 |
DPRINTF_MMU("helper_stqf: need to check MMU idx %d\n", mem_idx);
|
2311 |
break;
|
2312 |
} |
2313 |
#else
|
2314 |
u.q = QT0; |
2315 |
stq_raw(address_mask(env, addr), u.ll.upper); |
2316 |
stq_raw(address_mask(env, addr + 8), u.ll.lower);
|
2317 |
#endif
|
2318 |
} |
2319 |
|
2320 |
#if !defined(CONFIG_USER_ONLY)
|
2321 |
|
2322 |
static void do_unaligned_access(target_ulong addr, int is_write, int is_user, |
2323 |
void *retaddr);
|
2324 |
|
2325 |
#define MMUSUFFIX _mmu
|
2326 |
#define ALIGNED_ONLY
|
2327 |
|
2328 |
#define SHIFT 0 |
2329 |
#include "softmmu_template.h" |
2330 |
|
2331 |
#define SHIFT 1 |
2332 |
#include "softmmu_template.h" |
2333 |
|
2334 |
#define SHIFT 2 |
2335 |
#include "softmmu_template.h" |
2336 |
|
2337 |
#define SHIFT 3 |
2338 |
#include "softmmu_template.h" |
2339 |
|
2340 |
/* XXX: make it generic ? */
|
2341 |
static void cpu_restore_state2(void *retaddr) |
2342 |
{ |
2343 |
TranslationBlock *tb; |
2344 |
unsigned long pc; |
2345 |
|
2346 |
if (retaddr) {
|
2347 |
/* now we have a real cpu fault */
|
2348 |
pc = (unsigned long)retaddr; |
2349 |
tb = tb_find_pc(pc); |
2350 |
if (tb) {
|
2351 |
/* the PC is inside the translated code. It means that we have
|
2352 |
a virtual CPU fault */
|
2353 |
cpu_restore_state(tb, env, pc); |
2354 |
} |
2355 |
} |
2356 |
} |
2357 |
|
2358 |
static void do_unaligned_access(target_ulong addr, int is_write, int is_user, |
2359 |
void *retaddr)
|
2360 |
{ |
2361 |
#ifdef DEBUG_UNALIGNED
|
2362 |
printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx |
2363 |
"\n", addr, env->pc);
|
2364 |
#endif
|
2365 |
cpu_restore_state2(retaddr); |
2366 |
helper_raise_exception(env, TT_UNALIGNED); |
2367 |
} |
2368 |
|
2369 |
/* try to fill the TLB and return an exception if error. If retaddr is
|
2370 |
NULL, it means that the function was called in C code (i.e. not
|
2371 |
from generated code or from helper.c) */
|
2372 |
/* XXX: fix it to restore all registers */
|
2373 |
void tlb_fill(CPUState *env1, target_ulong addr, int is_write, int mmu_idx, |
2374 |
void *retaddr)
|
2375 |
{ |
2376 |
int ret;
|
2377 |
CPUState *saved_env; |
2378 |
|
2379 |
saved_env = env; |
2380 |
env = env1; |
2381 |
|
2382 |
ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, mmu_idx); |
2383 |
if (ret) {
|
2384 |
cpu_restore_state2(retaddr); |
2385 |
cpu_loop_exit(env); |
2386 |
} |
2387 |
env = saved_env; |
2388 |
} |
2389 |
|
2390 |
#endif /* !CONFIG_USER_ONLY */ |
2391 |
|
2392 |
#ifndef TARGET_SPARC64
|
2393 |
#if !defined(CONFIG_USER_ONLY)
|
2394 |
static void do_unassigned_access(target_phys_addr_t addr, int is_write, |
2395 |
int is_exec, int is_asi, int size) |
2396 |
{ |
2397 |
int fault_type;
|
2398 |
|
2399 |
#ifdef DEBUG_UNASSIGNED
|
2400 |
if (is_asi) {
|
2401 |
printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
|
2402 |
" asi 0x%02x from " TARGET_FMT_lx "\n", |
2403 |
is_exec ? "exec" : is_write ? "write" : "read", size, |
2404 |
size == 1 ? "" : "s", addr, is_asi, env->pc); |
2405 |
} else {
|
2406 |
printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
|
2407 |
" from " TARGET_FMT_lx "\n", |
2408 |
is_exec ? "exec" : is_write ? "write" : "read", size, |
2409 |
size == 1 ? "" : "s", addr, env->pc); |
2410 |
} |
2411 |
#endif
|
2412 |
/* Don't overwrite translation and access faults */
|
2413 |
fault_type = (env->mmuregs[3] & 0x1c) >> 2; |
2414 |
if ((fault_type > 4) || (fault_type == 0)) { |
2415 |
env->mmuregs[3] = 0; /* Fault status register */ |
2416 |
if (is_asi) {
|
2417 |
env->mmuregs[3] |= 1 << 16; |
2418 |
} |
2419 |
if (env->psrs) {
|
2420 |
env->mmuregs[3] |= 1 << 5; |
2421 |
} |
2422 |
if (is_exec) {
|
2423 |
env->mmuregs[3] |= 1 << 6; |
2424 |
} |
2425 |
if (is_write) {
|
2426 |
env->mmuregs[3] |= 1 << 7; |
2427 |
} |
2428 |
env->mmuregs[3] |= (5 << 2) | 2; |
2429 |
/* SuperSPARC will never place instruction fault addresses in the FAR */
|
2430 |
if (!is_exec) {
|
2431 |
env->mmuregs[4] = addr; /* Fault address register */ |
2432 |
} |
2433 |
} |
2434 |
/* overflow (same type fault was not read before another fault) */
|
2435 |
if (fault_type == ((env->mmuregs[3] & 0x1c)) >> 2) { |
2436 |
env->mmuregs[3] |= 1; |
2437 |
} |
2438 |
|
2439 |
if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) { |
2440 |
if (is_exec) {
|
2441 |
helper_raise_exception(env, TT_CODE_ACCESS); |
2442 |
} else {
|
2443 |
helper_raise_exception(env, TT_DATA_ACCESS); |
2444 |
} |
2445 |
} |
2446 |
|
2447 |
/* flush neverland mappings created during no-fault mode,
|
2448 |
so the sequential MMU faults report proper fault types */
|
2449 |
if (env->mmuregs[0] & MMU_NF) { |
2450 |
tlb_flush(env, 1);
|
2451 |
} |
2452 |
} |
2453 |
#endif
|
2454 |
#else
|
2455 |
#if defined(CONFIG_USER_ONLY)
|
2456 |
static void do_unassigned_access(target_ulong addr, int is_write, int is_exec, |
2457 |
int is_asi, int size) |
2458 |
#else
|
2459 |
static void do_unassigned_access(target_phys_addr_t addr, int is_write, |
2460 |
int is_exec, int is_asi, int size) |
2461 |
#endif
|
2462 |
{ |
2463 |
#ifdef DEBUG_UNASSIGNED
|
2464 |
printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx |
2465 |
"\n", addr, env->pc);
|
2466 |
#endif
|
2467 |
|
2468 |
if (is_exec) {
|
2469 |
helper_raise_exception(env, TT_CODE_ACCESS); |
2470 |
} else {
|
2471 |
helper_raise_exception(env, TT_DATA_ACCESS); |
2472 |
} |
2473 |
} |
2474 |
#endif
|
2475 |
|
2476 |
#if !defined(CONFIG_USER_ONLY)
|
2477 |
void cpu_unassigned_access(CPUState *env1, target_phys_addr_t addr,
|
2478 |
int is_write, int is_exec, int is_asi, int size) |
2479 |
{ |
2480 |
CPUState *saved_env; |
2481 |
|
2482 |
saved_env = env; |
2483 |
env = env1; |
2484 |
/* Ignore unassigned accesses outside of CPU context */
|
2485 |
if (env1) {
|
2486 |
do_unassigned_access(addr, is_write, is_exec, is_asi, size); |
2487 |
} |
2488 |
env = saved_env; |
2489 |
} |
2490 |
#endif
|