Archipelago » qemu

#include "cpu.h"

#include "dyngen-exec.h"

#include "helper.h"

#if !defined(CONFIG_USER_ONLY)

#include "softmmu_exec.h"

#endif

//#define DEBUG_MMU

//#define DEBUG_MXCC

//#define DEBUG_UNALIGNED

//#define DEBUG_UNASSIGNED

//#define DEBUG_ASI

//#define DEBUG_CACHE_CONTROL

#ifdef DEBUG_MMU

#define DPRINTF_MMU(fmt, ...)                                   \

    do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0)

#else

#define DPRINTF_MMU(fmt, ...) do {} while (0)

#endif

#ifdef DEBUG_MXCC

#define DPRINTF_MXCC(fmt, ...)                                  \

    do { printf("MXCC: " fmt , ## __VA_ARGS__); } while (0)

#else

#define DPRINTF_MXCC(fmt, ...) do {} while (0)

#endif

#ifdef DEBUG_ASI

#define DPRINTF_ASI(fmt, ...)                                   \

    do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0)

#endif

#ifdef DEBUG_CACHE_CONTROL

#define DPRINTF_CACHE_CONTROL(fmt, ...)                                 \

    do { printf("CACHE_CONTROL: " fmt , ## __VA_ARGS__); } while (0)

#else

#define DPRINTF_CACHE_CONTROL(fmt, ...) do {} while (0)

#endif

#ifdef TARGET_SPARC64

#ifndef TARGET_ABI32

#define AM_CHECK(env1) ((env1)->pstate & PS_AM)

#else

#define AM_CHECK(env1) (1)

#endif

#endif

#define DT0 (env->dt0)

#define DT1 (env->dt1)

#define QT0 (env->qt0)

#define QT1 (env->qt1)

#if !defined(CONFIG_USER_ONLY)

static void do_unassigned_access(target_phys_addr_t addr, int is_write,

                                 int is_exec, int is_asi, int size);

#else

#ifdef TARGET_SPARC64

static void do_unassigned_access(target_ulong addr, int is_write, int is_exec,

                                 int is_asi, int size);

#endif

#endif

#if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)

/* Calculates TSB pointer value for fault page size 8k or 64k */

static uint64_t ultrasparc_tsb_pointer(uint64_t tsb_register,

                                       uint64_t tag_access_register,

                                       int page_size)

{

    uint64_t tsb_base = tsb_register & ~0x1fffULL;

    int tsb_split = (tsb_register & 0x1000ULL) ? 1 : 0;

    int tsb_size  = tsb_register & 0xf;

    /* discard lower 13 bits which hold tag access context */

    uint64_t tag_access_va = tag_access_register & ~0x1fffULL;

    /* now reorder bits */

    uint64_t tsb_base_mask = ~0x1fffULL;

    uint64_t va = tag_access_va;

    /* move va bits to correct position */

    if (page_size == 8*1024) {

        va >>= 9;

    } else if (page_size == 64*1024) {

        va >>= 12;

    }

    if (tsb_size) {

        tsb_base_mask <<= tsb_size;

    }

    /* calculate tsb_base mask and adjust va if split is in use */

    if (tsb_split) {

        if (page_size == 8*1024) {

            va &= ~(1ULL << (13 + tsb_size));

        } else if (page_size == 64*1024) {

            va |= (1ULL << (13 + tsb_size));

        }

        tsb_base_mask <<= 1;

    }

    return ((tsb_base & tsb_base_mask) | (va & ~tsb_base_mask)) & ~0xfULL;

}

/* Calculates tag target register value by reordering bits

   in tag access register */

static uint64_t ultrasparc_tag_target(uint64_t tag_access_register)

{

    return ((tag_access_register & 0x1fff) << 48) | (tag_access_register >> 22);

}

static void replace_tlb_entry(SparcTLBEntry *tlb,

                              uint64_t tlb_tag, uint64_t tlb_tte,

                              CPUState *env1)

{

    target_ulong mask, size, va, offset;

    /* flush page range if translation is valid */

    if (TTE_IS_VALID(tlb->tte)) {

        mask = 0xffffffffffffe000ULL;

        mask <<= 3 * ((tlb->tte >> 61) & 3);

        size = ~mask + 1;

        va = tlb->tag & mask;

        for (offset = 0; offset < size; offset += TARGET_PAGE_SIZE) {

            tlb_flush_page(env1, va + offset);

        }

    }

    tlb->tag = tlb_tag;

    tlb->tte = tlb_tte;

}

static void demap_tlb(SparcTLBEntry *tlb, target_ulong demap_addr,

                      const char *strmmu, CPUState *env1)

{

    unsigned int i;

    target_ulong mask;

    uint64_t context;

    int is_demap_context = (demap_addr >> 6) & 1;

    /* demap context */

    switch ((demap_addr >> 4) & 3) {

    case 0: /* primary */

        context = env1->dmmu.mmu_primary_context;

        break;

    case 1: /* secondary */

        context = env1->dmmu.mmu_secondary_context;

        break;

    case 2: /* nucleus */

        context = 0;

        break;

    case 3: /* reserved */

    default:

        return;

    }

    for (i = 0; i < 64; i++) {

        if (TTE_IS_VALID(tlb[i].tte)) {

            if (is_demap_context) {

                /* will remove non-global entries matching context value */

                if (TTE_IS_GLOBAL(tlb[i].tte) ||

                    !tlb_compare_context(&tlb[i], context)) {

                    continue;

                }

            } else {

                /* demap page

                   will remove any entry matching VA */

                mask = 0xffffffffffffe000ULL;

                mask <<= 3 * ((tlb[i].tte >> 61) & 3);

                if (!compare_masked(demap_addr, tlb[i].tag, mask)) {

                    continue;

                }

                /* entry should be global or matching context value */

                if (!TTE_IS_GLOBAL(tlb[i].tte) &&

                    !tlb_compare_context(&tlb[i], context)) {

                    continue;

                }

            }

            replace_tlb_entry(&tlb[i], 0, 0, env1);

#ifdef DEBUG_MMU

            DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu, i);

            dump_mmu(stdout, fprintf, env1);

#endif

        }

    }

}

static void replace_tlb_1bit_lru(SparcTLBEntry *tlb,

                                 uint64_t tlb_tag, uint64_t tlb_tte,

                                 const char *strmmu, CPUState *env1)

{

    unsigned int i, replace_used;

    /* Try replacing invalid entry */

    for (i = 0; i < 64; i++) {

        if (!TTE_IS_VALID(tlb[i].tte)) {

            replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);

#ifdef DEBUG_MMU

            DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu, i);

            dump_mmu(stdout, fprintf, env1);

#endif

            return;

        }

    }

    /* All entries are valid, try replacing unlocked entry */

    for (replace_used = 0; replace_used < 2; ++replace_used) {

        /* Used entries are not replaced on first pass */

        for (i = 0; i < 64; i++) {

            if (!TTE_IS_LOCKED(tlb[i].tte) && !TTE_IS_USED(tlb[i].tte)) {

                replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);

#ifdef DEBUG_MMU

                DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n",

                            strmmu, (replace_used ? "used" : "unused"), i);

                dump_mmu(stdout, fprintf, env1);

#endif

                return;

            }

        }

        /* Now reset used bit and search for unused entries again */

        for (i = 0; i < 64; i++) {

            TTE_SET_UNUSED(tlb[i].tte);

        }

    }

#ifdef DEBUG_MMU

    DPRINTF_MMU("%s lru replacement failed: no entries available\n", strmmu);

#endif

    /* error state? */

}

#endif

static inline target_ulong address_mask(CPUState *env1, target_ulong addr)

{

#ifdef TARGET_SPARC64

    if (AM_CHECK(env1)) {

        addr &= 0xffffffffULL;

    }

#endif

    return addr;

}

/* returns true if access using this ASI is to have address translated by MMU

   otherwise access is to raw physical address */

static inline int is_translating_asi(int asi)

{

#ifdef TARGET_SPARC64

    /* Ultrasparc IIi translating asi

       - note this list is defined by cpu implementation

    */

    switch (asi) {

    case 0x04 ... 0x11:

    case 0x16 ... 0x19:

    case 0x1E ... 0x1F:

    case 0x24 ... 0x2C:

    case 0x70 ... 0x73:

    case 0x78 ... 0x79:

    case 0x80 ... 0xFF:

        return 1;

    default:

        return 0;

    }

#else

    /* TODO: check sparc32 bits */

    return 0;

#endif

}

static inline target_ulong asi_address_mask(CPUState *env1,

                                            int asi, target_ulong addr)

{

    if (is_translating_asi(asi)) {

        return address_mask(env, addr);

    } else {

        return addr;

    }

}

void helper_check_align(target_ulong addr, uint32_t align)

{

    if (addr & align) {

#ifdef DEBUG_UNALIGNED

        printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx

               "\n", addr, env->pc);

#endif

        helper_raise_exception(env, TT_UNALIGNED);

    }

}

#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) &&   \

    defined(DEBUG_MXCC)

static void dump_mxcc(CPUState *env)

{

    printf("mxccdata: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64

           "\n",

           env->mxccdata[0], env->mxccdata[1],

           env->mxccdata[2], env->mxccdata[3]);

    printf("mxccregs: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64

           "\n"

           "          %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64

           "\n",

           env->mxccregs[0], env->mxccregs[1],

           env->mxccregs[2], env->mxccregs[3],

           env->mxccregs[4], env->mxccregs[5],

           env->mxccregs[6], env->mxccregs[7]);

}

#endif

#if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY))     \

    && defined(DEBUG_ASI)

static void dump_asi(const char *txt, target_ulong addr, int asi, int size,

                     uint64_t r1)

{

    switch (size) {

    case 1:

        DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %02" PRIx64 "\n", txt,

                    addr, asi, r1 & 0xff);

        break;

    case 2:

        DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %04" PRIx64 "\n", txt,

                    addr, asi, r1 & 0xffff);

        break;

    case 4:

        DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %08" PRIx64 "\n", txt,

                    addr, asi, r1 & 0xffffffff);

        break;

    case 8:

        DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %016" PRIx64 "\n", txt,

                    addr, asi, r1);

        break;

    }

}

#endif

#ifndef TARGET_SPARC64

#ifndef CONFIG_USER_ONLY

/* Leon3 cache control */

static void leon3_cache_control_st(target_ulong addr, uint64_t val, int size)

{

    DPRINTF_CACHE_CONTROL("st addr:%08x, val:%" PRIx64 ", size:%d\n",

                          addr, val, size);

    if (size != 4) {

        DPRINTF_CACHE_CONTROL("32bits only\n");

        return;

    }

    switch (addr) {

    case 0x00:              /* Cache control */

        /* These values must always be read as zeros */

        val &= ~CACHE_CTRL_FD;

        val &= ~CACHE_CTRL_FI;

        val &= ~CACHE_CTRL_IB;

        val &= ~CACHE_CTRL_IP;

        val &= ~CACHE_CTRL_DP;

        env->cache_control = val;

        break;

    case 0x04:              /* Instruction cache configuration */

    case 0x08:              /* Data cache configuration */

        /* Read Only */

        break;

    default:

        DPRINTF_CACHE_CONTROL("write unknown register %08x\n", addr);

        break;

    };

}

static uint64_t leon3_cache_control_ld(target_ulong addr, int size)

{

    uint64_t ret = 0;

    if (size != 4) {

        DPRINTF_CACHE_CONTROL("32bits only\n");

        return 0;

    }

    switch (addr) {

    case 0x00:              /* Cache control */

        ret = env->cache_control;

        break;

        /* Configuration registers are read and only always keep those

           predefined values */

    case 0x04:              /* Instruction cache configuration */

        ret = 0x10220000;

        break;

    case 0x08:              /* Data cache configuration */

        ret = 0x18220000;

        break;

    default:

        DPRINTF_CACHE_CONTROL("read unknown register %08x\n", addr);

        break;

    };

    DPRINTF_CACHE_CONTROL("ld addr:%08x, ret:0x%" PRIx64 ", size:%d\n",

                          addr, ret, size);

    return ret;

}

uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)

{

    uint64_t ret = 0;

#if defined(DEBUG_MXCC) || defined(DEBUG_ASI)

    uint32_t last_addr = addr;

#endif

    helper_check_align(addr, size - 1);

    switch (asi) {

    case 2: /* SuperSparc MXCC registers and Leon3 cache control */

        switch (addr) {

        case 0x00:          /* Leon3 Cache Control */

        case 0x08:          /* Leon3 Instruction Cache config */

        case 0x0C:          /* Leon3 Date Cache config */

            if (env->def->features & CPU_FEATURE_CACHE_CTRL) {

                ret = leon3_cache_control_ld(addr, size);

            }

            break;

        case 0x01c00a00: /* MXCC control register */

            if (size == 8) {

                ret = env->mxccregs[3];

            } else {

                DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,

                             size);

            }

            break;

        case 0x01c00a04: /* MXCC control register */

            if (size == 4) {

                ret = env->mxccregs[3];

            } else {

                DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,

                             size);

            }

            break;

        case 0x01c00c00: /* Module reset register */

            if (size == 8) {

                ret = env->mxccregs[5];

                /* should we do something here? */

            } else {

                DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,

                             size);

            }

            break;

        case 0x01c00f00: /* MBus port address register */

            if (size == 8) {

                ret = env->mxccregs[7];

            } else {

                DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,

                             size);

            }

            break;

        default:

            DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr,

                         size);

            break;

        }

        DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "

                     "addr = %08x -> ret = %" PRIx64 ","

                     "addr = %08x\n", asi, size, sign, last_addr, ret, addr);

#ifdef DEBUG_MXCC

        dump_mxcc(env);

#endif

        break;

    case 3: /* MMU probe */

        {

            int mmulev;

            mmulev = (addr >> 8) & 15;

            if (mmulev > 4) {

                ret = 0;

            } else {

                ret = mmu_probe(env, addr, mmulev);

            }

            DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64 "\n",

                        addr, mmulev, ret);

        }

        break;

    case 4: /* read MMU regs */

        {

            int reg = (addr >> 8) & 0x1f;

            ret = env->mmuregs[reg];

            if (reg == 3) { /* Fault status cleared on read */

                env->mmuregs[3] = 0;

            } else if (reg == 0x13) { /* Fault status read */

                ret = env->mmuregs[3];

            } else if (reg == 0x14) { /* Fault address read */

                ret = env->mmuregs[4];

            }

            DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64 "\n", reg, ret);

        }

        break;

    case 5: /* Turbosparc ITLB Diagnostic */

    case 6: /* Turbosparc DTLB Diagnostic */

    case 7: /* Turbosparc IOTLB Diagnostic */

        break;

    case 9: /* Supervisor code access */

        switch (size) {

        case 1:

            ret = ldub_code(addr);

            break;

        case 2:

            ret = lduw_code(addr);

            break;

        default:

        case 4:

            ret = ldl_code(addr);

            break;

        case 8:

            ret = ldq_code(addr);

            break;

        }

        break;

    case 0xa: /* User data access */

        switch (size) {

        case 1:

            ret = ldub_user(addr);

            break;

        case 2:

            ret = lduw_user(addr);

            break;

        default:

        case 4:

            ret = ldl_user(addr);

            break;

        case 8:

            ret = ldq_user(addr);

            break;

        }

        break;

    case 0xb: /* Supervisor data access */

        switch (size) {

        case 1:

            ret = ldub_kernel(addr);

            break;

        case 2:

            ret = lduw_kernel(addr);

            break;

        default:

        case 4:

            ret = ldl_kernel(addr);

            break;

        case 8:

            ret = ldq_kernel(addr);

            break;

        }

        break;

    case 0xc: /* I-cache tag */

    case 0xd: /* I-cache data */

    case 0xe: /* D-cache tag */

    case 0xf: /* D-cache data */

        break;

    case 0x20: /* MMU passthrough */

        switch (size) {

        case 1:

            ret = ldub_phys(addr);

            break;

        case 2:

            ret = lduw_phys(addr);

            break;

        default:

        case 4:

            ret = ldl_phys(addr);

            break;

        case 8:

            ret = ldq_phys(addr);

            break;

        }

        break;

    case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */

        switch (size) {

        case 1:

            ret = ldub_phys((target_phys_addr_t)addr

                            | ((target_phys_addr_t)(asi & 0xf) << 32));

            break;

        case 2:

            ret = lduw_phys((target_phys_addr_t)addr

                            | ((target_phys_addr_t)(asi & 0xf) << 32));

            break;

        default:

        case 4:

            ret = ldl_phys((target_phys_addr_t)addr

                           | ((target_phys_addr_t)(asi & 0xf) << 32));

            break;

        case 8:

            ret = ldq_phys((target_phys_addr_t)addr

                           | ((target_phys_addr_t)(asi & 0xf) << 32));

            break;

        }

        break;

    case 0x30: /* Turbosparc secondary cache diagnostic */

    case 0x31: /* Turbosparc RAM snoop */

    case 0x32: /* Turbosparc page table descriptor diagnostic */

    case 0x39: /* data cache diagnostic register */

        ret = 0;

        break;

    case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */

        {

            int reg = (addr >> 8) & 3;

            switch (reg) {

            case 0: /* Breakpoint Value (Addr) */

                ret = env->mmubpregs[reg];

                break;

            case 1: /* Breakpoint Mask */

                ret = env->mmubpregs[reg];

                break;

            case 2: /* Breakpoint Control */

                ret = env->mmubpregs[reg];

                break;

            case 3: /* Breakpoint Status */

                ret = env->mmubpregs[reg];

                env->mmubpregs[reg] = 0ULL;

                break;

            }

            DPRINTF_MMU("read breakpoint reg[%d] 0x%016" PRIx64 "\n", reg,

                        ret);

        }

        break;

    case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */

        ret = env->mmubpctrv;

        break;

    case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */

        ret = env->mmubpctrc;

        break;

    case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */

        ret = env->mmubpctrs;

        break;

    case 0x4c: /* SuperSPARC MMU Breakpoint Action */

        ret = env->mmubpaction;

        break;

    case 8: /* User code access, XXX */

    default:

        do_unassigned_access(addr, 0, 0, asi, size);

        ret = 0;

        break;

    }

    if (sign) {

        switch (size) {

        case 1:

            ret = (int8_t) ret;

            break;

        case 2:

            ret = (int16_t) ret;

            break;

        case 4:

            ret = (int32_t) ret;

            break;

        default:

            break;

        }

    }

#ifdef DEBUG_ASI

    dump_asi("read ", last_addr, asi, size, ret);

#endif

    return ret;

}

void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size)

{

    helper_check_align(addr, size - 1);

    switch (asi) {

    case 2: /* SuperSparc MXCC registers and Leon3 cache control */

        switch (addr) {

        case 0x00:          /* Leon3 Cache Control */

        case 0x08:          /* Leon3 Instruction Cache config */

        case 0x0C:          /* Leon3 Date Cache config */

            if (env->def->features & CPU_FEATURE_CACHE_CTRL) {

                leon3_cache_control_st(addr, val, size);

            }

            break;

        case 0x01c00000: /* MXCC stream data register 0 */

            if (size == 8) {

                env->mxccdata[0] = val;

            } else {

                DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,

                             size);

            }

            break;

        case 0x01c00008: /* MXCC stream data register 1 */

            if (size == 8) {

                env->mxccdata[1] = val;

            } else {

                DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,

                             size);

            }

            break;

        case 0x01c00010: /* MXCC stream data register 2 */

            if (size == 8) {

                env->mxccdata[2] = val;

            } else {

                DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,

                             size);

            }

            break;

        case 0x01c00018: /* MXCC stream data register 3 */

            if (size == 8) {

                env->mxccdata[3] = val;

            } else {

                DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,

                             size);

            }

            break;

        case 0x01c00100: /* MXCC stream source */

            if (size == 8) {

                env->mxccregs[0] = val;

            } else {

                DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,

                             size);

            }

            env->mxccdata[0] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +

                                        0);

            env->mxccdata[1] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +

                                        8);

            env->mxccdata[2] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +

                                        16);

            env->mxccdata[3] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +

                                        24);

            break;

        case 0x01c00200: /* MXCC stream destination */

            if (size == 8) {

                env->mxccregs[1] = val;

            } else {

                DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,

                             size);

            }

            stq_phys((env->mxccregs[1] & 0xffffffffULL) +  0,

                     env->mxccdata[0]);

            stq_phys((env->mxccregs[1] & 0xffffffffULL) +  8,

                     env->mxccdata[1]);

            stq_phys((env->mxccregs[1] & 0xffffffffULL) + 16,

                     env->mxccdata[2]);

            stq_phys((env->mxccregs[1] & 0xffffffffULL) + 24,

                     env->mxccdata[3]);

            break;

        case 0x01c00a00: /* MXCC control register */

            if (size == 8) {

                env->mxccregs[3] = val;

            } else {

                DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,

                             size);

            }

            break;

        case 0x01c00a04: /* MXCC control register */

            if (size == 4) {

                env->mxccregs[3] = (env->mxccregs[3] & 0xffffffff00000000ULL)

                    | val;

            } else {

                DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,

                             size);

            }

            break;

        case 0x01c00e00: /* MXCC error register  */

            /* writing a 1 bit clears the error */

            if (size == 8) {

                env->mxccregs[6] &= ~val;

            } else {

                DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,

                             size);

            }

            break;

        case 0x01c00f00: /* MBus port address register */

            if (size == 8) {

                env->mxccregs[7] = val;

            } else {

                DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,

                             size);

            }

            break;

        default:

            DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr,

                         size);

            break;

        }

        DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64 "\n",

                     asi, size, addr, val);

#ifdef DEBUG_MXCC

        dump_mxcc(env);

#endif

        break;

    case 3: /* MMU flush */

        {

            int mmulev;

            mmulev = (addr >> 8) & 15;

            DPRINTF_MMU("mmu flush level %d\n", mmulev);

            switch (mmulev) {

            case 0: /* flush page */

                tlb_flush_page(env, addr & 0xfffff000);

                break;

            case 1: /* flush segment (256k) */

            case 2: /* flush region (16M) */

            case 3: /* flush context (4G) */

            case 4: /* flush entire */

                tlb_flush(env, 1);

                break;

            default:

                break;

            }

#ifdef DEBUG_MMU

            dump_mmu(stdout, fprintf, env);

#endif

        }

        break;

    case 4: /* write MMU regs */

        {

            int reg = (addr >> 8) & 0x1f;

            uint32_t oldreg;

            oldreg = env->mmuregs[reg];

            switch (reg) {

            case 0: /* Control Register */

                env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) |

                    (val & 0x00ffffff);

                /* Mappings generated during no-fault mode or MMU

                   disabled mode are invalid in normal mode */

                if ((oldreg & (MMU_E | MMU_NF | env->def->mmu_bm)) !=