Revision 7c60cc4b
| b/target-sparc/cpu.h | ||
|---|---|---|
| 188 | 188 |
typedef struct CPUSPARCState {
|
| 189 | 189 |
target_ulong gregs[8]; /* general registers */ |
| 190 | 190 |
target_ulong *regwptr; /* pointer to current register window */ |
| 191 |
float32 fpr[TARGET_FPREGS]; /* floating point registers */ |
|
| 192 | 191 |
target_ulong pc; /* program counter */ |
| 193 | 192 |
target_ulong npc; /* next program counter */ |
| 194 | 193 |
target_ulong y; /* multiply/divide register */ |
| ... | ... | |
| 197 | 196 |
target_ulong cc_src, cc_src2; |
| 198 | 197 |
target_ulong cc_dst; |
| 199 | 198 |
|
| 199 |
target_ulong t0, t1; /* temporaries live across basic blocks */ |
|
| 200 |
target_ulong cond; /* conditional branch result (XXX: save it in a |
|
| 201 |
temporary register when possible) */ |
|
| 202 |
|
|
| 200 | 203 |
uint32_t psr; /* processor state register */ |
| 201 | 204 |
target_ulong fsr; /* FPU state register */ |
| 205 |
float32 fpr[TARGET_FPREGS]; /* floating point registers */ |
|
| 202 | 206 |
uint32_t cwp; /* index of current register window (extracted |
| 203 | 207 |
from PSR) */ |
| 204 | 208 |
uint32_t wim; /* window invalid mask */ |
| ... | ... | |
| 271 | 275 |
uint64_t hpstate, htstate[MAXTL], hintp, htba, hver, hstick_cmpr, ssr; |
| 272 | 276 |
void *hstick; // UA 2005 |
| 273 | 277 |
#endif |
| 274 |
target_ulong t1, t2; |
|
| 275 | 278 |
uint32_t features; |
| 276 | 279 |
} CPUSPARCState; |
| 277 | 280 |
|
| b/target-sparc/exec.h | ||
|---|---|---|
| 4 | 4 |
#include "dyngen-exec.h" |
| 5 | 5 |
|
| 6 | 6 |
register struct CPUSPARCState *env asm(AREG0); |
| 7 |
|
|
| 8 |
#ifdef TARGET_SPARC64 |
|
| 9 |
#define T0 (env->t0) |
|
| 10 |
#define T2 (env->t2) |
|
| 11 | 7 |
#define REGWPTR env->regwptr |
| 12 |
#else |
|
| 13 |
register uint32_t T0 asm(AREG1); |
|
| 14 |
|
|
| 15 |
#undef REG_REGWPTR // Broken |
|
| 16 |
#ifdef REG_REGWPTR |
|
| 17 |
#if defined(__sparc__) |
|
| 18 |
register uint32_t *REGWPTR asm(AREG4); |
|
| 19 |
#else |
|
| 20 |
register uint32_t *REGWPTR asm(AREG3); |
|
| 21 |
#endif |
|
| 22 |
#define reg_REGWPTR |
|
| 23 |
|
|
| 24 |
#ifdef AREG4 |
|
| 25 |
register uint32_t T2 asm(AREG4); |
|
| 26 |
#define reg_T2 |
|
| 27 |
#else |
|
| 28 |
#define T2 (env->t2) |
|
| 29 |
#endif |
|
| 30 |
|
|
| 31 |
#else |
|
| 32 |
#define REGWPTR env->regwptr |
|
| 33 |
register uint32_t T2 asm(AREG3); |
|
| 34 |
#endif |
|
| 35 |
#define reg_T2 |
|
| 36 |
#endif |
|
| 37 | 8 |
|
| 38 | 9 |
#define FT0 (env->ft0) |
| 39 | 10 |
#define FT1 (env->ft1) |
| b/target-sparc/op_helper.c | ||
|---|---|---|
| 2189 | 2189 |
#define ADDR(x) (x) |
| 2190 | 2190 |
#endif |
| 2191 | 2191 |
|
| 2192 |
#ifdef __i386__ |
|
| 2193 |
void helper_std_i386(target_ulong addr, int mem_idx) |
|
| 2194 |
{
|
|
| 2195 |
uint64_t tmp = ((uint64_t)env->t1 << 32) | (uint64_t)(env->t2 & 0xffffffff); |
|
| 2196 |
|
|
| 2197 |
#if !defined(CONFIG_USER_ONLY) |
|
| 2198 |
switch (mem_idx) {
|
|
| 2199 |
case 0: |
|
| 2200 |
stq_user(ADDR(addr), tmp); |
|
| 2201 |
break; |
|
| 2202 |
case 1: |
|
| 2203 |
stq_kernel(ADDR(addr), tmp); |
|
| 2204 |
break; |
|
| 2205 |
#ifdef TARGET_SPARC64 |
|
| 2206 |
case 2: |
|
| 2207 |
stq_hypv(ADDR(addr), tmp); |
|
| 2208 |
break; |
|
| 2209 |
#endif |
|
| 2210 |
default: |
|
| 2211 |
break; |
|
| 2212 |
} |
|
| 2213 |
#else |
|
| 2214 |
stq_raw(ADDR(addr), tmp); |
|
| 2215 |
#endif |
|
| 2216 |
} |
|
| 2217 |
#endif /* __i386__ */ |
|
| 2218 |
|
|
| 2219 | 2192 |
void helper_stdf(target_ulong addr, int mem_idx) |
| 2220 | 2193 |
{
|
| 2221 | 2194 |
#if !defined(CONFIG_USER_ONLY) |
| ... | ... | |
| 2894 | 2867 |
if (tb) {
|
| 2895 | 2868 |
/* the PC is inside the translated code. It means that we have |
| 2896 | 2869 |
a virtual CPU fault */ |
| 2897 |
cpu_restore_state(tb, env, pc, (void *)T2);
|
|
| 2870 |
cpu_restore_state(tb, env, pc, (void *)env->cond);
|
|
| 2898 | 2871 |
} |
| 2899 | 2872 |
} |
| 2900 | 2873 |
cpu_loop_exit(); |
| b/target-sparc/translate.c | ||
|---|---|---|
| 46 | 46 |
according to jump_pc[T2] */ |
| 47 | 47 |
|
| 48 | 48 |
/* global register indexes */ |
| 49 |
static TCGv cpu_env, cpu_T[3], cpu_regwptr, cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
|
|
| 49 |
static TCGv cpu_env, cpu_T[2], cpu_regwptr, cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
|
|
| 50 | 50 |
static TCGv cpu_psr, cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8]; |
| 51 | 51 |
static TCGv cpu_cond, cpu_src1, cpu_src2, cpu_dst, cpu_addr, cpu_val; |
| 52 | 52 |
#ifdef TARGET_SPARC64 |
| ... | ... | |
| 4223 | 4223 |
tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7)); |
| 4224 | 4224 |
r_low = tcg_temp_new(TCG_TYPE_I32); |
| 4225 | 4225 |
gen_movl_reg_TN(rd + 1, r_low); |
| 4226 |
#ifndef __i386__ |
|
| 4227 | 4226 |
tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, cpu_val, |
| 4228 | 4227 |
r_low); |
| 4229 | 4228 |
tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx); |
| 4230 |
#else /* __i386__ */ |
|
| 4231 |
tcg_gen_st_tl(cpu_val, cpu_env, offsetof(CPUState, t1)); |
|
| 4232 |
tcg_gen_st_tl(r_low, cpu_env, offsetof(CPUState, t2)); |
|
| 4233 |
tcg_gen_helper_0_2(helper_std_i386, cpu_addr, |
|
| 4234 |
tcg_const_i32(dc->mem_idx)); |
|
| 4235 |
#endif /* __i386__ */ |
|
| 4236 | 4229 |
} |
| 4237 | 4230 |
break; |
| 4238 | 4231 |
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) |
| ... | ... | |
| 4475 | 4468 |
cpu_tmp32 = tcg_temp_new(TCG_TYPE_I32); |
| 4476 | 4469 |
cpu_tmp64 = tcg_temp_new(TCG_TYPE_I64); |
| 4477 | 4470 |
|
| 4478 |
cpu_cond = cpu_T[2]; |
|
| 4479 |
|
|
| 4480 | 4471 |
do {
|
| 4481 | 4472 |
if (env->nb_breakpoints > 0) {
|
| 4482 | 4473 |
for(j = 0; j < env->nb_breakpoints; j++) {
|
| ... | ... | |
| 4599 | 4590 |
cpu_regwptr = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0, |
| 4600 | 4591 |
offsetof(CPUState, regwptr), |
| 4601 | 4592 |
"regwptr"); |
| 4602 |
//#if TARGET_LONG_BITS > HOST_LONG_BITS |
|
| 4603 | 4593 |
#ifdef TARGET_SPARC64 |
| 4604 |
cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL, |
|
| 4605 |
TCG_AREG0, offsetof(CPUState, t0), "T0"); |
|
| 4606 |
cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL, |
|
| 4607 |
TCG_AREG0, offsetof(CPUState, t1), "T1"); |
|
| 4608 |
cpu_T[2] = tcg_global_mem_new(TCG_TYPE_TL, |
|
| 4609 |
TCG_AREG0, offsetof(CPUState, t2), "T2"); |
|
| 4610 | 4594 |
cpu_xcc = tcg_global_mem_new(TCG_TYPE_I32, |
| 4611 | 4595 |
TCG_AREG0, offsetof(CPUState, xcc), |
| 4612 | 4596 |
"xcc"); |
| 4613 |
#else |
|
| 4614 |
cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0"); |
|
| 4615 |
cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1"); |
|
| 4616 |
cpu_T[2] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "T2"); |
|
| 4617 | 4597 |
#endif |
| 4598 |
/* XXX: T0 and T1 should be temporaries */ |
|
| 4599 |
cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL, |
|
| 4600 |
TCG_AREG0, offsetof(CPUState, t0), "T0"); |
|
| 4601 |
cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL, |
|
| 4602 |
TCG_AREG0, offsetof(CPUState, t1), "T1"); |
|
| 4603 |
cpu_cond = tcg_global_mem_new(TCG_TYPE_TL, |
|
| 4604 |
TCG_AREG0, offsetof(CPUState, cond), "cond"); |
|
| 4618 | 4605 |
cpu_cc_src = tcg_global_mem_new(TCG_TYPE_TL, |
| 4619 | 4606 |
TCG_AREG0, offsetof(CPUState, cc_src), |
| 4620 | 4607 |
"cc_src"); |
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