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/*
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* MSI-X device support
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*
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* This module includes support for MSI-X in pci devices.
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*
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* Author: Michael S. Tsirkin <mst@redhat.com>
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*
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* Copyright (c) 2009, Red Hat Inc, Michael S. Tsirkin (mst@redhat.com)
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*
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* This work is licensed under the terms of the GNU GPL, version 2. See
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* the COPYING file in the top-level directory.
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*
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* Contributions after 2012-01-13 are licensed under the terms of the
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* GNU GPL, version 2 or (at your option) any later version.
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*/
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#include "hw.h" |
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#include "msi.h" |
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#include "msix.h" |
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#include "pci.h" |
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#include "range.h" |
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#define MSIX_CAP_LENGTH 12 |
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/* MSI enable bit and maskall bit are in byte 1 in FLAGS register */
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#define MSIX_CONTROL_OFFSET (PCI_MSIX_FLAGS + 1) |
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#define MSIX_ENABLE_MASK (PCI_MSIX_FLAGS_ENABLE >> 8) |
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#define MSIX_MASKALL_MASK (PCI_MSIX_FLAGS_MASKALL >> 8) |
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/* How much space does an MSIX table need. */
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/* The spec requires giving the table structure
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* a 4K aligned region all by itself. */
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#define MSIX_PAGE_SIZE 0x1000 |
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/* Reserve second half of the page for pending bits */
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#define MSIX_PAGE_PENDING (MSIX_PAGE_SIZE / 2) |
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#define MSIX_MAX_ENTRIES 32 |
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static MSIMessage msix_get_message(PCIDevice *dev, unsigned vector) |
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{ |
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uint8_t *table_entry = dev->msix_table_page + vector * PCI_MSIX_ENTRY_SIZE; |
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MSIMessage msg; |
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msg.address = pci_get_quad(table_entry + PCI_MSIX_ENTRY_LOWER_ADDR); |
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msg.data = pci_get_long(table_entry + PCI_MSIX_ENTRY_DATA); |
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return msg;
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} |
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/* Add MSI-X capability to the config space for the device. */
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/* Given a bar and its size, add MSI-X table on top of it
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* and fill MSI-X capability in the config space.
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* Original bar size must be a power of 2 or 0.
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* New bar size is returned. */
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static int msix_add_config(struct PCIDevice *pdev, unsigned short nentries, |
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unsigned bar_nr, unsigned bar_size) |
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{ |
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int config_offset;
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uint8_t *config; |
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uint32_t new_size; |
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if (nentries < 1 || nentries > PCI_MSIX_FLAGS_QSIZE + 1) |
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return -EINVAL;
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if (bar_size > 0x80000000) |
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return -ENOSPC;
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/* Add space for MSI-X structures */
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if (!bar_size) {
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new_size = MSIX_PAGE_SIZE; |
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} else if (bar_size < MSIX_PAGE_SIZE) { |
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bar_size = MSIX_PAGE_SIZE; |
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new_size = MSIX_PAGE_SIZE * 2;
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} else {
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new_size = bar_size * 2;
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} |
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pdev->msix_bar_size = new_size; |
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config_offset = pci_add_capability(pdev, PCI_CAP_ID_MSIX, |
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0, MSIX_CAP_LENGTH);
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if (config_offset < 0) |
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return config_offset;
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config = pdev->config + config_offset; |
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pci_set_word(config + PCI_MSIX_FLAGS, nentries - 1);
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/* Table on top of BAR */
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pci_set_long(config + PCI_MSIX_TABLE, bar_size | bar_nr); |
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/* Pending bits on top of that */
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pci_set_long(config + PCI_MSIX_PBA, (bar_size + MSIX_PAGE_PENDING) | |
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bar_nr); |
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pdev->msix_cap = config_offset; |
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/* Make flags bit writable. */
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pdev->wmask[config_offset + MSIX_CONTROL_OFFSET] |= MSIX_ENABLE_MASK | |
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MSIX_MASKALL_MASK; |
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pdev->msix_function_masked = true;
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return 0; |
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} |
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static uint64_t msix_mmio_read(void *opaque, target_phys_addr_t addr, |
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unsigned size)
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{ |
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PCIDevice *dev = opaque; |
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unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3; |
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void *page = dev->msix_table_page;
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return pci_get_long(page + offset);
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} |
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static uint8_t msix_pending_mask(int vector) |
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{ |
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return 1 << (vector % 8); |
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} |
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static uint8_t *msix_pending_byte(PCIDevice *dev, int vector) |
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{ |
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return dev->msix_table_page + MSIX_PAGE_PENDING + vector / 8; |
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} |
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static int msix_is_pending(PCIDevice *dev, int vector) |
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{ |
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return *msix_pending_byte(dev, vector) & msix_pending_mask(vector);
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} |
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static void msix_set_pending(PCIDevice *dev, int vector) |
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{ |
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*msix_pending_byte(dev, vector) |= msix_pending_mask(vector); |
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} |
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static void msix_clr_pending(PCIDevice *dev, int vector) |
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{ |
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*msix_pending_byte(dev, vector) &= ~msix_pending_mask(vector); |
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} |
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static bool msix_vector_masked(PCIDevice *dev, int vector, bool fmask) |
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{ |
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unsigned offset = vector * PCI_MSIX_ENTRY_SIZE + PCI_MSIX_ENTRY_VECTOR_CTRL;
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return fmask || dev->msix_table_page[offset] & PCI_MSIX_ENTRY_CTRL_MASKBIT;
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} |
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static bool msix_is_masked(PCIDevice *dev, int vector) |
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{ |
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return msix_vector_masked(dev, vector, dev->msix_function_masked);
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} |
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static void msix_fire_vector_notifier(PCIDevice *dev, |
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unsigned int vector, bool is_masked) |
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{ |
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MSIMessage msg; |
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int ret;
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if (!dev->msix_vector_use_notifier) {
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return;
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} |
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if (is_masked) {
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dev->msix_vector_release_notifier(dev, vector); |
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} else {
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msg = msix_get_message(dev, vector); |
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ret = dev->msix_vector_use_notifier(dev, vector, msg); |
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assert(ret >= 0);
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} |
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} |
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static void msix_handle_mask_update(PCIDevice *dev, int vector, bool was_masked) |
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{ |
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bool is_masked = msix_is_masked(dev, vector);
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if (is_masked == was_masked) {
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return;
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} |
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msix_fire_vector_notifier(dev, vector, is_masked); |
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if (!is_masked && msix_is_pending(dev, vector)) {
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msix_clr_pending(dev, vector); |
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msix_notify(dev, vector); |
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} |
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} |
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static void msix_update_function_masked(PCIDevice *dev) |
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{ |
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dev->msix_function_masked = !msix_enabled(dev) || |
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(dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] & MSIX_MASKALL_MASK); |
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} |
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/* Handle MSI-X capability config write. */
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void msix_write_config(PCIDevice *dev, uint32_t addr,
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uint32_t val, int len)
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{ |
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unsigned enable_pos = dev->msix_cap + MSIX_CONTROL_OFFSET;
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int vector;
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bool was_masked;
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if (!msix_present(dev) || !range_covers_byte(addr, len, enable_pos)) {
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return;
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} |
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was_masked = dev->msix_function_masked; |
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msix_update_function_masked(dev); |
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if (!msix_enabled(dev)) {
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return;
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} |
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pci_device_deassert_intx(dev); |
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if (dev->msix_function_masked == was_masked) {
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return;
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} |
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for (vector = 0; vector < dev->msix_entries_nr; ++vector) { |
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msix_handle_mask_update(dev, vector, |
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msix_vector_masked(dev, vector, was_masked)); |
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} |
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} |
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static void msix_mmio_write(void *opaque, target_phys_addr_t addr, |
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uint64_t val, unsigned size)
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{ |
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PCIDevice *dev = opaque; |
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unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3; |
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int vector = offset / PCI_MSIX_ENTRY_SIZE;
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bool was_masked;
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/* MSI-X page includes a read-only PBA and a writeable Vector Control. */
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if (vector >= dev->msix_entries_nr) {
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return;
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} |
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was_masked = msix_is_masked(dev, vector); |
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pci_set_long(dev->msix_table_page + offset, val); |
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msix_handle_mask_update(dev, vector, was_masked); |
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} |
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static const MemoryRegionOps msix_mmio_ops = { |
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.read = msix_mmio_read, |
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.write = msix_mmio_write, |
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.endianness = DEVICE_NATIVE_ENDIAN, |
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.valid = { |
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.min_access_size = 4,
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.max_access_size = 4,
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}, |
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}; |
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static void msix_mmio_setup(PCIDevice *d, MemoryRegion *bar) |
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{ |
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uint8_t *config = d->config + d->msix_cap; |
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uint32_t table = pci_get_long(config + PCI_MSIX_TABLE); |
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uint32_t offset = table & ~(MSIX_PAGE_SIZE - 1);
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/* TODO: for assigned devices, we'll want to make it possible to map
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* pending bits separately in case they are in a separate bar. */
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memory_region_add_subregion(bar, offset, &d->msix_mmio); |
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} |
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static void msix_mask_all(struct PCIDevice *dev, unsigned nentries) |
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{ |
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int vector;
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for (vector = 0; vector < nentries; ++vector) { |
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unsigned offset =
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vector * PCI_MSIX_ENTRY_SIZE + PCI_MSIX_ENTRY_VECTOR_CTRL; |
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bool was_masked = msix_is_masked(dev, vector);
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dev->msix_table_page[offset] |= PCI_MSIX_ENTRY_CTRL_MASKBIT; |
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msix_handle_mask_update(dev, vector, was_masked); |
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} |
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} |
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/* Initialize the MSI-X structures. Note: if MSI-X is supported, BAR size is
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* modified, it should be retrieved with msix_bar_size. */
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int msix_init(struct PCIDevice *dev, unsigned short nentries, |
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MemoryRegion *bar, |
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unsigned bar_nr, unsigned bar_size) |
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{ |
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int ret;
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/* Nothing to do if MSI is not supported by interrupt controller */
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if (!msi_supported) {
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return -ENOTSUP;
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} |
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if (nentries > MSIX_MAX_ENTRIES)
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return -EINVAL;
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dev->msix_entry_used = g_malloc0(MSIX_MAX_ENTRIES * |
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sizeof *dev->msix_entry_used);
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dev->msix_table_page = g_malloc0(MSIX_PAGE_SIZE); |
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msix_mask_all(dev, nentries); |
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memory_region_init_io(&dev->msix_mmio, &msix_mmio_ops, dev, |
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"msix", MSIX_PAGE_SIZE);
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dev->msix_entries_nr = nentries; |
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ret = msix_add_config(dev, nentries, bar_nr, bar_size); |
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if (ret)
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goto err_config;
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dev->cap_present |= QEMU_PCI_CAP_MSIX; |
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msix_mmio_setup(dev, bar); |
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return 0; |
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err_config:
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dev->msix_entries_nr = 0;
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memory_region_destroy(&dev->msix_mmio); |
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g_free(dev->msix_table_page); |
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dev->msix_table_page = NULL;
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g_free(dev->msix_entry_used); |
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dev->msix_entry_used = NULL;
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return ret;
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} |
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static void msix_free_irq_entries(PCIDevice *dev) |
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{ |
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int vector;
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for (vector = 0; vector < dev->msix_entries_nr; ++vector) { |
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dev->msix_entry_used[vector] = 0;
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msix_clr_pending(dev, vector); |
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} |
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} |
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/* Clean up resources for the device. */
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int msix_uninit(PCIDevice *dev, MemoryRegion *bar)
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{ |
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if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
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return 0; |
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pci_del_capability(dev, PCI_CAP_ID_MSIX, MSIX_CAP_LENGTH); |
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dev->msix_cap = 0;
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msix_free_irq_entries(dev); |
327 |
dev->msix_entries_nr = 0;
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memory_region_del_subregion(bar, &dev->msix_mmio); |
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memory_region_destroy(&dev->msix_mmio); |
330 |
g_free(dev->msix_table_page); |
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dev->msix_table_page = NULL;
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g_free(dev->msix_entry_used); |
333 |
dev->msix_entry_used = NULL;
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dev->cap_present &= ~QEMU_PCI_CAP_MSIX; |
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return 0; |
336 |
} |
337 |
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void msix_save(PCIDevice *dev, QEMUFile *f)
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{ |
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unsigned n = dev->msix_entries_nr;
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if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) {
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return;
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} |
345 |
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qemu_put_buffer(f, dev->msix_table_page, n * PCI_MSIX_ENTRY_SIZE); |
347 |
qemu_put_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8); |
348 |
} |
349 |
|
350 |
/* Should be called after restoring the config space. */
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void msix_load(PCIDevice *dev, QEMUFile *f)
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{ |
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unsigned n = dev->msix_entries_nr;
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unsigned int vector; |
355 |
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if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) {
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return;
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} |
359 |
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msix_free_irq_entries(dev); |
361 |
qemu_get_buffer(f, dev->msix_table_page, n * PCI_MSIX_ENTRY_SIZE); |
362 |
qemu_get_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8); |
363 |
msix_update_function_masked(dev); |
364 |
|
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for (vector = 0; vector < n; vector++) { |
366 |
msix_handle_mask_update(dev, vector, true);
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367 |
} |
368 |
} |
369 |
|
370 |
/* Does device support MSI-X? */
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int msix_present(PCIDevice *dev)
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{ |
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return dev->cap_present & QEMU_PCI_CAP_MSIX;
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374 |
} |
375 |
|
376 |
/* Is MSI-X enabled? */
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377 |
int msix_enabled(PCIDevice *dev)
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378 |
{ |
379 |
return (dev->cap_present & QEMU_PCI_CAP_MSIX) &&
|
380 |
(dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] & |
381 |
MSIX_ENABLE_MASK); |
382 |
} |
383 |
|
384 |
/* Size of bar where MSI-X table resides, or 0 if MSI-X not supported. */
|
385 |
uint32_t msix_bar_size(PCIDevice *dev) |
386 |
{ |
387 |
return (dev->cap_present & QEMU_PCI_CAP_MSIX) ?
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dev->msix_bar_size : 0;
|
389 |
} |
390 |
|
391 |
/* Send an MSI-X message */
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392 |
void msix_notify(PCIDevice *dev, unsigned vector) |
393 |
{ |
394 |
MSIMessage msg; |
395 |
|
396 |
if (vector >= dev->msix_entries_nr || !dev->msix_entry_used[vector])
|
397 |
return;
|
398 |
if (msix_is_masked(dev, vector)) {
|
399 |
msix_set_pending(dev, vector); |
400 |
return;
|
401 |
} |
402 |
|
403 |
msg = msix_get_message(dev, vector); |
404 |
|
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stl_le_phys(msg.address, msg.data); |
406 |
} |
407 |
|
408 |
void msix_reset(PCIDevice *dev)
|
409 |
{ |
410 |
if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
|
411 |
return;
|
412 |
msix_free_irq_entries(dev); |
413 |
dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &= |
414 |
~dev->wmask[dev->msix_cap + MSIX_CONTROL_OFFSET]; |
415 |
memset(dev->msix_table_page, 0, MSIX_PAGE_SIZE);
|
416 |
msix_mask_all(dev, dev->msix_entries_nr); |
417 |
} |
418 |
|
419 |
/* PCI spec suggests that devices make it possible for software to configure
|
420 |
* less vectors than supported by the device, but does not specify a standard
|
421 |
* mechanism for devices to do so.
|
422 |
*
|
423 |
* We support this by asking devices to declare vectors software is going to
|
424 |
* actually use, and checking this on the notification path. Devices that
|
425 |
* don't want to follow the spec suggestion can declare all vectors as used. */
|
426 |
|
427 |
/* Mark vector as used. */
|
428 |
int msix_vector_use(PCIDevice *dev, unsigned vector) |
429 |
{ |
430 |
if (vector >= dev->msix_entries_nr)
|
431 |
return -EINVAL;
|
432 |
dev->msix_entry_used[vector]++; |
433 |
return 0; |
434 |
} |
435 |
|
436 |
/* Mark vector as unused. */
|
437 |
void msix_vector_unuse(PCIDevice *dev, unsigned vector) |
438 |
{ |
439 |
if (vector >= dev->msix_entries_nr || !dev->msix_entry_used[vector]) {
|
440 |
return;
|
441 |
} |
442 |
if (--dev->msix_entry_used[vector]) {
|
443 |
return;
|
444 |
} |
445 |
msix_clr_pending(dev, vector); |
446 |
} |
447 |
|
448 |
void msix_unuse_all_vectors(PCIDevice *dev)
|
449 |
{ |
450 |
if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
|
451 |
return;
|
452 |
msix_free_irq_entries(dev); |
453 |
} |
454 |
|
455 |
unsigned int msix_nr_vectors_allocated(const PCIDevice *dev) |
456 |
{ |
457 |
return dev->msix_entries_nr;
|
458 |
} |
459 |
|
460 |
static int msix_set_notifier_for_vector(PCIDevice *dev, unsigned int vector) |
461 |
{ |
462 |
MSIMessage msg; |
463 |
|
464 |
if (msix_is_masked(dev, vector)) {
|
465 |
return 0; |
466 |
} |
467 |
msg = msix_get_message(dev, vector); |
468 |
return dev->msix_vector_use_notifier(dev, vector, msg);
|
469 |
} |
470 |
|
471 |
static void msix_unset_notifier_for_vector(PCIDevice *dev, unsigned int vector) |
472 |
{ |
473 |
if (msix_is_masked(dev, vector)) {
|
474 |
return;
|
475 |
} |
476 |
dev->msix_vector_release_notifier(dev, vector); |
477 |
} |
478 |
|
479 |
int msix_set_vector_notifiers(PCIDevice *dev,
|
480 |
MSIVectorUseNotifier use_notifier, |
481 |
MSIVectorReleaseNotifier release_notifier) |
482 |
{ |
483 |
int vector, ret;
|
484 |
|
485 |
assert(use_notifier && release_notifier); |
486 |
|
487 |
dev->msix_vector_use_notifier = use_notifier; |
488 |
dev->msix_vector_release_notifier = release_notifier; |
489 |
|
490 |
if ((dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &
|
491 |
(MSIX_ENABLE_MASK | MSIX_MASKALL_MASK)) == MSIX_ENABLE_MASK) { |
492 |
for (vector = 0; vector < dev->msix_entries_nr; vector++) { |
493 |
ret = msix_set_notifier_for_vector(dev, vector); |
494 |
if (ret < 0) { |
495 |
goto undo;
|
496 |
} |
497 |
} |
498 |
} |
499 |
return 0; |
500 |
|
501 |
undo:
|
502 |
while (--vector >= 0) { |
503 |
msix_unset_notifier_for_vector(dev, vector); |
504 |
} |
505 |
dev->msix_vector_use_notifier = NULL;
|
506 |
dev->msix_vector_release_notifier = NULL;
|
507 |
return ret;
|
508 |
} |
509 |
|
510 |
void msix_unset_vector_notifiers(PCIDevice *dev)
|
511 |
{ |
512 |
int vector;
|
513 |
|
514 |
assert(dev->msix_vector_use_notifier && |
515 |
dev->msix_vector_release_notifier); |
516 |
|
517 |
if ((dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &
|
518 |
(MSIX_ENABLE_MASK | MSIX_MASKALL_MASK)) == MSIX_ENABLE_MASK) { |
519 |
for (vector = 0; vector < dev->msix_entries_nr; vector++) { |
520 |
msix_unset_notifier_for_vector(dev, vector); |
521 |
} |
522 |
} |
523 |
dev->msix_vector_use_notifier = NULL;
|
524 |
dev->msix_vector_release_notifier = NULL;
|
525 |
} |