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1 | 80cabfad | bellard | /*
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2 | 80cabfad | bellard | * QEMU NE2000 emulation
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3 | 80cabfad | bellard | *
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4 | 80cabfad | bellard | * Copyright (c) 2003-2004 Fabrice Bellard
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5 | 80cabfad | bellard | *
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6 | 80cabfad | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 80cabfad | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 80cabfad | bellard | * in the Software without restriction, including without limitation the rights
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9 | 80cabfad | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 80cabfad | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 80cabfad | bellard | * furnished to do so, subject to the following conditions:
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12 | 80cabfad | bellard | *
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13 | 80cabfad | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 80cabfad | bellard | * all copies or substantial portions of the Software.
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15 | 80cabfad | bellard | *
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16 | 80cabfad | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 80cabfad | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 80cabfad | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 80cabfad | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 80cabfad | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 80cabfad | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 80cabfad | bellard | * THE SOFTWARE.
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23 | 80cabfad | bellard | */
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24 | 80cabfad | bellard | #include "vl.h" |
25 | 80cabfad | bellard | |
26 | 80cabfad | bellard | /* debug NE2000 card */
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27 | 80cabfad | bellard | //#define DEBUG_NE2000
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28 | 80cabfad | bellard | |
29 | b41a2cd1 | bellard | #define MAX_ETH_FRAME_SIZE 1514 |
30 | 80cabfad | bellard | |
31 | 80cabfad | bellard | #define E8390_CMD 0x00 /* The command register (for all pages) */ |
32 | 80cabfad | bellard | /* Page 0 register offsets. */
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33 | 80cabfad | bellard | #define EN0_CLDALO 0x01 /* Low byte of current local dma addr RD */ |
34 | 80cabfad | bellard | #define EN0_STARTPG 0x01 /* Starting page of ring bfr WR */ |
35 | 80cabfad | bellard | #define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */ |
36 | 80cabfad | bellard | #define EN0_STOPPG 0x02 /* Ending page +1 of ring bfr WR */ |
37 | 80cabfad | bellard | #define EN0_BOUNDARY 0x03 /* Boundary page of ring bfr RD WR */ |
38 | 80cabfad | bellard | #define EN0_TSR 0x04 /* Transmit status reg RD */ |
39 | 80cabfad | bellard | #define EN0_TPSR 0x04 /* Transmit starting page WR */ |
40 | 80cabfad | bellard | #define EN0_NCR 0x05 /* Number of collision reg RD */ |
41 | 80cabfad | bellard | #define EN0_TCNTLO 0x05 /* Low byte of tx byte count WR */ |
42 | 80cabfad | bellard | #define EN0_FIFO 0x06 /* FIFO RD */ |
43 | 80cabfad | bellard | #define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */ |
44 | 80cabfad | bellard | #define EN0_ISR 0x07 /* Interrupt status reg RD WR */ |
45 | 80cabfad | bellard | #define EN0_CRDALO 0x08 /* low byte of current remote dma address RD */ |
46 | 80cabfad | bellard | #define EN0_RSARLO 0x08 /* Remote start address reg 0 */ |
47 | 80cabfad | bellard | #define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */ |
48 | 80cabfad | bellard | #define EN0_RSARHI 0x09 /* Remote start address reg 1 */ |
49 | 80cabfad | bellard | #define EN0_RCNTLO 0x0a /* Remote byte count reg WR */ |
50 | 80cabfad | bellard | #define EN0_RCNTHI 0x0b /* Remote byte count reg WR */ |
51 | 80cabfad | bellard | #define EN0_RSR 0x0c /* rx status reg RD */ |
52 | 80cabfad | bellard | #define EN0_RXCR 0x0c /* RX configuration reg WR */ |
53 | 80cabfad | bellard | #define EN0_TXCR 0x0d /* TX configuration reg WR */ |
54 | 80cabfad | bellard | #define EN0_COUNTER0 0x0d /* Rcv alignment error counter RD */ |
55 | 80cabfad | bellard | #define EN0_DCFG 0x0e /* Data configuration reg WR */ |
56 | 80cabfad | bellard | #define EN0_COUNTER1 0x0e /* Rcv CRC error counter RD */ |
57 | 80cabfad | bellard | #define EN0_IMR 0x0f /* Interrupt mask reg WR */ |
58 | 80cabfad | bellard | #define EN0_COUNTER2 0x0f /* Rcv missed frame error counter RD */ |
59 | 80cabfad | bellard | |
60 | 80cabfad | bellard | #define EN1_PHYS 0x11 |
61 | 80cabfad | bellard | #define EN1_CURPAG 0x17 |
62 | 80cabfad | bellard | #define EN1_MULT 0x18 |
63 | 80cabfad | bellard | |
64 | a343df16 | bellard | #define EN2_STARTPG 0x21 /* Starting page of ring bfr RD */ |
65 | a343df16 | bellard | #define EN2_STOPPG 0x22 /* Ending page +1 of ring bfr RD */ |
66 | a343df16 | bellard | |
67 | 80cabfad | bellard | /* Register accessed at EN_CMD, the 8390 base addr. */
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68 | 80cabfad | bellard | #define E8390_STOP 0x01 /* Stop and reset the chip */ |
69 | 80cabfad | bellard | #define E8390_START 0x02 /* Start the chip, clear reset */ |
70 | 80cabfad | bellard | #define E8390_TRANS 0x04 /* Transmit a frame */ |
71 | 80cabfad | bellard | #define E8390_RREAD 0x08 /* Remote read */ |
72 | 80cabfad | bellard | #define E8390_RWRITE 0x10 /* Remote write */ |
73 | 80cabfad | bellard | #define E8390_NODMA 0x20 /* Remote DMA */ |
74 | 80cabfad | bellard | #define E8390_PAGE0 0x00 /* Select page chip registers */ |
75 | 80cabfad | bellard | #define E8390_PAGE1 0x40 /* using the two high-order bits */ |
76 | 80cabfad | bellard | #define E8390_PAGE2 0x80 /* Page 3 is invalid. */ |
77 | 80cabfad | bellard | |
78 | 80cabfad | bellard | /* Bits in EN0_ISR - Interrupt status register */
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79 | 80cabfad | bellard | #define ENISR_RX 0x01 /* Receiver, no error */ |
80 | 80cabfad | bellard | #define ENISR_TX 0x02 /* Transmitter, no error */ |
81 | 80cabfad | bellard | #define ENISR_RX_ERR 0x04 /* Receiver, with error */ |
82 | 80cabfad | bellard | #define ENISR_TX_ERR 0x08 /* Transmitter, with error */ |
83 | 80cabfad | bellard | #define ENISR_OVER 0x10 /* Receiver overwrote the ring */ |
84 | 80cabfad | bellard | #define ENISR_COUNTERS 0x20 /* Counters need emptying */ |
85 | 80cabfad | bellard | #define ENISR_RDC 0x40 /* remote dma complete */ |
86 | 80cabfad | bellard | #define ENISR_RESET 0x80 /* Reset completed */ |
87 | 80cabfad | bellard | #define ENISR_ALL 0x3f /* Interrupts we will enable */ |
88 | 80cabfad | bellard | |
89 | 80cabfad | bellard | /* Bits in received packet status byte and EN0_RSR*/
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90 | 80cabfad | bellard | #define ENRSR_RXOK 0x01 /* Received a good packet */ |
91 | 80cabfad | bellard | #define ENRSR_CRC 0x02 /* CRC error */ |
92 | 80cabfad | bellard | #define ENRSR_FAE 0x04 /* frame alignment error */ |
93 | 80cabfad | bellard | #define ENRSR_FO 0x08 /* FIFO overrun */ |
94 | 80cabfad | bellard | #define ENRSR_MPA 0x10 /* missed pkt */ |
95 | 80cabfad | bellard | #define ENRSR_PHY 0x20 /* physical/multicast address */ |
96 | 80cabfad | bellard | #define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */ |
97 | 80cabfad | bellard | #define ENRSR_DEF 0x80 /* deferring */ |
98 | 80cabfad | bellard | |
99 | 80cabfad | bellard | /* Transmitted packet status, EN0_TSR. */
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100 | 80cabfad | bellard | #define ENTSR_PTX 0x01 /* Packet transmitted without error */ |
101 | 80cabfad | bellard | #define ENTSR_ND 0x02 /* The transmit wasn't deferred. */ |
102 | 80cabfad | bellard | #define ENTSR_COL 0x04 /* The transmit collided at least once. */ |
103 | 80cabfad | bellard | #define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */ |
104 | 80cabfad | bellard | #define ENTSR_CRS 0x10 /* The carrier sense was lost. */ |
105 | 80cabfad | bellard | #define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */ |
106 | 80cabfad | bellard | #define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */ |
107 | 80cabfad | bellard | #define ENTSR_OWC 0x80 /* There was an out-of-window collision. */ |
108 | 80cabfad | bellard | |
109 | ee9dbb29 | bellard | #define NE2000_PMEM_SIZE (32*1024) |
110 | ee9dbb29 | bellard | #define NE2000_PMEM_START (16*1024) |
111 | ee9dbb29 | bellard | #define NE2000_PMEM_END (NE2000_PMEM_SIZE+NE2000_PMEM_START)
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112 | ee9dbb29 | bellard | #define NE2000_MEM_SIZE NE2000_PMEM_END
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113 | 80cabfad | bellard | |
114 | 80cabfad | bellard | typedef struct NE2000State { |
115 | 80cabfad | bellard | uint8_t cmd; |
116 | 80cabfad | bellard | uint32_t start; |
117 | 80cabfad | bellard | uint32_t stop; |
118 | 80cabfad | bellard | uint8_t boundary; |
119 | 80cabfad | bellard | uint8_t tsr; |
120 | 80cabfad | bellard | uint8_t tpsr; |
121 | 80cabfad | bellard | uint16_t tcnt; |
122 | 80cabfad | bellard | uint16_t rcnt; |
123 | 80cabfad | bellard | uint32_t rsar; |
124 | 8d6c7eb8 | bellard | uint8_t rsr; |
125 | 7c9d8e07 | bellard | uint8_t rxcr; |
126 | 80cabfad | bellard | uint8_t isr; |
127 | 80cabfad | bellard | uint8_t dcfg; |
128 | 80cabfad | bellard | uint8_t imr; |
129 | 80cabfad | bellard | uint8_t phys[6]; /* mac address */ |
130 | 80cabfad | bellard | uint8_t curpag; |
131 | 80cabfad | bellard | uint8_t mult[8]; /* multicast mask array */ |
132 | 80cabfad | bellard | int irq;
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133 | 4a9c9687 | bellard | PCIDevice *pci_dev; |
134 | 7c9d8e07 | bellard | VLANClientState *vc; |
135 | 7c9d8e07 | bellard | uint8_t macaddr[6];
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136 | 80cabfad | bellard | uint8_t mem[NE2000_MEM_SIZE]; |
137 | 80cabfad | bellard | } NE2000State; |
138 | 80cabfad | bellard | |
139 | 80cabfad | bellard | static void ne2000_reset(NE2000State *s) |
140 | 80cabfad | bellard | { |
141 | 80cabfad | bellard | int i;
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142 | 80cabfad | bellard | |
143 | 80cabfad | bellard | s->isr = ENISR_RESET; |
144 | 7c9d8e07 | bellard | memcpy(s->mem, s->macaddr, 6);
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145 | 80cabfad | bellard | s->mem[14] = 0x57; |
146 | 80cabfad | bellard | s->mem[15] = 0x57; |
147 | 80cabfad | bellard | |
148 | 80cabfad | bellard | /* duplicate prom data */
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149 | 80cabfad | bellard | for(i = 15;i >= 0; i--) { |
150 | 80cabfad | bellard | s->mem[2 * i] = s->mem[i];
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151 | 80cabfad | bellard | s->mem[2 * i + 1] = s->mem[i]; |
152 | 80cabfad | bellard | } |
153 | 80cabfad | bellard | } |
154 | 80cabfad | bellard | |
155 | 80cabfad | bellard | static void ne2000_update_irq(NE2000State *s) |
156 | 80cabfad | bellard | { |
157 | 80cabfad | bellard | int isr;
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158 | a343df16 | bellard | isr = (s->isr & s->imr) & 0x7f;
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159 | a541f297 | bellard | #if defined(DEBUG_NE2000)
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160 | a541f297 | bellard | printf("NE2000: Set IRQ line %d to %d (%02x %02x)\n",
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161 | a541f297 | bellard | s->irq, isr ? 1 : 0, s->isr, s->imr); |
162 | a541f297 | bellard | #endif
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163 | 4a9c9687 | bellard | if (s->irq == 16) { |
164 | 4a9c9687 | bellard | /* PCI irq */
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165 | 4a9c9687 | bellard | pci_set_irq(s->pci_dev, 0, (isr != 0)); |
166 | 4a9c9687 | bellard | } else {
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167 | 4a9c9687 | bellard | /* ISA irq */
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168 | 4a9c9687 | bellard | pic_set_irq(s->irq, (isr != 0));
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169 | 4a9c9687 | bellard | } |
170 | 80cabfad | bellard | } |
171 | 80cabfad | bellard | |
172 | 7c9d8e07 | bellard | #define POLYNOMIAL 0x04c11db6 |
173 | 7c9d8e07 | bellard | |
174 | 7c9d8e07 | bellard | /* From FreeBSD */
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175 | 7c9d8e07 | bellard | /* XXX: optimize */
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176 | 7c9d8e07 | bellard | static int compute_mcast_idx(const uint8_t *ep) |
177 | 7c9d8e07 | bellard | { |
178 | 7c9d8e07 | bellard | uint32_t crc; |
179 | 7c9d8e07 | bellard | int carry, i, j;
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180 | 7c9d8e07 | bellard | uint8_t b; |
181 | 7c9d8e07 | bellard | |
182 | 7c9d8e07 | bellard | crc = 0xffffffff;
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183 | 7c9d8e07 | bellard | for (i = 0; i < 6; i++) { |
184 | 7c9d8e07 | bellard | b = *ep++; |
185 | 7c9d8e07 | bellard | for (j = 0; j < 8; j++) { |
186 | 7c9d8e07 | bellard | carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01); |
187 | 7c9d8e07 | bellard | crc <<= 1;
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188 | 7c9d8e07 | bellard | b >>= 1;
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189 | 7c9d8e07 | bellard | if (carry)
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190 | 7c9d8e07 | bellard | crc = ((crc ^ POLYNOMIAL) | carry); |
191 | 7c9d8e07 | bellard | } |
192 | 7c9d8e07 | bellard | } |
193 | 7c9d8e07 | bellard | return (crc >> 26); |
194 | 7c9d8e07 | bellard | } |
195 | 7c9d8e07 | bellard | |
196 | b41a2cd1 | bellard | /* return the max buffer size if the NE2000 can receive more data */
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197 | b41a2cd1 | bellard | static int ne2000_can_receive(void *opaque) |
198 | 80cabfad | bellard | { |
199 | b41a2cd1 | bellard | NE2000State *s = opaque; |
200 | 80cabfad | bellard | int avail, index, boundary;
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201 | 80cabfad | bellard | |
202 | 80cabfad | bellard | if (s->cmd & E8390_STOP)
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203 | 80cabfad | bellard | return 0; |
204 | 80cabfad | bellard | index = s->curpag << 8;
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205 | 80cabfad | bellard | boundary = s->boundary << 8;
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206 | 80cabfad | bellard | if (index < boundary)
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207 | 80cabfad | bellard | avail = boundary - index; |
208 | 80cabfad | bellard | else
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209 | 80cabfad | bellard | avail = (s->stop - s->start) - (index - boundary); |
210 | 80cabfad | bellard | if (avail < (MAX_ETH_FRAME_SIZE + 4)) |
211 | 80cabfad | bellard | return 0; |
212 | b41a2cd1 | bellard | return MAX_ETH_FRAME_SIZE;
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213 | 80cabfad | bellard | } |
214 | 80cabfad | bellard | |
215 | b41a2cd1 | bellard | #define MIN_BUF_SIZE 60 |
216 | b41a2cd1 | bellard | |
217 | b41a2cd1 | bellard | static void ne2000_receive(void *opaque, const uint8_t *buf, int size) |
218 | 80cabfad | bellard | { |
219 | b41a2cd1 | bellard | NE2000State *s = opaque; |
220 | 80cabfad | bellard | uint8_t *p; |
221 | 7c9d8e07 | bellard | int total_len, next, avail, len, index, mcast_idx;
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222 | b41a2cd1 | bellard | uint8_t buf1[60];
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223 | 7c9d8e07 | bellard | static const uint8_t broadcast_macaddr[6] = |
224 | 7c9d8e07 | bellard | { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; |
225 | b41a2cd1 | bellard | |
226 | 80cabfad | bellard | #if defined(DEBUG_NE2000)
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227 | 80cabfad | bellard | printf("NE2000: received len=%d\n", size);
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228 | 80cabfad | bellard | #endif
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229 | 80cabfad | bellard | |
230 | 7c9d8e07 | bellard | if (!ne2000_can_receive(s))
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231 | 7c9d8e07 | bellard | return;
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232 | 7c9d8e07 | bellard | |
233 | 7c9d8e07 | bellard | /* XXX: check this */
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234 | 7c9d8e07 | bellard | if (s->rxcr & 0x10) { |
235 | 7c9d8e07 | bellard | /* promiscuous: receive all */
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236 | 7c9d8e07 | bellard | } else {
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237 | 7c9d8e07 | bellard | if (!memcmp(buf, broadcast_macaddr, 6)) { |
238 | 7c9d8e07 | bellard | /* broadcast address */
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239 | 7c9d8e07 | bellard | if (!(s->rxcr & 0x04)) |
240 | 7c9d8e07 | bellard | return;
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241 | 7c9d8e07 | bellard | } else if (buf[0] & 0x01) { |
242 | 7c9d8e07 | bellard | /* multicast */
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243 | 7c9d8e07 | bellard | if (!(s->rxcr & 0x08)) |
244 | 7c9d8e07 | bellard | return;
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245 | 7c9d8e07 | bellard | mcast_idx = compute_mcast_idx(buf); |
246 | 7c9d8e07 | bellard | if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7)))) |
247 | 7c9d8e07 | bellard | return;
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248 | 7c9d8e07 | bellard | } else if (s->mem[0] == buf[0] && |
249 | 7c9d8e07 | bellard | s->mem[2] == buf[1] && |
250 | 7c9d8e07 | bellard | s->mem[4] == buf[2] && |
251 | 7c9d8e07 | bellard | s->mem[6] == buf[3] && |
252 | 7c9d8e07 | bellard | s->mem[8] == buf[4] && |
253 | 7c9d8e07 | bellard | s->mem[10] == buf[5]) { |
254 | 7c9d8e07 | bellard | /* match */
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255 | 7c9d8e07 | bellard | } else {
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256 | 7c9d8e07 | bellard | return;
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257 | 7c9d8e07 | bellard | } |
258 | 7c9d8e07 | bellard | } |
259 | 7c9d8e07 | bellard | |
260 | 7c9d8e07 | bellard | |
261 | b41a2cd1 | bellard | /* if too small buffer, then expand it */
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262 | b41a2cd1 | bellard | if (size < MIN_BUF_SIZE) {
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263 | b41a2cd1 | bellard | memcpy(buf1, buf, size); |
264 | b41a2cd1 | bellard | memset(buf1 + size, 0, MIN_BUF_SIZE - size);
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265 | b41a2cd1 | bellard | buf = buf1; |
266 | b41a2cd1 | bellard | size = MIN_BUF_SIZE; |
267 | b41a2cd1 | bellard | } |
268 | b41a2cd1 | bellard | |
269 | 80cabfad | bellard | index = s->curpag << 8;
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270 | 80cabfad | bellard | /* 4 bytes for header */
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271 | 80cabfad | bellard | total_len = size + 4;
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272 | 80cabfad | bellard | /* address for next packet (4 bytes for CRC) */
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273 | 80cabfad | bellard | next = index + ((total_len + 4 + 255) & ~0xff); |
274 | 80cabfad | bellard | if (next >= s->stop)
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275 | 80cabfad | bellard | next -= (s->stop - s->start); |
276 | 80cabfad | bellard | /* prepare packet header */
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277 | 80cabfad | bellard | p = s->mem + index; |
278 | 8d6c7eb8 | bellard | s->rsr = ENRSR_RXOK; /* receive status */
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279 | 8d6c7eb8 | bellard | /* XXX: check this */
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280 | 8d6c7eb8 | bellard | if (buf[0] & 0x01) |
281 | 8d6c7eb8 | bellard | s->rsr |= ENRSR_PHY; |
282 | 8d6c7eb8 | bellard | p[0] = s->rsr;
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283 | 80cabfad | bellard | p[1] = next >> 8; |
284 | 80cabfad | bellard | p[2] = total_len;
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285 | 80cabfad | bellard | p[3] = total_len >> 8; |
286 | 80cabfad | bellard | index += 4;
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287 | 80cabfad | bellard | |
288 | 80cabfad | bellard | /* write packet data */
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289 | 80cabfad | bellard | while (size > 0) { |
290 | 80cabfad | bellard | avail = s->stop - index; |
291 | 80cabfad | bellard | len = size; |
292 | 80cabfad | bellard | if (len > avail)
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293 | 80cabfad | bellard | len = avail; |
294 | 80cabfad | bellard | memcpy(s->mem + index, buf, len); |
295 | 80cabfad | bellard | buf += len; |
296 | 80cabfad | bellard | index += len; |
297 | 80cabfad | bellard | if (index == s->stop)
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298 | 80cabfad | bellard | index = s->start; |
299 | 80cabfad | bellard | size -= len; |
300 | 80cabfad | bellard | } |
301 | 80cabfad | bellard | s->curpag = next >> 8;
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302 | 8d6c7eb8 | bellard | |
303 | 80cabfad | bellard | /* now we can signal we have receive something */
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304 | 80cabfad | bellard | s->isr |= ENISR_RX; |
305 | 80cabfad | bellard | ne2000_update_irq(s); |
306 | 80cabfad | bellard | } |
307 | 80cabfad | bellard | |
308 | b41a2cd1 | bellard | static void ne2000_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
309 | 80cabfad | bellard | { |
310 | b41a2cd1 | bellard | NE2000State *s = opaque; |
311 | 40545f84 | bellard | int offset, page, index;
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312 | 80cabfad | bellard | |
313 | 80cabfad | bellard | addr &= 0xf;
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314 | 80cabfad | bellard | #ifdef DEBUG_NE2000
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315 | 80cabfad | bellard | printf("NE2000: write addr=0x%x val=0x%02x\n", addr, val);
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316 | 80cabfad | bellard | #endif
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317 | 80cabfad | bellard | if (addr == E8390_CMD) {
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318 | 80cabfad | bellard | /* control register */
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319 | 80cabfad | bellard | s->cmd = val; |
320 | a343df16 | bellard | if (!(val & E8390_STOP)) { /* START bit makes no sense on RTL8029... */ |
321 | ee9dbb29 | bellard | s->isr &= ~ENISR_RESET; |
322 | 80cabfad | bellard | /* test specific case: zero length transfert */
|
323 | 80cabfad | bellard | if ((val & (E8390_RREAD | E8390_RWRITE)) &&
|
324 | 80cabfad | bellard | s->rcnt == 0) {
|
325 | 80cabfad | bellard | s->isr |= ENISR_RDC; |
326 | 80cabfad | bellard | ne2000_update_irq(s); |
327 | 80cabfad | bellard | } |
328 | 80cabfad | bellard | if (val & E8390_TRANS) {
|
329 | 40545f84 | bellard | index = (s->tpsr << 8);
|
330 | 40545f84 | bellard | /* XXX: next 2 lines are a hack to make netware 3.11 work */
|
331 | 40545f84 | bellard | if (index >= NE2000_PMEM_END)
|
332 | 40545f84 | bellard | index -= NE2000_PMEM_SIZE; |
333 | 40545f84 | bellard | /* fail safe: check range on the transmitted length */
|
334 | 40545f84 | bellard | if (index + s->tcnt <= NE2000_PMEM_END) {
|
335 | 7c9d8e07 | bellard | qemu_send_packet(s->vc, s->mem + index, s->tcnt); |
336 | 40545f84 | bellard | } |
337 | 80cabfad | bellard | /* signal end of transfert */
|
338 | 80cabfad | bellard | s->tsr = ENTSR_PTX; |
339 | 80cabfad | bellard | s->isr |= ENISR_TX; |
340 | 40545f84 | bellard | s->cmd &= ~E8390_TRANS; |
341 | 80cabfad | bellard | ne2000_update_irq(s); |
342 | 80cabfad | bellard | } |
343 | 80cabfad | bellard | } |
344 | 80cabfad | bellard | } else {
|
345 | 80cabfad | bellard | page = s->cmd >> 6;
|
346 | 80cabfad | bellard | offset = addr | (page << 4);
|
347 | 80cabfad | bellard | switch(offset) {
|
348 | 80cabfad | bellard | case EN0_STARTPG:
|
349 | 80cabfad | bellard | s->start = val << 8;
|
350 | 80cabfad | bellard | break;
|
351 | 80cabfad | bellard | case EN0_STOPPG:
|
352 | 80cabfad | bellard | s->stop = val << 8;
|
353 | 80cabfad | bellard | break;
|
354 | 80cabfad | bellard | case EN0_BOUNDARY:
|
355 | 80cabfad | bellard | s->boundary = val; |
356 | 80cabfad | bellard | break;
|
357 | 80cabfad | bellard | case EN0_IMR:
|
358 | 80cabfad | bellard | s->imr = val; |
359 | 80cabfad | bellard | ne2000_update_irq(s); |
360 | 80cabfad | bellard | break;
|
361 | 80cabfad | bellard | case EN0_TPSR:
|
362 | 80cabfad | bellard | s->tpsr = val; |
363 | 80cabfad | bellard | break;
|
364 | 80cabfad | bellard | case EN0_TCNTLO:
|
365 | 80cabfad | bellard | s->tcnt = (s->tcnt & 0xff00) | val;
|
366 | 80cabfad | bellard | break;
|
367 | 80cabfad | bellard | case EN0_TCNTHI:
|
368 | 80cabfad | bellard | s->tcnt = (s->tcnt & 0x00ff) | (val << 8); |
369 | 80cabfad | bellard | break;
|
370 | 80cabfad | bellard | case EN0_RSARLO:
|
371 | 80cabfad | bellard | s->rsar = (s->rsar & 0xff00) | val;
|
372 | 80cabfad | bellard | break;
|
373 | 80cabfad | bellard | case EN0_RSARHI:
|
374 | 80cabfad | bellard | s->rsar = (s->rsar & 0x00ff) | (val << 8); |
375 | 80cabfad | bellard | break;
|
376 | 80cabfad | bellard | case EN0_RCNTLO:
|
377 | 80cabfad | bellard | s->rcnt = (s->rcnt & 0xff00) | val;
|
378 | 80cabfad | bellard | break;
|
379 | 80cabfad | bellard | case EN0_RCNTHI:
|
380 | 80cabfad | bellard | s->rcnt = (s->rcnt & 0x00ff) | (val << 8); |
381 | 80cabfad | bellard | break;
|
382 | 7c9d8e07 | bellard | case EN0_RXCR:
|
383 | 7c9d8e07 | bellard | s->rxcr = val; |
384 | 7c9d8e07 | bellard | break;
|
385 | 80cabfad | bellard | case EN0_DCFG:
|
386 | 80cabfad | bellard | s->dcfg = val; |
387 | 80cabfad | bellard | break;
|
388 | 80cabfad | bellard | case EN0_ISR:
|
389 | ee9dbb29 | bellard | s->isr &= ~(val & 0x7f);
|
390 | 80cabfad | bellard | ne2000_update_irq(s); |
391 | 80cabfad | bellard | break;
|
392 | 80cabfad | bellard | case EN1_PHYS ... EN1_PHYS + 5: |
393 | 80cabfad | bellard | s->phys[offset - EN1_PHYS] = val; |
394 | 80cabfad | bellard | break;
|
395 | 80cabfad | bellard | case EN1_CURPAG:
|
396 | 80cabfad | bellard | s->curpag = val; |
397 | 80cabfad | bellard | break;
|
398 | 80cabfad | bellard | case EN1_MULT ... EN1_MULT + 7: |
399 | 80cabfad | bellard | s->mult[offset - EN1_MULT] = val; |
400 | 80cabfad | bellard | break;
|
401 | 80cabfad | bellard | } |
402 | 80cabfad | bellard | } |
403 | 80cabfad | bellard | } |
404 | 80cabfad | bellard | |
405 | b41a2cd1 | bellard | static uint32_t ne2000_ioport_read(void *opaque, uint32_t addr) |
406 | 80cabfad | bellard | { |
407 | b41a2cd1 | bellard | NE2000State *s = opaque; |
408 | 80cabfad | bellard | int offset, page, ret;
|
409 | 80cabfad | bellard | |
410 | 80cabfad | bellard | addr &= 0xf;
|
411 | 80cabfad | bellard | if (addr == E8390_CMD) {
|
412 | 80cabfad | bellard | ret = s->cmd; |
413 | 80cabfad | bellard | } else {
|
414 | 80cabfad | bellard | page = s->cmd >> 6;
|
415 | 80cabfad | bellard | offset = addr | (page << 4);
|
416 | 80cabfad | bellard | switch(offset) {
|
417 | 80cabfad | bellard | case EN0_TSR:
|
418 | 80cabfad | bellard | ret = s->tsr; |
419 | 80cabfad | bellard | break;
|
420 | 80cabfad | bellard | case EN0_BOUNDARY:
|
421 | 80cabfad | bellard | ret = s->boundary; |
422 | 80cabfad | bellard | break;
|
423 | 80cabfad | bellard | case EN0_ISR:
|
424 | 80cabfad | bellard | ret = s->isr; |
425 | 80cabfad | bellard | break;
|
426 | ee9dbb29 | bellard | case EN0_RSARLO:
|
427 | ee9dbb29 | bellard | ret = s->rsar & 0x00ff;
|
428 | ee9dbb29 | bellard | break;
|
429 | ee9dbb29 | bellard | case EN0_RSARHI:
|
430 | ee9dbb29 | bellard | ret = s->rsar >> 8;
|
431 | ee9dbb29 | bellard | break;
|
432 | 80cabfad | bellard | case EN1_PHYS ... EN1_PHYS + 5: |
433 | 80cabfad | bellard | ret = s->phys[offset - EN1_PHYS]; |
434 | 80cabfad | bellard | break;
|
435 | 80cabfad | bellard | case EN1_CURPAG:
|
436 | 80cabfad | bellard | ret = s->curpag; |
437 | 80cabfad | bellard | break;
|
438 | 80cabfad | bellard | case EN1_MULT ... EN1_MULT + 7: |
439 | 80cabfad | bellard | ret = s->mult[offset - EN1_MULT]; |
440 | 80cabfad | bellard | break;
|
441 | 8d6c7eb8 | bellard | case EN0_RSR:
|
442 | 8d6c7eb8 | bellard | ret = s->rsr; |
443 | 8d6c7eb8 | bellard | break;
|
444 | a343df16 | bellard | case EN2_STARTPG:
|
445 | a343df16 | bellard | ret = s->start >> 8;
|
446 | a343df16 | bellard | break;
|
447 | a343df16 | bellard | case EN2_STOPPG:
|
448 | a343df16 | bellard | ret = s->stop >> 8;
|
449 | a343df16 | bellard | break;
|
450 | 80cabfad | bellard | default:
|
451 | 80cabfad | bellard | ret = 0x00;
|
452 | 80cabfad | bellard | break;
|
453 | 80cabfad | bellard | } |
454 | 80cabfad | bellard | } |
455 | 80cabfad | bellard | #ifdef DEBUG_NE2000
|
456 | 80cabfad | bellard | printf("NE2000: read addr=0x%x val=%02x\n", addr, ret);
|
457 | 80cabfad | bellard | #endif
|
458 | 80cabfad | bellard | return ret;
|
459 | 80cabfad | bellard | } |
460 | 80cabfad | bellard | |
461 | ee9dbb29 | bellard | static inline void ne2000_mem_writeb(NE2000State *s, uint32_t addr, |
462 | 69b91039 | bellard | uint32_t val) |
463 | ee9dbb29 | bellard | { |
464 | ee9dbb29 | bellard | if (addr < 32 || |
465 | ee9dbb29 | bellard | (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { |
466 | ee9dbb29 | bellard | s->mem[addr] = val; |
467 | ee9dbb29 | bellard | } |
468 | ee9dbb29 | bellard | } |
469 | ee9dbb29 | bellard | |
470 | ee9dbb29 | bellard | static inline void ne2000_mem_writew(NE2000State *s, uint32_t addr, |
471 | ee9dbb29 | bellard | uint32_t val) |
472 | ee9dbb29 | bellard | { |
473 | ee9dbb29 | bellard | addr &= ~1; /* XXX: check exact behaviour if not even */ |
474 | ee9dbb29 | bellard | if (addr < 32 || |
475 | ee9dbb29 | bellard | (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { |
476 | 69b91039 | bellard | *(uint16_t *)(s->mem + addr) = cpu_to_le16(val); |
477 | 69b91039 | bellard | } |
478 | 69b91039 | bellard | } |
479 | 69b91039 | bellard | |
480 | 69b91039 | bellard | static inline void ne2000_mem_writel(NE2000State *s, uint32_t addr, |
481 | 69b91039 | bellard | uint32_t val) |
482 | 69b91039 | bellard | { |
483 | 57ccbabe | bellard | addr &= ~1; /* XXX: check exact behaviour if not even */ |
484 | 69b91039 | bellard | if (addr < 32 || |
485 | 69b91039 | bellard | (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { |
486 | 57ccbabe | bellard | cpu_to_le32wu((uint32_t *)(s->mem + addr), val); |
487 | ee9dbb29 | bellard | } |
488 | ee9dbb29 | bellard | } |
489 | ee9dbb29 | bellard | |
490 | ee9dbb29 | bellard | static inline uint32_t ne2000_mem_readb(NE2000State *s, uint32_t addr) |
491 | ee9dbb29 | bellard | { |
492 | ee9dbb29 | bellard | if (addr < 32 || |
493 | ee9dbb29 | bellard | (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { |
494 | ee9dbb29 | bellard | return s->mem[addr];
|
495 | ee9dbb29 | bellard | } else {
|
496 | ee9dbb29 | bellard | return 0xff; |
497 | ee9dbb29 | bellard | } |
498 | ee9dbb29 | bellard | } |
499 | ee9dbb29 | bellard | |
500 | ee9dbb29 | bellard | static inline uint32_t ne2000_mem_readw(NE2000State *s, uint32_t addr) |
501 | ee9dbb29 | bellard | { |
502 | ee9dbb29 | bellard | addr &= ~1; /* XXX: check exact behaviour if not even */ |
503 | ee9dbb29 | bellard | if (addr < 32 || |
504 | ee9dbb29 | bellard | (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { |
505 | 69b91039 | bellard | return le16_to_cpu(*(uint16_t *)(s->mem + addr));
|
506 | ee9dbb29 | bellard | } else {
|
507 | ee9dbb29 | bellard | return 0xffff; |
508 | ee9dbb29 | bellard | } |
509 | ee9dbb29 | bellard | } |
510 | ee9dbb29 | bellard | |
511 | 69b91039 | bellard | static inline uint32_t ne2000_mem_readl(NE2000State *s, uint32_t addr) |
512 | 69b91039 | bellard | { |
513 | 57ccbabe | bellard | addr &= ~1; /* XXX: check exact behaviour if not even */ |
514 | 69b91039 | bellard | if (addr < 32 || |
515 | 69b91039 | bellard | (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { |
516 | 57ccbabe | bellard | return le32_to_cpupu((uint32_t *)(s->mem + addr));
|
517 | 69b91039 | bellard | } else {
|
518 | 69b91039 | bellard | return 0xffffffff; |
519 | 69b91039 | bellard | } |
520 | 69b91039 | bellard | } |
521 | 69b91039 | bellard | |
522 | 3df3f6fd | bellard | static inline void ne2000_dma_update(NE2000State *s, int len) |
523 | 3df3f6fd | bellard | { |
524 | 3df3f6fd | bellard | s->rsar += len; |
525 | 3df3f6fd | bellard | /* wrap */
|
526 | 3df3f6fd | bellard | /* XXX: check what to do if rsar > stop */
|
527 | 3df3f6fd | bellard | if (s->rsar == s->stop)
|
528 | 3df3f6fd | bellard | s->rsar = s->start; |
529 | 3df3f6fd | bellard | |
530 | 3df3f6fd | bellard | if (s->rcnt <= len) {
|
531 | 3df3f6fd | bellard | s->rcnt = 0;
|
532 | 3df3f6fd | bellard | /* signal end of transfert */
|
533 | 3df3f6fd | bellard | s->isr |= ENISR_RDC; |
534 | 3df3f6fd | bellard | ne2000_update_irq(s); |
535 | 3df3f6fd | bellard | } else {
|
536 | 3df3f6fd | bellard | s->rcnt -= len; |
537 | 3df3f6fd | bellard | } |
538 | 3df3f6fd | bellard | } |
539 | 3df3f6fd | bellard | |
540 | b41a2cd1 | bellard | static void ne2000_asic_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
541 | 80cabfad | bellard | { |
542 | b41a2cd1 | bellard | NE2000State *s = opaque; |
543 | 80cabfad | bellard | |
544 | 80cabfad | bellard | #ifdef DEBUG_NE2000
|
545 | 80cabfad | bellard | printf("NE2000: asic write val=0x%04x\n", val);
|
546 | 80cabfad | bellard | #endif
|
547 | ee9dbb29 | bellard | if (s->rcnt == 0) |
548 | 3df3f6fd | bellard | return;
|
549 | 80cabfad | bellard | if (s->dcfg & 0x01) { |
550 | 80cabfad | bellard | /* 16 bit access */
|
551 | ee9dbb29 | bellard | ne2000_mem_writew(s, s->rsar, val); |
552 | 3df3f6fd | bellard | ne2000_dma_update(s, 2);
|
553 | 80cabfad | bellard | } else {
|
554 | 80cabfad | bellard | /* 8 bit access */
|
555 | ee9dbb29 | bellard | ne2000_mem_writeb(s, s->rsar, val); |
556 | 3df3f6fd | bellard | ne2000_dma_update(s, 1);
|
557 | 80cabfad | bellard | } |
558 | 80cabfad | bellard | } |
559 | 80cabfad | bellard | |
560 | b41a2cd1 | bellard | static uint32_t ne2000_asic_ioport_read(void *opaque, uint32_t addr) |
561 | 80cabfad | bellard | { |
562 | b41a2cd1 | bellard | NE2000State *s = opaque; |
563 | 80cabfad | bellard | int ret;
|
564 | 80cabfad | bellard | |
565 | 80cabfad | bellard | if (s->dcfg & 0x01) { |
566 | 80cabfad | bellard | /* 16 bit access */
|
567 | ee9dbb29 | bellard | ret = ne2000_mem_readw(s, s->rsar); |
568 | 3df3f6fd | bellard | ne2000_dma_update(s, 2);
|
569 | 80cabfad | bellard | } else {
|
570 | 80cabfad | bellard | /* 8 bit access */
|
571 | ee9dbb29 | bellard | ret = ne2000_mem_readb(s, s->rsar); |
572 | 3df3f6fd | bellard | ne2000_dma_update(s, 1);
|
573 | 80cabfad | bellard | } |
574 | 80cabfad | bellard | #ifdef DEBUG_NE2000
|
575 | 80cabfad | bellard | printf("NE2000: asic read val=0x%04x\n", ret);
|
576 | 80cabfad | bellard | #endif
|
577 | 80cabfad | bellard | return ret;
|
578 | 80cabfad | bellard | } |
579 | 80cabfad | bellard | |
580 | 69b91039 | bellard | static void ne2000_asic_ioport_writel(void *opaque, uint32_t addr, uint32_t val) |
581 | 69b91039 | bellard | { |
582 | 69b91039 | bellard | NE2000State *s = opaque; |
583 | 69b91039 | bellard | |
584 | 69b91039 | bellard | #ifdef DEBUG_NE2000
|
585 | 69b91039 | bellard | printf("NE2000: asic writel val=0x%04x\n", val);
|
586 | 69b91039 | bellard | #endif
|
587 | 69b91039 | bellard | if (s->rcnt == 0) |
588 | 3df3f6fd | bellard | return;
|
589 | 69b91039 | bellard | /* 32 bit access */
|
590 | 69b91039 | bellard | ne2000_mem_writel(s, s->rsar, val); |
591 | 3df3f6fd | bellard | ne2000_dma_update(s, 4);
|
592 | 69b91039 | bellard | } |
593 | 69b91039 | bellard | |
594 | 69b91039 | bellard | static uint32_t ne2000_asic_ioport_readl(void *opaque, uint32_t addr) |
595 | 69b91039 | bellard | { |
596 | 69b91039 | bellard | NE2000State *s = opaque; |
597 | 69b91039 | bellard | int ret;
|
598 | 69b91039 | bellard | |
599 | 69b91039 | bellard | /* 32 bit access */
|
600 | 69b91039 | bellard | ret = ne2000_mem_readl(s, s->rsar); |
601 | 3df3f6fd | bellard | ne2000_dma_update(s, 4);
|
602 | 69b91039 | bellard | #ifdef DEBUG_NE2000
|
603 | 69b91039 | bellard | printf("NE2000: asic readl val=0x%04x\n", ret);
|
604 | 69b91039 | bellard | #endif
|
605 | 69b91039 | bellard | return ret;
|
606 | 69b91039 | bellard | } |
607 | 69b91039 | bellard | |
608 | b41a2cd1 | bellard | static void ne2000_reset_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
609 | 80cabfad | bellard | { |
610 | 80cabfad | bellard | /* nothing to do (end of reset pulse) */
|
611 | 80cabfad | bellard | } |
612 | 80cabfad | bellard | |
613 | b41a2cd1 | bellard | static uint32_t ne2000_reset_ioport_read(void *opaque, uint32_t addr) |
614 | 80cabfad | bellard | { |
615 | b41a2cd1 | bellard | NE2000State *s = opaque; |
616 | 80cabfad | bellard | ne2000_reset(s); |
617 | 80cabfad | bellard | return 0; |
618 | 80cabfad | bellard | } |
619 | 80cabfad | bellard | |
620 | 30ca2aab | bellard | static void ne2000_save(QEMUFile* f,void* opaque) |
621 | 30ca2aab | bellard | { |
622 | 30ca2aab | bellard | NE2000State* s=(NE2000State*)opaque; |
623 | 30ca2aab | bellard | |
624 | 30ca2aab | bellard | qemu_put_8s(f, &s->cmd); |
625 | 30ca2aab | bellard | qemu_put_be32s(f, &s->start); |
626 | 30ca2aab | bellard | qemu_put_be32s(f, &s->stop); |
627 | 30ca2aab | bellard | qemu_put_8s(f, &s->boundary); |
628 | 30ca2aab | bellard | qemu_put_8s(f, &s->tsr); |
629 | 30ca2aab | bellard | qemu_put_8s(f, &s->tpsr); |
630 | 30ca2aab | bellard | qemu_put_be16s(f, &s->tcnt); |
631 | 30ca2aab | bellard | qemu_put_be16s(f, &s->rcnt); |
632 | 30ca2aab | bellard | qemu_put_be32s(f, &s->rsar); |
633 | 30ca2aab | bellard | qemu_put_8s(f, &s->rsr); |
634 | 30ca2aab | bellard | qemu_put_8s(f, &s->isr); |
635 | 30ca2aab | bellard | qemu_put_8s(f, &s->dcfg); |
636 | 30ca2aab | bellard | qemu_put_8s(f, &s->imr); |
637 | 30ca2aab | bellard | qemu_put_buffer(f, s->phys, 6);
|
638 | 30ca2aab | bellard | qemu_put_8s(f, &s->curpag); |
639 | 30ca2aab | bellard | qemu_put_buffer(f, s->mult, 8);
|
640 | 30ca2aab | bellard | qemu_put_be32s(f, &s->irq); |
641 | 30ca2aab | bellard | qemu_put_buffer(f, s->mem, NE2000_MEM_SIZE); |
642 | 30ca2aab | bellard | } |
643 | 30ca2aab | bellard | |
644 | 30ca2aab | bellard | static int ne2000_load(QEMUFile* f,void* opaque,int version_id) |
645 | 30ca2aab | bellard | { |
646 | 30ca2aab | bellard | NE2000State* s=(NE2000State*)opaque; |
647 | 30ca2aab | bellard | |
648 | 30ca2aab | bellard | if (version_id != 1) |
649 | 30ca2aab | bellard | return -EINVAL;
|
650 | 30ca2aab | bellard | |
651 | 30ca2aab | bellard | qemu_get_8s(f, &s->cmd); |
652 | 30ca2aab | bellard | qemu_get_be32s(f, &s->start); |
653 | 30ca2aab | bellard | qemu_get_be32s(f, &s->stop); |
654 | 30ca2aab | bellard | qemu_get_8s(f, &s->boundary); |
655 | 30ca2aab | bellard | qemu_get_8s(f, &s->tsr); |
656 | 30ca2aab | bellard | qemu_get_8s(f, &s->tpsr); |
657 | 30ca2aab | bellard | qemu_get_be16s(f, &s->tcnt); |
658 | 30ca2aab | bellard | qemu_get_be16s(f, &s->rcnt); |
659 | 30ca2aab | bellard | qemu_get_be32s(f, &s->rsar); |
660 | 30ca2aab | bellard | qemu_get_8s(f, &s->rsr); |
661 | 30ca2aab | bellard | qemu_get_8s(f, &s->isr); |
662 | 30ca2aab | bellard | qemu_get_8s(f, &s->dcfg); |
663 | 30ca2aab | bellard | qemu_get_8s(f, &s->imr); |
664 | 30ca2aab | bellard | qemu_get_buffer(f, s->phys, 6);
|
665 | 30ca2aab | bellard | qemu_get_8s(f, &s->curpag); |
666 | 30ca2aab | bellard | qemu_get_buffer(f, s->mult, 8);
|
667 | 30ca2aab | bellard | qemu_get_be32s(f, &s->irq); |
668 | 30ca2aab | bellard | qemu_get_buffer(f, s->mem, NE2000_MEM_SIZE); |
669 | 30ca2aab | bellard | |
670 | 30ca2aab | bellard | return 0; |
671 | 30ca2aab | bellard | } |
672 | 30ca2aab | bellard | |
673 | 7c9d8e07 | bellard | void isa_ne2000_init(int base, int irq, NICInfo *nd) |
674 | 80cabfad | bellard | { |
675 | b41a2cd1 | bellard | NE2000State *s; |
676 | 7c9d8e07 | bellard | |
677 | b41a2cd1 | bellard | s = qemu_mallocz(sizeof(NE2000State));
|
678 | b41a2cd1 | bellard | if (!s)
|
679 | b41a2cd1 | bellard | return;
|
680 | b41a2cd1 | bellard | |
681 | b41a2cd1 | bellard | register_ioport_write(base, 16, 1, ne2000_ioport_write, s); |
682 | b41a2cd1 | bellard | register_ioport_read(base, 16, 1, ne2000_ioport_read, s); |
683 | 80cabfad | bellard | |
684 | b41a2cd1 | bellard | register_ioport_write(base + 0x10, 1, 1, ne2000_asic_ioport_write, s); |
685 | b41a2cd1 | bellard | register_ioport_read(base + 0x10, 1, 1, ne2000_asic_ioport_read, s); |
686 | b41a2cd1 | bellard | register_ioport_write(base + 0x10, 2, 2, ne2000_asic_ioport_write, s); |
687 | b41a2cd1 | bellard | register_ioport_read(base + 0x10, 2, 2, ne2000_asic_ioport_read, s); |
688 | 80cabfad | bellard | |
689 | b41a2cd1 | bellard | register_ioport_write(base + 0x1f, 1, 1, ne2000_reset_ioport_write, s); |
690 | b41a2cd1 | bellard | register_ioport_read(base + 0x1f, 1, 1, ne2000_reset_ioport_read, s); |
691 | 80cabfad | bellard | s->irq = irq; |
692 | 7c9d8e07 | bellard | memcpy(s->macaddr, nd->macaddr, 6);
|
693 | 80cabfad | bellard | |
694 | 80cabfad | bellard | ne2000_reset(s); |
695 | b41a2cd1 | bellard | |
696 | 7c9d8e07 | bellard | s->vc = qemu_new_vlan_client(nd->vlan, ne2000_receive, s); |
697 | 7c9d8e07 | bellard | |
698 | 7c9d8e07 | bellard | snprintf(s->vc->info_str, sizeof(s->vc->info_str),
|
699 | 7c9d8e07 | bellard | "ne2000 macaddr=%02x:%02x:%02x:%02x:%02x:%02x",
|
700 | 7c9d8e07 | bellard | s->macaddr[0],
|
701 | 7c9d8e07 | bellard | s->macaddr[1],
|
702 | 7c9d8e07 | bellard | s->macaddr[2],
|
703 | 7c9d8e07 | bellard | s->macaddr[3],
|
704 | 7c9d8e07 | bellard | s->macaddr[4],
|
705 | 7c9d8e07 | bellard | s->macaddr[5]);
|
706 | 7c9d8e07 | bellard | |
707 | 30ca2aab | bellard | register_savevm("ne2000", 0, 1, ne2000_save, ne2000_load, s); |
708 | 80cabfad | bellard | } |
709 | 69b91039 | bellard | |
710 | 69b91039 | bellard | /***********************************************************/
|
711 | 69b91039 | bellard | /* PCI NE2000 definitions */
|
712 | 69b91039 | bellard | |
713 | 69b91039 | bellard | typedef struct PCINE2000State { |
714 | 69b91039 | bellard | PCIDevice dev; |
715 | 69b91039 | bellard | NE2000State ne2000; |
716 | 69b91039 | bellard | } PCINE2000State; |
717 | 69b91039 | bellard | |
718 | 69b91039 | bellard | static void ne2000_map(PCIDevice *pci_dev, int region_num, |
719 | 69b91039 | bellard | uint32_t addr, uint32_t size, int type)
|
720 | 69b91039 | bellard | { |
721 | 69b91039 | bellard | PCINE2000State *d = (PCINE2000State *)pci_dev; |
722 | 69b91039 | bellard | NE2000State *s = &d->ne2000; |
723 | 69b91039 | bellard | |
724 | 69b91039 | bellard | register_ioport_write(addr, 16, 1, ne2000_ioport_write, s); |
725 | 69b91039 | bellard | register_ioport_read(addr, 16, 1, ne2000_ioport_read, s); |
726 | 69b91039 | bellard | |
727 | 69b91039 | bellard | register_ioport_write(addr + 0x10, 1, 1, ne2000_asic_ioport_write, s); |
728 | 69b91039 | bellard | register_ioport_read(addr + 0x10, 1, 1, ne2000_asic_ioport_read, s); |
729 | 69b91039 | bellard | register_ioport_write(addr + 0x10, 2, 2, ne2000_asic_ioport_write, s); |
730 | 69b91039 | bellard | register_ioport_read(addr + 0x10, 2, 2, ne2000_asic_ioport_read, s); |
731 | 69b91039 | bellard | register_ioport_write(addr + 0x10, 4, 4, ne2000_asic_ioport_writel, s); |
732 | 69b91039 | bellard | register_ioport_read(addr + 0x10, 4, 4, ne2000_asic_ioport_readl, s); |
733 | 69b91039 | bellard | |
734 | 69b91039 | bellard | register_ioport_write(addr + 0x1f, 1, 1, ne2000_reset_ioport_write, s); |
735 | 69b91039 | bellard | register_ioport_read(addr + 0x1f, 1, 1, ne2000_reset_ioport_read, s); |
736 | 69b91039 | bellard | } |
737 | 69b91039 | bellard | |
738 | 7c9d8e07 | bellard | void pci_ne2000_init(PCIBus *bus, NICInfo *nd)
|
739 | 69b91039 | bellard | { |
740 | 69b91039 | bellard | PCINE2000State *d; |
741 | 69b91039 | bellard | NE2000State *s; |
742 | 69b91039 | bellard | uint8_t *pci_conf; |
743 | 69b91039 | bellard | |
744 | 46e50e9d | bellard | d = (PCINE2000State *)pci_register_device(bus, |
745 | 46e50e9d | bellard | "NE2000", sizeof(PCINE2000State), |
746 | 46e50e9d | bellard | -1,
|
747 | 4a9c9687 | bellard | NULL, NULL); |
748 | 69b91039 | bellard | pci_conf = d->dev.config; |
749 | 69b91039 | bellard | pci_conf[0x00] = 0xec; // Realtek 8029 |
750 | 69b91039 | bellard | pci_conf[0x01] = 0x10; |
751 | 69b91039 | bellard | pci_conf[0x02] = 0x29; |
752 | 69b91039 | bellard | pci_conf[0x03] = 0x80; |
753 | 69b91039 | bellard | pci_conf[0x0a] = 0x00; // ethernet network controller |
754 | 69b91039 | bellard | pci_conf[0x0b] = 0x02; |
755 | 69b91039 | bellard | pci_conf[0x0e] = 0x00; // header_type |
756 | 4a9c9687 | bellard | pci_conf[0x3d] = 1; // interrupt pin 0 |
757 | 69b91039 | bellard | |
758 | 30ca2aab | bellard | pci_register_io_region(&d->dev, 0, 0x100, |
759 | 69b91039 | bellard | PCI_ADDRESS_SPACE_IO, ne2000_map); |
760 | 69b91039 | bellard | s = &d->ne2000; |
761 | 4a9c9687 | bellard | s->irq = 16; // PCI interrupt |
762 | 4a9c9687 | bellard | s->pci_dev = (PCIDevice *)d; |
763 | 7c9d8e07 | bellard | memcpy(s->macaddr, nd->macaddr, 6);
|
764 | 69b91039 | bellard | ne2000_reset(s); |
765 | 7c9d8e07 | bellard | s->vc = qemu_new_vlan_client(nd->vlan, ne2000_receive, s); |
766 | 7c9d8e07 | bellard | |
767 | 7c9d8e07 | bellard | snprintf(s->vc->info_str, sizeof(s->vc->info_str),
|
768 | 7c9d8e07 | bellard | "ne2000 pci macaddr=%02x:%02x:%02x:%02x:%02x:%02x",
|
769 | 7c9d8e07 | bellard | s->macaddr[0],
|
770 | 7c9d8e07 | bellard | s->macaddr[1],
|
771 | 7c9d8e07 | bellard | s->macaddr[2],
|
772 | 7c9d8e07 | bellard | s->macaddr[3],
|
773 | 7c9d8e07 | bellard | s->macaddr[4],
|
774 | 7c9d8e07 | bellard | s->macaddr[5]);
|
775 | 7c9d8e07 | bellard | |
776 | 30ca2aab | bellard | /* XXX: instance number ? */
|
777 | 30ca2aab | bellard | register_savevm("ne2000", 0, 1, ne2000_save, ne2000_load, s); |
778 | 30ca2aab | bellard | register_savevm("ne2000_pci", 0, 1, generic_pci_save, generic_pci_load, |
779 | 30ca2aab | bellard | &d->dev); |
780 | 69b91039 | bellard | } |