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/*
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 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions are met:
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 *     * Redistributions of source code must retain the above copyright
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 *       notice, this list of conditions and the following disclaimer.
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 *     * Redistributions in binary form must reproduce the above copyright
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 *       notice, this list of conditions and the following disclaimer in the
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 *       documentation and/or other materials provided with the distribution.
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 *     * Neither the name of the Open Source and Linux Lab nor the
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 *       names of its contributors may be used to endorse or promote products
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 *       derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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#include "cpu.h"
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#include "dyngen-exec.h"
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#include "helpers.h"
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#include "host-utils.h"
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static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
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        void *retaddr);
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#define ALIGNED_ONLY
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#define MMUSUFFIX _mmu
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#define SHIFT 0
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#include "softmmu_template.h"
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#define SHIFT 1
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#include "softmmu_template.h"
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#define SHIFT 2
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#include "softmmu_template.h"
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#define SHIFT 3
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#include "softmmu_template.h"
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static void do_restore_state(void *pc_ptr)
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{
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    TranslationBlock *tb;
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    uint32_t pc = (uint32_t)(intptr_t)pc_ptr;
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    tb = tb_find_pc(pc);
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    if (tb) {
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        cpu_restore_state(tb, env, pc);
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    }
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}
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static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
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        void *retaddr)
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{
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    if (xtensa_option_enabled(env->config, XTENSA_OPTION_UNALIGNED_EXCEPTION) &&
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            !xtensa_option_enabled(env->config, XTENSA_OPTION_HW_ALIGNMENT)) {
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        do_restore_state(retaddr);
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        HELPER(exception_cause_vaddr)(
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                env->pc, LOAD_STORE_ALIGNMENT_CAUSE, addr);
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    }
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}
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void tlb_fill(target_ulong vaddr, int is_write, int mmu_idx, void *retaddr)
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{
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    CPUState *saved_env = env;
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    env = cpu_single_env;
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    {
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        uint32_t paddr;
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        uint32_t page_size;
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        unsigned access;
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        int ret = xtensa_get_physical_addr(env, vaddr, is_write, mmu_idx,
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                &paddr, &page_size, &access);
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        qemu_log("%s(%08x, %d, %d) -> %08x, ret = %d\n", __func__,
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                vaddr, is_write, mmu_idx, paddr, ret);
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        if (ret == 0) {
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            tlb_set_page(env,
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                    vaddr & TARGET_PAGE_MASK,
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                    paddr & TARGET_PAGE_MASK,
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                    access, mmu_idx, page_size);
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        } else {
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            do_restore_state(retaddr);
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            HELPER(exception_cause_vaddr)(env->pc, ret, vaddr);
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        }
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    }
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    env = saved_env;
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}
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void HELPER(exception)(uint32_t excp)
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{
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    env->exception_index = excp;
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    cpu_loop_exit(env);
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}
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void HELPER(exception_cause)(uint32_t pc, uint32_t cause)
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{
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    uint32_t vector;
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    env->pc = pc;
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    if (env->sregs[PS] & PS_EXCM) {
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        if (env->config->ndepc) {
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            env->sregs[DEPC] = pc;
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        } else {
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            env->sregs[EPC1] = pc;
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        }
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        vector = EXC_DOUBLE;
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    } else {
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        env->sregs[EPC1] = pc;
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        vector = (env->sregs[PS] & PS_UM) ? EXC_USER : EXC_KERNEL;
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    }
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    env->sregs[EXCCAUSE] = cause;
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    env->sregs[PS] |= PS_EXCM;
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    HELPER(exception)(vector);
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}
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void HELPER(exception_cause_vaddr)(uint32_t pc, uint32_t cause, uint32_t vaddr)
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{
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    env->sregs[EXCVADDR] = vaddr;
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    HELPER(exception_cause)(pc, cause);
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}
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uint32_t HELPER(nsa)(uint32_t v)
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{
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    if (v & 0x80000000) {
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        v = ~v;
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    }
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    return v ? clz32(v) - 1 : 31;
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}
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uint32_t HELPER(nsau)(uint32_t v)
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{
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    return v ? clz32(v) : 32;
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}
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static void copy_window_from_phys(CPUState *env,
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        uint32_t window, uint32_t phys, uint32_t n)
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{
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    assert(phys < env->config->nareg);
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    if (phys + n <= env->config->nareg) {
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        memcpy(env->regs + window, env->phys_regs + phys,
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                n * sizeof(uint32_t));
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    } else {
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        uint32_t n1 = env->config->nareg - phys;
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        memcpy(env->regs + window, env->phys_regs + phys,
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                n1 * sizeof(uint32_t));
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        memcpy(env->regs + window + n1, env->phys_regs,
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                (n - n1) * sizeof(uint32_t));
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    }
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}
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static void copy_phys_from_window(CPUState *env,
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        uint32_t phys, uint32_t window, uint32_t n)
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{
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    assert(phys < env->config->nareg);
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    if (phys + n <= env->config->nareg) {
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        memcpy(env->phys_regs + phys, env->regs + window,
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                n * sizeof(uint32_t));
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    } else {
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        uint32_t n1 = env->config->nareg - phys;
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        memcpy(env->phys_regs + phys, env->regs + window,
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                n1 * sizeof(uint32_t));
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        memcpy(env->phys_regs, env->regs + window + n1,
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                (n - n1) * sizeof(uint32_t));
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    }
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}
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static inline unsigned windowbase_bound(unsigned a, const CPUState *env)
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{
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    return a & (env->config->nareg / 4 - 1);
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}
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static inline unsigned windowstart_bit(unsigned a, const CPUState *env)
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{
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    return 1 << windowbase_bound(a, env);
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}
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void xtensa_sync_window_from_phys(CPUState *env)
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{
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    copy_window_from_phys(env, 0, env->sregs[WINDOW_BASE] * 4, 16);
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}
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void xtensa_sync_phys_from_window(CPUState *env)
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{
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    copy_phys_from_window(env, env->sregs[WINDOW_BASE] * 4, 0, 16);
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}
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static void rotate_window_abs(uint32_t position)
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{
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    xtensa_sync_phys_from_window(env);
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    env->sregs[WINDOW_BASE] = windowbase_bound(position, env);
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    xtensa_sync_window_from_phys(env);
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}
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static void rotate_window(uint32_t delta)
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{
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    rotate_window_abs(env->sregs[WINDOW_BASE] + delta);
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}
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void HELPER(wsr_windowbase)(uint32_t v)
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{
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    rotate_window_abs(v);
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}
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void HELPER(entry)(uint32_t pc, uint32_t s, uint32_t imm)
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{
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    int callinc = (env->sregs[PS] & PS_CALLINC) >> PS_CALLINC_SHIFT;
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    if (s > 3 || ((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) != 0) {
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        qemu_log("Illegal entry instruction(pc = %08x), PS = %08x\n",
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                pc, env->sregs[PS]);
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        HELPER(exception_cause)(pc, ILLEGAL_INSTRUCTION_CAUSE);
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    } else {
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        env->regs[(callinc << 2) | (s & 3)] = env->regs[s] - (imm << 3);
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        rotate_window(callinc);
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        env->sregs[WINDOW_START] |=
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            windowstart_bit(env->sregs[WINDOW_BASE], env);
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    }
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}
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void HELPER(window_check)(uint32_t pc, uint32_t w)
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{
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    uint32_t windowbase = windowbase_bound(env->sregs[WINDOW_BASE], env);
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    uint32_t windowstart = env->sregs[WINDOW_START];
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    uint32_t m, n;
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    if ((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) {
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        return;
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    }
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    for (n = 1; ; ++n) {
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        if (n > w) {
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            return;
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        }
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        if (windowstart & windowstart_bit(windowbase + n, env)) {
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            break;
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        }
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    }
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    m = windowbase_bound(windowbase + n, env);
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    rotate_window(n);
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    env->sregs[PS] = (env->sregs[PS] & ~PS_OWB) |
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        (windowbase << PS_OWB_SHIFT) | PS_EXCM;
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    env->sregs[EPC1] = env->pc = pc;
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    if (windowstart & windowstart_bit(m + 1, env)) {
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        HELPER(exception)(EXC_WINDOW_OVERFLOW4);
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    } else if (windowstart & windowstart_bit(m + 2, env)) {
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        HELPER(exception)(EXC_WINDOW_OVERFLOW8);
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    } else {
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        HELPER(exception)(EXC_WINDOW_OVERFLOW12);
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    }
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}
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uint32_t HELPER(retw)(uint32_t pc)
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{
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    int n = (env->regs[0] >> 30) & 0x3;
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    int m = 0;
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    uint32_t windowbase = windowbase_bound(env->sregs[WINDOW_BASE], env);
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    uint32_t windowstart = env->sregs[WINDOW_START];
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    uint32_t ret_pc = 0;
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    if (windowstart & windowstart_bit(windowbase - 1, env)) {
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        m = 1;
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    } else if (windowstart & windowstart_bit(windowbase - 2, env)) {
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        m = 2;
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    } else if (windowstart & windowstart_bit(windowbase - 3, env)) {
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        m = 3;
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    }
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    if (n == 0 || (m != 0 && m != n) ||
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            ((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) != 0) {
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        qemu_log("Illegal retw instruction(pc = %08x), "
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                "PS = %08x, m = %d, n = %d\n",
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                pc, env->sregs[PS], m, n);
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        HELPER(exception_cause)(pc, ILLEGAL_INSTRUCTION_CAUSE);
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    } else {
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        int owb = windowbase;
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        ret_pc = (pc & 0xc0000000) | (env->regs[0] & 0x3fffffff);
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        rotate_window(-n);
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        if (windowstart & windowstart_bit(env->sregs[WINDOW_BASE], env)) {
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            env->sregs[WINDOW_START] &= ~windowstart_bit(owb, env);
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        } else {
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            /* window underflow */
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            env->sregs[PS] = (env->sregs[PS] & ~PS_OWB) |
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                (windowbase << PS_OWB_SHIFT) | PS_EXCM;
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            env->sregs[EPC1] = env->pc = pc;
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            if (n == 1) {
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                HELPER(exception)(EXC_WINDOW_UNDERFLOW4);
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            } else if (n == 2) {
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                HELPER(exception)(EXC_WINDOW_UNDERFLOW8);
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            } else if (n == 3) {
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                HELPER(exception)(EXC_WINDOW_UNDERFLOW12);
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            }
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        }
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    }
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    return ret_pc;
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}
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void HELPER(rotw)(uint32_t imm4)
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{
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    rotate_window(imm4);
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}
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void HELPER(restore_owb)(void)
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{
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    rotate_window_abs((env->sregs[PS] & PS_OWB) >> PS_OWB_SHIFT);
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}
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void HELPER(movsp)(uint32_t pc)
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{
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    if ((env->sregs[WINDOW_START] &
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            (windowstart_bit(env->sregs[WINDOW_BASE] - 3, env) |
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             windowstart_bit(env->sregs[WINDOW_BASE] - 2, env) |
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             windowstart_bit(env->sregs[WINDOW_BASE] - 1, env))) == 0) {
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        HELPER(exception_cause)(pc, ALLOCA_CAUSE);
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    }
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}
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void HELPER(wsr_lbeg)(uint32_t v)
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{
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    if (env->sregs[LBEG] != v) {
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        tb_invalidate_phys_page_range(
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                env->sregs[LEND] - 1, env->sregs[LEND], 0);
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        env->sregs[LBEG] = v;
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    }
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}
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void HELPER(wsr_lend)(uint32_t v)
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{
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    if (env->sregs[LEND] != v) {
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        tb_invalidate_phys_page_range(
349 797d780b Max Filippov
                env->sregs[LEND] - 1, env->sregs[LEND], 0);
350 797d780b Max Filippov
        env->sregs[LEND] = v;
351 797d780b Max Filippov
        tb_invalidate_phys_page_range(
352 797d780b Max Filippov
                env->sregs[LEND] - 1, env->sregs[LEND], 0);
353 797d780b Max Filippov
    }
354 797d780b Max Filippov
}
355 797d780b Max Filippov
356 553e44f9 Max Filippov
void HELPER(dump_state)(void)
357 553e44f9 Max Filippov
{
358 553e44f9 Max Filippov
    cpu_dump_state(env, stderr, fprintf, 0);
359 553e44f9 Max Filippov
}
360 b994e91b Max Filippov
361 b994e91b Max Filippov
void HELPER(waiti)(uint32_t pc, uint32_t intlevel)
362 b994e91b Max Filippov
{
363 b994e91b Max Filippov
    env->pc = pc;
364 b994e91b Max Filippov
    env->sregs[PS] = (env->sregs[PS] & ~PS_INTLEVEL) |
365 b994e91b Max Filippov
        (intlevel << PS_INTLEVEL_SHIFT);
366 b994e91b Max Filippov
    check_interrupts(env);
367 b994e91b Max Filippov
    if (env->pending_irq_level) {
368 b994e91b Max Filippov
        cpu_loop_exit(env);
369 b994e91b Max Filippov
        return;
370 b994e91b Max Filippov
    }
371 b994e91b Max Filippov
372 b994e91b Max Filippov
    if (xtensa_option_enabled(env->config, XTENSA_OPTION_TIMER_INTERRUPT)) {
373 b994e91b Max Filippov
        int i;
374 b994e91b Max Filippov
        uint32_t wake_ccount = env->sregs[CCOUNT] - 1;
375 b994e91b Max Filippov
376 b994e91b Max Filippov
        for (i = 0; i < env->config->nccompare; ++i) {
377 b994e91b Max Filippov
            if (env->sregs[CCOMPARE + i] - env->sregs[CCOUNT] <
378 b994e91b Max Filippov
                    wake_ccount - env->sregs[CCOUNT]) {
379 b994e91b Max Filippov
                wake_ccount = env->sregs[CCOMPARE + i];
380 b994e91b Max Filippov
            }
381 b994e91b Max Filippov
        }
382 b994e91b Max Filippov
        env->wake_ccount = wake_ccount;
383 b994e91b Max Filippov
        qemu_mod_timer(env->ccompare_timer, qemu_get_clock_ns(vm_clock) +
384 b994e91b Max Filippov
                muldiv64(wake_ccount - env->sregs[CCOUNT],
385 b994e91b Max Filippov
                    1000000, env->config->clock_freq_khz));
386 b994e91b Max Filippov
    }
387 b994e91b Max Filippov
    env->halt_clock = qemu_get_clock_ns(vm_clock);
388 b994e91b Max Filippov
    env->halted = 1;
389 b994e91b Max Filippov
    HELPER(exception)(EXCP_HLT);
390 b994e91b Max Filippov
}
391 b994e91b Max Filippov
392 b994e91b Max Filippov
void HELPER(timer_irq)(uint32_t id, uint32_t active)
393 b994e91b Max Filippov
{
394 b994e91b Max Filippov
    xtensa_timer_irq(env, id, active);
395 b994e91b Max Filippov
}
396 b994e91b Max Filippov
397 b994e91b Max Filippov
void HELPER(advance_ccount)(uint32_t d)
398 b994e91b Max Filippov
{
399 b994e91b Max Filippov
    xtensa_advance_ccount(env, d);
400 b994e91b Max Filippov
}
401 b994e91b Max Filippov
402 b994e91b Max Filippov
void HELPER(check_interrupts)(CPUState *env)
403 b994e91b Max Filippov
{
404 b994e91b Max Filippov
    check_interrupts(env);
405 b994e91b Max Filippov
}
406 b67ea0cd Max Filippov
407 b67ea0cd Max Filippov
void HELPER(wsr_rasid)(uint32_t v)
408 b67ea0cd Max Filippov
{
409 b67ea0cd Max Filippov
    v = (v & 0xffffff00) | 0x1;
410 b67ea0cd Max Filippov
    if (v != env->sregs[RASID]) {
411 b67ea0cd Max Filippov
        env->sregs[RASID] = v;
412 b67ea0cd Max Filippov
        tlb_flush(env, 1);
413 b67ea0cd Max Filippov
    }
414 b67ea0cd Max Filippov
}
415 b67ea0cd Max Filippov
416 b67ea0cd Max Filippov
static uint32_t get_page_size(const CPUState *env, bool dtlb, uint32_t way)
417 b67ea0cd Max Filippov
{
418 b67ea0cd Max Filippov
    uint32_t tlbcfg = env->sregs[dtlb ? DTLBCFG : ITLBCFG];
419 b67ea0cd Max Filippov
420 b67ea0cd Max Filippov
    switch (way) {
421 b67ea0cd Max Filippov
    case 4:
422 b67ea0cd Max Filippov
        return (tlbcfg >> 16) & 0x3;
423 b67ea0cd Max Filippov
424 b67ea0cd Max Filippov
    case 5:
425 b67ea0cd Max Filippov
        return (tlbcfg >> 20) & 0x1;
426 b67ea0cd Max Filippov
427 b67ea0cd Max Filippov
    case 6:
428 b67ea0cd Max Filippov
        return (tlbcfg >> 24) & 0x1;
429 b67ea0cd Max Filippov
430 b67ea0cd Max Filippov
    default:
431 b67ea0cd Max Filippov
        return 0;
432 b67ea0cd Max Filippov
    }
433 b67ea0cd Max Filippov
}
434 b67ea0cd Max Filippov
435 b67ea0cd Max Filippov
/*!
436 b67ea0cd Max Filippov
 * Get bit mask for the virtual address bits translated by the TLB way
437 b67ea0cd Max Filippov
 */
438 b67ea0cd Max Filippov
uint32_t xtensa_tlb_get_addr_mask(const CPUState *env, bool dtlb, uint32_t way)
439 b67ea0cd Max Filippov
{
440 b67ea0cd Max Filippov
    if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
441 b67ea0cd Max Filippov
        bool varway56 = dtlb ?
442 b67ea0cd Max Filippov
            env->config->dtlb.varway56 :
443 b67ea0cd Max Filippov
            env->config->itlb.varway56;
444 b67ea0cd Max Filippov
445 b67ea0cd Max Filippov
        switch (way) {
446 b67ea0cd Max Filippov
        case 4:
447 b67ea0cd Max Filippov
            return 0xfff00000 << get_page_size(env, dtlb, way) * 2;
448 b67ea0cd Max Filippov
449 b67ea0cd Max Filippov
        case 5:
450 b67ea0cd Max Filippov
            if (varway56) {
451 b67ea0cd Max Filippov
                return 0xf8000000 << get_page_size(env, dtlb, way);
452 b67ea0cd Max Filippov
            } else {
453 b67ea0cd Max Filippov
                return 0xf8000000;
454 b67ea0cd Max Filippov
            }
455 b67ea0cd Max Filippov
456 b67ea0cd Max Filippov
        case 6:
457 b67ea0cd Max Filippov
            if (varway56) {
458 b67ea0cd Max Filippov
                return 0xf0000000 << (1 - get_page_size(env, dtlb, way));
459 b67ea0cd Max Filippov
            } else {
460 b67ea0cd Max Filippov
                return 0xf0000000;
461 b67ea0cd Max Filippov
            }
462 b67ea0cd Max Filippov
463 b67ea0cd Max Filippov
        default:
464 b67ea0cd Max Filippov
            return 0xfffff000;
465 b67ea0cd Max Filippov
        }
466 b67ea0cd Max Filippov
    } else {
467 b67ea0cd Max Filippov
        return REGION_PAGE_MASK;
468 b67ea0cd Max Filippov
    }
469 b67ea0cd Max Filippov
}
470 b67ea0cd Max Filippov
471 b67ea0cd Max Filippov
/*!
472 b67ea0cd Max Filippov
 * Get bit mask for the 'VPN without index' field.
473 b67ea0cd Max Filippov
 * See ISA, 4.6.5.6, data format for RxTLB0
474 b67ea0cd Max Filippov
 */
475 b67ea0cd Max Filippov
static uint32_t get_vpn_mask(const CPUState *env, bool dtlb, uint32_t way)
476 b67ea0cd Max Filippov
{
477 b67ea0cd Max Filippov
    if (way < 4) {
478 b67ea0cd Max Filippov
        bool is32 = (dtlb ?
479 b67ea0cd Max Filippov
                env->config->dtlb.nrefillentries :
480 b67ea0cd Max Filippov
                env->config->itlb.nrefillentries) == 32;
481 b67ea0cd Max Filippov
        return is32 ? 0xffff8000 : 0xffffc000;
482 b67ea0cd Max Filippov
    } else if (way == 4) {
483 b67ea0cd Max Filippov
        return xtensa_tlb_get_addr_mask(env, dtlb, way) << 2;
484 b67ea0cd Max Filippov
    } else if (way <= 6) {
485 b67ea0cd Max Filippov
        uint32_t mask = xtensa_tlb_get_addr_mask(env, dtlb, way);
486 b67ea0cd Max Filippov
        bool varway56 = dtlb ?
487 b67ea0cd Max Filippov
            env->config->dtlb.varway56 :
488 b67ea0cd Max Filippov
            env->config->itlb.varway56;
489 b67ea0cd Max Filippov
490 b67ea0cd Max Filippov
        if (varway56) {
491 b67ea0cd Max Filippov
            return mask << (way == 5 ? 2 : 3);
492 b67ea0cd Max Filippov
        } else {
493 b67ea0cd Max Filippov
            return mask << 1;
494 b67ea0cd Max Filippov
        }
495 b67ea0cd Max Filippov
    } else {
496 b67ea0cd Max Filippov
        return 0xfffff000;
497 b67ea0cd Max Filippov
    }
498 b67ea0cd Max Filippov
}
499 b67ea0cd Max Filippov
500 b67ea0cd Max Filippov
/*!
501 b67ea0cd Max Filippov
 * Split virtual address into VPN (with index) and entry index
502 b67ea0cd Max Filippov
 * for the given TLB way
503 b67ea0cd Max Filippov
 */
504 b67ea0cd Max Filippov
void split_tlb_entry_spec_way(const CPUState *env, uint32_t v, bool dtlb,
505 b67ea0cd Max Filippov
        uint32_t *vpn, uint32_t wi, uint32_t *ei)
506 b67ea0cd Max Filippov
{
507 b67ea0cd Max Filippov
    bool varway56 = dtlb ?
508 b67ea0cd Max Filippov
        env->config->dtlb.varway56 :
509 b67ea0cd Max Filippov
        env->config->itlb.varway56;
510 b67ea0cd Max Filippov
511 b67ea0cd Max Filippov
    if (!dtlb) {
512 b67ea0cd Max Filippov
        wi &= 7;
513 b67ea0cd Max Filippov
    }
514 b67ea0cd Max Filippov
515 b67ea0cd Max Filippov
    if (wi < 4) {
516 b67ea0cd Max Filippov
        bool is32 = (dtlb ?
517 b67ea0cd Max Filippov
                env->config->dtlb.nrefillentries :
518 b67ea0cd Max Filippov
                env->config->itlb.nrefillentries) == 32;
519 b67ea0cd Max Filippov
        *ei = (v >> 12) & (is32 ? 0x7 : 0x3);
520 b67ea0cd Max Filippov
    } else {
521 b67ea0cd Max Filippov
        switch (wi) {
522 b67ea0cd Max Filippov
        case 4:
523 b67ea0cd Max Filippov
            {
524 b67ea0cd Max Filippov
                uint32_t eibase = 20 + get_page_size(env, dtlb, wi) * 2;
525 b67ea0cd Max Filippov
                *ei = (v >> eibase) & 0x3;
526 b67ea0cd Max Filippov
            }
527 b67ea0cd Max Filippov
            break;
528 b67ea0cd Max Filippov
529 b67ea0cd Max Filippov
        case 5:
530 b67ea0cd Max Filippov
            if (varway56) {
531 b67ea0cd Max Filippov
                uint32_t eibase = 27 + get_page_size(env, dtlb, wi);
532 b67ea0cd Max Filippov
                *ei = (v >> eibase) & 0x3;
533 b67ea0cd Max Filippov
            } else {
534 b67ea0cd Max Filippov
                *ei = (v >> 27) & 0x1;
535 b67ea0cd Max Filippov
            }
536 b67ea0cd Max Filippov
            break;
537 b67ea0cd Max Filippov
538 b67ea0cd Max Filippov
        case 6:
539 b67ea0cd Max Filippov
            if (varway56) {
540 b67ea0cd Max Filippov
                uint32_t eibase = 29 - get_page_size(env, dtlb, wi);
541 b67ea0cd Max Filippov
                *ei = (v >> eibase) & 0x7;
542 b67ea0cd Max Filippov
            } else {
543 b67ea0cd Max Filippov
                *ei = (v >> 28) & 0x1;
544 b67ea0cd Max Filippov
            }
545 b67ea0cd Max Filippov
            break;
546 b67ea0cd Max Filippov
547 b67ea0cd Max Filippov
        default:
548 b67ea0cd Max Filippov
            *ei = 0;
549 b67ea0cd Max Filippov
            break;
550 b67ea0cd Max Filippov
        }
551 b67ea0cd Max Filippov
    }
552 b67ea0cd Max Filippov
    *vpn = v & xtensa_tlb_get_addr_mask(env, dtlb, wi);
553 b67ea0cd Max Filippov
}
554 b67ea0cd Max Filippov
555 b67ea0cd Max Filippov
/*!
556 b67ea0cd Max Filippov
 * Split TLB address into TLB way, entry index and VPN (with index).
557 b67ea0cd Max Filippov
 * See ISA, 4.6.5.5 - 4.6.5.8 for the TLB addressing format
558 b67ea0cd Max Filippov
 */
559 b67ea0cd Max Filippov
static void split_tlb_entry_spec(uint32_t v, bool dtlb,
560 b67ea0cd Max Filippov
        uint32_t *vpn, uint32_t *wi, uint32_t *ei)
561 b67ea0cd Max Filippov
{
562 b67ea0cd Max Filippov
    if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
563 b67ea0cd Max Filippov
        *wi = v & (dtlb ? 0xf : 0x7);
564 b67ea0cd Max Filippov
        split_tlb_entry_spec_way(env, v, dtlb, vpn, *wi, ei);
565 b67ea0cd Max Filippov
    } else {
566 b67ea0cd Max Filippov
        *vpn = v & REGION_PAGE_MASK;
567 b67ea0cd Max Filippov
        *wi = 0;
568 b67ea0cd Max Filippov
        *ei = (v >> 29) & 0x7;
569 b67ea0cd Max Filippov
    }
570 b67ea0cd Max Filippov
}
571 b67ea0cd Max Filippov
572 b67ea0cd Max Filippov
static xtensa_tlb_entry *get_tlb_entry(uint32_t v, bool dtlb, uint32_t *pwi)
573 b67ea0cd Max Filippov
{
574 b67ea0cd Max Filippov
    uint32_t vpn;
575 b67ea0cd Max Filippov
    uint32_t wi;
576 b67ea0cd Max Filippov
    uint32_t ei;
577 b67ea0cd Max Filippov
578 b67ea0cd Max Filippov
    split_tlb_entry_spec(v, dtlb, &vpn, &wi, &ei);
579 b67ea0cd Max Filippov
    if (pwi) {
580 b67ea0cd Max Filippov
        *pwi = wi;
581 b67ea0cd Max Filippov
    }
582 b67ea0cd Max Filippov
    return xtensa_tlb_get_entry(env, dtlb, wi, ei);
583 b67ea0cd Max Filippov
}
584 b67ea0cd Max Filippov
585 b67ea0cd Max Filippov
uint32_t HELPER(rtlb0)(uint32_t v, uint32_t dtlb)
586 b67ea0cd Max Filippov
{
587 b67ea0cd Max Filippov
    if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
588 b67ea0cd Max Filippov
        uint32_t wi;
589 b67ea0cd Max Filippov
        const xtensa_tlb_entry *entry = get_tlb_entry(v, dtlb, &wi);
590 b67ea0cd Max Filippov
        return (entry->vaddr & get_vpn_mask(env, dtlb, wi)) | entry->asid;
591 b67ea0cd Max Filippov
    } else {
592 b67ea0cd Max Filippov
        return v & REGION_PAGE_MASK;
593 b67ea0cd Max Filippov
    }
594 b67ea0cd Max Filippov
}
595 b67ea0cd Max Filippov
596 b67ea0cd Max Filippov
uint32_t HELPER(rtlb1)(uint32_t v, uint32_t dtlb)
597 b67ea0cd Max Filippov
{
598 b67ea0cd Max Filippov
    const xtensa_tlb_entry *entry = get_tlb_entry(v, dtlb, NULL);
599 b67ea0cd Max Filippov
    return entry->paddr | entry->attr;
600 b67ea0cd Max Filippov
}
601 b67ea0cd Max Filippov
602 b67ea0cd Max Filippov
void HELPER(itlb)(uint32_t v, uint32_t dtlb)
603 b67ea0cd Max Filippov
{
604 b67ea0cd Max Filippov
    if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
605 b67ea0cd Max Filippov
        uint32_t wi;
606 b67ea0cd Max Filippov
        xtensa_tlb_entry *entry = get_tlb_entry(v, dtlb, &wi);
607 b67ea0cd Max Filippov
        if (entry->variable && entry->asid) {
608 b67ea0cd Max Filippov
            tlb_flush_page(env, entry->vaddr);
609 b67ea0cd Max Filippov
            entry->asid = 0;
610 b67ea0cd Max Filippov
        }
611 b67ea0cd Max Filippov
    }
612 b67ea0cd Max Filippov
}
613 b67ea0cd Max Filippov
614 b67ea0cd Max Filippov
uint32_t HELPER(ptlb)(uint32_t v, uint32_t dtlb)
615 b67ea0cd Max Filippov
{
616 b67ea0cd Max Filippov
    if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
617 b67ea0cd Max Filippov
        uint32_t wi;
618 b67ea0cd Max Filippov
        uint32_t ei;
619 b67ea0cd Max Filippov
        uint8_t ring;
620 b67ea0cd Max Filippov
        int res = xtensa_tlb_lookup(env, v, dtlb, &wi, &ei, &ring);
621 b67ea0cd Max Filippov
622 b67ea0cd Max Filippov
        switch (res) {
623 b67ea0cd Max Filippov
        case 0:
624 b67ea0cd Max Filippov
            if (ring >= xtensa_get_ring(env)) {
625 b67ea0cd Max Filippov
                return (v & 0xfffff000) | wi | (dtlb ? 0x10 : 0x8);
626 b67ea0cd Max Filippov
            }
627 b67ea0cd Max Filippov
            break;
628 b67ea0cd Max Filippov
629 b67ea0cd Max Filippov
        case INST_TLB_MULTI_HIT_CAUSE:
630 b67ea0cd Max Filippov
        case LOAD_STORE_TLB_MULTI_HIT_CAUSE:
631 b67ea0cd Max Filippov
            HELPER(exception_cause_vaddr)(env->pc, res, v);
632 b67ea0cd Max Filippov
            break;
633 b67ea0cd Max Filippov
        }
634 b67ea0cd Max Filippov
        return 0;
635 b67ea0cd Max Filippov
    } else {
636 b67ea0cd Max Filippov
        return (v & REGION_PAGE_MASK) | 0x1;
637 b67ea0cd Max Filippov
    }
638 b67ea0cd Max Filippov
}
639 b67ea0cd Max Filippov
640 b67ea0cd Max Filippov
void xtensa_tlb_set_entry(CPUState *env, bool dtlb,
641 b67ea0cd Max Filippov
        unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte)
642 b67ea0cd Max Filippov
{
643 b67ea0cd Max Filippov
    xtensa_tlb_entry *entry = xtensa_tlb_get_entry(env, dtlb, wi, ei);
644 b67ea0cd Max Filippov
645 b67ea0cd Max Filippov
    if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
646 b67ea0cd Max Filippov
        if (entry->variable) {
647 b67ea0cd Max Filippov
            if (entry->asid) {
648 b67ea0cd Max Filippov
                tlb_flush_page(env, entry->vaddr);
649 b67ea0cd Max Filippov
            }
650 b67ea0cd Max Filippov
            entry->vaddr = vpn;
651 b67ea0cd Max Filippov
            entry->paddr = pte & xtensa_tlb_get_addr_mask(env, dtlb, wi);
652 b67ea0cd Max Filippov
            entry->asid = (env->sregs[RASID] >> ((pte >> 1) & 0x18)) & 0xff;
653 b67ea0cd Max Filippov
            entry->attr = pte & 0xf;
654 b67ea0cd Max Filippov
        } else {
655 b67ea0cd Max Filippov
            qemu_log("%s %d, %d, %d trying to set immutable entry\n",
656 b67ea0cd Max Filippov
                    __func__, dtlb, wi, ei);
657 b67ea0cd Max Filippov
        }
658 b67ea0cd Max Filippov
    } else {
659 b67ea0cd Max Filippov
        tlb_flush_page(env, entry->vaddr);
660 b67ea0cd Max Filippov
        if (xtensa_option_enabled(env->config,
661 b67ea0cd Max Filippov
                    XTENSA_OPTION_REGION_TRANSLATION)) {
662 b67ea0cd Max Filippov
            entry->paddr = pte & REGION_PAGE_MASK;
663 b67ea0cd Max Filippov
        }
664 b67ea0cd Max Filippov
        entry->attr = pte & 0xf;
665 b67ea0cd Max Filippov
    }
666 b67ea0cd Max Filippov
}
667 b67ea0cd Max Filippov
668 b67ea0cd Max Filippov
void HELPER(wtlb)(uint32_t p, uint32_t v, uint32_t dtlb)
669 b67ea0cd Max Filippov
{
670 b67ea0cd Max Filippov
    uint32_t vpn;
671 b67ea0cd Max Filippov
    uint32_t wi;
672 b67ea0cd Max Filippov
    uint32_t ei;
673 b67ea0cd Max Filippov
    split_tlb_entry_spec(v, dtlb, &vpn, &wi, &ei);
674 b67ea0cd Max Filippov
    xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, p);
675 b67ea0cd Max Filippov
}