target-xtensa: implement relocatable vectors
See ISA, 4.4.3 for details.
Vector addresses recorded in core configuration are absolute values thatcorrespond to default VECBASE value.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-xtensa: add gdb support
Specific xtensa processor overlay for GDB contains register map inthe gdb/xtensa-config.c. This description is used by the GDB to e.g.parse 'g' response packets and it may be reused in the qemu's gdbstub(only XTREG definitions for non-pseudoregisters are needed)....
target-xtensa: implement memory protection options
- TLB opcode group;- region protection option (ISA, 4.6.3);- region translation option (ISA, 4.6.4);- MMU option (ISA, 4.6.5).
Cache control attribute bits are not used by this implementation.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>...
target-xtensa: implement boolean option
See ISA, 4.3.9
target-xtensa: add dc232b core and board
This is Diamond 232L Standard Core Rev.B (LE).
MAINTAINERS: add xtensa maintainer
Add myself as target-xtensa and DC232B maintainer.
target-xtensa: add regression testsuite
target-xtensa: implement interrupt option
See ISA, 4.4.6 (interrupt option), 4.4.7 (high priority interruptoption) and 4.4.8 (timer interrupt option) for details.
target-xtensa: implement accurate window check
See ISA, 4.7.1.3 for details.
Window check is inserted before commands that push "used registerwatermark" beyond its current level. Used register watermark is reset oninstructions that change WINDOW_BASE/WINDOW_START SRs....
target-xtensa: implement CPENABLE and PRID SRs
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