root / tests / xtensa / test_timer.S @ 7d890b40
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.include "macros.inc" |
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test_suite timer |
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test ccount |
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rsr a3, ccount |
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rsr a4, ccount |
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sub a3, a4, a3 |
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assert eqi, a3, 1 |
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test_end |
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test ccompare |
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movi a2, 0 |
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wsr a2, intenable |
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rsr a2, interrupt |
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wsr a2, intclear |
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wsr a2, ccompare1 |
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wsr a2, ccompare2 |
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movi a3, 20 |
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rsr a2, ccount |
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addi a2, a2, 20 |
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wsr a2, ccompare0 |
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rsr a2, interrupt |
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assert eqi, a2, 0 |
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loop a3, 1f |
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rsr a3, interrupt |
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bnez a3, 2f |
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1: |
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test_fail |
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2: |
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test_end |
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test ccompare0_interrupt |
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set_vector kernel, 2f |
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movi a2, 0 |
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wsr a2, intenable |
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rsr a2, interrupt |
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wsr a2, intclear |
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wsr a2, ccompare1 |
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wsr a2, ccompare2 |
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movi a3, 20 |
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rsr a2, ccount |
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addi a2, a2, 20 |
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wsr a2, ccompare0 |
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rsync |
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rsr a2, interrupt |
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assert eqi, a2, 0 |
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movi a2, 0x40 |
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wsr a2, intenable |
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rsil a2, 0 |
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loop a3, 1f |
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nop |
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1: |
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test_fail |
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2: |
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rsr a2, exccause |
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assert eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */ |
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test_end |
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test ccompare1_interrupt |
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set_vector level3, 2f |
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movi a2, 0 |
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wsr a2, intenable |
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rsr a2, interrupt |
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wsr a2, intclear |
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wsr a2, ccompare0 |
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wsr a2, ccompare2 |
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movi a3, 20 |
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rsr a2, ccount |
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addi a2, a2, 20 |
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wsr a2, ccompare1 |
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rsync |
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rsr a2, interrupt |
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assert eqi, a2, 0 |
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movi a2, 0x400 |
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wsr a2, intenable |
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rsil a2, 2 |
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loop a3, 1f |
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nop |
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1: |
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test_fail |
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2: |
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test_end |
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test ccompare2_interrupt |
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set_vector level5, 2f |
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movi a2, 0 |
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wsr a2, intenable |
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rsr a2, interrupt |
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wsr a2, intclear |
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wsr a2, ccompare0 |
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wsr a2, ccompare1 |
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movi a3, 20 |
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rsr a2, ccount |
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addi a2, a2, 20 |
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wsr a2, ccompare2 |
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rsync |
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rsr a2, interrupt |
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assert eqi, a2, 0 |
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movi a2, 0x2000 |
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wsr a2, intenable |
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rsil a2, 4 |
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loop a3, 1f |
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nop |
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1: |
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test_fail |
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2: |
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test_end |
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test_suite_end |