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target-i386: Use mulu2 and muls2
These correspond very closely to the insns that we're emulating.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-i386: Use clz/ctz for bsf/bsr helpers
And mark the helpers as NO_RWG_SE.
Signed-off-by: Richard Henderson <rth@twiddle.net>
target-i386: Implement tzcnt and fix lzcnt
We weren't computing flags for lzcnt at all. At the same time,adjust the implementation of bsf/bsr to avoid the local branch,using movcond instead.
target-i386: Implement MULX
target-i386: Implement PDEP, PEXT
target-i386: Use CC_SRC2 for ADC and SBB
Add another slot in ENV and store two of the three inputs. This lets usdo less work when carry-out is not needed, and avoids the unpredictableCC_OP after translating these insns.
target-i386: Make helper_cc_compute_{all,c} const
Pass the data in explicitly, rather than indirectly via env.This avoids all sorts of unnecessary register spillage.
exec: move include files to include/exec/
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
target-i386: rename helper flags
Rename helper flags to the new ones. This is purely a mechanical change,it's possible to use better flags by looking at the helpers.
Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
x86: Implement SMEP and SMAP
This patch implements Supervisor Mode Execution Prevention (SMEP) andSupervisor Mode Access Prevention (SMAP) for x86. The purpose of thepatch, obviously, is to help kernel developers debug the support forthose features....
x86: avoid AREG0 for misc helpers
Add an explicit CPUX86State parameter instead of relying on AREG0.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
x86: avoid AREG0 in segmentation helpers
Rename remains of op_helper.c to seg_helper.c.
x86: switch to AREG0 free mode
Remove temporary wrappers and switch to AREG0 free mode.
x86: avoid AREG0 for FPU helpers
Make FPU helpers take a parameter for CPUState insteadof relying on global env.
Introduce temporary wrappers for FPU load and store ops. Removewrappers for non-AREG0 code. Don't call unconverted helpersdirectly.
x86: avoid AREG0 for condition code helpers
x86: avoid AREG0 for integer helpers
x86: avoid AREG0 for SVM helpers
x86: avoid AREG0 for SMM helpers
x86: avoid AREG0 for exceptions
Merge raise_exception_env() to raise_exception(), likewise withraise_exception_err_env() and raise_exception_err().
Introduce cpu_svm_check_intercept_param() and cpu_vmexit()...
target-i386: fix SSE rounding and flush to zero
SSE rounding and flush to zero control has never been implemented. Howevergiven that softfloat-native was using a single state for FPU and SSE andgiven that glibc is setting both FPU and SSE state in fesetround(), this...
target-i386: implement lzcnt emulation
lzcnt is a AMD Phenom/Barcelona added instruction returning thenumber of leading zero bits in a word.As this is similar to the "bsr" instruction, reuse the existingcode. There need to be some more changes, though, as lzcnt always...
target-i386: add RDTSCP support
RDTSCP reads the time stamp counter and atomically also the contentof a 32-bit MSR, which can be freely set by the OS. This allows CPUlocal data to be queried by userspace.Linux uses this to allow a fast implementation of the getcpu()...
x86: Add support for resume flag
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
TCG variable type checking.
Signed-off-by: Paul Brook <paul@codesourcery.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
SYSENTER/SYSEXIT IA-32e implementation (Alexander Graf).
On Intel CPUs, sysenter and sysexit are valid in 64-bit mode. This patchmakes both 64-bit aware and enables them for Intel CPUs.Add cpu save/load for 64-bit wide sysenter variables.
Signed-off-by: Alexander Graf <agraf@suse.de>...
Fix some warnings that would be generated by gcc -Wredundant-decls
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5115 c046a42c-6fe2-441c-8c8c-71466251a162
HLT, MWAIT and MONITOR insn fixes (initial patch by Alexander Graf)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4746 c046a42c-6fe2-441c-8c8c-71466251a162
reworked SVM interrupt handling logic - fixed vmrun EIP saved value - reworked cr8 handling - added CPUState.hflags2
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4662 c046a42c-6fe2-441c-8c8c-71466251a162
32 bit SVM fixes - INVLPG and INVLPGA updates
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4660 c046a42c-6fe2-441c-8c8c-71466251a162
SVM rework
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4605 c046a42c-6fe2-441c-8c8c-71466251a162
proper helper definition registering (all targets must do that)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4530 c046a42c-6fe2-441c-8c8c-71466251a162
cmpxchg8b fix - added cmpxchg16b
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4522 c046a42c-6fe2-441c-8c8c-71466251a162
convert eflags manipulation insns to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4515 c046a42c-6fe2-441c-8c8c-71466251a162
converted LSL/LAR/VERW/VERR to TCG - force 16 bit memory access for LSL/LAR
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4513 c046a42c-6fe2-441c-8c8c-71466251a162
converted INTO/CMPXCHG8B to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4510 c046a42c-6fe2-441c-8c8c-71466251a162
BSR/BSF TCG conversion
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4477 c046a42c-6fe2-441c-8c8c-71466251a162
converted condition code supprot to TCG - converted shift ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4470 c046a42c-6fe2-441c-8c8c-71466251a162
converted more helpers to TCG - fixed some SVM issues
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4459 c046a42c-6fe2-441c-8c8c-71466251a162
converted more helpers to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4447 c046a42c-6fe2-441c-8c8c-71466251a162
converted x87 FPU ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4444 c046a42c-6fe2-441c-8c8c-71466251a162
converted SSE/MMX ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4441 c046a42c-6fe2-441c-8c8c-71466251a162
use the TCG code generator
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3944 c046a42c-6fe2-441c-8c8c-71466251a162