root / cpu-exec.c @ 7f777bf3
History | View | Annotate | Download (23.9 kB)
1 | 7d13299d | bellard | /*
|
---|---|---|---|
2 | 7d13299d | bellard | * i386 emulator main execution loop
|
3 | 7d13299d | bellard | *
|
4 | 7d13299d | bellard | * Copyright (c) 2003 Fabrice Bellard
|
5 | 7d13299d | bellard | *
|
6 | 3ef693a0 | bellard | * This library is free software; you can redistribute it and/or
|
7 | 3ef693a0 | bellard | * modify it under the terms of the GNU Lesser General Public
|
8 | 3ef693a0 | bellard | * License as published by the Free Software Foundation; either
|
9 | 3ef693a0 | bellard | * version 2 of the License, or (at your option) any later version.
|
10 | 7d13299d | bellard | *
|
11 | 3ef693a0 | bellard | * This library is distributed in the hope that it will be useful,
|
12 | 3ef693a0 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
13 | 3ef693a0 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
14 | 3ef693a0 | bellard | * Lesser General Public License for more details.
|
15 | 7d13299d | bellard | *
|
16 | 3ef693a0 | bellard | * You should have received a copy of the GNU Lesser General Public
|
17 | 3ef693a0 | bellard | * License along with this library; if not, write to the Free Software
|
18 | 3ef693a0 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
19 | 7d13299d | bellard | */
|
20 | e4533c7a | bellard | #include "config.h" |
21 | 93ac68bc | bellard | #include "exec.h" |
22 | 956034d7 | bellard | #include "disas.h" |
23 | 7d13299d | bellard | |
24 | 36bdbe54 | bellard | int tb_invalidated_flag;
|
25 | 36bdbe54 | bellard | |
26 | dc99065b | bellard | //#define DEBUG_EXEC
|
27 | 9de5e440 | bellard | //#define DEBUG_SIGNAL
|
28 | 7d13299d | bellard | |
29 | 93ac68bc | bellard | #if defined(TARGET_ARM) || defined(TARGET_SPARC)
|
30 | e4533c7a | bellard | /* XXX: unify with i386 target */
|
31 | e4533c7a | bellard | void cpu_loop_exit(void) |
32 | e4533c7a | bellard | { |
33 | e4533c7a | bellard | longjmp(env->jmp_env, 1);
|
34 | e4533c7a | bellard | } |
35 | e4533c7a | bellard | #endif
|
36 | e4533c7a | bellard | |
37 | 7d13299d | bellard | /* main execution loop */
|
38 | 7d13299d | bellard | |
39 | e4533c7a | bellard | int cpu_exec(CPUState *env1)
|
40 | 7d13299d | bellard | { |
41 | e4533c7a | bellard | int saved_T0, saved_T1, saved_T2;
|
42 | e4533c7a | bellard | CPUState *saved_env; |
43 | 04369ff2 | bellard | #ifdef reg_EAX
|
44 | 04369ff2 | bellard | int saved_EAX;
|
45 | 04369ff2 | bellard | #endif
|
46 | 04369ff2 | bellard | #ifdef reg_ECX
|
47 | 04369ff2 | bellard | int saved_ECX;
|
48 | 04369ff2 | bellard | #endif
|
49 | 04369ff2 | bellard | #ifdef reg_EDX
|
50 | 04369ff2 | bellard | int saved_EDX;
|
51 | 04369ff2 | bellard | #endif
|
52 | 04369ff2 | bellard | #ifdef reg_EBX
|
53 | 04369ff2 | bellard | int saved_EBX;
|
54 | 04369ff2 | bellard | #endif
|
55 | 04369ff2 | bellard | #ifdef reg_ESP
|
56 | 04369ff2 | bellard | int saved_ESP;
|
57 | 04369ff2 | bellard | #endif
|
58 | 04369ff2 | bellard | #ifdef reg_EBP
|
59 | 04369ff2 | bellard | int saved_EBP;
|
60 | 04369ff2 | bellard | #endif
|
61 | 04369ff2 | bellard | #ifdef reg_ESI
|
62 | 04369ff2 | bellard | int saved_ESI;
|
63 | 04369ff2 | bellard | #endif
|
64 | 04369ff2 | bellard | #ifdef reg_EDI
|
65 | 04369ff2 | bellard | int saved_EDI;
|
66 | 04369ff2 | bellard | #endif
|
67 | 8c6939c0 | bellard | #ifdef __sparc__
|
68 | 8c6939c0 | bellard | int saved_i7, tmp_T0;
|
69 | 8c6939c0 | bellard | #endif
|
70 | 68a79315 | bellard | int code_gen_size, ret, interrupt_request;
|
71 | 7d13299d | bellard | void (*gen_func)(void); |
72 | 9de5e440 | bellard | TranslationBlock *tb, **ptb; |
73 | dab2ed99 | bellard | uint8_t *tc_ptr, *cs_base, *pc; |
74 | 6dbad63e | bellard | unsigned int flags; |
75 | 8c6939c0 | bellard | |
76 | 7d13299d | bellard | /* first we save global registers */
|
77 | 7d13299d | bellard | saved_T0 = T0; |
78 | 7d13299d | bellard | saved_T1 = T1; |
79 | e4533c7a | bellard | saved_T2 = T2; |
80 | 7d13299d | bellard | saved_env = env; |
81 | 7d13299d | bellard | env = env1; |
82 | e4533c7a | bellard | #ifdef __sparc__
|
83 | e4533c7a | bellard | /* we also save i7 because longjmp may not restore it */
|
84 | e4533c7a | bellard | asm volatile ("mov %%i7, %0" : "=r" (saved_i7)); |
85 | e4533c7a | bellard | #endif
|
86 | e4533c7a | bellard | |
87 | e4533c7a | bellard | #if defined(TARGET_I386)
|
88 | 04369ff2 | bellard | #ifdef reg_EAX
|
89 | 04369ff2 | bellard | saved_EAX = EAX; |
90 | 04369ff2 | bellard | EAX = env->regs[R_EAX]; |
91 | 04369ff2 | bellard | #endif
|
92 | 04369ff2 | bellard | #ifdef reg_ECX
|
93 | 04369ff2 | bellard | saved_ECX = ECX; |
94 | 04369ff2 | bellard | ECX = env->regs[R_ECX]; |
95 | 04369ff2 | bellard | #endif
|
96 | 04369ff2 | bellard | #ifdef reg_EDX
|
97 | 04369ff2 | bellard | saved_EDX = EDX; |
98 | 04369ff2 | bellard | EDX = env->regs[R_EDX]; |
99 | 04369ff2 | bellard | #endif
|
100 | 04369ff2 | bellard | #ifdef reg_EBX
|
101 | 04369ff2 | bellard | saved_EBX = EBX; |
102 | 04369ff2 | bellard | EBX = env->regs[R_EBX]; |
103 | 04369ff2 | bellard | #endif
|
104 | 04369ff2 | bellard | #ifdef reg_ESP
|
105 | 04369ff2 | bellard | saved_ESP = ESP; |
106 | 04369ff2 | bellard | ESP = env->regs[R_ESP]; |
107 | 04369ff2 | bellard | #endif
|
108 | 04369ff2 | bellard | #ifdef reg_EBP
|
109 | 04369ff2 | bellard | saved_EBP = EBP; |
110 | 04369ff2 | bellard | EBP = env->regs[R_EBP]; |
111 | 04369ff2 | bellard | #endif
|
112 | 04369ff2 | bellard | #ifdef reg_ESI
|
113 | 04369ff2 | bellard | saved_ESI = ESI; |
114 | 04369ff2 | bellard | ESI = env->regs[R_ESI]; |
115 | 04369ff2 | bellard | #endif
|
116 | 04369ff2 | bellard | #ifdef reg_EDI
|
117 | 04369ff2 | bellard | saved_EDI = EDI; |
118 | 04369ff2 | bellard | EDI = env->regs[R_EDI]; |
119 | 04369ff2 | bellard | #endif
|
120 | 7d13299d | bellard | |
121 | 9de5e440 | bellard | /* put eflags in CPU temporary format */
|
122 | fc2b4c48 | bellard | CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
123 | fc2b4c48 | bellard | DF = 1 - (2 * ((env->eflags >> 10) & 1)); |
124 | 9de5e440 | bellard | CC_OP = CC_OP_EFLAGS; |
125 | fc2b4c48 | bellard | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
126 | e4533c7a | bellard | #elif defined(TARGET_ARM)
|
127 | e4533c7a | bellard | { |
128 | e4533c7a | bellard | unsigned int psr; |
129 | e4533c7a | bellard | psr = env->cpsr; |
130 | e4533c7a | bellard | env->CF = (psr >> 29) & 1; |
131 | e4533c7a | bellard | env->NZF = (psr & 0xc0000000) ^ 0x40000000; |
132 | e4533c7a | bellard | env->VF = (psr << 3) & 0x80000000; |
133 | e4533c7a | bellard | env->cpsr = psr & ~0xf0000000;
|
134 | e4533c7a | bellard | } |
135 | 93ac68bc | bellard | #elif defined(TARGET_SPARC)
|
136 | 67867308 | bellard | #elif defined(TARGET_PPC)
|
137 | e4533c7a | bellard | #else
|
138 | e4533c7a | bellard | #error unsupported target CPU
|
139 | e4533c7a | bellard | #endif
|
140 | 3fb2ded1 | bellard | env->exception_index = -1;
|
141 | 9d27abd9 | bellard | |
142 | 7d13299d | bellard | /* prepare setjmp context for exception handling */
|
143 | 3fb2ded1 | bellard | for(;;) {
|
144 | 3fb2ded1 | bellard | if (setjmp(env->jmp_env) == 0) { |
145 | 3fb2ded1 | bellard | /* if an exception is pending, we execute it here */
|
146 | 3fb2ded1 | bellard | if (env->exception_index >= 0) { |
147 | 3fb2ded1 | bellard | if (env->exception_index >= EXCP_INTERRUPT) {
|
148 | 3fb2ded1 | bellard | /* exit request from the cpu execution loop */
|
149 | 3fb2ded1 | bellard | ret = env->exception_index; |
150 | 3fb2ded1 | bellard | break;
|
151 | 3fb2ded1 | bellard | } else if (env->user_mode_only) { |
152 | 3fb2ded1 | bellard | /* if user mode only, we simulate a fake exception
|
153 | 3fb2ded1 | bellard | which will be hanlded outside the cpu execution
|
154 | 3fb2ded1 | bellard | loop */
|
155 | 83479e77 | bellard | #if defined(TARGET_I386)
|
156 | 3fb2ded1 | bellard | do_interrupt_user(env->exception_index, |
157 | 3fb2ded1 | bellard | env->exception_is_int, |
158 | 3fb2ded1 | bellard | env->error_code, |
159 | 3fb2ded1 | bellard | env->exception_next_eip); |
160 | 83479e77 | bellard | #endif
|
161 | 3fb2ded1 | bellard | ret = env->exception_index; |
162 | 3fb2ded1 | bellard | break;
|
163 | 3fb2ded1 | bellard | } else {
|
164 | 83479e77 | bellard | #if defined(TARGET_I386)
|
165 | 3fb2ded1 | bellard | /* simulate a real cpu exception. On i386, it can
|
166 | 3fb2ded1 | bellard | trigger new exceptions, but we do not handle
|
167 | 3fb2ded1 | bellard | double or triple faults yet. */
|
168 | 3fb2ded1 | bellard | do_interrupt(env->exception_index, |
169 | 3fb2ded1 | bellard | env->exception_is_int, |
170 | 3fb2ded1 | bellard | env->error_code, |
171 | d05e66d2 | bellard | env->exception_next_eip, 0);
|
172 | ce09776b | bellard | #elif defined(TARGET_PPC)
|
173 | ce09776b | bellard | do_interrupt(env); |
174 | 83479e77 | bellard | #endif
|
175 | 3fb2ded1 | bellard | } |
176 | 3fb2ded1 | bellard | env->exception_index = -1;
|
177 | 3fb2ded1 | bellard | } |
178 | 3fb2ded1 | bellard | T0 = 0; /* force lookup of first TB */ |
179 | 3fb2ded1 | bellard | for(;;) {
|
180 | 8c6939c0 | bellard | #ifdef __sparc__
|
181 | 3fb2ded1 | bellard | /* g1 can be modified by some libc? functions */
|
182 | 3fb2ded1 | bellard | tmp_T0 = T0; |
183 | 8c6939c0 | bellard | #endif
|
184 | 68a79315 | bellard | interrupt_request = env->interrupt_request; |
185 | 2e255c6b | bellard | if (__builtin_expect(interrupt_request, 0)) { |
186 | 68a79315 | bellard | #if defined(TARGET_I386)
|
187 | 68a79315 | bellard | /* if hardware interrupt pending, we execute it */
|
188 | 68a79315 | bellard | if ((interrupt_request & CPU_INTERRUPT_HARD) &&
|
189 | 3f337316 | bellard | (env->eflags & IF_MASK) && |
190 | 3f337316 | bellard | !(env->hflags & HF_INHIBIT_IRQ_MASK)) { |
191 | 68a79315 | bellard | int intno;
|
192 | 68a79315 | bellard | intno = cpu_x86_get_pic_interrupt(env); |
193 | 68a79315 | bellard | if (loglevel) {
|
194 | 68a79315 | bellard | fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
|
195 | 68a79315 | bellard | } |
196 | d05e66d2 | bellard | do_interrupt(intno, 0, 0, 0, 1); |
197 | 68a79315 | bellard | env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
198 | 907a5b26 | bellard | /* ensure that no TB jump will be modified as
|
199 | 907a5b26 | bellard | the program flow was changed */
|
200 | 907a5b26 | bellard | #ifdef __sparc__
|
201 | 907a5b26 | bellard | tmp_T0 = 0;
|
202 | 907a5b26 | bellard | #else
|
203 | 907a5b26 | bellard | T0 = 0;
|
204 | 907a5b26 | bellard | #endif
|
205 | 68a79315 | bellard | } |
206 | ce09776b | bellard | #elif defined(TARGET_PPC)
|
207 | ce09776b | bellard | if ((interrupt_request & CPU_INTERRUPT_HARD)) {
|
208 | ce09776b | bellard | do_queue_exception(EXCP_EXTERNAL); |
209 | ce09776b | bellard | if (check_exception_state(env))
|
210 | ce09776b | bellard | do_interrupt(env); |
211 | ce09776b | bellard | env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
212 | ce09776b | bellard | } |
213 | 68a79315 | bellard | #endif
|
214 | 68a79315 | bellard | if (interrupt_request & CPU_INTERRUPT_EXIT) {
|
215 | 68a79315 | bellard | env->interrupt_request &= ~CPU_INTERRUPT_EXIT; |
216 | 68a79315 | bellard | env->exception_index = EXCP_INTERRUPT; |
217 | 68a79315 | bellard | cpu_loop_exit(); |
218 | 68a79315 | bellard | } |
219 | 3fb2ded1 | bellard | } |
220 | 7d13299d | bellard | #ifdef DEBUG_EXEC
|
221 | 3fb2ded1 | bellard | if (loglevel) {
|
222 | e4533c7a | bellard | #if defined(TARGET_I386)
|
223 | 3fb2ded1 | bellard | /* restore flags in standard format */
|
224 | 3fb2ded1 | bellard | env->regs[R_EAX] = EAX; |
225 | 3fb2ded1 | bellard | env->regs[R_EBX] = EBX; |
226 | 3fb2ded1 | bellard | env->regs[R_ECX] = ECX; |
227 | 3fb2ded1 | bellard | env->regs[R_EDX] = EDX; |
228 | 3fb2ded1 | bellard | env->regs[R_ESI] = ESI; |
229 | 3fb2ded1 | bellard | env->regs[R_EDI] = EDI; |
230 | 3fb2ded1 | bellard | env->regs[R_EBP] = EBP; |
231 | 3fb2ded1 | bellard | env->regs[R_ESP] = ESP; |
232 | 3fb2ded1 | bellard | env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
233 | 68a79315 | bellard | cpu_x86_dump_state(env, logfile, X86_DUMP_CCOP); |
234 | 3fb2ded1 | bellard | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
235 | e4533c7a | bellard | #elif defined(TARGET_ARM)
|
236 | 1b21b62a | bellard | env->cpsr = compute_cpsr(); |
237 | 3fb2ded1 | bellard | cpu_arm_dump_state(env, logfile, 0);
|
238 | 1b21b62a | bellard | env->cpsr &= ~0xf0000000;
|
239 | 93ac68bc | bellard | #elif defined(TARGET_SPARC)
|
240 | 93a40ea9 | bellard | cpu_sparc_dump_state (env, logfile, 0);
|
241 | 67867308 | bellard | #elif defined(TARGET_PPC)
|
242 | 67867308 | bellard | cpu_ppc_dump_state(env, logfile, 0);
|
243 | e4533c7a | bellard | #else
|
244 | e4533c7a | bellard | #error unsupported target CPU
|
245 | e4533c7a | bellard | #endif
|
246 | 3fb2ded1 | bellard | } |
247 | 7d13299d | bellard | #endif
|
248 | 3f337316 | bellard | /* we record a subset of the CPU state. It will
|
249 | 3f337316 | bellard | always be the same before a given translated block
|
250 | 3f337316 | bellard | is executed. */
|
251 | e4533c7a | bellard | #if defined(TARGET_I386)
|
252 | 2e255c6b | bellard | flags = env->hflags; |
253 | 3f337316 | bellard | flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK)); |
254 | 3fb2ded1 | bellard | cs_base = env->segs[R_CS].base; |
255 | 3fb2ded1 | bellard | pc = cs_base + env->eip; |
256 | e4533c7a | bellard | #elif defined(TARGET_ARM)
|
257 | 3fb2ded1 | bellard | flags = 0;
|
258 | 3fb2ded1 | bellard | cs_base = 0;
|
259 | 3fb2ded1 | bellard | pc = (uint8_t *)env->regs[15];
|
260 | 93ac68bc | bellard | #elif defined(TARGET_SPARC)
|
261 | 67867308 | bellard | flags = 0;
|
262 | ce09776b | bellard | cs_base = (uint8_t *)env->npc; |
263 | 67867308 | bellard | pc = (uint8_t *) env->pc; |
264 | 67867308 | bellard | #elif defined(TARGET_PPC)
|
265 | 67867308 | bellard | flags = 0;
|
266 | 67867308 | bellard | cs_base = 0;
|
267 | 67867308 | bellard | pc = (uint8_t *)env->nip; |
268 | e4533c7a | bellard | #else
|
269 | e4533c7a | bellard | #error unsupported CPU
|
270 | e4533c7a | bellard | #endif
|
271 | 3fb2ded1 | bellard | tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base, |
272 | 3fb2ded1 | bellard | flags); |
273 | d4e8164f | bellard | if (!tb) {
|
274 | 1376847f | bellard | TranslationBlock **ptb1; |
275 | 1376847f | bellard | unsigned int h; |
276 | 1376847f | bellard | target_ulong phys_pc, phys_page1, phys_page2, virt_page2; |
277 | 1376847f | bellard | |
278 | 1376847f | bellard | |
279 | 3fb2ded1 | bellard | spin_lock(&tb_lock); |
280 | 1376847f | bellard | |
281 | 1376847f | bellard | tb_invalidated_flag = 0;
|
282 | 1376847f | bellard | |
283 | 1376847f | bellard | /* find translated block using physical mappings */
|
284 | 1376847f | bellard | phys_pc = get_phys_addr_code(env, (unsigned long)pc); |
285 | 1376847f | bellard | phys_page1 = phys_pc & TARGET_PAGE_MASK; |
286 | 1376847f | bellard | phys_page2 = -1;
|
287 | 1376847f | bellard | h = tb_phys_hash_func(phys_pc); |
288 | 1376847f | bellard | ptb1 = &tb_phys_hash[h]; |
289 | 1376847f | bellard | for(;;) {
|
290 | 1376847f | bellard | tb = *ptb1; |
291 | 1376847f | bellard | if (!tb)
|
292 | 1376847f | bellard | goto not_found;
|
293 | 1376847f | bellard | if (tb->pc == (unsigned long)pc && |
294 | 1376847f | bellard | tb->page_addr[0] == phys_page1 &&
|
295 | 1376847f | bellard | tb->cs_base == (unsigned long)cs_base && |
296 | 1376847f | bellard | tb->flags == flags) { |
297 | 1376847f | bellard | /* check next page if needed */
|
298 | b516f85c | bellard | if (tb->page_addr[1] != -1) { |
299 | b516f85c | bellard | virt_page2 = ((unsigned long)pc & TARGET_PAGE_MASK) + |
300 | b516f85c | bellard | TARGET_PAGE_SIZE; |
301 | 1376847f | bellard | phys_page2 = get_phys_addr_code(env, virt_page2); |
302 | 1376847f | bellard | if (tb->page_addr[1] == phys_page2) |
303 | 1376847f | bellard | goto found;
|
304 | 1376847f | bellard | } else {
|
305 | 1376847f | bellard | goto found;
|
306 | 1376847f | bellard | } |
307 | 1376847f | bellard | } |
308 | 1376847f | bellard | ptb1 = &tb->phys_hash_next; |
309 | 1376847f | bellard | } |
310 | 1376847f | bellard | not_found:
|
311 | 3fb2ded1 | bellard | /* if no translated code available, then translate it now */
|
312 | d4e8164f | bellard | tb = tb_alloc((unsigned long)pc); |
313 | 3fb2ded1 | bellard | if (!tb) {
|
314 | 3fb2ded1 | bellard | /* flush must be done */
|
315 | b453b70b | bellard | tb_flush(env); |
316 | 3fb2ded1 | bellard | /* cannot fail at this point */
|
317 | 3fb2ded1 | bellard | tb = tb_alloc((unsigned long)pc); |
318 | 3fb2ded1 | bellard | /* don't forget to invalidate previous TB info */
|
319 | 3fb2ded1 | bellard | ptb = &tb_hash[tb_hash_func((unsigned long)pc)]; |
320 | 3fb2ded1 | bellard | T0 = 0;
|
321 | 3fb2ded1 | bellard | } |
322 | 3fb2ded1 | bellard | tc_ptr = code_gen_ptr; |
323 | 3fb2ded1 | bellard | tb->tc_ptr = tc_ptr; |
324 | 3fb2ded1 | bellard | tb->cs_base = (unsigned long)cs_base; |
325 | 3fb2ded1 | bellard | tb->flags = flags; |
326 | facc68be | bellard | cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size); |
327 | 1376847f | bellard | code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1)); |
328 | 1376847f | bellard | |
329 | 1376847f | bellard | /* check next page if needed */
|
330 | 1376847f | bellard | virt_page2 = ((unsigned long)pc + tb->size - 1) & TARGET_PAGE_MASK; |
331 | 1376847f | bellard | phys_page2 = -1;
|
332 | 1376847f | bellard | if (((unsigned long)pc & TARGET_PAGE_MASK) != virt_page2) { |
333 | 1376847f | bellard | phys_page2 = get_phys_addr_code(env, virt_page2); |
334 | 1376847f | bellard | } |
335 | 1376847f | bellard | tb_link_phys(tb, phys_pc, phys_page2); |
336 | 1376847f | bellard | |
337 | 1376847f | bellard | found:
|
338 | 36bdbe54 | bellard | if (tb_invalidated_flag) {
|
339 | 36bdbe54 | bellard | /* as some TB could have been invalidated because
|
340 | 36bdbe54 | bellard | of memory exceptions while generating the code, we
|
341 | 36bdbe54 | bellard | must recompute the hash index here */
|
342 | 36bdbe54 | bellard | ptb = &tb_hash[tb_hash_func((unsigned long)pc)]; |
343 | 36bdbe54 | bellard | while (*ptb != NULL) |
344 | 36bdbe54 | bellard | ptb = &(*ptb)->hash_next; |
345 | 36bdbe54 | bellard | T0 = 0;
|
346 | 36bdbe54 | bellard | } |
347 | 1376847f | bellard | /* we add the TB in the virtual pc hash table */
|
348 | 3fb2ded1 | bellard | *ptb = tb; |
349 | 3fb2ded1 | bellard | tb->hash_next = NULL;
|
350 | 3fb2ded1 | bellard | tb_link(tb); |
351 | 25eb4484 | bellard | spin_unlock(&tb_lock); |
352 | 9de5e440 | bellard | } |
353 | 9d27abd9 | bellard | #ifdef DEBUG_EXEC
|
354 | 3fb2ded1 | bellard | if (loglevel) {
|
355 | 3fb2ded1 | bellard | fprintf(logfile, "Trace 0x%08lx [0x%08lx] %s\n",
|
356 | 3fb2ded1 | bellard | (long)tb->tc_ptr, (long)tb->pc, |
357 | 3fb2ded1 | bellard | lookup_symbol((void *)tb->pc));
|
358 | 3fb2ded1 | bellard | } |
359 | 9d27abd9 | bellard | #endif
|
360 | 8c6939c0 | bellard | #ifdef __sparc__
|
361 | 3fb2ded1 | bellard | T0 = tmp_T0; |
362 | 8c6939c0 | bellard | #endif
|
363 | facc68be | bellard | /* see if we can patch the calling TB. */
|
364 | facc68be | bellard | if (T0 != 0) { |
365 | 3fb2ded1 | bellard | spin_lock(&tb_lock); |
366 | 3fb2ded1 | bellard | tb_add_jump((TranslationBlock *)(T0 & ~3), T0 & 3, tb); |
367 | 3fb2ded1 | bellard | spin_unlock(&tb_lock); |
368 | 3fb2ded1 | bellard | } |
369 | 3fb2ded1 | bellard | tc_ptr = tb->tc_ptr; |
370 | 83479e77 | bellard | env->current_tb = tb; |
371 | 3fb2ded1 | bellard | /* execute the generated code */
|
372 | 3fb2ded1 | bellard | gen_func = (void *)tc_ptr;
|
373 | 8c6939c0 | bellard | #if defined(__sparc__)
|
374 | 3fb2ded1 | bellard | __asm__ __volatile__("call %0\n\t"
|
375 | 3fb2ded1 | bellard | "mov %%o7,%%i0"
|
376 | 3fb2ded1 | bellard | : /* no outputs */
|
377 | 3fb2ded1 | bellard | : "r" (gen_func)
|
378 | 3fb2ded1 | bellard | : "i0", "i1", "i2", "i3", "i4", "i5"); |
379 | 8c6939c0 | bellard | #elif defined(__arm__)
|
380 | 3fb2ded1 | bellard | asm volatile ("mov pc, %0\n\t" |
381 | 3fb2ded1 | bellard | ".global exec_loop\n\t"
|
382 | 3fb2ded1 | bellard | "exec_loop:\n\t"
|
383 | 3fb2ded1 | bellard | : /* no outputs */
|
384 | 3fb2ded1 | bellard | : "r" (gen_func)
|
385 | 3fb2ded1 | bellard | : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14"); |
386 | ae228531 | bellard | #else
|
387 | 3fb2ded1 | bellard | gen_func(); |
388 | ae228531 | bellard | #endif
|
389 | 83479e77 | bellard | env->current_tb = NULL;
|
390 | 4cbf74b6 | bellard | /* reset soft MMU for next block (it can currently
|
391 | 4cbf74b6 | bellard | only be set by a memory fault) */
|
392 | 4cbf74b6 | bellard | #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
|
393 | 3f337316 | bellard | if (env->hflags & HF_SOFTMMU_MASK) {
|
394 | 3f337316 | bellard | env->hflags &= ~HF_SOFTMMU_MASK; |
395 | 4cbf74b6 | bellard | /* do not allow linking to another block */
|
396 | 4cbf74b6 | bellard | T0 = 0;
|
397 | 4cbf74b6 | bellard | } |
398 | 4cbf74b6 | bellard | #endif
|
399 | 3fb2ded1 | bellard | } |
400 | 3fb2ded1 | bellard | } else {
|
401 | 7d13299d | bellard | } |
402 | 3fb2ded1 | bellard | } /* for(;;) */
|
403 | 3fb2ded1 | bellard | |
404 | 7d13299d | bellard | |
405 | e4533c7a | bellard | #if defined(TARGET_I386)
|
406 | 9de5e440 | bellard | /* restore flags in standard format */
|
407 | fc2b4c48 | bellard | env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
408 | 9de5e440 | bellard | |
409 | 7d13299d | bellard | /* restore global registers */
|
410 | 04369ff2 | bellard | #ifdef reg_EAX
|
411 | 04369ff2 | bellard | EAX = saved_EAX; |
412 | 04369ff2 | bellard | #endif
|
413 | 04369ff2 | bellard | #ifdef reg_ECX
|
414 | 04369ff2 | bellard | ECX = saved_ECX; |
415 | 04369ff2 | bellard | #endif
|
416 | 04369ff2 | bellard | #ifdef reg_EDX
|
417 | 04369ff2 | bellard | EDX = saved_EDX; |
418 | 04369ff2 | bellard | #endif
|
419 | 04369ff2 | bellard | #ifdef reg_EBX
|
420 | 04369ff2 | bellard | EBX = saved_EBX; |
421 | 04369ff2 | bellard | #endif
|
422 | 04369ff2 | bellard | #ifdef reg_ESP
|
423 | 04369ff2 | bellard | ESP = saved_ESP; |
424 | 04369ff2 | bellard | #endif
|
425 | 04369ff2 | bellard | #ifdef reg_EBP
|
426 | 04369ff2 | bellard | EBP = saved_EBP; |
427 | 04369ff2 | bellard | #endif
|
428 | 04369ff2 | bellard | #ifdef reg_ESI
|
429 | 04369ff2 | bellard | ESI = saved_ESI; |
430 | 04369ff2 | bellard | #endif
|
431 | 04369ff2 | bellard | #ifdef reg_EDI
|
432 | 04369ff2 | bellard | EDI = saved_EDI; |
433 | 04369ff2 | bellard | #endif
|
434 | e4533c7a | bellard | #elif defined(TARGET_ARM)
|
435 | 1b21b62a | bellard | env->cpsr = compute_cpsr(); |
436 | 93ac68bc | bellard | #elif defined(TARGET_SPARC)
|
437 | 67867308 | bellard | #elif defined(TARGET_PPC)
|
438 | e4533c7a | bellard | #else
|
439 | e4533c7a | bellard | #error unsupported target CPU
|
440 | e4533c7a | bellard | #endif
|
441 | 8c6939c0 | bellard | #ifdef __sparc__
|
442 | 8c6939c0 | bellard | asm volatile ("mov %0, %%i7" : : "r" (saved_i7)); |
443 | 8c6939c0 | bellard | #endif
|
444 | 7d13299d | bellard | T0 = saved_T0; |
445 | 7d13299d | bellard | T1 = saved_T1; |
446 | e4533c7a | bellard | T2 = saved_T2; |
447 | 7d13299d | bellard | env = saved_env; |
448 | 7d13299d | bellard | return ret;
|
449 | 7d13299d | bellard | } |
450 | 6dbad63e | bellard | |
451 | 1a18c71b | bellard | #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
|
452 | e4533c7a | bellard | |
453 | 6dbad63e | bellard | void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector) |
454 | 6dbad63e | bellard | { |
455 | 6dbad63e | bellard | CPUX86State *saved_env; |
456 | 6dbad63e | bellard | |
457 | 6dbad63e | bellard | saved_env = env; |
458 | 6dbad63e | bellard | env = s; |
459 | a412ac57 | bellard | if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) { |
460 | a513fe19 | bellard | selector &= 0xffff;
|
461 | 2e255c6b | bellard | cpu_x86_load_seg_cache(env, seg_reg, selector, |
462 | 2e255c6b | bellard | (uint8_t *)(selector << 4), 0xffff, 0); |
463 | a513fe19 | bellard | } else {
|
464 | b453b70b | bellard | load_seg(seg_reg, selector); |
465 | a513fe19 | bellard | } |
466 | 6dbad63e | bellard | env = saved_env; |
467 | 6dbad63e | bellard | } |
468 | 9de5e440 | bellard | |
469 | d0a1ffc9 | bellard | void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32) |
470 | d0a1ffc9 | bellard | { |
471 | d0a1ffc9 | bellard | CPUX86State *saved_env; |
472 | d0a1ffc9 | bellard | |
473 | d0a1ffc9 | bellard | saved_env = env; |
474 | d0a1ffc9 | bellard | env = s; |
475 | d0a1ffc9 | bellard | |
476 | d0a1ffc9 | bellard | helper_fsave(ptr, data32); |
477 | d0a1ffc9 | bellard | |
478 | d0a1ffc9 | bellard | env = saved_env; |
479 | d0a1ffc9 | bellard | } |
480 | d0a1ffc9 | bellard | |
481 | d0a1ffc9 | bellard | void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32) |
482 | d0a1ffc9 | bellard | { |
483 | d0a1ffc9 | bellard | CPUX86State *saved_env; |
484 | d0a1ffc9 | bellard | |
485 | d0a1ffc9 | bellard | saved_env = env; |
486 | d0a1ffc9 | bellard | env = s; |
487 | d0a1ffc9 | bellard | |
488 | d0a1ffc9 | bellard | helper_frstor(ptr, data32); |
489 | d0a1ffc9 | bellard | |
490 | d0a1ffc9 | bellard | env = saved_env; |
491 | d0a1ffc9 | bellard | } |
492 | d0a1ffc9 | bellard | |
493 | e4533c7a | bellard | #endif /* TARGET_I386 */ |
494 | e4533c7a | bellard | |
495 | 9de5e440 | bellard | #undef EAX
|
496 | 9de5e440 | bellard | #undef ECX
|
497 | 9de5e440 | bellard | #undef EDX
|
498 | 9de5e440 | bellard | #undef EBX
|
499 | 9de5e440 | bellard | #undef ESP
|
500 | 9de5e440 | bellard | #undef EBP
|
501 | 9de5e440 | bellard | #undef ESI
|
502 | 9de5e440 | bellard | #undef EDI
|
503 | 9de5e440 | bellard | #undef EIP
|
504 | 9de5e440 | bellard | #include <signal.h> |
505 | 9de5e440 | bellard | #include <sys/ucontext.h> |
506 | 9de5e440 | bellard | |
507 | 3fb2ded1 | bellard | #if defined(TARGET_I386)
|
508 | 3fb2ded1 | bellard | |
509 | b56dad1c | bellard | /* 'pc' is the host PC at which the exception was raised. 'address' is
|
510 | fd6ce8f6 | bellard | the effective address of the memory exception. 'is_write' is 1 if a
|
511 | fd6ce8f6 | bellard | write caused the exception and otherwise 0'. 'old_set' is the
|
512 | fd6ce8f6 | bellard | signal set which should be restored */
|
513 | 2b413144 | bellard | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
514 | 2b413144 | bellard | int is_write, sigset_t *old_set)
|
515 | 9de5e440 | bellard | { |
516 | a513fe19 | bellard | TranslationBlock *tb; |
517 | a513fe19 | bellard | int ret;
|
518 | 68a79315 | bellard | |
519 | 83479e77 | bellard | if (cpu_single_env)
|
520 | 83479e77 | bellard | env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
521 | fd6ce8f6 | bellard | #if defined(DEBUG_SIGNAL)
|
522 | 3fb2ded1 | bellard | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
|
523 | fd6ce8f6 | bellard | pc, address, is_write, *(unsigned long *)old_set); |
524 | 9de5e440 | bellard | #endif
|
525 | 25eb4484 | bellard | /* XXX: locking issue */
|
526 | fd6ce8f6 | bellard | if (is_write && page_unprotect(address)) {
|
527 | fd6ce8f6 | bellard | return 1; |
528 | fd6ce8f6 | bellard | } |
529 | 3fb2ded1 | bellard | /* see if it is an MMU fault */
|
530 | 93a40ea9 | bellard | ret = cpu_x86_handle_mmu_fault(env, address, is_write, |
531 | 93a40ea9 | bellard | ((env->hflags & HF_CPL_MASK) == 3), 0); |
532 | 3fb2ded1 | bellard | if (ret < 0) |
533 | 3fb2ded1 | bellard | return 0; /* not an MMU fault */ |
534 | 3fb2ded1 | bellard | if (ret == 0) |
535 | 3fb2ded1 | bellard | return 1; /* the MMU fault was handled without causing real CPU fault */ |
536 | 3fb2ded1 | bellard | /* now we have a real cpu fault */
|
537 | a513fe19 | bellard | tb = tb_find_pc(pc); |
538 | a513fe19 | bellard | if (tb) {
|
539 | 9de5e440 | bellard | /* the PC is inside the translated code. It means that we have
|
540 | 9de5e440 | bellard | a virtual CPU fault */
|
541 | 3fb2ded1 | bellard | cpu_restore_state(tb, env, pc); |
542 | 3fb2ded1 | bellard | } |
543 | 4cbf74b6 | bellard | if (ret == 1) { |
544 | 3fb2ded1 | bellard | #if 0
|
545 | 4cbf74b6 | bellard | printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
|
546 | 4cbf74b6 | bellard | env->eip, env->cr[2], env->error_code);
|
547 | 3fb2ded1 | bellard | #endif
|
548 | 4cbf74b6 | bellard | /* we restore the process signal mask as the sigreturn should
|
549 | 4cbf74b6 | bellard | do it (XXX: use sigsetjmp) */
|
550 | 4cbf74b6 | bellard | sigprocmask(SIG_SETMASK, old_set, NULL);
|
551 | 4cbf74b6 | bellard | raise_exception_err(EXCP0E_PAGE, env->error_code); |
552 | 4cbf74b6 | bellard | } else {
|
553 | 4cbf74b6 | bellard | /* activate soft MMU for this block */
|
554 | 3f337316 | bellard | env->hflags |= HF_SOFTMMU_MASK; |
555 | 4cbf74b6 | bellard | sigprocmask(SIG_SETMASK, old_set, NULL);
|
556 | 4cbf74b6 | bellard | cpu_loop_exit(); |
557 | 4cbf74b6 | bellard | } |
558 | 3fb2ded1 | bellard | /* never comes here */
|
559 | 3fb2ded1 | bellard | return 1; |
560 | 3fb2ded1 | bellard | } |
561 | 3fb2ded1 | bellard | |
562 | e4533c7a | bellard | #elif defined(TARGET_ARM)
|
563 | 3fb2ded1 | bellard | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
564 | 3fb2ded1 | bellard | int is_write, sigset_t *old_set)
|
565 | 3fb2ded1 | bellard | { |
566 | 3fb2ded1 | bellard | /* XXX: do more */
|
567 | 3fb2ded1 | bellard | return 0; |
568 | 3fb2ded1 | bellard | } |
569 | 93ac68bc | bellard | #elif defined(TARGET_SPARC)
|
570 | 93ac68bc | bellard | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
571 | 93ac68bc | bellard | int is_write, sigset_t *old_set)
|
572 | 93ac68bc | bellard | { |
573 | b453b70b | bellard | /* XXX: locking issue */
|
574 | b453b70b | bellard | if (is_write && page_unprotect(address)) {
|
575 | b453b70b | bellard | return 1; |
576 | b453b70b | bellard | } |
577 | b453b70b | bellard | return 0; |
578 | 93ac68bc | bellard | } |
579 | 67867308 | bellard | #elif defined (TARGET_PPC)
|
580 | 67867308 | bellard | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
581 | 67867308 | bellard | int is_write, sigset_t *old_set)
|
582 | 67867308 | bellard | { |
583 | 67867308 | bellard | TranslationBlock *tb; |
584 | ce09776b | bellard | int ret;
|
585 | 67867308 | bellard | |
586 | ce09776b | bellard | #if 1 |
587 | 67867308 | bellard | if (cpu_single_env)
|
588 | 67867308 | bellard | env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
589 | 67867308 | bellard | #endif
|
590 | 67867308 | bellard | #if defined(DEBUG_SIGNAL)
|
591 | 67867308 | bellard | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
|
592 | 67867308 | bellard | pc, address, is_write, *(unsigned long *)old_set); |
593 | 67867308 | bellard | #endif
|
594 | 67867308 | bellard | /* XXX: locking issue */
|
595 | 67867308 | bellard | if (is_write && page_unprotect(address)) {
|
596 | 67867308 | bellard | return 1; |
597 | 67867308 | bellard | } |
598 | 67867308 | bellard | |
599 | ce09776b | bellard | /* see if it is an MMU fault */
|
600 | 7f957d28 | bellard | ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
|
601 | ce09776b | bellard | if (ret < 0) |
602 | ce09776b | bellard | return 0; /* not an MMU fault */ |
603 | ce09776b | bellard | if (ret == 0) |
604 | ce09776b | bellard | return 1; /* the MMU fault was handled without causing real CPU fault */ |
605 | ce09776b | bellard | |
606 | 67867308 | bellard | /* now we have a real cpu fault */
|
607 | 67867308 | bellard | tb = tb_find_pc(pc); |
608 | 67867308 | bellard | if (tb) {
|
609 | 67867308 | bellard | /* the PC is inside the translated code. It means that we have
|
610 | 67867308 | bellard | a virtual CPU fault */
|
611 | 67867308 | bellard | cpu_restore_state(tb, env, pc); |
612 | 67867308 | bellard | } |
613 | ce09776b | bellard | if (ret == 1) { |
614 | 67867308 | bellard | #if 0
|
615 | ce09776b | bellard | printf("PF exception: NIP=0x%08x error=0x%x %p\n",
|
616 | ce09776b | bellard | env->nip, env->error_code, tb);
|
617 | 67867308 | bellard | #endif
|
618 | 67867308 | bellard | /* we restore the process signal mask as the sigreturn should
|
619 | 67867308 | bellard | do it (XXX: use sigsetjmp) */
|
620 | 67867308 | bellard | sigprocmask(SIG_SETMASK, old_set, NULL);
|
621 | ce09776b | bellard | do_queue_exception_err(env->exception_index, env->error_code); |
622 | ce09776b | bellard | } else {
|
623 | ce09776b | bellard | /* activate soft MMU for this block */
|
624 | ce09776b | bellard | sigprocmask(SIG_SETMASK, old_set, NULL);
|
625 | ce09776b | bellard | cpu_loop_exit(); |
626 | ce09776b | bellard | } |
627 | 67867308 | bellard | /* never comes here */
|
628 | 67867308 | bellard | return 1; |
629 | 67867308 | bellard | } |
630 | e4533c7a | bellard | #else
|
631 | e4533c7a | bellard | #error unsupported target CPU
|
632 | e4533c7a | bellard | #endif
|
633 | 9de5e440 | bellard | |
634 | 2b413144 | bellard | #if defined(__i386__)
|
635 | 2b413144 | bellard | |
636 | e4533c7a | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, |
637 | e4533c7a | bellard | void *puc)
|
638 | 9de5e440 | bellard | { |
639 | 9de5e440 | bellard | struct ucontext *uc = puc;
|
640 | 9de5e440 | bellard | unsigned long pc; |
641 | 9de5e440 | bellard | |
642 | d691f669 | bellard | #ifndef REG_EIP
|
643 | d691f669 | bellard | /* for glibc 2.1 */
|
644 | fd6ce8f6 | bellard | #define REG_EIP EIP
|
645 | fd6ce8f6 | bellard | #define REG_ERR ERR
|
646 | fd6ce8f6 | bellard | #define REG_TRAPNO TRAPNO
|
647 | d691f669 | bellard | #endif
|
648 | fc2b4c48 | bellard | pc = uc->uc_mcontext.gregs[REG_EIP]; |
649 | fd6ce8f6 | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
650 | fd6ce8f6 | bellard | uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
|
651 | fd6ce8f6 | bellard | (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0, |
652 | 2b413144 | bellard | &uc->uc_sigmask); |
653 | 2b413144 | bellard | } |
654 | 2b413144 | bellard | |
655 | 25eb4484 | bellard | #elif defined(__powerpc)
|
656 | 2b413144 | bellard | |
657 | e4533c7a | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, |
658 | e4533c7a | bellard | void *puc)
|
659 | 2b413144 | bellard | { |
660 | 25eb4484 | bellard | struct ucontext *uc = puc;
|
661 | 25eb4484 | bellard | struct pt_regs *regs = uc->uc_mcontext.regs;
|
662 | 25eb4484 | bellard | unsigned long pc; |
663 | 25eb4484 | bellard | int is_write;
|
664 | 25eb4484 | bellard | |
665 | 25eb4484 | bellard | pc = regs->nip; |
666 | 25eb4484 | bellard | is_write = 0;
|
667 | 25eb4484 | bellard | #if 0
|
668 | 25eb4484 | bellard | /* ppc 4xx case */
|
669 | 25eb4484 | bellard | if (regs->dsisr & 0x00800000)
|
670 | 25eb4484 | bellard | is_write = 1;
|
671 | 25eb4484 | bellard | #else
|
672 | 25eb4484 | bellard | if (regs->trap != 0x400 && (regs->dsisr & 0x02000000)) |
673 | 25eb4484 | bellard | is_write = 1;
|
674 | 25eb4484 | bellard | #endif
|
675 | 25eb4484 | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
676 | 2b413144 | bellard | is_write, &uc->uc_sigmask); |
677 | 2b413144 | bellard | } |
678 | 2b413144 | bellard | |
679 | 2f87c607 | bellard | #elif defined(__alpha__)
|
680 | 2f87c607 | bellard | |
681 | e4533c7a | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, |
682 | 2f87c607 | bellard | void *puc)
|
683 | 2f87c607 | bellard | { |
684 | 2f87c607 | bellard | struct ucontext *uc = puc;
|
685 | 2f87c607 | bellard | uint32_t *pc = uc->uc_mcontext.sc_pc; |
686 | 2f87c607 | bellard | uint32_t insn = *pc; |
687 | 2f87c607 | bellard | int is_write = 0; |
688 | 2f87c607 | bellard | |
689 | 8c6939c0 | bellard | /* XXX: need kernel patch to get write flag faster */
|
690 | 2f87c607 | bellard | switch (insn >> 26) { |
691 | 2f87c607 | bellard | case 0x0d: // stw |
692 | 2f87c607 | bellard | case 0x0e: // stb |
693 | 2f87c607 | bellard | case 0x0f: // stq_u |
694 | 2f87c607 | bellard | case 0x24: // stf |
695 | 2f87c607 | bellard | case 0x25: // stg |
696 | 2f87c607 | bellard | case 0x26: // sts |
697 | 2f87c607 | bellard | case 0x27: // stt |
698 | 2f87c607 | bellard | case 0x2c: // stl |
699 | 2f87c607 | bellard | case 0x2d: // stq |
700 | 2f87c607 | bellard | case 0x2e: // stl_c |
701 | 2f87c607 | bellard | case 0x2f: // stq_c |
702 | 2f87c607 | bellard | is_write = 1;
|
703 | 2f87c607 | bellard | } |
704 | 2f87c607 | bellard | |
705 | 2f87c607 | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
706 | 2f87c607 | bellard | is_write, &uc->uc_sigmask); |
707 | 2f87c607 | bellard | } |
708 | 8c6939c0 | bellard | #elif defined(__sparc__)
|
709 | 8c6939c0 | bellard | |
710 | e4533c7a | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, |
711 | e4533c7a | bellard | void *puc)
|
712 | 8c6939c0 | bellard | { |
713 | 8c6939c0 | bellard | uint32_t *regs = (uint32_t *)(info + 1);
|
714 | 8c6939c0 | bellard | void *sigmask = (regs + 20); |
715 | 8c6939c0 | bellard | unsigned long pc; |
716 | 8c6939c0 | bellard | int is_write;
|
717 | 8c6939c0 | bellard | uint32_t insn; |
718 | 8c6939c0 | bellard | |
719 | 8c6939c0 | bellard | /* XXX: is there a standard glibc define ? */
|
720 | 8c6939c0 | bellard | pc = regs[1];
|
721 | 8c6939c0 | bellard | /* XXX: need kernel patch to get write flag faster */
|
722 | 8c6939c0 | bellard | is_write = 0;
|
723 | 8c6939c0 | bellard | insn = *(uint32_t *)pc; |
724 | 8c6939c0 | bellard | if ((insn >> 30) == 3) { |
725 | 8c6939c0 | bellard | switch((insn >> 19) & 0x3f) { |
726 | 8c6939c0 | bellard | case 0x05: // stb |
727 | 8c6939c0 | bellard | case 0x06: // sth |
728 | 8c6939c0 | bellard | case 0x04: // st |
729 | 8c6939c0 | bellard | case 0x07: // std |
730 | 8c6939c0 | bellard | case 0x24: // stf |
731 | 8c6939c0 | bellard | case 0x27: // stdf |
732 | 8c6939c0 | bellard | case 0x25: // stfsr |
733 | 8c6939c0 | bellard | is_write = 1;
|
734 | 8c6939c0 | bellard | break;
|
735 | 8c6939c0 | bellard | } |
736 | 8c6939c0 | bellard | } |
737 | 8c6939c0 | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
738 | 8c6939c0 | bellard | is_write, sigmask); |
739 | 8c6939c0 | bellard | } |
740 | 8c6939c0 | bellard | |
741 | 8c6939c0 | bellard | #elif defined(__arm__)
|
742 | 8c6939c0 | bellard | |
743 | e4533c7a | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, |
744 | e4533c7a | bellard | void *puc)
|
745 | 8c6939c0 | bellard | { |
746 | 8c6939c0 | bellard | struct ucontext *uc = puc;
|
747 | 8c6939c0 | bellard | unsigned long pc; |
748 | 8c6939c0 | bellard | int is_write;
|
749 | 8c6939c0 | bellard | |
750 | 8c6939c0 | bellard | pc = uc->uc_mcontext.gregs[R15]; |
751 | 8c6939c0 | bellard | /* XXX: compute is_write */
|
752 | 8c6939c0 | bellard | is_write = 0;
|
753 | 8c6939c0 | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
754 | 8c6939c0 | bellard | is_write, |
755 | 8c6939c0 | bellard | &uc->uc_sigmask); |
756 | 8c6939c0 | bellard | } |
757 | 8c6939c0 | bellard | |
758 | 38e584a0 | bellard | #elif defined(__mc68000)
|
759 | 38e584a0 | bellard | |
760 | 38e584a0 | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, |
761 | 38e584a0 | bellard | void *puc)
|
762 | 38e584a0 | bellard | { |
763 | 38e584a0 | bellard | struct ucontext *uc = puc;
|
764 | 38e584a0 | bellard | unsigned long pc; |
765 | 38e584a0 | bellard | int is_write;
|
766 | 38e584a0 | bellard | |
767 | 38e584a0 | bellard | pc = uc->uc_mcontext.gregs[16];
|
768 | 38e584a0 | bellard | /* XXX: compute is_write */
|
769 | 38e584a0 | bellard | is_write = 0;
|
770 | 38e584a0 | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
771 | 38e584a0 | bellard | is_write, |
772 | 38e584a0 | bellard | &uc->uc_sigmask); |
773 | 38e584a0 | bellard | } |
774 | 38e584a0 | bellard | |
775 | 9de5e440 | bellard | #else
|
776 | 2b413144 | bellard | |
777 | 3fb2ded1 | bellard | #error host CPU specific signal handler needed
|
778 | 2b413144 | bellard | |
779 | 9de5e440 | bellard | #endif |