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cleanup cpu-exec.c, part 0/N: consolidate handle_cpu_signal
handle_cpu_signal is very nearly copy-paste code for each target, with afew minor variations. This patch sets up appropriate defaults for ageneric handle_cpu_signal and provides overrides for particular targets...
Save/restore ARMv6 MMU state
Correctly save/restore ARMV6 MMU state.
Signed-off-by: Paul Brook <paul@codesourcery.com>
Update to a hopefully more future proof FSF address
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
The _exit syscall is used for both thread termination in NPTL applications,and process termination in legacy applications. Try to guess which we wantbased on the presence of multiple threads.
Also implement locking when modifying the CPU list.
Signed-off-by: Paul Brook <paul@codesourcery.com>...
Fix cpu_arm_handle_mmu_fault warning
This patch fixes:
/scratch/froydnj/qemu.git/target-arm/helper.c:451: warning: no previous prototype for 'cpu_arm_handle_mmu_fault'
by moving the declaration of the function to cpu.h from exec.h. cpu.hseems to be the place most other ports declare the corresponding...
Update FSF address in GPL/LGPL boilerplate
The attached patch updates the FSF address in the GPL/LGPL boilerplatein most GPL/LGPLed files, and also in COPYING.LIB.
Signed-off-by: Stuart Brady <stuart.brady@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>...
Implement ARMv7 cp15 cache ID registers.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6105 c046a42c-6fe2-441c-8c8c-71466251a162
Implement (very) basic Thumb2-EE support. This doesn't actually implementEE state, just the associated system coprocessor registers. It is sufficientto keep OS setup and context switching code happy.
Refactor translation block CPU state handling (Jan Kiszka)
This patch refactors the way the CPU state is handled that is associatedwith a TB. The basic motivation is to move more arch specific code outof generic files. Specifically the long #ifdef clutter in tb_find_fast()...
Convert CPU_PC_FROM_TB to static inline (Jan Kiszka)
as macros should be avoided when possible.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5735 c046a42c-6fe2-441c-8c8c-71466251a162
Fix ARMv6 translation table base address calculation.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5514 c046a42c-6fe2-441c-8c8c-71466251a162
Move interrupt_request and user_mode_only to common cpu state.Save and restore env->interrupt_request and env->halted.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4817 c046a42c-6fe2-441c-8c8c-71466251a162
Move CPU save/load registration to common code.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4808 c046a42c-6fe2-441c-8c8c-71466251a162
Add instruction counter.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4799 c046a42c-6fe2-441c-8c8c-71466251a162
Fix typo.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4624 c046a42c-6fe2-441c-8c8c-71466251a162
Move clone() register setup to target specific code. Handle fork-like clone.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4623 c046a42c-6fe2-441c-8c8c-71466251a162
Push common interrupt variables to cpu-defs.h (Glauber Costa)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4612 c046a42c-6fe2-441c-8c8c-71466251a162
Implement ARM magic kernel page and TLS register.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4610 c046a42c-6fe2-441c-8c8c-71466251a162
moved halted field to CPU_COMMON
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4609 c046a42c-6fe2-441c-8c8c-71466251a162
Add basic OMAP2 chip support.
Add the OMAP242x (arm1136 core) initialisation with basic on-chipperipherals and update OMAP1 peripherals which are re-used in OMAP2.Make palmte.c and sd.c errors go to stderr.Allow disabling SD chipselect.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4213 c046a42c-6fe2-441c-8c8c-71466251a162
Move the excess of arm_load_kernel() parameters into a struct.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4212 c046a42c-6fe2-441c-8c8c-71466251a162
ARM N=Z=1 flag fix.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4156 c046a42c-6fe2-441c-8c8c-71466251a162
ARM TCG conversion 10/16.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4147 c046a42c-6fe2-441c-8c8c-71466251a162
ARM TCG conversion 1/16.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4138 c046a42c-6fe2-441c-8c8c-71466251a162
Prevent cpsr_write/_read be put out of line in op.o (fixes a segfault on some platforms).
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3633 c046a42c-6fe2-441c-8c8c-71466251a162
ARMv7 support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3572 c046a42c-6fe2-441c-8c8c-71466251a162
added cpu_model parameter to cpu_init()
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3562 c046a42c-6fe2-441c-8c8c-71466251a162
Replace is_user variable with mmu_idx in softmmu core, allowing support of more than 2 mmu access modes.Add backward compatibility is_user variable in targets code when needed.Implement per target cpu_mmu_index function, avoiding duplicated code and #ifdef TARGET_xxx in softmmu core functions....
Unify '-cpu ?' option.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3380 c046a42c-6fe2-441c-8c8c-71466251a162
Move get_sp_from_cpustate from cpu.h to target_signal.h.Enable sigaltstack processing for more architectures.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3253 c046a42c-6fe2-441c-8c8c-71466251a162
linux-user sigaltstack() syscall, by Thayne Harbaugh.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3252 c046a42c-6fe2-441c-8c8c-71466251a162
find -type f | xargs sed -i 's/[\t ]*$//g' # Yes, again. Note the star in the regex.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3177 c046a42c-6fe2-441c-8c8c-71466251a162
find -type f | xargs sed -i 's/[\t ]$//g' # on most files
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3173 c046a42c-6fe2-441c-8c8c-71466251a162
Basic OMAP310 support. Basic Palm Tungsten|E machine emulation.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3091 c046a42c-6fe2-441c-8c8c-71466251a162
Various reg offset shift typos.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3085 c046a42c-6fe2-441c-8c8c-71466251a162
Reset ARM cp15.c1_sys to default values. Fix XScale cp15 accesses.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3013 c046a42c-6fe2-441c-8c8c-71466251a162
Move target-specific defines to the target directories.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2940 c046a42c-6fe2-441c-8c8c-71466251a162
ARM946 CPU support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2783 c046a42c-6fe2-441c-8c8c-71466251a162
Account for machine with RAM which is not mapped at 0x0 in arm_boot.c.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2757 c046a42c-6fe2-441c-8c8c-71466251a162
Implement iwMMXt instruction set for the PXA270 cpu.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2752 c046a42c-6fe2-441c-8c8c-71466251a162
Core features of ARM XScale processors. Main PXA270 and PXA255 peripherals.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2749 c046a42c-6fe2-441c-8c8c-71466251a162
ARM reabbot support (orginal patch by Aurelien Jarno).
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2476 c046a42c-6fe2-441c-8c8c-71466251a162
Fix typo in help output.List ARM cpus.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2475 c046a42c-6fe2-441c-8c8c-71466251a162
Implement --cpu for ARM.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2474 c046a42c-6fe2-441c-8c8c-71466251a162
siginfo fix for Darwin/Mac OS X, by Pierre d'Herbemont.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2369 c046a42c-6fe2-441c-8c8c-71466251a162
Check ELF binaries for machine type and endianness.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2274 c046a42c-6fe2-441c-8c8c-71466251a162
Fix comment typo.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2197 c046a42c-6fe2-441c-8c8c-71466251a162
Add Arm926 core support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1765 c046a42c-6fe2-441c-8c8c-71466251a162
Arm Linux EABI syscall support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1756 c046a42c-6fe2-441c-8c8c-71466251a162
Implement Arm BKPT instruction.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1740 c046a42c-6fe2-441c-8c8c-71466251a162
ARM CPU suspend/halt (Paul Brook)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1663 c046a42c-6fe2-441c-8c8c-71466251a162
ARM system emulation (Paul Brook)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1661 c046a42c-6fe2-441c-8c8c-71466251a162
added CPU_COMMON and CPUState.tb_jmp_cache[]
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1630 c046a42c-6fe2-441c-8c8c-71466251a162
gdb support for user mode (Paul Brook)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1367 c046a42c-6fe2-441c-8c8c-71466251a162
VFP register ordering (Paul Brook)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1355 c046a42c-6fe2-441c-8c8c-71466251a162
soft float support
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1337 c046a42c-6fe2-441c-8c8c-71466251a162
ARM VFP support (Paul Brook)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1309 c046a42c-6fe2-441c-8c8c-71466251a162
initial user mmu support
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1270 c046a42c-6fe2-441c-8c8c-71466251a162
armv5te support (Paul Brook)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1258 c046a42c-6fe2-441c-8c8c-71466251a162
monitor fixes
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1110 c046a42c-6fe2-441c-8c8c-71466251a162
precise self modifying code support
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@745 c046a42c-6fe2-441c-8c8c-71466251a162
added TARGET_LONG_BITS
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@580 c046a42c-6fe2-441c-8c8c-71466251a162
new directory structure
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@385 c046a42c-6fe2-441c-8c8c-71466251a162