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Use the correct header in the TCG MIPS code to find cacheflush() on OpenBSD.
Use the correct header in the TCG MIPS code to find cacheflush() on OpenBSDto fix compilation of the MIPS host support for OpenBSD/mips64 based architecures.
Signed-off-by: Brad Smith <brad@comstyle.com>...
tcp/mips: Change TCG_AREG0 (fp -> s0)
Register fp (frame pointer) is a bad choice for compilationswithout optimisation, because the compiler makes heavy useof this register (so the resulting code crashes).
Register s0 had been used for TCG_AREG1 in earlier releases,...
tcg/mips: use seb/seh instructions on MIPS32R2
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg-mips: add guest base support
tcg-mips: implement nor
tcg: Allow target-specific implementation of NOR.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg: Allow target-specific implementation of NAND.
tcg: Allow target-specific implementation of EQV.
remove remaining occurrences AREG[1-9] and TCG_AREG[1-9]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg: Add comments for all optional instructions not implemented.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
tcg: initial mips support
Based on a patch from Arnaud Patard (Rtp) <arnaud.patard@rtp-net.org>