qemu tcg: Remove one entry of INDEX_op_ld_i64 from ppc_op_defs
There two entries of INDEX_op_ld_i64 in the ppc_op_defs. That causes anassertion failure in tcg_add_target_add_op_defs() when --enable-debug isused on a ppc64 backend (that's ppc64 host, not target)....
softmmu templates: optionally pass CPUState to memory access functions
Optionally, make memory access helpers take a parameter for CPUStateinstead of relying on global env.
On most targets, perform simple moves to reorder registers. On i386,switch from regparm(3) calling convention to standard stack-based...
Rename CPUState -> CPUArchState
Scripted conversion: for file in .[hc] hw/.[hc] hw/kvm/*.[hc] linux-user/*.[hc] linux-user/m68k/*.[hc] bsd-user/*.[hc] darwin-user/*.[hc] tcg/*/*.[hc] target-*/cpu.h; do sed -i "s/CPUState/CPUArchState/g" $file done...
Merge branch 's390-1.0' of git://repo.or.cz/qemu/agraf
tcg: Use TCGReg for standard tcg-target entry points.
Including tcg_out_ld, tcg_out_st, tcg_out_mov, tcg_out_movi.
Signed-off-by: Richard Henderson <rth@twiddle.net>Reviewed-by: Andreas Färber <afaerber@suse.de>Reviewed-by: Stefan Weil <sw@weilnetz.de>...
tcg: Standardize on TCGReg as the enum for hard registers
Most targets did not name the enum; tci used TCGRegister.
tcg-ppc64: Fix compile errors for userspace only builds with gcc 4.6
tcg/ppc64/tcg-target.c has a couple of places where variables are setunconditionally, but otherwise used only for softmmu builds, notuserspace only builds. This causes compiler warnings (which are fatal...
tcg: Don't declare TCG_TARGET_REG_BITS in tcg-target.h
It is now declared for all tcg targets in tcg.h,so the tcg target specific declarations are redundant.
Signed-off-by: Stefan Weil <weil@mail.berlios.de>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
tcg/ppc64: Only one call output register needed for 64 bit hosts
The second register is only needed for 32 bit hosts.
Cc: Vassili Karpov <av1474@comtv.ru>Fine-with-me'd-by: Vassili Karpov <av1474@comtv.ru>Signed-off-by: Stefan Weil <weil@mail.berlios.de>...
tcg/ppc64: Fix zero extension code generation bug for ppc64 host
The ppc64 code generation backend uses an rldicr (Rotate Left DoubleImmediate and Clear Right) instruction to implement zero extension ofa 32 bit quantity to a 64 bit quantity (INDEX_op_ext32u_i64). However...
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