target-xtensa: implement RST3 group
- access to Special Registers (wsr, rsr);- access to User Registers (wur, rur);- misc. operations option (value clamp, sign extension, min, max);- conditional moves.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>...
target-xtensa: implement shifts (ST1 and RST1 groups)
- ST1: SAR (shift amount special register) manipulation, NSA;- RST1: shifts, 16-bit multiplication.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-xtensa: implement LSAI group
- base + offset load/store operations for 1/2/4 byte values;- cache operations (not implemented);- multiprocessor synchronization operations.
target-xtensa: implement conditional jumps
- BZ (comparison to zero);- BI0 (comparison to signed immediate);- BI1 (comparison to unsigned immediate);- B (two registers comparison, bit sets comparison);- BEQZ.N/BNEZ.N (narrow comparison to zero).
target-xtensa: implement JX/RET0/CALLX
Group SNM0 (indirect jumps and calls).
target-xtensa: add special and user registers
Special Registers hold the majority of the state added to the processorby the options. See ISA, 5.3 for details.
User Registers hold state added in support of designer's TIE and in somecases of options that Tensilica provides. See ISA, 5.4 for details....
target-xtensa: implement disas_xtensa_insn
Set up disas_xtensa_insn switch structure, mark required options on highlevel groups. Implement arithmetic/bit logic/jump/call0.
Implement code generation loop with single step/breakpoint checking.
target-xtensa: implement narrow instructions
Instructions with op0 >= 8 are 2 bytes long, others are 3 bytes long.
target-xtensa: implement RT0 group
NEG and ABS are the only members of RT0 group.
target-xtensa: add sample board
Sample board and sample CPU core are used for debug and may be used fordevelopment of custom SoC emulators.
This board has two fixed size memory regions for DTCM and ITCM andvariable length SRAM region.
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